A high-speed interface circuit for RISC-V-based IO chip NoC network node
By introducing a RISC-V configuration management unit into the IO core NoC network node, the problems of slow initialization speed and resource consumption of high-speed interface IPs are solved, achieving efficient configuration management and improving system performance and stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 58TH RES INST OF CETC
- Filing Date
- 2025-07-03
- Publication Date
- 2026-08-04
AI Technical Summary
Under nanoscale process conditions, in IO chip NoC network nodes, high-speed interface IPs such as PCIe, RapidIO, and DDR are slow during initialization, and the configuration process consumes routing node resources, affecting system performance.
A RISC-V-based configuration management unit is adopted, including a RISC-V instruction core, a CROSSBAR bus, and a configuration bridge. It is connected to various on-chip IPs via an AXI bus. Driver software is written to implement initialization configuration management. An asynchronous FIFO structure is used to bridge different clock domains to realize data interaction and configuration signal conversion.
It significantly reduces the number of NoC network nodes, lowers configuration data transmission latency, improves configuration efficiency, reduces configuration and testing time, and enhances system performance and stability.
Smart Images
Figure CN120763100B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of chip technology, and in particular relates to a high-speed interface circuit for RISC-V-based IO chip NoC network nodes. Background Technology
[0002] Under nanoscale manufacturing conditions, chip design faces severe challenges such as rising manufacturing costs and declining yields. Chip technology has emerged as a key approach to solving these problems. By stacking modular and miniaturized chips from different processes to form chips, higher performance can be achieved at a lower cost. Based on their functions, chips can be categorized into various types, including computing chips, storage chips, control chips, and I / O chips.
[0003] When the IO chip adopts a NoC network architecture, the high-speed interface IPs such as PCIe, RapidIO, and DDR are slow to initialize when using NoC network routing. Furthermore, the CPU consumes routing node resources during the configuration process, affecting the overall system performance. Summary of the Invention
[0004] The purpose of this invention is to solve the problems mentioned in the background art and to propose a high-speed interface circuit for NoC network nodes based on RISC-V IO cores.
[0005] This application provides a high-speed interface circuit for a RISC-V-based IO chip NoC network node, comprising PCIe, RapidIO, DDR, and a configuration management unit; wherein, the configuration management unit uses a RISC-V instruction core as a processor, is connected to the configuration channels of each on-chip IP through an AXI bus, and specific driver software is written to realize the initialization configuration management function of each on-chip IP;
[0006] The configuration management unit includes a RISC-V instruction core, a CROSSBAR bus, and a configuration unit;
[0007] The RISC-V instruction core is the core computing and control unit;
[0008] The CROSSBAR bus is a channel for data exchange between the configuration unit and other configuration units in the system;
[0009] The AXI 1to6 conversion bridge is the hub for data flow within the configuration unit;
[0010] The configuration unit includes an AXI 1-to-6 conversion bridge and multiple configuration bridges; the AXI interface output from the CROSSBAR bus performs 1-to-6 processing.
[0011] Furthermore, the configuration bridge includes a PCIe configuration bridge, a RapidIO configuration bridge, and a DDR configuration bridge;
[0012] The configuration bridge transmits the configuration signals initiated by the RISC-V core to different components of NoD through different protocol conversions; the configuration bridge is used for PCIe, Rapid IO and DDR configuration; PCIe uses AXI and AHB; Rapid IO uses AXI and APB; DDR uses AHB and APB bus bridges.
[0013] Furthermore, the configuration bridge operates in two clock domains: the configuration unit clock that interfaces with RISC-V operates in the low clock domain, while each IP configuration interface operates in its own clock domain; two asynchronous FIFO structures are used to bridge the two clock domains.
[0014] Furthermore, the RISC-V instruction core's functions include receiving data from the configuration unit via CROSSBAR. This data includes parameters required for instruction execution and configuration information that needs to be processed.
[0015] On the other hand, the RISC-V instruction core transmits the instruction execution results, control signals, and other data generated after performing operations and control logic to the outside via CROSSBAR for feedback to other configuration interfaces within the configuration unit.
[0016] Furthermore, the RISC-V instruction core is bidirectionally connected to the CROSSBAR bus; the CROSSBAR bus is used to receive global system configuration parameters and send control commands to external modules.
[0017] Furthermore, the AXI 1to6 conversion bridge is used to receive data and instructions from the RISC-V instruction core, including various configuration commands and parameters for the PCIe configuration bridge, RapidIO configuration bridge, and DDR configuration bridge;
[0018] Upon receiving data and instructions, the AXI 1to6 conversion bridge converts and adapts the single-input AXI data according to the AXI bus protocol specification, and distributes it to the PCIe configuration bridge, RapidIO configuration bridge, and DDR configuration bridge.
[0019] Furthermore, the PCIe configuration bridge connects to the AXI 1to6 conversion bridge via AXI-BUS, receiving configuration commands and parameters from the conversion bridge. Following the AXI interface protocol standard, it performs configuration operations on PCIe-related registers, including setting the operating mode of the PCIe device and allocating address space. Simultaneously, the PCIe configuration bridge collects the status information and data read results of the PCIe device and transmits them back to the AXI 1to6 conversion bridge via AXI-BUS. Additionally, the PCIe configuration bridge also connects to an external AHB-BUS, enabling data interaction with the physical layer of the PCIe IP via AHB-BUS.
[0020] The RapidIO configuration bridge communicates with the AXI 1to6 converter bridge via AXI-BUS, receives configuration data and commands from the converter bridge, and configures the RapidIO IP registers according to the AXI interface protocol standard. It obtains the operating status and configuration execution feedback of the RapidIO device through the RapidIO configuration bridge; the RapidIO configuration bridge connects to the APB-BUS to interact with the corresponding external bus module, receiving control signals from the RapidIO physical layer from the APB-BUS to assist in configuration.
[0021] The DDR configuration bridge interacts with the AXI 1to6 conversion bridge via AHB-BUS, receiving DDR memory configuration commands and parameters from the conversion bridge; the DDR configuration bridge connects to APB-BUS, interacts with the DDR physical layer APB bus module, and receives read / write enable signals and status query commands from the APB bus.
[0022] Furthermore, the configuration process is as follows:
[0023] When the RISC-V instruction core detects the chip reset signal, it first checks the hardware readiness status of Nandflash, PCIe, and DDR.
[0024] When a certain IP is ready and can be initialized, the RISC-V instruction core performs the initialization work of the corresponding IP. If the corresponding IP is successfully initialized, the bit in the init_status array representing the status of the corresponding IP will be updated, changing the 1 of uninitialized to 0 of successful initialization.
[0025] After all IPs have been accessed once, the RISC-V instruction core checks the readiness status of the IPs that failed to initialize. If the readiness status is OK, the corresponding IP will be initialized, and the init_status array will be updated according to the initialization result.
[0026] Compared to the traditional method of mounting a CPU in a NoC network node and then using an address routing table to initialize configuration and detect high-speed interface IP registers, the method proposed in this invention, which builds a configuration bridge between the CPU and the high-speed interface IP, can not only significantly reduce the number of NoC network nodes used and reduce system complexity, but also greatly reduce the latency of configuration data transmission to the high-speed interface, greatly improve configuration efficiency, and effectively reduce configuration and detection time, providing a better option for configuring high-speed interface IPs of IO cores in NoC network architecture.
[0027] To more clearly illustrate the functional characteristics and structural parameters of the present invention, further explanation is provided below in conjunction with the accompanying drawings and specific embodiments. Attached Figure Description
[0028] Figure 1 This is a configuration unit architecture diagram provided in the embodiments of this application;
[0029] Figure 2 This is a PCIe configuration unit architecture diagram provided in the embodiments of this application;
[0030] Figure 3 This is a configuration structure diagram of Rapid IO IP provided in the embodiments of this application;
[0031] Figure 4 This is a DDR IP configuration structure diagram provided in the embodiments of this application;
[0032] Figure 5 This is a structural diagram of the configuration unit provided in the embodiments of this application;
[0033] Figure 6 This is a flowchart provided in the embodiments of this application;
[0034] Figure 7 This is a configuration diagram for the routing node method;
[0035] Figure 8 This is a structural diagram of the configuration bridge mode provided in the embodiments of this application. Detailed Implementation
[0036] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0037] In the I / O core, high-speed interface IPs such as PCIe, RapidIO, and DDR need to complete the initialization configuration of I / O devices during the initial startup of the NoC network system. However, the I / O core of the NoC network lacks a main control processor (CPU) to execute the initialization configuration tasks of each peripheral high-speed I / O device. Therefore, a powerful configuration management unit is urgently needed to efficiently and accurately complete the initialization operation of the high-speed interface IPs.
[0038] This invention aims to achieve efficient initialization and configuration of I / O devices by adding a configuration bridge unit between the RISC-V core and interface IP through an innovative design, thereby breaking through the bottleneck of existing technologies and improving the performance and stability of the entire system.
[0039] The interface circuitry comprises interconnect networks, PCIe, RapidIO, DDR IPs, and a configuration management unit. The configuration management unit uses an advanced RISC-V instruction core as its processor, connects to the configuration channels of each on-chip IP via the AXI bus, and employs customized driver software to implement initialization and configuration management functions for each on-chip IP. The configuration management unit includes a RISC-V instruction core, a CROSSBAR bus, and a configuration unit.
[0040] The configuration unit includes an AXI 1-to-6 conversion bridge, a PCIe configuration bridge, a RapidIO configuration bridge, and a DDR configuration bridge. Among them, the three high-speed interfaces, PCIe, RapidIO, and DDR, each have their own independent controllers and physical layers and require separate configuration. Therefore, the AXI interface output from the CROSSBAR bus is processed in a 1-to-6 manner to fully meet diverse configuration requirements.
[0041] The configuration management unit consists of a RISC-V instruction core, ITCM, DTCM, ICB bus, UART, and configuration bridge circuit; the NoC network consists of routers, resource network interfaces, channels, routing algorithms, and flow control mechanisms, with PCIe, Rapid IO, DDR, and NF IP cores mounted in the resource network interfaces.
[0042] Data Interaction of the RISC-V Instruction Core: The RISC-V instruction core plays a crucial role as the core computation and control unit. On one hand, the RISC-V instruction core receives data from the configuration unit through the CROSSBAR. This data includes key information such as parameters required for instruction execution and configuration information to be processed. On the other hand, the instruction execution results and control signals generated by the RISC-V instruction core after executing computation and control logic are transmitted externally through the CROSSBAR. This data is then fed back to other configuration interfaces within the configuration unit, enabling efficient data interaction and coordinated system control.
[0043] • CROSSBAR Bus: The CROSSBAR bus is the key channel for data exchange between the configuration unit and other configuration units in the system. The RISC-V instruction core is bidirectionally connected to the CROSSBAR bus, enabling smooth data transmission and reception between the instruction core and the external system. This includes receiving global system configuration parameters to provide accurate basis for subsequent configuration operations; and sending control commands to external modules to precisely regulate the system's operating status and ensure the stable operation of the entire system.
[0044] • The pivotal role of the AXI 1to6 conversion bridge: The AXI 1to6 conversion bridge is the core hub for data flow within the configuration unit. It receives data and instructions from the RISC-V instruction core, including various configuration commands and parameters for the PCIe configuration bridge, RapidIO configuration bridge, and DDR configuration bridge. Upon receiving the data and instructions, the AXI 1to6 conversion bridge accurately converts and adapts the single-input AXI data according to the AXI bus protocol specification, and efficiently distributes it to the PCIe configuration bridge, RapidIO configuration bridge, and DDR configuration bridge.
[0045] For example, when the RISC-V instruction core needs to configure the PCIe configuration bridge, it sends data containing detailed configuration parameters and operation instructions to the AXI 1to6 translation bridge. After a series of precise processing steps, the translation bridge accurately transmits the data to the PCIe configuration bridge via the AXI-BUS (connected to the PCIe configuration bridge in the diagram). Conversely, if the PCIe configuration bridge, RapidIO configuration bridge, or DDR configuration bridge generates feedback data, such as configuration status or data read results, it will first be transmitted to the AXI 1to6 translation bridge. The translation bridge then organizes and summarizes this feedback data according to the protocol and sends it back to the RISC-V instruction core, enabling the instruction core to know the configuration execution status in real time, obtain relevant data results, and then make timely adjustments and optimizations to the system configuration.
[0046] The AXI 1-to-6 converter bridge is a general design and will not be described in detail here.
[0047] The functions of the three configuration bridges are explained in detail below.
[0048] PCIe Configuration Bridge
[0049] The PCIe configuration bridge connects to the AXI 1to6 conversion bridge via AXI-BUS, receiving configuration commands and parameters from the conversion bridge. Following the AXI interface protocol standard, it performs configuration operations on PCIe-related registers, including setting the operating mode of the PCIe device and allocating address space. Simultaneously, the PCIe configuration bridge collects status information of the PCIe device (such as link status and device operating status) and data read results, transmitting them back to the AXI 1to6 conversion bridge via AXI-BUS. Furthermore, the PCIe configuration bridge also connects to an external AHB-BUS, enabling data exchange with the physical layer of the PCIe IP via AHB-BUS.
[0050] PCIe IP system architecture as follows Figure 2 As shown below, in conjunction with the above Figure 2 A detailed description of the entire subsystem is provided: The PC1eIP system includes a clock reset unit, PC1e CTRL, MISCE, PHY CREG, AHB MATRIX, and PHY;
[0051] The clock reset unit is used to generate clock and reset signals. Its inputs include the clock required by the PCIe controller configuration port AXI_BUS, the pc1k output from the PHY, the auxiliary clock signal used by the PCIe in low-power mode, and the system reset signal. The clock reset unit's inputs and outputs include various reset signals required by the PCIe controller configuration port AXI_BUS, the PHY's reset signal, and the reset signals used by the controller. It is the clock and reset management module for the entire subsystem.
[0052] PCIe CTRL is the core module for completing protocol conversion and requires register configuration via AXI_BUS.
[0053] MISCE stores the sideband signals of the PCIe controller. Since the signals need to be synchronized with the controller's core clock, MISCE also includes an asynchronous bridge for clock synchronization between the configuration clock and the core clock.
[0054] PHY CREG is a sideband signal module that stores the PHY and is used to control the control and status signals of the storable PHY. It needs to be configured via AHB_BUS registers.
[0055] AHB MATRIX is a route selector used to perform address decoding between the MISCE and PHY CREG on the AHB bus.
[0056] PHY is a high-speed SerDes used to generate differential pairs for data exchange. PCIe IP devices and external PCIe devices exchange data through PHY.
[0057] Rapid IO Configuration Bridge
[0058] The RapidIO configuration bridge communicates with the AXI 1to6 conversion bridge via AXI-BUS, receiving configuration data and commands from the conversion bridge and configuring the RapidIO IP registers according to the AXI interface protocol standard. It obtains data such as the operating status of the RapidIO device (e.g., link bandwidth usage, node connection status) and configuration execution feedback (whether configuration was successful). The RapidIO configuration bridge also connects to the APB-BUS to interact with the corresponding external bus module, receiving control signals from the RapidIO physical layer from the APB-BUS to assist in configuration.
[0059] Rapid IO IP system architecture as follows Figure 3 As shown below. (Combined with...) Figure 3 The entire configuration system is described in detail: Rapid IO IP includes Rapid IO CTRL, MISCE, PHY CREG, APB MATRIX, and PHY;
[0060] Rapid IO CTRL is the core module that performs Rapid IO protocol conversion, and its registers are configured via AXI_BUS;
[0061] MISCE stores the sideband signals of the Rapid IO controller. Since the signals in MISCE need to be synchronized with the controller's core clock, MISCE contains an asynchronous bridge for clock synchronization between the configuration clock and the core clock.
[0062] The PHY CREG is a sideband signal module that stores the PHY. It controls the control and status signals of the storable PHY and requires register configuration via APB_BUS.
[0063] APB MATRIX is a routing selector used to perform address decoding between the MISCE and PHY CREG on the APB bus.
[0064] The PHY is a high-speed SerDes device used to generate differential pairs for data exchange. RapidIO IP and external RapidIO devices exchange data through the PHY.
[0065] DDR configuration bridge
[0066] The DDR configuration bridge interacts with the AXI 1to6 conversion bridge via AHB-BUS, receiving DDR memory configuration commands and parameters (such as memory address allocation, read / write timing settings, etc.) from the conversion bridge; the DDR configuration bridge connects to APB-BUS, interacts with the DDR physical layer APB bus module, and receives read / write enable signals and status query commands from the APB bus.
[0067] DDR is a double-data-rate synchronous dynamic random access memory (DRAM), with a data transfer rate twice that of the system clock, offering superior performance compared to traditional SDRAM. DDR IP internally has two configuration channels using AHB and APB interfaces, used to access the registers on the DDR IP controller and PHY side, respectively.
[0068] The Slave Interface CTRL port is the controller port for the DDR IP. It is mainly used to access the controller's internal registers to configure the controller's status and bit width, and to set the load mode and timing parameters for SDRAM initialization.
[0069] The PHY end is the PHY port of the DDR IP, mainly used to access the DDR PHY port. DDR training is located in the PHY. DDR training is the necessary process for configuring port channels and corresponding physical layer controls. Completing the training can ensure that the channel transmits data correctly.
[0070] In summary, through clear bus connections and protocol adaptation, the various parts within this configuration unit enable the RISC-V instruction core to control various configuration bridges, and facilitate data interaction between the configuration bridges and external buses and devices, ensuring the orderly operation of system configuration functions and data flow.
[0071] The configuration bridge transmits configuration signals initiated by the RISC-V core to different components of NoD through different protocol conversions; the configuration bridge is used for PCIe, Rapid IO, and DDR configuration; PCIe uses AXI and AHB; Rapid IO uses AXI and APB; DDR uses AHB and APB bus bridges;
[0072] as follows Figure 5 As shown ( Figure 5 for Figure 1(Detailed description of the configuration unit in the middle), the master device port of the configuration bridge connects to the RISC-V core to implement the configuration function through the AXI bus interface.
[0073] Design requirements analysis reveals that the configuration bridge operates in two clock domains: the configuration unit interface with the RISC-V operates in the low clock domain, while each IP configuration interface operates in its own clock domain. To synchronize these two different clock domains, two asynchronous FIFO structures are used to bridge them. Figure 5 Asynchronous bridge implementation unit.
[0074] After the configuration bridge is connected to the CROSSBAR bus as a device, the configuration of each IP is completed in the software by manipulating the registers. The workflow of the configuration software is as follows: Figure 6 As shown. This system first reads the status registers of each IP inside the NoC chip to confirm whether the reset was successful. Based on the complexity of the configuration driver, it completes the initialization configuration of Rapid IO, DDR, and PCIe. After completing the corresponding configuration, it pulls the configuration completion indicator light high, or prints the incomplete configuration information through UART.
[0075] The configuration bridge method proposed in this invention can realize the initialization configuration of high-speed interfaces IPCIe, Rapid IO, and DDR without the CPU being mounted on the NoC network node. It reduces the number of NoC network nodes and the routing time of configuration information in the network, and is applicable to the node register configuration of all NoC networks.
[0076] Configuring high-speed nodes via routing nodes is as follows: Figure 7 As shown.
[0077] The method of configuring high-speed nodes by configuring bridges is as follows: Figure 8 As shown.
[0078] The comparison shows that the proposed bridge configuration method allows NoC network nodes to complete the initial configuration of high-speed interfaces even without CPU nodes attached. In summary, compared to the routing node method, this approach reduces the number of NoC network nodes and saves on routing configuration information, thus reducing the configuration time for high-speed interfaces.
[0079] The PCIe, RapidIO, and DDR configuration method for high-speed interface IPs of NoC network nodes based on RISC-V proposed in this invention has broad applicability, applicable not only to specific NoC network nodes but also to the initial configuration of all NoC network nodes. Compared with traditional network routing configuration methods, this invention significantly reduces the routing latency of configuration information while reducing the number of NoC network nodes to be configured, thus greatly improving system configuration efficiency.
[0080] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.
Claims
1. A RISC-V based IO core NoC network node high speed interface circuit, characterized in that, It includes PCIe, RapidIO, DDR, and a configuration management unit; the configuration management unit uses a RISC-V instruction core as the processor, is connected to the configuration channels of each on-chip IP through the AXI bus, and writes targeted driver software to realize the initialization configuration management function of each on-chip IP. The configuration management unit includes a RISC-V instruction core, a CROSSBAR bus, and a configuration unit; The RISC-V instruction core is the core computing and control unit; The CROSSBAR bus is a channel for data exchange between the configuration unit and other configuration units in the system; The configuration unit includes an AXI 1 to 6 conversion bridge and multiple configuration bridges; the AXI interface output from the CROSSBAR bus performs 1-to-6 processing; the AXI 1 to 6 conversion bridge is the hub for data flow within the configuration unit.
2. The interface circuit according to claim 1, characterized in that, The configuration bridges include the PCIe configuration bridge, the RapidIO configuration bridge, and the DDR configuration bridge; The configuration bridge transmits the configuration signals initiated by the RISC-V instruction core to different components of NoD through different protocol conversions. The configuration bridge is used for PCIe, Rapid IO and DDR configuration. PCIe uses AXI and AHB; Rapid IO uses AXI and APB; DDR uses AHB and APB bus bridges.
3. The interface circuit according to claim 1, characterized in that, The configuration bridge operates in two clock domains: the configuration unit that interfaces with RISC-V operates in the low clock domain, and each IP configuration interface operates in its own clock domain; two asynchronous FIFO structures are used to bridge the two clock domains.
4. The interface circuit according to claim 1, characterized in that, The RISC-V instruction core's functions include receiving data from the configuration unit via CROSSBAR. This data includes parameters required for instruction execution and configuration information that needs to be processed. On the other hand, the RISC-V instruction core transmits the instruction execution results, control signals, and other data generated after performing operations and control logic to the outside via CROSSBAR for feedback to other configuration interfaces within the configuration unit.
5. The interface circuit according to claim 1, characterized in that, The RISC-V instruction core is bidirectionally connected to the CROSSBAR bus; the CROSSBAR bus is used to receive global system configuration parameters and send control commands to external modules.
6. The interface circuit according to claim 1, characterized in that, The AXI 1to6 conversion bridge is used to receive data and instructions from the RISC-V instruction core. The data and instructions include various configuration commands and parameters for the PCIe configuration bridge, RapidIO configuration bridge, and DDR configuration bridge. Upon receiving data and instructions, the AXI 1to6 conversion bridge converts and adapts the single-input AXI data according to the AXI bus protocol specification, and distributes it to the PCIe configuration bridge, RapidIO configuration bridge, and DDR configuration bridge.
7. The interface circuit according to claim 2, characterized in that, The PCIe configuration bridge connects to the AXI 1to6 conversion bridge via AXI-BUS, receives configuration commands and parameters from the conversion bridge, and performs configuration operations on PCIe-related registers according to the AXI interface protocol standard, including setting the operating mode of the PCIe device and allocating address space. At the same time, the PCIe configuration bridge collects the status information and data read results of the PCIe device and transmits them back to the AXI 1to6 conversion bridge via AXI-BUS. In addition, the PCIe configuration bridge also connects to an external AHB-BUS, enabling data exchange with the physical layer of the PCIe IP via the AHB-BUS; The RapidIO configuration bridge is used to communicate with the AXI 1to6 conversion bridge via AXI-BUS, receive configuration data and commands from the conversion bridge, and configure the RapidIO IP registers according to the AXI interface protocol standard. It also obtains the operating status and configuration execution feedback of the RapidIO device. Furthermore, the RapidIO configuration bridge connects to the APB-BUS to interact with the corresponding external bus module, receiving control signals from the RapidIO physical layer from the APB-BUS to assist in configuration. The DDR configuration bridge interacts with the AXI 1to6 conversion bridge via AHB-BUS, receiving DDR memory configuration commands and parameters from the conversion bridge; the DDR configuration bridge connects to APB-BUS, interacts with the DDR physical layer APB bus module, and receives read / write enable signals and status query commands from the APB bus.
8. The interface circuit according to claim 1, characterized in that, The configuration process is as follows: When the RISC-V instruction core detects the chip reset signal, it first checks the hardware readiness status of Nandflash, PCIe, and DDR. When a certain IP is ready and can be initialized, the RISC-V instruction core performs the initialization work of the corresponding IP. If the corresponding IP is successfully initialized, the bit in the init_status array representing the status of the corresponding IP will be updated, changing the 1 of uninitialized to 0 of successful initialization. After all IPs have been accessed once, the RISC-V instruction core checks the readiness status of the IPs that failed to initialize. If the readiness status is OK, the corresponding IP will be initialized, and the init_status array will be updated according to the initialization result.