Cache consistency test method, device and equipment and readable storage medium

Abstract

The application provides a cache consistency test method and device, electronic equipment and a computer readable storage medium, including: obtaining a test sequence of a multi-core cache system; the multi-core cache system includes at least two processor cores and a multi-level cache; the test sequence includes operation instructions for each processor core; inputting the test sequence into a simulation model, processing the test sequence in turn through the multi-level cache of the simulation model according to a cache consistency protocol, and outputting a state checkpoint of the multi-core cache system; the state checkpoint is used to represent the current cache state of each processor core in the multi-core cache system; testing the cache consistency of the multi-core cache system according to the state checkpoint, and obtaining a test result. The embodiment of the application can improve the reliability and comprehensiveness of the cache consistency test.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a cache consistency testing method, apparatus, electronic device, and computer-readable storage medium. Background Technology

[0002] In a multi-core processor system, when multiple processor cores share the same memory data, the cache states of different processor cores may be inconsistent, which may lead to abnormal system operation. Therefore, it is necessary to test the cache state consistency in a multi-core processor system.

[0003] In related technologies, verification components are typically used to test the consistency of cache states of various modules in a multi-core processor system by tracking cache states and verification rules in real time.

[0004] However, the methods in related technologies support testing the cache state within a module or between some modules, which has limited coverage. Summary of the Invention

[0005] This application provides a cache consistency testing method, apparatus, electronic device, and computer-readable storage medium to solve problems in related technologies.

[0006] In a first aspect, embodiments of this application provide a cache consistency testing method, the method comprising:

[0007] Obtain a test sequence for a multi-core cache system; the multi-core cache system includes at least two processor cores and a multi-level cache; the test sequence includes operation instructions for each processor core.

[0008] The test sequence is input into the simulation model. According to the cache coherence protocol, the test sequence is processed sequentially through the multi-level cache of the simulation model, and the status checkpoint of the multi-core cache system is output. The status checkpoint is used to characterize the current cache state of each processor core in the multi-core cache system.

[0009] The cache consistency of the multi-core cache system was tested based on the state checkpoints, and the test results were obtained.

[0010] Secondly, embodiments of this application provide a cache consistency testing device, the device comprising: an acquisition module, a processing module, and a testing module.

[0011] The acquisition module is used to acquire the test sequence of a multi-core cache system; the multi-core cache system includes at least two processor cores and a multi-level cache; the test sequence includes operation instructions for each processor core.

[0012] The processing module is used to input the test sequence into the simulation model, process the test sequence sequentially through the multi-level cache of the simulation model according to the cache coherence protocol, and output the status checkpoint of the multi-core cache system. The status checkpoint is used to characterize the current cache status of each processor core in the multi-core cache system.

[0013] The testing module is used to test the cache consistency of a multi-core cache system based on state checkpoints and obtain test results.

[0014] Thirdly, embodiments of this application also provide an electronic device, including a processor;

[0015] Memory used to store the processor's executable instructions;

[0016] The processor is configured to execute the instructions to implement the method of the first aspect.

[0017] Fourthly, embodiments of this application also provide a computer-readable storage medium that, when the instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to perform the method of the first aspect.

[0018] This application embodiment acquires a test sequence for a multi-core cache system, specifying that the multi-core cache system includes at least two processor cores and a multi-level cache. The test sequence includes operation instructions for each processor core, realistically simulating concurrent behavior of multiple cores accessing shared or private memory regions simultaneously in a multi-core system, thus improving the comprehensive coverage of multi-core interaction scenarios. The acquired test sequence can be input into a simulation model. According to the cache coherence protocol, the test sequence is processed sequentially through the multi-level cache of the simulation model, and a state checkpoint of the multi-core cache system is output. This state checkpoint records the complete state information of all processor cores and cache lines in each level of cache at a specific moment, covering extreme consistency scenarios that are difficult to reproduce with physical hardware. It reflects the state dependencies between multiple cores due to protocol interactions, forming a globally consistent time profile, providing a reliable basis for subsequent consistency testing. Finally, the cache coherence of the multi-core cache system is tested based on the state checkpoint, and the test results are obtained. Consistency testing based on the state checkpoint can determine whether all cache copies meet the requirements of the cache coherence protocol from the perspective of the entire system, reducing misjudgments caused by local observations, thereby improving the reliability and comprehensiveness of the test.

[0019] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a flowchart illustrating the steps of a cache consistency testing method provided in an embodiment of this application;

[0022] Figure 2 This is a flowchart of another cache consistency testing method provided in an embodiment of this application;

[0023] Figure 3 An ordered state diagram provided for embodiments of this application;

[0024] Figure 4 This is another ordered state diagram provided in the embodiments of this application;

[0025] Figure 5 This is yet another ordered state diagram provided in the embodiments of this application;

[0026] Figure 6 This is a schematic diagram of a simulation model architecture provided in an embodiment of this application;

[0027] Figure 7 This is a block diagram of a cache consistency testing device provided in an embodiment of this application;

[0028] Figure 8 This is a block diagram of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0030] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and are not limited in number; for example, a first object can be one or more. Furthermore, the term "and / or" in the specification and claims is used to describe the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. In the embodiments of this application, the term "multiple" refers to two or more, and other quantifiers are similar.

[0031] In a multi-core processor system, when multiple processor cores share the same memory data, the cache states of different processor cores may be inconsistent, which may lead to abnormal system operation. Therefore, it is necessary to test the cache state consistency in a multi-core processor system.

[0032] Cache state consistency refers to the logical consistency of data at the same memory address across multiple caches in a multi-core processor system. In other words, regardless of which processor core accesses the data, it should obtain the correct value. This is typically achieved through cache consistency protocols, ensuring that when one processor core modifies data, the corresponding copy in other caches is updated or invalidated, thus avoiding the reading of outdated data.

[0033] In related technologies, various methods are typically used to test cache consistency in multi-core processor systems. These include targeted testing, random testing, testing through verified components, and testing by constructing a cache reference model.

[0034] Directed testing involves manually designing specific scenarios, such as two cores performing read and write operations on the same address, to verify whether the cache state is correctly transitioned according to the protocol. It is suitable for verifying critical paths and boundary conditions. However, because directed testing involves manually set scenarios, its coverage is limited and cannot cover the vast space of consistent state transitions.

[0035] Random testing uses a random generator to initiate read and write operations randomly across multiple cores, simulating concurrent access and checking for consistency errors. It is suitable for discovering hidden problems in complex scenarios. However, random testing, based on randomization, cannot cover the complete state transition space. Due to its uncertainty, random testing generates a large number of repetitive instructions, leading to excessively long test sequences and increased testing time.

[0036] By using component testing to verify state consistency or state transition errors within a module or between some modules, components such as monitors or scoreboards can be used. However, this method only supports verifying state transitions within a module or between some modules and cannot support overall cache consistency in multi-core processor systems (e.g., the Xiangshan Nanhu V5 multi-core cache system).

[0037] This approach involves constructing a cache reference model using SystemC, SystemVerilog, and C / C++ to simulate and verify cache coherency. SystemC is an open-source C++ library for hardware system-level modeling, providing a high-level abstract programming framework that allows developers to describe complex hardware behavior and system-level models using C++, thus enabling more efficient design and verification of complex systems. SystemVerilog is a superset and extension of Verilog, combining the features of hardware description and hardware verification languages. Verilog is a hardware description language for electronic design automation, widely used in integrated circuit design, verification, and assertion, supporting advanced verification functions such as object-oriented programming, random testing, and functional coverage. However, this cache reference model approach only supports one type of cache coherency and cannot support cache systems with hierarchical protocol structures. For example, the Xiangshan Nanhu V5 cache system supports both the TileLink protocol and the Cache Coherent Interconnect (CHI) protocol.

[0038] Against this background, embodiments of this application provide a cache consistency testing method that can improve the accuracy and comprehensiveness of cache consistency testing.

[0039] Figure 1 This is a flowchart illustrating the steps of a cache consistency testing method provided in an embodiment of this application. Figure 1 As shown, the method may include steps 101-103.

[0040] Step 101: Obtain the test sequence for the multi-core cache system; the multi-core cache system includes at least two processor cores and a multi-level cache; the test sequence includes operation instructions for each processor core.

[0041] In this embodiment, the multi-core caching system includes at least two processor cores, such as a central processing unit (CPU) 0, CPU1, and CPU2. Each core can execute instructions independently, and there is a need for concurrent access to shared memory. The multi-core caching system includes multi-level caches, and all cache levels work together through a cache coherence protocol to ensure that cached data remains consistent across multiple cores. Cache coherence protocols may include MESI, MOESI, TileLink, and CHI protocols, etc.

[0042] MESI is a cache coherence protocol primarily used in multi-core processors to resolve inconsistencies in cached data between different CPU cores. The four letters in MESI represent four states: M stands for Modified, meaning the cache line's data has been modified but not yet written back to main memory (essentially dirty data); E stands for Exclusive, meaning the cache line's data exists only in the current CPU's cache and is consistent with the data in main memory; S stands for Shared, meaning the cache line's data exists in the caches of multiple CPUs and is consistent with the data in main memory; and I stands for Invalidated, meaning the cache line's data is invalid and cannot be read.

[0043] The MOESI protocol adds an Owned (O) state to the MESI protocol. O means that the data is shared in multiple caches and is dirty data, and only one cache is responsible for eventually writing it back to main memory.

[0044] TileLink is a chip-level interconnect standard that allows multiple master devices to access memory and other slave devices in a consistent memory mapping manner. TileLink is designed to provide a high-speed, scalable on-chip interconnect with low latency and high throughput for connecting general-purpose multiprocessors, coprocessors, accelerators, and various simple or complex devices to systems on chip.

[0045] CHI is a high-performance, scalable on-chip interconnect protocol belonging to the Advanced Microcontroller Bus Architecture (AMBA) protocol. It is used to achieve efficient and reliable cache coherency and data communication in multi-core system-on-a-chip (SoC). It employs a directory-based architecture, supports large-scale system expansion, and is widely used in server-grade and high-end mobile processor platforms.

[0046] A generation algorithm can be embedded in the verification platform to obtain test sequences. These test sequences can include operation instruction types such as load, store, and evict. Load can represent the processor core reading data from the cache or memory, triggering a cache hit check or data request; store can represent the processor core writing data to the cache, which may change the state of the cache block and requires exclusive access; evict can represent the processor core evicting a cache block due to insufficient cache space, triggering data write-back (especially dirty data) and permission release.

[0047] Step 102: Input the test sequence into the simulation model. According to the cache coherence protocol, process the test sequence sequentially through the multi-level cache of the simulation model and output the status checkpoint of the multi-core cache system.

[0048] In this embodiment, state checkpoints are used to characterize the current cache state of each processor core in a multi-core cache system. State checkpoints may include information such as data storage address, data storage state, and data content. After the test sequence is input into the simulation model, the multi-level cache in the simulation model can process the test sequence layer by layer according to a preset cache consistency protocol. For example, the model can read the test sequence. After each instruction to run a test sequence is read, each module of the model completes the corresponding request and response, and then changes its own consistency state according to the cache consistency protocol. Simultaneously, the model also outputs the global consistency state of the system as a checkpoint. After each instruction is executed, a global state checkpoint is generated for subsequent cache consistency testing.

[0049] After obtaining the global state checkpoints of the multi-core caching system, all state checkpoints can be written to a JSON file for storage.

[0050] Step 103: Test the cache consistency of the multi-core cache system based on the state checkpoints and obtain the test results.

[0051] In this embodiment, the testing tool can verify the current system's cache state against expectations by checking state checkpoints according to predefined cache consistency protocol rules. For example, if a cache line is in a "modified" state and is exclusively used by one core, then the corresponding cache lines in all other cores must be in an "invalid" state to prevent old data from being misused. Similarly, if data at a certain address has been written back to main memory or a higher-order cache, its state in the lower-order cache should also be correctly updated or marked as clean.

[0052] This application embodiment acquires a test sequence for a multi-core cache system, specifying that the multi-core cache system includes at least two processor cores and a multi-level cache. The test sequence includes operation instructions for each processor core, realistically simulating concurrent behavior of multiple cores accessing shared or private memory regions simultaneously in a multi-core system, thus improving the comprehensive coverage of multi-core interaction scenarios. The acquired test sequence can be input into a simulation model. According to the cache coherence protocol, the test sequence is processed sequentially through the multi-level cache of the simulation model, and a state checkpoint of the multi-core cache system is output. This state checkpoint records the complete state information of all processor cores and cache lines in each level of cache at a specific moment, covering extreme consistency scenarios that are difficult to reproduce with physical hardware. It reflects the state dependencies between multiple cores due to protocol interactions, forming a globally consistent time profile, providing a reliable basis for subsequent consistency testing. Finally, the cache coherence of the multi-core cache system is tested based on the state checkpoint, and the test results are obtained. Consistency testing based on the state checkpoint can determine whether all cache copies meet the requirements of the cache coherence protocol from the perspective of the entire system, reducing misjudgments caused by local observations, thereby improving the reliability and comprehensiveness of the test.

[0053] Figure 2 This is a flowchart illustrating the steps of another cache consistency testing method provided in an embodiment of this application. Figure 2 As shown, the method may include steps 201-203.

[0054] Step 201: Obtain the test sequence for the multi-core cache system; the multi-core cache system includes at least two processor cores and a multi-level cache; the test sequence includes operation instructions for each processor core.

[0055] Step 202: Input the test sequence into the simulation model. According to the cache coherence protocol, process the test sequence sequentially through the multi-level cache of the simulation model and output the status checkpoint of the multi-core cache system. The status checkpoint is used to characterize the current cache status of each processor core in the multi-core cache system.

[0056] Step 203: Test the cache consistency of the multi-core cache system based on the state checkpoints and obtain the test results.

[0057] The specific implementation methods for steps 201-203 above can be found in the above description. Figure 1 Examples are not described here.

[0058] Optionally, step 202 above may include sub-steps 2021-2023.

[0059] Sub-step 2021: Input the test sequence into the simulation model, and convert the test sequence into a first request through the first cache according to the first protocol.

[0060] In this embodiment, the format of the first request matches the format supported by the first protocol. The cache coherence protocol may include the first protocol and the second protocol. The multi-level cache of the simulation model includes a first cache, a second cache, and a third cache, which can also be understood as the multi-level cache of the simulation model including a level 1 cache (L1), a level 2 cache (L2), and a level 3 cache (L3). The level 1 cache, level 2 cache, and level 3 cache are connected sequentially. The level 1 cache is a private data cache for each processor core, and each processor core has one level 1 cache.

[0061] For example, taking the Tilelink protocol as the first protocol, the Tilelink protocol is a standardized cache coherency interaction interface between L1 and the upstream processor core and downstream L2. The load / store / evict operations of the test sequence are abstract operations of the processor core, while L1 and L2 belong to different levels of cache components and need to define the request format through the standardized protocol (Tilelink protocol). After reading the test sequence, L1 can convert the test sequence into a Tilelink request, i.e., the first request mentioned above.

[0062] Sub-step 2022: Process the first request sequentially through the second and third caches to obtain response information, and send the response information to the first cache.

[0063] In this embodiment, the portion of the second cache facing the upstream first cache is modeled using a first protocol, while the portion facing the downstream third protocol is modeled using a second protocol. The internal cache state of the second cache is based on the first protocol, and when sending requests or returning responses downstream, it is converted into transactions related to the second protocol. The second cache can be an inter-core semi-shared cache; for example, among CPU0, CPU1, CPU2, and CPU3, CPU0 and CPU1 share a single L2 cache. When the second cache receives a first request, it can process the first request sequentially through the second cache and the third cache to obtain response information, and then send the response information back to the first cache. For example, the second cache can directly send response information to the first cache, the third cache can send response information to the second cache, and the second cache can forward the response information to the first cache.

[0064] Sub-step 2023: Update the cache status of the processor core corresponding to the first cache according to the response information, and output the status checkpoint of the multi-core cache system.

[0065] In this embodiment, the response information can be understood as a signal that triggers a cache state transition, and different response information can drive the state of the first cache to be updated according to the protocol rules.

[0066] For example, taking the TileLink protocol: if the response information carries data and read permission (GrantData), CPU0's L1 sends a request to obtain readable data from the invalid state (AcquireBlock.NtoB), and L2 returns the response information GrantData, which contains data and read permission (B). In CPU0's L1, the state of the cache block changes from invalid (I) to readable (B), and the data carried by GrantData is written.

[0067] This embodiment inputs test sequences into a simulation model and, according to a first protocol, converts the test sequences into first requests through a first cache. This transforms abstract test operations (e.g., load / store / evict) into specific requests conforming to the protocol specifications, achieving effective communication and consistency coordination between different cache levels. The first request is processed sequentially through a second and third cache to obtain response information, which is then sent to the first cache. This hierarchical request processing reduces the limitations of single-cache processing (e.g., the second cache only knows its local cache state), while the third cache's global perspective ensures the response information conforms to consistency rules. Then, the cache state of the processor core corresponding to the first cache is updated based on the response information, and a status checkpoint for the multi-core cache system is output. The cache state can be dynamically adjusted through the consistency protocol, improving cache data consistency and providing a data foundation for subsequent cache consistency testing.

[0068] Optionally, the above sub-step 2022 may include sub-steps 20221-20224.

[0069] Sub-step 20221: Determine if the data corresponding to the first request exists in the second cache.

[0070] In this embodiment of the application, after receiving the first request sent by the first cache, it is possible to check whether the second cache contains the data corresponding to the first request. For example, the memory of the second cache can be queried through the data address in the first request (e.g., 0x1000) to match whether there is a cache block at that address, and at the same time check whether the status of the cache block allows a response, such as whether it is an "invalid (I)" status. If invalid, it is considered that there is no valid data.

[0071] Sub-step 20222: If it exists, generate response information through the second cache of the simulation model and send the response information to the first cache.

[0072] In this embodiment, if it is determined that the data corresponding to the first request exists in the second cache, a response message conforming to the first protocol (e.g., the TileLink protocol for L1-L2 interaction) is generated based on the type of the first request (e.g., reading data, obtaining permissions, etc.) and the state of the data in the second cache, and the response message is sent to the first cache. For example, if the first request is AcquireBlock.NtoB (L1 requests readable data from an invalid state), and the data in L2 is in a "readable (B)" state, a GrantData response is generated, containing a data block and "B" permissions, and a GrantData response is returned to L1.

[0073] Sub-step 20223: If it does not exist, then according to the second protocol, convert the first request into a second request through the second cache.

[0074] In this embodiment, the format of the second request matches the format supported by the second protocol. The second protocol is the protocol for interaction between the second cache (L2) and the downstream cache (e.g., the third protocol L3). For example, L2 and L3 may use the CHI protocol, and L1 and L2 may use the TileLink protocol. In this case, the second protocol is the CHI protocol.

[0075] If it is determined that the data corresponding to the first request does not exist in the second cache, the first request can be converted into a second request through the second cache. That is, the first request that follows the first protocol (e.g., AcquireBlock of the TileLink protocol) is converted into a second request that conforms to the second protocol (e.g., the CHI protocol), and the second request is sent to the third cache.

[0076] Sub-step 20224: Process the second request through the third cache, obtain the response information, and send the response information to the first cache.

[0077] In this embodiment, the third cache is a globally shared cache that can be directly connected to the main memory controller and is responsible for managing the state of the global cache blocks and their interaction with the main memory. It maintains a state directory for all cache blocks in the entire system (e.g., recording which L2 or L1 nodes hold copies, their permission levels, and whether the data is dirty). After receiving a second request from the second cache, the third cache can determine whether it can directly respond to the request. If a permission conflict exists (e.g., other cores hold conflicting permissions), it coordinates permissions through protocol interaction, ultimately generating a response and forwarding it to L1 via L2.

[0078] For example, after receiving the second request, the third cache can parse the request to obtain the target address (e.g., 0x4000) and the required permissions (e.g., "Unique," meaning exclusive permissions that allow data modification while other cores are invalidated). The L3 cache can query the global status of the target address through its built-in consistency directory. If the directory shows "no other core holds a cache block at this address" or "other cores only hold shared permissions," the L3 cache can respond directly. If the directory shows that a core holds exclusive permissions for this address or that there is dirty data, then there is a permission conflict. In this case, the L3 cache must first revoke the conflicting permissions before satisfying the current request.

[0079] If a permission conflict exists, L3, according to the CHI protocol rules, sends corresponding snooping requests to the core holding the conflicting permission. Examples include snooping for exclusive access (SnpUnique) and snooping for non-shared dirty data (SnpNotSharedDirty). SnpUnique requests the target core (e.g., CPU1) to return the data at that address and release the exclusive access (transferring it to an invalid state). This is suitable for scenarios where the current request requires exclusive access, and the target core holds exclusive access. SnpNotSharedDirty checks whether the target core holds non-shared dirty data (i.e., the core is the sole holder and the data has been modified). If it is dirty data, the data must be written back to L3 before releasing the permission. These requests are sent to the corresponding core's L2 or L1 via the interconnect network, triggering a state update, such as the Unique state changing to the Invalid state, and a response is returned, such as carrying data (SnpAckData) and confirming the release (SnpAck).

[0080] After L3 sends the corresponding snooping request to the core holding conflicting permissions, it can wait and collect responses from all the snooped cores. If it receives SnpAckData, it retrieves the dirty data and updates its local cache to ensure that L3 holds the latest data. If it receives SnpAck, it confirms that the target core has released the conflicting permissions and updates the directory state, i.e., marks the cache blocks of these cores as Invalid. After all conflicting permissions are revoked and data synchronization is completed, L3's local state meets the response conditions, such as holding the latest data and having no global conflicting permissions. Based on the requirements of the second request, it generates a response, such as GrantData in the CH protocol, containing data and Unique permissions, and sends it to L2 that forwarded the request. L2 then converts the response into the format of the first protocol, such as TileLink, and finally sends it to the first cache (L1), triggering an L1 state update.

[0081] This embodiment can determine whether the data corresponding to the first request exists in the second cache. If it does, a response is generated through the second cache of the simulation model and sent to the first cache. The local sharing characteristic of the second cache can be used to achieve a nearby response to the request, reducing response latency and improving system performance. If the data does not exist, the first request is converted into a second request through the second cache according to the second protocol. Protocol conversion can achieve collaboration at heterogeneous protocol layers, preserving the low-latency characteristics of the upper-layer protocol while utilizing the high scalability of the lower-layer protocol, supporting a flexible architecture of multi-level caching. Finally, the second request is processed through the third cache to obtain the response information, which is then sent to the first cache. This reduces consistency errors caused by multiple cores simultaneously modifying the same data, reduces invalid communication, and thus improves the efficiency of consistency testing.

[0082] Optionally, step 201 above may include sub-steps 2011-2013.

[0083] Sub-step 2011: Determine the state transition relationship of each processor core in the multi-core cache system according to the cache coherence protocol.

[0084] In this embodiment, cache state transitions can be understood as the switching process of a data block in the cache between different states, typically triggered by processor read / write operations or requests detected on the bus. Common states include Modified, Shared, and Invalid, depending on the cache coherence protocol used. The state transition relationships among processor cores can also be understood as a state transition space. The coherent state transition space refers to the set of possible state combinations and state transition paths for all caches to shared memory blocks in a multi-core system. Since each core's cache may be in different states, the entire state space grows exponentially and becomes extremely large as the number of cores, addresses, and operation types increase. There are numerous complex dependencies between state transitions, and even a slight omission can lead to a consistency vulnerability.

[0085] For example, a multi-core cache system can be in one of three valid states according to the TileLink protocol: invalid (I), readable (B), and readable-writable (T). Based on this, the state transition relationships between processor cores in a multi-core cache system can include: transitions between shared states, transitions between exclusive states, and transitions between shared and exclusive states. A shared state indicates that all processor cores in the multi-core cache system are in an invalid or readable state. An exclusive state indicates that only one processor core in the multi-core cache system is in a readable-writable state, while the remaining processor cores are in an invalid state.

[0086] Sub-step 2012: Based on the state transition relationships, generate an ordered state diagram of the state transition relationships of each processor core in the multi-core cache system.

[0087] In this embodiment, each node of the ordered state graph can be used to represent the global cache state of each processor core in a multi-core cache system. The connecting lines in the ordered state graph can be viewed as the connection relationship between two vertices in the ordered graph, representing the transition from one state to another in the global state space. A state can be abstracted as a vertex in the ordered state graph, and the transition between states (caused by an operation) can be abstracted as the edge connection relationship between vertices in the ordered graph. The multidimensional state space can be compressed into a two-dimensional ordered graph, and the transition between different states in the space can be abstracted as path search between vertices in the ordered graph.

[0088] An ordered state diagram is defined as follows: G = (V, E), where G can represent a global ordered state diagram, V can represent a state space, and E can represent a set of state transitions. When E(i,j)≠0, state i can be transformed into state j in one step; otherwise, it cannot be transformed.

[0089] For example, Figure 3 This is an ordered state diagram provided in an embodiment of this application. For example... Figure 3 As shown, Figure 3 It can represent the transformation relationship between the global shared states of 3 cores. In the transformation relationship between shared states, any two shared state transformations can be obtained by several cores performing Load or Evict operations, indicating that the ordered graph is strongly connected.

[0090] Figure 4 This is another ordered state diagram provided in the embodiments of this application. For example... Figure 4 As shown, Figure 4 It can represent the transition relationship between the global exclusive states of 3 cores. In the transition relationship between exclusive states, any two exclusive state transitions can be obtained by several cores performing Load or Evict operations, indicating that the ordered graph is strongly connected.

[0091] Figure 5 This is yet another ordered state diagram provided in the embodiments of this application. For example... Figure 5 As shown, Figure 5This can represent the transformation relationship between the globally exclusive state and the globally shared state of the three cores. The globally shared state can be transformed into the globally exclusive state through a single Store operation. The globally exclusive state may not be transformed into the globally shared state through a single operation (non-adjacent in the ordered graph). For example, the Invalid, Invalid, Read-Write (IIT) state cannot be transformed into the Read-Read, Read-Read, Read-Read (BBB) ​​state through a single operation. Some globally exclusive states can be transformed into the globally shared state by adding several additional operations.

[0092] Sub-step 2013: Based on the ordered state diagram, generate a test sequence for the multi-core cache system using a generation algorithm.

[0093] In this embodiment of the application, after generating an ordered state diagram of the state transition relationships of each processor core in a multi-core cache system, the critical paths of the ordered state diagram can be traversed, and the triggering conditions on the paths can be converted into operation instructions to obtain a test sequence.

[0094] This embodiment determines the state transition relationships of each processor core in a multi-core cache system based on the cache coherency protocol. Then, based on these state transition relationships, an ordered state graph representing the state transition relationships of each processor core in the multi-core cache system is generated. This graph visualizes the transition relationships in the form of nodes (states) and directed edges (transitions), allowing for intuitive identification of the system's behavioral paths and ensuring these paths are prioritized for coverage in subsequent tests. Furthermore, based on the ordered state graph, a test sequence for the multi-core cache system is generated using a generation algorithm. This algorithm traverses all paths in the ordered state graph, generating test sequences that cover all state nodes and all transition edges, thereby improving the comprehensiveness and objectivity of test coverage.

[0095] Optionally, the above sub-step 2013 may include sub-steps 20131-20133.

[0096] Sub-step 20131: Determine whether the ordered state diagram of the state transition relationship constitutes an Eulerian circuit.

[0097] In this embodiment, it can be determined whether an ordered state graph with state transition relationships constitutes an Eulerian circuit. An Eulerian circuit is a graph in which all edges are traversed without repetition, starting from a single point. If the starting and ending points of an Eulerian circuit are the same, it is called an Eulerian circuit.

[0098] The necessary and sufficient conditions for the existence of an Eulerian path are as follows: First, the graph must be connected; otherwise, it is impossible to traverse all edges at once. Second, for an undirected graph: there must be exactly two vertices connected by an odd number of edges, while all other vertices are connected by an even number of edges; or all vertices are connected by an even number of edges. For the two odd-numbered vertices, one is the starting point and the other is the ending point. The starting point needs to leave, and the ending point needs to enter, so the odd-numbered vertices are connected by an odd number of edges. If there exists an Eulerian path where all vertices are connected by an even number of edges, then it is an Eulerian circuit. This is because its starting point is also its ending point, and leaving will lead to returning, forming an even number of edges. Third, for a directed graph: excluding the starting and ending points, the out-degree and in-degree of all vertices must be equal. The out-degree of the starting point is one greater than its in-degree, and the in-degree of the ending point is one greater than its out-degree. If the starting and ending points also have the same out-degree and in-degree, then it is an Eulerian circuit.

[0099] Sub-step 20132: When the ordered state diagram of the state transition relationship forms an Eulerian circuit, generate the test sequence of the multi-core cache system according to the ordered state diagram using the Eulerian circuit algorithm.

[0100] In this application embodiment, based on the above embodiments, and referring to Figure 3 , Figure 3 The numbers on the connecting lines of each node represent the order in which all edges are traversed without repetition, starting from one of those points. Since each core in state I or B can perform a Load or Evict operation to transition to state B or I, and each globally shared state has n incoming and outgoing edges, this means that the in-degree and out-degree of each vertex in the ordered graph are equal, both equal to n. Therefore... Figure 3 The ordered state graph shown is strongly connected, and the in-degree and out-degree of each vertex are equal. Figure 3 The ordered state diagram shown forms an Eulerian circuit. It can be determined according to... Figure 3 The test sequence corresponding to the transformation relationship between globally shared states in a multi-core cache system is generated by using the Euler circuit algorithm.

[0101] refer to Figure 4 , Figure 4 The numbers on the connecting lines of each node represent the order in which all edges are traversed without repetition, starting from one of those points. Since each core in state I or T can perform a Store or Evict operation to transition to state T or I, and each globally exclusive state has n incoming and outgoing edges, this means that the in-degree and out-degree of each vertex in the ordered graph are equal, both equal to n. Figure 4 The ordered state graph shown is strongly connected, and the in-degree and out-degree of each vertex are equal. Figure 4 The ordered state diagram shown forms an Eulerian circuit. It can be determined according to... Figure 4 The test sequence corresponding to the transition relationship between global exclusive states in a multi-core cache system is generated by using the Euler circuit algorithm.

[0102] Sub-step 20133: When the ordered state diagram of the state transition relationship does not constitute an Eulerian circuit, generate a test sequence for the multi-core cache system based on the ordered state diagram using the shortest path algorithm.

[0103] In this application embodiment, based on the above embodiments, and referring to Figure 5 The transitions between states can be abstracted into a path problem between vertices. Figure 5 The shortest path between vertices in the ordered state graph shown can be considered as the minimum number of transitions required between states. Since a globally exclusive state may not be able to be transformed into a globally shared state in a single operation (because they are not adjacent in the ordered graph), for example, if the IIT state cannot be transformed into the BBB state in a single operation, the IIT state can be transformed into the IIB state first, and then the IIB state can be transformed into the BBB state to achieve the transformation from the IIT state to the BBB state. Some globally exclusive states can be transformed into globally shared states by adding several additional operations. Figure 5 The ordered state diagram shown does not constitute an Eulerian circuit, but can be determined according to... Figure 5 The test sequence corresponding to the transformation relationship between the global shared state and the global exclusive state in a multi-core cache system is generated by using the shortest path algorithm.

[0104] This embodiment determines whether the ordered state graph of state transition relationships constitutes an Eulerian circuit. When the ordered state graph of state transition relationships constitutes an Eulerian circuit, a test sequence for the multi-core cache system is generated based on the ordered state graph using the Eulerian circuit algorithm. The sequence generated by the Eulerian circuit algorithm traverses every edge of the state graph, i.e., every state transition, ensuring that all transitions are tested. This reduces the possibility of protocol vulnerabilities going undetected due to missed transitions. Furthermore, the number of steps required to traverse all edges using an Eulerian circuit is equal to the number of edges in the ordered graph, eliminating the need to repeatedly execute the same transition, thus shortening the test sequence length and reducing redundant operations and simulation testing time. When the ordered state graph of state transition relationships does not constitute an Eulerian circuit, the non-Eulerian circuit ordered state graph cannot cover all edges through a single path. Therefore, a test sequence for the multi-core cache system can be generated based on the ordered state graph using a shortest path algorithm. The shortest path algorithm can cover all state transitions by repeatedly traversing the fewest edges, further improving the comprehensiveness of test coverage.

[0105] Optionally, the above cache consistency test method may also include step 204.

[0106] Step 204: Based on the structure of the multi-core cache system and the cache coherence protocol, construct a simulation model using the target language.

[0107] In this embodiment, the simulation model may include at least two processor cores and a multi-level cache. The multi-level cache of the simulation model includes a first cache, a second cache, and a third cache. Each processor core has its own first cache, and the caches at each level interact sequentially through a cache coherence protocol. Alternatively, the multi-level cache of the simulation model can be understood as including a Level 1 cache (L1), a Level 2 cache (L2), and a Level 3 cache (L3). The Level 1, Level 2, and Level 3 caches are connected sequentially. The Level 1 cache is a private data cache for each processor core. The target language can be SystemC or a high-level programming language such as Python; no specific limitation is made here.

[0108] Figure 6 This is a schematic diagram of a simulation model architecture provided for an embodiment of this application. Figure 6 As shown, the simulation model can include C0, C1, C2 and C3, namely CPU0, CPU1, CPU2 and CPU3. Each of C0, C1, C2 and C3 has a corresponding L1 cache; C0 and C1 can share a L2 cache, C2 and C3 can share a L2 cache; C0, C1, C2 and C3 can share a L3 cache.

[0109] Based on the structure of the multi-core caching system and the cache consistency protocol, this embodiment constructs a simulation model using a target language, which provides a data foundation for cache consistency testing. At the same time, the simulation model supports parameter configuration and module modification, which can improve the flexibility of cache consistency testing.

[0110] Optionally, step 204 above may include sub-steps 2041-2044.

[0111] Sub-step 2041: Based on the structure of the multi-core caching system and the first protocol, construct the first cache using the target language.

[0112] Sub-step 2042: Based on the structure of the multi-core caching system, the first protocol and the second protocol, construct the second cache using the target language.

[0113] Sub-step 2043: Based on the structure of the multi-core caching system and the second protocol, construct a third cache using the target language.

[0114] Sub-step 2044: Connect the first buffer, the second buffer, and the third buffer through a first-in-first-out queue to obtain the simulation model.

[0115] In this embodiment, for sub-steps 2041-2044, the multi-core caching system (e.g., the Xiangshan Nanhu V5 caching subsystem) can be deconstructed. Based on the structure of the multi-core caching system, SystemC layered modeling is used to construct L1, L2, and L3 models respectively, that is, to construct models for the first-level cache, second-level cache, and third-level cache respectively, or to construct models for the first cache, second cache, and third cache respectively. The models of the first cache, second cache, and third cache are connected through a first-in-first-out (FIFO) queue and exchange data using data packets. The FIFO is the core communication component connecting the L1, L2, and L3 models.

[0116] For example, in the process of building the simulation model above, taking the Tilelink protocol as the first protocol and the CHI protocol as the second protocol, L1 can be modeled and implemented using the Tilelink protocol. Each core L1 is responsible for handling local core requests. When it is necessary to access data that is not in L1, it will use the TileLink protocol to send a request to L2.

[0117] L2 is modeled and implemented using the Tilelink protocol to face the upstream L1 part. L2 uses the TileLink protocol to communicate with all core L1s, receives read and write requests from L1s, and decides whether to respond directly or forward to L3 based on the request type and internal state.

[0118] The portion of L2 that faces downstream L3 is modeled and implemented using the CHI protocol. When L2 cannot fulfill a request from L1, it converts the TileLink request into a corresponding CHI transaction and sends it to L3. Simultaneously, upon receiving a response from L3, L2 also converts it back into TileLink format and returns it to L1.

[0119] The L2 internal cache state is implemented based on the Tilelink protocol, and is converted into CHI-related transactions when sending requests or returning responses downstream. Although the L2 internal state follows the TileLink protocol, when interacting with L3, a conversion process from TileLink to CHI is involved to adapt to different protocol requirements.

[0120] L3Cache uses the CHI protocol to build its model, including simulations of double data rate synchronous dynamic random access memory (DDR). L3 is the last layer in the entire simulation model's cache hierarchy, typically existing as a globally shared resource. It is entirely based on the CHI protocol, handling complex requests from L2 and ensuring data consistency and efficient transfer across multiple processor cores through a snooping mechanism. L3 can manage a wider range of data sharing and, when necessary, communicate with L1 or L2 caches of other cores to resolve privilege occupancy issues.

[0121] This embodiment ensures that the interaction conforms to timing and communication rules by limiting a specific method of constructing the simulation model, enabling the model to accurately reproduce the behavior of a real multi-core cache system, improving the accuracy of the simulation model, and providing a reliable carrier for the verification of subsequent test sequences.

[0122] Optionally, step 203 above may include sub-step 2031.

[0123] Sub-step 2031: Perform a differential comparison between the state checkpoint and the global cache state of the multi-core cache system to obtain the test results.

[0124] In this embodiment, a state checkpoint can be understood as the expected global state obtained through a simulation model before or during the execution of a test sequence, based on the cache consistency protocol and the test objective. The global cache state of a multi-core cache system represents the actual real-time global state generated after the execution of the test sequence. The information it contains completely corresponds to the structure and dimensions of the state checkpoint, serving as an objective record of the actual behavior of the multi-core cache system. Through automated tools or algorithms, the fields, addresses, and states of the state checkpoint and the global cache state can be compared to obtain the test results.

[0125] This embodiment obtains test results by differentially comparing the state checkpoint with the global cache state of the multi-core cache system. Differential comparison can improve test efficiency and the accuracy of locating differences.

[0126] Optionally, the above cache consistency test method may also include steps 205-207.

[0127] Step 205: Based on the test results, determine whether the state checkpoint is consistent with the global cache state of the multi-core cache system.

[0128] In this embodiment of the application, based on the test results (e.g., a list of differences) obtained from the above differential comparison, a preset rule is used to determine whether the state checkpoint and the global cache state of the multi-core cache system are completely matched.

[0129] Step 206: If the state checkpoint is consistent with the global cache state of the multi-core cache system, then the cache consistency test of the multi-core cache system is successful.

[0130] In the embodiments of this application, when the state checkpoint is completely consistent with the global cache state, it means that in the scenario corresponding to the current test sequence, the behavior of the multi-core cache system is completely in line with the expectations of the cache consistency protocol. It can also be understood that no logical errors have occurred from the kernel cache state transition, data synchronization to global permission coordination.

[0131] For example, in the scenario where "CPU0 acquires exclusive access and modifies the data, and then CPU1 reads the address", if the checkpoint expects "CPU0 to be in the T state, CPU1 to be in the I state and triggers a reacquisition when reading", and the global state matches perfectly, then the cache consistency test of the multi-core cache system is determined to be successful.

[0132] Step 207: If the state checkpoint is inconsistent with the global cache state of the multi-core cache system, then the cache consistency test of the multi-core cache system is determined to have failed.

[0133] In the embodiments of this application, when there is a difference, that is, when the state checkpoint is inconsistent with the global cache state of the multi-core cache system, an alarm can be triggered and the context can be recorded, indicating that the system may have violated the cache consistency protocol in the current test scenario. This may be due to a state transition error (e.g., failure to correctly invalidate other core caches), data synchronization omission (e.g., dirty data not being written back), or a defect in the permission arbitration logic (e.g., granting exclusive rights to multiple cores at the same time).

[0134] For example, if the state checkpoint requires that "after CPU0 obtains the T state, the cache of CPU1 at the same address must be in the I state", but in the actual global state, CPU1 is still in the B state, then the check fails, indicating that the cache consistency test of the multi-core cache system has failed.

[0135] This embodiment determines whether the state checkpoint is consistent with the global cache state of the multi-core cache system based on the test results. If they are consistent, the test is considered successful; otherwise, the test is considered a failure. This improves the objectivity of the test result judgment and provides a reliable basis for repairing defects in the multi-core cache system.

[0136] In summary, this embodiment of the application obtains a test sequence for a multi-core cache system, specifying that the multi-core cache system includes at least two processor cores and a multi-level cache. The test sequence includes operation instructions for each processor core, which can realistically simulate the concurrent behavior of multiple cores accessing shared or private memory regions simultaneously in a multi-core system, improving the comprehensiveness of coverage of multi-core interaction scenarios. The obtained test sequence can be input into a simulation model. According to the cache coherence protocol, the test sequence is processed sequentially through the multi-level cache of the simulation model, and a state checkpoint of the multi-core cache system is output. This state checkpoint can record the complete state information of all processor cores and cache lines in their respective levels at a specific moment, covering extreme consistency scenarios that are difficult to reproduce with physical hardware, reflecting the state dependencies between multi-cores caused by protocol interactions, forming a globally consistent time profile, and providing a reliable basis for subsequent consistency testing. Finally, the cache coherence of the multi-core cache system is tested based on the state checkpoint, and the test results are obtained. Consistency testing based on the state checkpoint can determine whether all cache copies meet the requirements of the cache coherence protocol from the perspective of the entire system, reducing misjudgments caused by local observations, thereby improving the reliability and comprehensiveness of the test.

[0137] This application also provides a cache consistency testing apparatus. Figure 7 This is a block diagram of a cache consistency testing apparatus provided in an embodiment of this application. Figure 7 As shown, the device 700 may include: an acquisition module 701, a processing module 702, and a testing module 703.

[0138] The acquisition module 701 is used to acquire the test sequence of a multi-core cache system; the multi-core cache system includes at least two processor cores and a multi-level cache; the test sequence includes operation instructions for each processor core.

[0139] The processing module 702 is used to input the test sequence into the simulation model, process the test sequence sequentially through the multi-level cache of the simulation model according to the cache coherence protocol, and output the status checkpoint of the multi-core cache system; the status checkpoint is used to characterize the current cache status of each processor core in the multi-core cache system.

[0140] Test module 703 is used to test the cache consistency of a multi-core cache system based on state checkpoints and obtain test results.

[0141] Optionally, the cache coherence protocol includes a first protocol and a second protocol. The multi-level cache of the simulation model includes a first cache, a second cache, and a third cache. The processing module 702 is specifically used to input the test sequence into the simulation model, convert the test sequence into a first request through the first cache according to the first protocol, the format of the first request matches the format supported by the first protocol, process the first request sequentially through the second cache and the third cache to obtain response information, and send the response information to the first cache, update the cache state of the processor core corresponding to the first cache according to the response information, and output the status checkpoint of the multi-core cache system.

[0142] Optionally, the processing module 702 is specifically used to determine whether the data corresponding to the first request exists in the second cache; if it exists, a response message is generated through the second cache of the simulation model and sent to the first cache; if it does not exist, the first request is converted into a second request through the second cache according to the second protocol; the format of the second request matches the format supported by the second protocol; the second request is processed through the third cache to obtain the response message and sent to the first cache.

[0143] Optionally, the acquisition module 701 is specifically used to determine the state transition relationship of each processor core in the multi-core cache system according to the cache coherence protocol; generate an ordered state diagram of the state transition relationship of each processor core in the multi-core cache system according to the state transition relationship; and generate a test sequence of the multi-core cache system according to the ordered state diagram through a generation algorithm.

[0144] Optionally, the state transition relationships of each processor core in a multi-core cache system include: the transition relationship between shared states, the transition relationship between exclusive states, and the transition relationship between shared and exclusive states; the shared state indicates that all processor cores in the multi-core cache system are in an invalid or readable state; the exclusive state indicates that only one processor core in the multi-core cache system is in a readable and writable state, and the remaining processor cores are in an invalid state.

[0145] Optionally, the acquisition module 701 is specifically used to determine whether the ordered state diagram of the state transition relationship constitutes an Eulerian circuit; when the ordered state diagram of the state transition relationship constitutes an Eulerian circuit, a test sequence of the multi-core cache system is generated according to the ordered state diagram using the Eulerian circuit algorithm; when the ordered state diagram of the state transition relationship does not constitute an Eulerian circuit, a test sequence of the multi-core cache system is generated according to the ordered state diagram using the shortest path algorithm.

[0146] Optionally, such as Figure 7As shown, the device 700 may further include a construction module 704. The construction module 704 is used to construct a simulation model using a target language based on the structure of the multi-core cache system and the cache coherence protocol. The simulation model includes at least two processor cores and a multi-level cache. The multi-level cache of the simulation model includes a first cache, a second cache, and a third cache. Each processor core has its own first cache, and the caches at each level interact sequentially through the cache coherence protocol.

[0147] Optionally, the construction module 704 is specifically used to construct a first cache using a target language based on the structure of the multi-core cache system and the first protocol; construct a second cache using a target language based on the structure of the multi-core cache system, the first protocol, and the second protocol; construct a third cache using a target language based on the structure of the multi-core cache system and the second protocol; and connect the first cache, the second cache, and the third cache using a first-in-first-out queue to obtain a simulation model.

[0148] Optionally, the test module 703 is specifically used to perform differential comparison between the state checkpoint and the global cache state of the multi-core cache system to obtain the test results.

[0149] Optionally, such as Figure 7 As shown, the device 700 may further include a judgment module 705 and a determination module 706.

[0150] The judgment module 705 is used to determine whether the state checkpoint is consistent with the global cache state of the multi-core cache system based on the test results; the determination module 706 is used to determine that the cache consistency test of the multi-core cache system is successful if the state checkpoint is consistent with the global cache state of the multi-core cache system; the determination module 706 is also used to determine that the cache consistency test of the multi-core cache system fails if the state checkpoint is inconsistent with the global cache state of the multi-core cache system.

[0151] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0152] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0153] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0154] This application also provides a cache consistency testing apparatus, including a memory and one or more programs, wherein one or more programs are stored in the memory and configured to be executed by one or more processors, and the one or more programs include methods for performing the methods described in one or more of the above embodiments.

[0155] This application also provides an electronic device. See [link to relevant documentation]. Figure 8 , Figure 8 This is a block diagram illustrating an electronic device 800 according to an exemplary embodiment. For example, the electronic device 800 may be a mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.

[0156] Reference Figure 8 The electronic device 800 may include one or more of the following components: a processing component 802, a memory 804, a power supply component 806, a multimedia component 808, an audio component 810, an input / output (I / O) interface 812, a sensor component 814, and a communication component 816.

[0157] Processing component 802 typically controls the overall operation of electronic device 800, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 802 may include one or more processors 820 to execute instructions to complete all or part of the steps of the methods described above. Furthermore, processing component 802 may include one or more modules to facilitate interaction between processing component 802 and other components. For example, processing component 802 may include a multimedia module to facilitate interaction between multimedia component 808 and processing component 802.

[0158] Memory 804 is used to store various types of data to support the operation of electronic device 800. Examples of this data include instructions for any application or method operating on electronic device 800, contact data, phonebook data, messages, pictures, multimedia, etc. Memory 804 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0159] Power supply component 806 provides power to various components of electronic device 800. Power supply component 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 800.

[0160] Multimedia component 808 includes a screen that provides an output interface between the electronic device 800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may not only sense the boundaries of touch or swipe actions but also detect the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 808 includes a front-facing camera and / or a rear-facing camera. When the electronic device 800 is in an operating mode, such as a shooting mode or a multimedia mode, the front-facing camera and / or the rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0161] Audio component 810 is used to output and / or input audio signals. For example, audio component 810 includes a microphone (MIC) used to receive external audio signals when electronic device 800 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 804 or transmitted via communication component 816. In some embodiments, audio component 810 also includes a speaker for outputting audio signals.

[0162] I / O interface 812 provides an interface between processing component 802 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0163] Sensor assembly 814 includes one or more sensors for providing state assessments of various aspects of electronic device 800. For example, sensor assembly 814 can detect the on / off state of electronic device 800, the relative positioning of components such as the display and keypad of electronic device 800, changes in position of electronic device 800 or a component of electronic device 800, the presence or absence of user contact with electronic device 800, orientation or acceleration / deceleration of electronic device 800, and temperature changes of electronic device 800. Sensor assembly 814 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 814 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 814 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0164] Communication component 816 facilitates wired or wireless communication between electronic device 800 and other devices. Electronic device 800 can access wireless networks based on communication standards, such as WiFi, carrier networks (such as 2G, 3G, 4G, or 5G), or combinations thereof. In one exemplary embodiment, communication component 816 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 816 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0165] In an exemplary embodiment, the electronic device 800 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to implement the methods provided in the embodiments of this application.

[0166] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 804 including instructions, which can be executed by a processor 820 of an electronic device 800 to perform the above-described method. For example, the non-transitory storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0167] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the methods described in the above embodiments.

[0168] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0169] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A cache coherency test method characterized by, The method comprises: obtaining a test sequence of a multi-core cache system, comprising: determining state transition relationships of processor cores in the multi-core cache system according to a cache coherence protocol; generating an ordered state graph of the state transition relationships of the processor cores in the multi-core cache system according to the state transition relationships; and generating a test sequence of the multi-core cache system by a generation algorithm according to the ordered state graph; the multi-core cache system comprises at least two processor cores and multiple levels of caches; and the test sequence comprises operation instructions for each of the processor cores; inputting the test sequence into a simulation model, processing the test sequence by multiple levels of caches of the simulation model in sequence according to a cache coherence protocol, and outputting a state checkpoint of the multi-core cache system, comprising: the cache coherence protocol comprises a first protocol and a second protocol, and the multiple levels of caches of the simulation model comprise a first cache, a second cache and a third cache; inputting the test sequence into the simulation model, converting the test sequence into a first request by the first cache according to the first protocol; the format of the first request matches a format supported by the first protocol; processing the first request by the second cache and the third cache in sequence, obtaining response information, and sending the response information to the first cache; updating a cache state of the processor core corresponding to the first cache according to the response information, and outputting the state checkpoint of the multi-core cache system; the state checkpoint is used to represent current cache states of the processor cores in the multi-core cache system; testing cache coherence of the multi-core cache system according to the state checkpoint, and obtaining a test result.

2. The method of claim 1, wherein, the processing of the first request by the second cache and the third cache in sequence, the obtaining of the response information, and the sending of the response information to the first cache, comprising: determining whether the second cache has data corresponding to the first request; if yes, generating the response information by the second cache of the simulation model, and sending the response information to the first cache; if no, converting the first request into a second request by the second cache according to the second protocol; the format of the second request matches a format supported by the second protocol; processing the second request by the third cache, obtaining response information, and sending the response information to the first cache.

3. The method of claim 1, wherein, the state transition relationships of the processor cores in the multi-core cache system comprise: conversion relationships between shared states, conversion relationships between exclusive states, and conversion relationships between the shared states and the exclusive states; the shared state indicates that all processor cores in the multi-core cache system are in an invalid state or a readable state; the exclusive state indicates that only one processor core in the multi-core cache system is in a readable and writable state, and the remaining processor cores are in an invalid state.

4. The method of claim 1, wherein, the generation of the test sequence of the multi-core cache system according to the ordered state graph by the generation algorithm, comprising: determining whether the ordered state graph of the state transition relationships constitutes an Euler circuit. When the ordered state graph of the state transition relationship constitutes an Euler circuit, a test sequence of the multi-core cache system is generated by an Euler circuit algorithm according to the ordered state graph; When the ordered state graph of the state transition relationship does not constitute an Euler circuit, a test sequence of the multi-core cache system is generated by a shortest path algorithm according to the ordered state graph.

5. The method of claim 1, wherein, The method further comprises: According to the structure of the multi-core cache system and the cache coherency protocol, the simulation model is constructed by a target language; the simulation model comprises at least two processor cores and multi-level caches, and the multi-level caches of the simulation model comprise a first cache, a second cache and a third cache, each of the processor cores corresponds to a first cache, and each level of cache interacts with each other through a cache coherency protocol.

6. The method of claim 5, wherein, According to the structure of the multi-core cache system and the cache coherency protocol, the simulation model is constructed by a target language, comprising: According to the structure of the multi-core cache system and the first protocol, the first cache is constructed by the target language; According to the structure of the multi-core cache system, the first protocol and the second protocol, the second cache is constructed by the target language; According to the structure of the multi-core cache system and the second protocol, the third cache is constructed by the target language; The first cache, the second cache and the third cache are connected by a first-in-first-out queue to obtain the simulation model.

7. The method of claim 1, wherein, According to the state checkpoint, the cache coherency of the multi-core cache system is tested to obtain a test result, comprising: The state checkpoint is compared with the global cache state of the multi-core cache system to obtain the test result.

8. The method of claim 7, wherein, The method further comprises: According to the test result, it is determined whether the state checkpoint is consistent with the global cache state of the multi-core cache system; If the state checkpoint is consistent with the global cache state of the multi-core cache system, it is determined that the cache coherency test of the multi-core cache system is successful; If the state checkpoint is not consistent with the global cache state of the multi-core cache system, it is determined that the cache coherency test of the multi-core cache system fails.

9. A cache coherency test apparatus characterized by, The device comprises: An acquisition module is configured to acquire a test sequence of a multi-core cache system, comprising: determining a state transition relationship of each processor core in the multi-core cache system according to a cache coherency protocol; generating an ordered state graph of the state transition relationship of each processor core in the multi-core cache system according to the state transition relationship; and generating a test sequence of the multi-core cache system by an algorithm according to the ordered state graph; the multi-core cache system comprises at least two processor cores and multi-level caches; and the test sequence comprises operation instructions for each processor core. The processing module is configured to input the test sequence into a simulation model, sequentially process the test sequence through a multi-level cache of the simulation model according to a cache coherency protocol, and output a state checkpoint of the multi-core cache system, including: the cache coherency protocol includes a first protocol and a second protocol, and the multi-level cache of the simulation model includes a first cache, a second cache and a third cache; the test sequence is input into the simulation model, and the test sequence is converted into a first request through the first cache according to the first protocol; the format of the first request matches the format supported by the first protocol; the first request is sequentially processed through the second cache and the third cache to obtain response information, and the response information is sent to the first cache; the cache state of the processor core corresponding to the first cache is updated according to the response information, and the state checkpoint of the multi-core cache system is output; the state checkpoint is used to represent the current cache state of each processor core in the multi-core cache system; The test module is configured to test the cache coherency of the multi-core cache system according to the state checkpoint, and obtain a test result.

10. An electronic device, comprising: It includes: a processor; a memory for storing instructions executable by the processor; wherein the processor is configured to execute the instructions to implement the method of any one of claims 1-8.

11. A computer readable storage medium, characterized in that, When the instructions in the computer-readable storage medium are executed by the processor of the electronic device, the electronic device can perform the method of any one of claims 1-8.

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