A packaging structure and a packaging method of a power semiconductor

Abstract

The application relates to a packaging structure and a packaging method of a power semiconductor, which comprise a substrate, a driving chip, a first power chip, a second power chip, a low-thermal-conductivity plastic packaging layer and a high-thermal-conductivity plastic packaging layer; a plurality of welding points and wires are arranged on the substrate, the wires on the substrate are electrically connected with the welding points and form a driving circuit; the driving chip, the first power chip and the second power chip are respectively mounted on different welding points on the substrate and are electrically connected with the wires on the substrate; the driving chip is completely covered by the low-thermal-conductivity plastic packaging layer; the low-thermal-conductivity plastic packaging layer, the first power chip and the second power chip are completely covered by the high-thermal-conductivity plastic packaging layer. The driving chip is packaged by the low-thermal-conductivity plastic packaging layer and the low-thermal-conductivity plastic packaging layer outside the power chip and the driving chip is packaged by the high-thermal-conductivity plastic packaging layer, so that the efficiency of heat transfer from the power chip to the driving chip is reduced, and the difference between the thermal expansion coefficients of the low-thermal-conductivity plastic packaging layer and the driving chip is smaller, thereby preventing the substrate of the driving chip from being broken.

Description

Technical Field

[0001] This invention relates to the field of chip packaging, and in particular to a packaging structure and packaging method for power semiconductors. Background Technology

[0002] With the development of third-generation GaN and SiC semiconductor devices, high frequency, high density, and high efficiency have become industry trends. To reduce interference, when manufacturing third-generation semiconductors that require high-frequency applications, it is usually necessary to combine the driver chip and two power device chips into a half-bridge circuit and then package them together.

[0003] Please see Figure 1 This diagram illustrates the structure of a conventional half-bridge power semiconductor, including a substrate A, a first power chip B, a second power chip C, a driver chip D, and a filling layer E. The first power chip B, second power chip C, and driver chip D are mounted on mounting areas of substrate A and electrically connected to the substrate via electrical contacts. The driver chip D is electrically connected to both the first power chip B and the second power chip C. The filling layer E fills the gaps between the first power chip B, second power chip C, driver chip D, and substrate A to achieve thermal conduction and electrical isolation between the first power chip B, second power chip C, and driver chip D, and to dissipate heat from the first power chip B and second power chip C. However, this existing structural design is prone to overheating and damage to the power semiconductor during prolonged high-load operation. Summary of the Invention

[0004] Therefore, the purpose of this invention is to overcome the defects or deficiencies of the prior art and provide a packaging structure and packaging method for power semiconductors.

[0005] A power semiconductor packaging structure includes a substrate, a driver chip, a first power chip, a second power chip, a low thermal conductivity molding compound, and a high thermal conductivity molding compound. The substrate has a plurality of solder joints and traces, and the traces on the substrate electrically connect the solder joints to form a driver circuit. The driver chip, the first power chip, and the second power chip are respectively mounted on different solder joints on the substrate and electrically connected to the traces on the substrate. The driver chip is completely encapsulated by the low thermal conductivity molding compound. The low thermal conductivity molding compound, the first power chip, and the second power chip are completely encapsulated by the high thermal conductivity molding compound.

[0006] The driver chip is encapsulated using a low thermal conductivity molding compound, and then the power chip and the surrounding low thermal conductivity molding compound are encapsulated using a high thermal conductivity molding compound. This reduces the heat transfer efficiency from the power chip to the driver chip without affecting the heat dissipation effect of the power chip through the high thermal conductivity molding compound, and prevents the Si substrate of the driver chip from cracking.

[0007] Furthermore, the difference in the coefficient of thermal expansion between the low thermal conductivity molding compound layer and the substrate of the driver chip is less than 6 × 10⁻⁶. -6 / ℃.

[0008] Furthermore, the distance between the driver chip and the first power chip or the second power chip is between 200μm and 2000μm. If the distance between the driver chip and the first power chip or the second power chip is less than 200μm, the heat generated by the power chip is more easily conducted to the driver chip, which can easily cause the substrate of the driver chip to crack due to stress. If the distance between the driver chip and the first power chip or the second power chip is greater than 3000μm, it will result in the driver leads of the package structure being too long, leading to excessively large parasitic inductance on them.

[0009] Furthermore, it also includes a buffer layer disposed on the top of the first power chip and the second power chip away from the substrate. The buffer layer has a thermal conductivity greater than 1 W / m·K, an elastic modulus less than 1 GPa, and its coefficient of thermal expansion differs from that of the first power chip and the second power chip by less than 8 × 10⁻⁶. -6 / ℃. The buffer layer alleviates the mechanical stress caused by the difference in thermal expansion coefficients during the packaging process, reduces stress concentration between the first power chip, the second power chip, and the heat sink, prevents the first power chip and the second power chip from cracking or solder joint failure, and assists in heat transfer between the first power chip and the second power chip.

[0010] Furthermore, it also includes a heat dissipation copper sheet, which is disposed on the buffer layer and penetrates the high thermal conductivity molding compound. The high thermal conductivity molding compound partially covers the heat dissipation copper sheet, leaving one side of the copper sheet in contact with the outside. The heat dissipation copper sheet is used to provide an efficient heat dissipation path for the first power chip and the second power chip, thereby improving their heat dissipation effect.

[0011] Furthermore, it also includes a transition molding layer disposed between the low thermal conductivity molding layer and the high thermal conductivity molding layer, which completely isolates the low thermal conductivity molding layer and the high thermal conductivity molding layer.

[0012] Furthermore, the coefficient of thermal expansion of the transition molding layer is between that of the low thermal conductivity molding layer and the high thermal conductivity molding layer.

[0013] The transition molding layer is used to provide a certain thermal expansion buffer between the low thermal conductivity molding layer and the high thermal conductivity molding layer, so as to prevent stress concentration and cracking at the junction of the low thermal conductivity molding layer and the high thermal conductivity molding layer when heated.

[0014] A method for packaging a power semiconductor includes the following steps:

[0015] S1: The driver chip is first packaged using a low thermal conductivity plastic sealant layer to form a uniformly thick low thermal conductivity plastic sealant layer that completely wraps the driver chip, resulting in the driver chip after the first packaging.

[0016] S2: Install the first packaged driver chip onto the solder joints of the substrate and electrically connect it to the substrate.

[0017] S3: The first power chip and the second power chip are mounted on the solder joints of the substrate and electrically connected to the substrate to obtain a half-bridge circuit of power semiconductors.

[0018] S4: The half-bridge circuit of the power semiconductor is packaged by a high thermal conductivity plastic sealant layer, which fills the area around the low thermal conductivity plastic sealant layer, the first power chip, and the second power chip and fills the gap between the first power chip, the second power chip and the substrate. The high thermal conductivity plastic sealant layer completely covers the low thermal conductivity plastic sealant layer, the first power chip and the second power chip.

[0019] Preferably, steps SA and SB are further included between steps S3 and S4:

[0020] SA: A buffer layer is coated on the side of the first power chip and the second power chip away from the substrate;

[0021] SB: A heat dissipation copper sheet is fixed above the buffer layer to obtain the main structure of the power semiconductor;

[0022] Step S3 is as follows: The main structure of the power semiconductor is encapsulated by a high thermal conductivity molding compound, which fills the low thermal conductivity molding compound, the first power chip, the second power chip, the buffer layer and the heat dissipation copper sheet and fills the gap between the first power chip, the second power chip and the substrate. The high thermal conductivity molding compound completely covers the low thermal conductivity molding compound, the first power chip, the second power chip and the buffer layer, and partially covers the heat dissipation copper sheet so that one side of the heat dissipation copper sheet is in contact with the outside.

[0023] Preferably, step Sα is further included between steps S2 and S3:

[0024] Sα: Encapsulate a transition molding layer on the low thermal conductivity molding layer;

[0025] Step S4 is as follows: The main structure of the power semiconductor is encapsulated by a high thermal conductivity molding compound, which fills the area around the first power chip, the second power chip, the buffer layer, the heat sink copper sheet, and the transition molding compound, and fills the gap between the first power chip, the second power chip, and the substrate; the high thermal conductivity molding compound completely covers the first power chip, the second power chip, and the buffer layer, and is isolated from the low thermal conductivity molding compound by the transition molding compound, and partially covers the heat sink copper sheet so that one side of the heat sink copper sheet is in contact with the outside.

[0026] To better understand and implement this invention, the following detailed description is provided in conjunction with the accompanying drawings. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the structure of a half-bridge power semiconductor in the prior art;

[0028] Figure 2 This is a schematic diagram of a power semiconductor packaging structure according to the present invention;

[0029] Figure 3 This is a schematic diagram of a preferred power semiconductor packaging structure according to the present invention;

[0030] Figure 4 This is a flowchart of a power semiconductor packaging method according to the present invention;

[0031] Figure 5 This is a flowchart of a preferred power semiconductor packaging method according to the present invention. Detailed Implementation

[0032] To address the problem of power semiconductors being damaged by overheating under prolonged high-load operation in existing technologies, this invention first attempts to improve the heat dissipation efficiency of power semiconductors by increasing the thermal conductivity of the filler layer and designing a copper sheet for heat dissipation. The results show that although the heat dissipation efficiency is improved, damage still occurs under prolonged high-load use.

[0033] Therefore, this invention disassembles and analyzes the structure of existing power semiconductors, discovering that the cause of damage after prolonged high-load use is the cracking of the substrate of the driver chip. For the driver chip, which is typically a Si substrate device, the linear coefficient of thermal expansion is approximately 2.3 × 10⁻⁶. -6 / ℃-2.6×10 -6 / ℃, while the thermally conductive molding compound (thermal conductivity 4-5W / m) encapsulated on power chips and driver chips The coefficient of thermal expansion of K) reaches 10 × 10 -6 / ℃-12×10 -6 / ℃. The difference in thermal expansion coefficients between the Si substrate of the driver chip and the thermally conductive molding compound reaches 7×10⁻⁶. -6 / ℃-10×10 -6 The temperature of / ℃ causes excessive stress on the Si substrate of the driver chip when the heat generated by the power chip is transferred to the Si substrate of the driver chip and the surrounding thermally conductive molding compound, resulting in the Si substrate of the driver chip cracking.

[0034] Therefore, to prevent the Si substrate of the driver chip from cracking, the above situation can be addressed through two approaches:

[0035] 1) Reduce the coefficient of thermal expansion of the thermally conductive molding compound to decrease the difference in the coefficient of thermal expansion between the Si substrate of the driver chip and the surrounding thermally conductive molding compound. However, reducing only the overall coefficient of thermal expansion of the thermally conductive molding compound is not feasible in industrial practice because there are currently no mass-produced materials with high thermal conductivity, low coefficient of thermal expansion, and suitable for semiconductor molding.

[0036] 2) Reducing the thermal conductivity from the power chip to the driver chip prevents heat from being transferred too quickly to the Si substrate of the driver chip and the surrounding thermally conductive molding compound, thus minimizing thermal expansion. However, directly reducing the thermal conductivity of the molding compound would make it difficult for the enormous heat generated by the power chip to be conducted to the outside, resulting in significant heat accumulation in the power chip and potential damage. On the other hand, increasing the distance between the power chip and the driver chip to reduce thermal conductivity would result in a very large power semiconductor. To meet market demands, the package size of power semiconductors needs to be sufficiently small; therefore, increasing the distance between the driver chip and the power chip on the substrate cannot reduce the heat conducted from the power chip to the driver chip.

[0037] Therefore, this invention designs a packaging structure and method for power semiconductors. It encapsulates the driver chip using a low thermal conductivity molding compound, and then encapsulates both the power chip and the low thermal conductivity molding compound outside the driver chip using a high thermal conductivity molding compound. This reduces the heat transfer efficiency from the power chip to the driver chip, minimizes the difference in thermal expansion coefficients between the low thermal conductivity molding compound and the Si substrate of the driver chip, and does not affect the heat dissipation effect of the power chip through the high thermal conductivity molding compound, thus preventing the Si substrate of the driver chip from cracking during prolonged high-load use.

[0038] Specifically, please refer to Figure 2 The power semiconductor packaging structure of the present invention includes: a substrate 10, a driver chip 20, a first power chip 30, a second power chip 40, a low thermal conductivity molding compound 50, and a high thermal conductivity molding compound 60.

[0039] The substrate 10 is provided with a plurality of solder joints 12 and traces. The traces on the substrate 10 electrically connect the plurality of solder joints 12 to form a driving circuit.

[0040] The driver chip 20 has a Si substrate, and the coefficient of thermal expansion of the Si substrate is 2.3 × 10⁻⁶. -6 / ℃-2.6×10 -6 / ℃.

[0041] The driver chip 20, the first power chip 30, and the second power chip 40 are respectively mounted on several different solder points 12 on the substrate 10 and electrically connected to the traces of the substrate 10. The driver chip 20 is electrically connected to the first power chip 30 and the second power chip 40 through the traces of the substrate 10 and can establish communication.

[0042] Preferably, the distance between the driver chip 20 and the first power chip 30 or the second power chip 40 is between 200μm and 2000μm. If the distance between the driver chip and the first or second power chip is less than 200μm, the heat generated by the power chip is more easily conducted to the driver chip, which can easily cause the substrate of the driver chip to crack due to stress. If the distance between the driver chip and the first or second power chip is greater than 3000μm, it will result in the driver leads of the package structure being too long, leading to excessively large parasitic inductance on them.

[0043] The thermal conductivity of the low thermal conductivity molding compound 50 is less than 1 W / m. K, the coefficient of thermal expansion is not greater than 8×10 -6 / ℃, the difference in the coefficient of thermal expansion between the low thermal conductivity molding layer 50 and the Si substrate of the driver chip 20 is less than 6×10. -6 / ℃. In this embodiment, the low thermal conductivity molding layer 50 is an epoxy resin-based molding compound with a thermal conductivity of 0.96 W / m. K, the coefficient of thermal expansion is 8×10 -6 / ℃; it fills the area around the driver chip 20 and fills the gap between the driver chip 20 and the substrate 10 to form a first encapsulation of the driver chip 20, forming a low thermal conductivity plastic sealant 50 with uniform thickness, so that the driver chip 20 is completely covered by the low thermal conductivity plastic sealant 50.

[0044] The thermal conductivity of the high thermal conductivity sealing layer 60 is 4-5 W / m. K, whose coefficient of thermal expansion is no greater than 12 × 10⁻⁶. -6 / ℃. In this embodiment, the high thermal conductivity sealing layer 60 is a highly filled epoxy resin with added aluminum oxide (Al2O3). 3， Its thermal conductivity is 5 W / m K, coefficient of thermal expansion 12×10-6 / ℃; it fills the space around the low thermal conductivity molding compound 50, the first power chip 30, and the second power chip 40, and fills the gaps between the first power chip 30, the second power chip 40, and the substrate 10, to complete the encapsulation of the first power chip 30 and the second power chip 40, and to complete the second encapsulation of the driver chip 20, forming a high thermal conductivity molding compound 60 with uniform thickness, ensuring that the first power chip 30, the second power chip 40, and the low thermal conductivity molding compound 50 are completely wrapped by the high thermal conductivity molding compound 60. In this embodiment, the thickness of the high thermal conductivity molding compound 60 is 0.65mm-1.3mm.

[0045] The buffer layer 70 has a thermal conductivity greater than 1 W / m·K, an elastic modulus less than 1 GPa, a thickness of 50-150 μm, and its coefficient of thermal expansion is less than 8 × 10⁻⁶ compared to that of the first power chip 30 and the second power chip 40. -6 / ℃. In this embodiment, the buffer layer 70 is an organosilicon elastomer with an elastic modulus of less than 0.5 GPa, which can effectively alleviate mechanical stress caused by differences in thermal expansion coefficients; and alumina is added therein as a thermally conductive filler to achieve a thermal conductivity of 1-3 W / m. K; and by adding inorganic fillers, the difference between its coefficient of thermal expansion and that of the first power chip 30 and the second power chip 40 is adjusted to be less than 8 × 10. -6 / ℃.

[0046] The buffer layers 70 are respectively disposed on the top of the first power chip 30 and the second power chip 40 away from the substrate 10. The buffer layers 70 alleviate the mechanical stress caused by the difference in thermal expansion coefficients during the packaging process, reduce stress concentration between the first power chip 30, the second power chip 40 and the heat sink 80, prevent the first power chip 30 and the second power chip 40 from cracking or solder joint failure, and assist the first power chip 30 and the second power chip 40 in transferring heat to the heat sink 80.

[0047] The heat dissipation copper fin 80 is disposed on the buffer layer 70 and penetrates the high thermal conductivity molding compound 60. At this time, the high thermal conductivity molding compound 60 fills the area around the low thermal conductivity molding compound 50, the first power chip 30, the second power chip 40, the buffer layer 70, and the heat dissipation copper fin 80, and fills the gaps between the first power chip 30, the second power chip 40, and the substrate 10. The low thermal conductivity molding compound 50, the first power chip 30, the second power chip 40, and the buffer layer 70 are completely covered by the high thermal conductivity molding compound 60, which partially covers the heat dissipation copper fin 80, allowing one side of the heat dissipation copper fin 80 to contact the outside. The heat dissipation copper fin 80 further provides an efficient heat dissipation path for the first power chip 30 and the second power chip 40, improving their heat dissipation effect.

[0048] For preferred options, please refer to [link / reference]. Figure 3 The system also includes a transition molding layer 90, the coefficient of thermal expansion of which is between that of the low thermal conductivity molding layer 50 and the high thermal conductivity molding layer 60. In this embodiment, the transition molding layer 90 is an epoxy resin filled with silica, and its coefficient of thermal expansion is controlled to be between that of the low thermal conductivity molding layer 50 and the high thermal conductivity molding layer 60 by adjusting the proportion of silica therein. The transition molding layer 90 is disposed between the low thermal conductivity molding layer 50 and the high thermal conductivity molding layer 60 and completely isolates the low thermal conductivity molding layer 50 and the high thermal conductivity molding layer 60. The transition molding layer 90 is used to provide a certain thermal expansion buffer between the low thermal conductivity molding layer 50 and the high thermal conductivity molding layer 60, preventing stress concentration and cracking at the interface between the low thermal conductivity molding layer 50 and the high thermal conductivity molding layer 60 when heated.

[0049] A method for packaging a power semiconductor, comprising the following steps:

[0050] S1: The driver chip is first packaged using a low thermal conductivity plastic sealant layer to form a uniformly thick low thermal conductivity plastic sealant layer that completely encapsulates the driver chip, resulting in the driver chip after the first packaging.

[0051] S2: Install the first packaged driver chip onto the solder joints of the substrate and electrically connect it to the substrate.

[0052] S3: The first power chip and the second power chip are mounted onto the solder joints of the substrate and electrically connected to the substrate to obtain a half-bridge circuit of power semiconductors. The distance between the driving chip and the first power chip or the second power chip is between 200μm and 2000μm.

[0053] S4: A high thermal conductivity molding compound is used to encapsulate the half-bridge circuit of the power semiconductor. This high thermal conductivity molding compound fills the area around the low thermal conductivity molding compound, the first power chip, and the second power chip, and also fills the gaps between the first power chip, the second power chip, and the substrate. The high thermal conductivity molding compound completely covers the low thermal conductivity molding compound, the first power chip, and the second power chip. This completes the encapsulation of the first and second power chips, and a second encapsulation of the driver chip, forming a high thermal conductivity molding compound with uniform thickness.

[0054] For preferred options, please refer to [link / reference]. Figure 4 The steps S3 and S4 are further divided into steps SA and SB:

[0055] SA: A buffer layer is coated on the side of the first power chip and the second power chip away from the substrate. The buffer layer has a thermal conductivity greater than 1 W / m·K, an elastic modulus less than 1 GPa, a thickness of 50-150 μm, and its coefficient of thermal expansion is less than 8 × 10⁻⁶ compared with the coefficients of thermal expansion of the first power chip and the second power chip. -6 / ℃.

[0056] SB: A heat dissipation copper sheet is fixed above the buffer layer to obtain the main structure of the power semiconductor. This provides an efficient heat dissipation path for the first power chip and the second power chip, improving their heat dissipation effect.

[0057] Step S4 involves encapsulating the main structure of the power semiconductor using a high thermal conductivity molding compound. This compound fills the space around the low thermal conductivity molding compound, the first power chip, the second power chip, the buffer layer, and the heat sink copper sheet, filling the gaps between the first and second power chips and the substrate. The high thermal conductivity molding compound completely covers the low thermal conductivity molding compound, the first power chip, the second power chip, and the buffer layer, and partially covers the heat sink copper sheet so that one side of the heat sink copper sheet is in contact with the outside. This completes the encapsulation of the first and second power chips, and a second encapsulation of the driver chip, forming a high thermal conductivity molding compound with uniform thickness.

[0058] Preferably, in another embodiment, please refer to Figure 5 The step Sα is further included between steps S2 and S3:

[0059] Sα: A transition molding layer is encapsulated on the low thermal conductivity molding layer.

[0060] Step S4 involves encapsulating the main structure of the power semiconductor using a high thermal conductivity molding compound. This compound fills the space around the first power chip, the second power chip, the buffer layer, the heat sink copper sheet, and the transition molding compound, filling the gaps between the first and second power chips and the substrate. The high thermal conductivity molding compound completely covers the first power chip, the second power chip, and the buffer layer. It is isolated from the low thermal conductivity molding compound by the transition molding compound and partially covers the heat sink copper sheet, ensuring one side of the heat sink copper sheet is in contact with the outside. This completes the encapsulation of the first and second power chips and the second encapsulation of the driver chip, forming a high thermal conductivity molding compound with uniform thickness.

[0061] The embodiments described above are merely examples of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and the present invention also intends to include these modifications and variations.

Claims

1. A packaging structure of a power semiconductor, characterized by: The application relates to a power semiconductor half-bridge circuit, which comprises a substrate, a driving chip, a first power chip, a second power chip, a low-thermal-conductivity plastic encapsulation layer and a high-thermal-conductivity plastic encapsulation layer; a plurality of welding spots and wires are arranged on the substrate, the wires on the substrate are electrically connected with the welding spots and form a driving circuit; the driving chip, the first power chip and the second power chip are respectively arranged on different welding spots on the substrate and are electrically connected with the wires on the substrate; the driving chip is completely covered by the low-thermal-conductivity plastic encapsulation layer; the low-thermal-conductivity plastic encapsulation layer, the first power chip and the second power chip are completely covered by the high-thermal-conductivity plastic encapsulation layer. The difference between the low-thermal-conductivity plastic sealing layer and the thermal expansion coefficient of the substrate of the driving chip is less than 6*10 -6 / ℃, the thermal conductivity of the low-thermal-conductivity plastic sealing layer is less than 1W / m K, and the thermal expansion coefficient is not greater than 8*10 -6 / ℃. The high-thermal-conductivity plastic sealing layer has a thermal conductivity of 4-5 W / m K, and a thermal expansion coefficient of not more than 12*10 -6 / ℃. The distance between the driving chip and the first power chip or the second power chip is between 200 mu m and 2000 mu m. Further comprising a buffer layer disposed on the top of the first and second power chips away from the substrate, the buffer layer has a thermal conductivity greater than 1 W / m K, an elastic modulus less than 1 GPa, and a coefficient of thermal expansion that differs from the coefficient of thermal expansion of the first and second power chips by less than 8 x 10 -6 / °C. Further comprising a buffer layer disposed on the top of the first and second power chips away from the substrate, the buffer layer has a thermal conductivity greater than 1 W / m K, an elastic modulus less than 1 GPa, and a coefficient of thermal expansion that differs from the coefficient of thermal expansion of the first and second power chips by less than 8 x 10 -6 / °C.

2. The packaging structure of a power semiconductor according to claim 1, characterized by: The application further comprises a heat dissipation copper sheet, which is arranged on the buffer layer and penetrates through the high-thermal-conductivity plastic encapsulation layer; the high-thermal-conductivity plastic encapsulation layer semi-encapsulates the heat dissipation copper sheet so that one side of the heat dissipation copper sheet is in contact with the outside.

3. The packaging structure of a power semiconductor according to claim 1 or 2, characterized in that: The application further comprises a transition plastic encapsulation layer, which is arranged between the low-thermal-conductivity plastic encapsulation layer and the high-thermal-conductivity plastic encapsulation layer and completely separates the low-thermal-conductivity plastic encapsulation layer and the high-thermal-conductivity plastic encapsulation layer.

4. The packaging structure of a power semiconductor according to claim 3, characterized by: The thermal expansion coefficient of the transition plastic encapsulation layer is between that of the low-thermal-conductivity plastic encapsulation layer and that of the high-thermal-conductivity plastic encapsulation layer.

5. A packaging method of a packaging structure of a power semiconductor as claimed in claim 1, characterized by: The application comprises the following steps: S1: the driving chip is encapsulated for the first time by the low-thermal-conductivity plastic encapsulation layer; the driving chip is completely wrapped by the low-thermal-conductivity plastic encapsulation layer with uniform thickness; and the driving chip after the first encapsulation is obtained. S2: the driving chip after the first encapsulation is arranged on the welding spot of the substrate and is electrically connected with the substrate. S3: the first power chip and the second power chip are arranged on the welding spot of the substrate and are electrically connected with the substrate; and the power semiconductor half-bridge circuit is obtained. S4: the power semiconductor half-bridge circuit is encapsulated by the high-thermal-conductivity plastic encapsulation layer; the high-thermal-conductivity plastic encapsulation layer is filled around the low-thermal-conductivity plastic encapsulation layer, the first power chip and the second power chip and fills the gap between the first power chip, the second power chip and the substrate; and the high-thermal-conductivity plastic encapsulation layer completely covers the low-thermal-conductivity plastic encapsulation layer, the first power chip and the second power chip.

6. The packaging method of a power semiconductor according to claim 5, characterized by: The steps S3 and S4 further comprise steps SA and SB: SA: a buffer layer is coated on the side of the first power chip and the second power chip away from the substrate. SB: a heat dissipation copper sheet is fixed above the buffer layer; and the main structure of the power semiconductor is obtained. S4: the main structure of the power semiconductor is encapsulated by the high-thermal-conductivity plastic encapsulation layer; the high-thermal-conductivity plastic encapsulation layer is filled around the low-thermal-conductivity plastic encapsulation layer, the first power chip, the second power chip, the buffer layer and the heat dissipation copper sheet and fills the gap between the first power chip and the second power chip and the substrate; and the high-thermal-conductivity plastic encapsulation layer completely covers the low-thermal-conductivity plastic encapsulation layer, the first power chip, the second power chip and the buffer layer and semi-encapsulates the heat dissipation copper sheet so that one side of the heat dissipation copper sheet is in contact with the outside.

7. The packaging method of a power semiconductor according to claim 6, characterized by: The steps S2 and S3 further comprise a step Salpha: Salpha: a transition plastic encapsulation layer is encapsulated on the low-thermal-conductivity plastic encapsulation layer. The step S4 is: the main structure of the power semiconductor is packaged by a high-thermal-conductivity plastic packaging layer, which is filled around the first power chip, the second power chip, the buffer layer, the heat-dissipation copper sheet and the transition plastic packaging layer and fills the gap between the first power chip, the second power chip and the substrate; the high-thermal-conductivity plastic packaging layer completely covers the first power chip, the second power chip and the buffer layer, is isolated from the low-thermal-conductivity plastic packaging layer through the transition plastic packaging layer and semi-encapsulates the heat-dissipation copper sheet so that one side of the heat-dissipation copper sheet is in contact with the outside world.

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