Low power asynchronous handshake circuit and asynchronous circuit

Abstract

The application relates to the chip technical field, in particular to a low-power-consumption asynchronous handshake circuit and an asynchronous circuit, the asynchronous handshake circuit comprising a first flip-flop, a second flip-flop and a third flip-flop; a clock port of the first flip-flop is used for receiving a single pulse signal generated based on a first clock, a data port of the first flip-flop is connected with vdd, and an output port of the first flip-flop is connected with a data port of the second flip-flop; an output port of the second flip-flop is connected with a data port of the third flip-flop, and a clock port of the second flip-flop and an output port of the third flip-flop are both connected with a second clock; if the first flip-flop is an asynchronous low-level effective reset port, the asynchronous handshake circuit further comprises an inverter, an output port of the third flip-flop is connected with a data port of the inverter, and an output port of the inverter is connected with a reset port of the first flip-flop. The application reduces the power consumption of the asynchronous handshake circuit and improves the timing convergence speed of the asynchronous handshake circuit.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a low-power asynchronous handshake circuit and an asynchronous circuit. Background Technology

[0002] Asynchronous circuits are digital circuits that operate independently of a global clock signal. Data transmission and processing in asynchronous circuits can occur at any point in time, unrestricted by a clock signal. Instead of relying on a global clock, asynchronous circuits coordinate the operation of various components through asynchronous handshake circuits. Existing asynchronous handshake circuits require checking the setup time and hold time of flip-flops, as well as their recovery time and removal time. Therefore, existing asynchronous handshake circuits are complex in structure, consume a lot of power, and have slow timing convergence. Thus, reducing the power consumption and improving the timing convergence speed of asynchronous handshake circuits has become an urgent technical problem to be solved. Summary of the Invention

[0003] The purpose of this invention is to provide a low-power asynchronous handshake circuit and an asynchronous circuit, which reduces the power consumption of the asynchronous handshake circuit and improves the timing convergence speed of the asynchronous handshake circuit.

[0004] According to a first aspect of the present invention, a low-power asynchronous handshake circuit is provided, comprising a first flip-flop, a second flip-flop, and a third flip-flop;

[0005] The clock port of the first flip-flop is used to receive a single pulse signal generated based on the first clock, the data port of the first flip-flop is connected to VDD, and the output port of the first flip-flop is connected to the data port of the second flip-flop.

[0006] The output port of the second flip-flop is connected to the data port of the third flip-flop, and the clock port of the second flip-flop and the output port of the third flip-flop are both connected to the second clock.

[0007] If the first flip-flop is an asynchronous low-level active reset port, the asynchronous handshake circuit also includes an inverter, the output port of the third flip-flop is connected to the data port of the inverter, and the output port of the inverter is connected to the reset port of the first flip-flop.

[0008] If the first flip-flop is an asynchronous high-level active reset port, then the output port of the third flip-flop is directly connected to the reset port of the first flip-flop.

[0009] According to a second aspect of the present invention, an asynchronous circuit is provided, comprising a data transmitting circuit, a data receiving circuit, and the asynchronous handshake circuit, wherein the data transmitting circuit is connected to a first clock, the data receiving circuit is connected to a second clock, and the data transmitting circuit and the data receiving circuit perform a handshake based on the asynchronous handshake circuit.

[0010] Compared with existing technologies, this invention has significant advantages and beneficial effects. Through the above technical solution, the low-power asynchronous handshake circuit and asynchronous circuit provided by this invention achieve considerable technological advancement and practicality, and have broad industrial application value. It has at least the following beneficial effects:

[0011] The asynchronous handshake circuit of the present invention has a simple structure and low power consumption. The clock port of the first flip-flop is controlled by a single pulse signal, and the data port of the first flip-flop is connected to VDD. It does not require setup time checks and hold time checks between the data port and the clock port of the first flip-flop, nor does it require clear time checks and recovery time checks between the reset port and the clock port of the first flip-flop. It does not require defining a clock at the clock port of the first flip-flop, thereby improving the timing convergence speed of the asynchronous handshake circuit. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 The present invention provides a schematic diagram of a low-power asynchronous handshake circuit with an asynchronous low-level active reset port as the trigger provided in the embodiment of the invention. Detailed Implementation

[0014] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] This invention provides a low-power asynchronous handshake circuit, such as... Figure 1 As shown, it includes a first flip-flop (R0), a second flip-flop (R1), and a third flip-flop (R2).

[0016] The clock port of the first flip-flop is used to receive a single pulse signal generated based on the first clock. The clock port of the first flip-flop is controlled by the single pulse signal. It should be noted that the clock port of the traditional handshake circuit is controlled by a continuous pulse signal, i.e., a clock signal. In this embodiment of the invention, the clock port of the first flip-flop is controlled by a single pulse signal, and it is not necessary to define a clock on the clock port of the first flip-flop.

[0017] The setup and hold times between the clock and data ports of the first flip-flop must not violate timing rules; otherwise, the circuit will malfunction. In this embodiment, the data port of the first flip-flop is connected to Vdd, which represents the positive power supply voltage. Connecting the data port of the first flip-flop to Vdd ensures that the data port is always tied (high), preventing timing violations between the clock and data ports. The output port of the first flip-flop is connected to the data port of the second flip-flop. The output port of the second flip-flop is connected to the data port of the third flip-flop. Both the clock ports of the second and third flip-flops are connected to a second clock, which is asynchronous.

[0018] like Figure 1 As shown in the example, if the first flip-flop is an asynchronous low-level active reset port, the asynchronous handshake circuit further includes an inverter (I). The output port of the third flip-flop is connected to the data port of the inverter, and the output port of the inverter is connected to the reset port of the first flip-flop. An asynchronous low-level active reset port means that the reset port is asynchronous and active low. An asynchronous reset port means that the flip-flop can be reset even without a clock signal when a reset signal arrives. A low-level active reset port means that when the reset port of the first flip-flop is low, the first flip-flop is reset, and the value stored in the first flip-flop is reset to 1. When the reset port of the first flip-flop is high, the first flip-flop is in a released state and can proceed to the next handshake operation.

[0019] If the first flip-flop has an asynchronous high-level active reset port, then the output port of the third flip-flop is directly connected to the reset port of the first flip-flop. An asynchronous reset port means that the flip-flop can be reset even without a clock signal when a reset signal arrives. A high-level active reset port means that when the reset port of the first flip-flop is high, the first flip-flop is reset, and the value stored in the first flip-flop is reset to 1. When the reset port of the first flip-flop is low, the first flip-flop is in a released state and can proceed to the next handshake operation.

[0020] In a preferred embodiment, the clock frequency of the first clock is greater than or equal to the clock frequency of the second clock, i.e., the first clock is a fast clock and the second clock is a slow clock. When the reset port of the first flip-flop sends a reset active level, timing violations of the clear time and recovery time are not allowed. Such violations would cause the circuit to malfunction. Therefore, in the prior art, it is necessary to check whether timing violations of the clear time and recovery time occur between the reset port and the clock port of the first flip-flop. To avoid timing violations of the clear time and recovery time when the inverter sends a low level to the reset port of the first flip-flop, as an embodiment, the time interval between the generation of a single pulse signal by the first clock is greater than a preset time interval, which is twice the second clock cycle. This ensures that the time interval between the generation of two pulse signals by the first clock is large enough to prevent timing violations of the recovery time and removal time between the clock port and the reset port of the first flip-flop. Therefore, it is not necessary to check the recovery time and removal time of the flip-flop.

[0021] It should be noted that the convergence of the asynchronous handshake circuit requires convergence of two timing aspects: first, setup and hold checks between the data port and clock port of the first flip-flop; second, removal and recovery checks between the reset port and clock port of the first flip-flop. In this embodiment of the invention, by always connecting the data port of the first flip-flop to VDD and staggering the interval between clock reset and clock, i.e., when a pulse arrives at the first flip-flop, no reset signal arrives, and when a reset signal arrives, no clock signal arrives, the asynchronous handshake circuit described in this embodiment of the invention does not need to check the above two timing aspects of the first flip-flop. It can be understood that since these two timing aspects do not need to be checked, the timing of the one-step handshake circuit of this invention meets the requirements, therefore, there is no need to define clock constraints for the clock port of the first flip-flop, thus improving the timing convergence speed of the asynchronous handshake circuit.

[0022] In one embodiment, the first flip-flop is an asynchronous low-level active reset port. If the first flip-flop is in a handshake initial state (where the value stored in the first flip-flop is 0 and the reset port of the first flip-flop is high), then when the clock port of the first flip-flop receives a single pulse signal, the data port of the first flip-flop acquires the value of vdd and updates the value stored in the first flip-flop to 1. When the first rising edge of the second clock arrives, the second flip-flop acquires the 1 stored in the first flip-flop and updates the value stored in the second flip-flop to 1. When the second rising edge of the second clock arrives, the third flip-flop acquires the 1 stored in the second flip-flop and updates the value stored in the third flip-flop to 1. It should be noted that during this process, after the value stored in the first flip-flop is updated to 1, it remains 1, which is equivalent to expanding the single pulse signal received by the clock port of the first flip-flop into a level, ensuring that the third flip-flop can correctly acquire the single pulse signal received by the clock port of the first flip-flop. The inverter obtains a 1 from the third flip-flop and converts it to a 0, sending a low level to the reset port of the first flip-flop. This is equivalent to the third flip-flop, after sampling, sending a clear signal to the first flip-flop via the inverter. This clears the high level from the reset port of the first flip-flop, resetting its stored value to 0, thus pulling down the high level of the first flip-flop to prepare for the next handshake operation. When the third rising edge of the second clock arrives, the second flip-flop obtains the 0 stored in the first flip-flop and updates its stored value to 0. When the fourth rising edge of the second clock arrives, the third flip-flop obtains the 0 stored in the second flip-flop and updates its stored value to 0. The inverter obtains the 0 from the third flip-flop and converts it to a 1, sending a high level to the reset port of the first flip-flop, releasing the first flip-flop and completing one handshake operation. Furthermore, releasing the first flip-flop prepares for the next handshake operation. When the clock port of the first flip-flop receives another single pulse signal, the next handshake operation can proceed according to the above process.

[0023] In another embodiment, the first flip-flop is an asynchronous high-level active reset port. If the first flip-flop is in a handshake initial state (where the value stored in the first flip-flop is 0 and the reset port of the first flip-flop is low), when the clock port of the first flip-flop receives a single pulse signal, the data port of the first flip-flop acquires the value of vdd and updates the value stored in the first flip-flop to 1. When the first rising edge of the second clock arrives, the second flip-flop acquires the 1 stored in the first flip-flop and updates the value stored in the second flip-flop to 1. It should be noted that during this process, after the value stored in the first flip-flop is updated to 1, it remains 1, which is equivalent to expanding the single pulse signal received by the clock port of the first flip-flop into a level, ensuring that the third flip-flop can correctly acquire the single pulse signal received by the clock port of the first flip-flop. When the second rising edge of the second clock arrives, the third flip-flop acquires the 1 stored in the second flip-flop, updates the value stored in the third flip-flop to 1, and sends a high level to the reset port of the first flip-flop, resetting the stored value of the first flip-flop to 0. When the third rising edge of the second clock arrives, the second flip-flop retrieves the 0 stored in the first flip-flop and updates the value stored in the second flip-flop to 0. When the fourth rising edge of the second clock arrives, the third flip-flop retrieves the 0 stored in the second flip-flop and updates the value stored in the third flip-flop to 0. The output port of the third flip-flop sends a low level to the reset port of the first flip-flop, releasing the first flip-flop and completing a handshake operation.

[0024] In the initial state, the value stored in the first flip-flop may be 0 or 1. If the value stored in the first flip-flop is 0 in the initial state, the first flip-flop can immediately perform the handshake transmission. If the value stored in the first flip-flop is 1 in the initial state, it is necessary to wait for two clock cycles corresponding to the second clock before the first flip-flop can be reset to 0. As an embodiment, in the initial state of the asynchronous handshake circuit, if the first flip-flop is an asynchronous low-level active reset port, the reset port of the first flip-flop is high; if the first flip-flop is an asynchronous high-level active reset port, the reset port of the first flip-flop is low. If the value stored in the first flip-flop is 0, it is determined that the first flip-flop is in the initial handshake state. If the value stored in the first flip-flop is 1, after the reset signal of the second clock domain is withdrawn, the state of the first flip-flop after waiting for two clock cycles corresponding to the second clock is determined as the initial handshake state.

[0025] Since the initial state of the first flip-flop is not fixed, in order to ensure the reliable operation of the asynchronous handshake circuit, as another embodiment, in the initial state of the asynchronous handshake circuit, if the first flip-flop is an asynchronous low-level active reset port, then the reset port of the first flip-flop is high-level; if the first flip-flop is an asynchronous high-level active reset port, then the reset port of the first flip-flop is low-level. In the initial state of the asynchronous handshake circuit, after uniformly removing the reset signal of the second clock domain, the state of the first flip-flop after waiting for two clock cycles corresponding to the second clock is determined as the initial handshake state.

[0026] Furthermore, in digital circuits, timing issues can cause certain signals to be in an uncertain state at the sampling time, resulting in metastability. This state can lead to abnormal circuit function or data errors. The structure of the second and third flip-flops also plays a role in eliminating metastability, ensuring the stability of circuit function and the correctness of acquired data.

[0027] As one embodiment, the asynchronous handshake circuit further includes a finite state machine (FSM), such as Figure 1 As shown, the finite state machine is connected to the first clock and is used to generate a single pulse signal based on the first clock and transmit it to the clock port of the first flip-flop.

[0028] In one embodiment, the reset ports of both the second and third flip-flops are connected to the second clock reset signal, such as... Figure 1 In the example shown, the reset ports of the second and third flip-flops are asynchronous low-level active reset ports. It should be noted that when the first flip-flop is set to an asynchronous high-level active reset port, the reset ports of the second and third flip-flops can also be set to asynchronous high-level active reset ports. Figure 1 Taking the example shown, specifically, when it is necessary to reset the second and third flip-flops in the initial state or during operation, the second clock reset signal is set to a low level. It should be noted that in the initial state, the values ​​stored in the second and third flip-flops need to be set to 0, therefore the second clock reset signal needs to be set to a low level. During operation, if the second and / or third flip-flops malfunction or encounter other abnormalities requiring reset, the second clock reset signal is also directly set to a low level to quickly reset them. At other times during operation, the second clock reset signal is set to a high level, so that the second and third flip-flops are in the released state and can operate normally.

[0029] The asynchronous handshake circuit of the low-power asynchronous handshake circuit described in this embodiment of the invention has a simple structure and low power consumption. The clock port of the first flip-flop is controlled by a single pulse signal, and the data port of the first flip-flop is connected to VDD. It does not require setup time checks and hold time checks between the data port and the clock port of the first flip-flop, nor does it require clear time checks and recovery time checks between the reset port and the clock port of the first flip-flop. It does not require defining a clock at the clock port of the first flip-flop, thereby improving the timing convergence speed of the asynchronous handshake circuit.

[0030] This invention also provides an asynchronous circuit, including a data transmitting circuit, a data receiving circuit, and the asynchronous handshake circuit described in this embodiment. The data transmitting circuit is connected to a first clock and operates under the first clock. The data receiving circuit is connected to a second clock and operates under the second clock. The data transmitting circuit and the data receiving circuit perform a handshake based on the asynchronous handshake circuit. After the data transmitting circuit and the data receiving circuit establish a handshake through the asynchronous handshake circuit described in this embodiment, data can be transmitted according to specific application requirements.

[0031] The asynchronous circuit described in this embodiment of the invention includes a low-power asynchronous handshake circuit, which has a simple structure and low power consumption. The clock port of the first flip-flop is controlled by a single pulse signal, and the data port of the first flip-flop is connected to VDD. It does not require setup time checks and hold time checks between the data port and the clock port of the first flip-flop, nor does it require clear time checks and recovery time checks between the reset port and the clock port of the first flip-flop. It does not require defining a clock at the clock port of the first flip-flop, which improves the timing convergence speed of the asynchronous handshake circuit, thereby improving the handshake speed between the data transmission circuit and the data receiving circuit, and thus improving the data transmission efficiency between the data transmission circuit and the data receiving circuit.

[0032] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A low-power asynchronous handshake circuit, characterized in that, comprising a first flip-flop, a second flip-flop, and a third flip-flop; wherein the clock port of the first flip-flop is configured to receive a single pulse signal generated based on a first clock, the data port of the first flip-flop is connected to vdd, and the output port of the first flip-flop is connected to the data port of the second flip-flop; the output port of the second flip-flop is connected to the data port of the third flip-flop, and the clock ports of the second flip-flop and the third flip-flop are both connected to a second clock; if the first flip-flop is an asynchronous low-active reset port, the asynchronous handshake circuit further comprises an inverter, the output port of the third flip-flop is connected to the data port of the inverter, and the output port of the inverter is connected to the reset port of the first flip-flop; if the first flip-flop is an asynchronous high-active reset port, the output port of the third flip-flop is directly connected to the reset port of the first flip-flop.

2. The asynchronous handshake circuit of claim 1, characterized in that, if the first flip-flop is an asynchronous low-active reset port, and if the first flip-flop is in a handshake initial state in which the value stored in the first flip-flop is 0 and the reset port of the first flip-flop is high, when the clock port of the first flip-flop receives the single pulse signal, the data port of the first flip-flop obtains the value of vdd, and the value stored in the first flip-flop is updated to 1; when the first rising edge of the second clock arrives, the second flip-flop obtains the 1 stored in the first flip-flop, and the value stored in the second flip-flop is updated to 1; when the second rising edge of the second clock arrives, the third flip-flop obtains the 1 stored in the second flip-flop, and the value stored in the third flip-flop is updated to 1; the inverter obtains the 1 from the third flip-flop and converts it to 0, sends a low level to the reset port of the first flip-flop, and the first flip-flop resets the stored value to 0; when the third rising edge of the second clock arrives, the second flip-flop obtains the 0 stored in the first flip-flop, and the value stored in the second flip-flop is updated to 0; when the fourth rising edge of the second clock arrives, the third flip-flop obtains the 0 stored in the second flip-flop, and the value stored in the third flip-flop is updated to 0; the inverter obtains the 0 from the third flip-flop and converts it to 1, sends a high level to the reset port of the first flip-flop, and releases the first flip-flop, completing a handshake operation.

3. The asynchronous handshake circuit of claim 1, characterized in that, The first flip-flop is an asynchronous high-level effective reset port. If the first flip-flop is in a handshake initial state, that is, the value stored in the first flip-flop is 0 and the reset port of the first flip-flop is at a low level, when the clock port of the first flip-flop receives a single pulse signal, the data port of the first flip-flop obtains the value of vdd, the value stored in the first flip-flop is updated to 1, when the first rising edge of the second clock arrives, the second flip-flop obtains the 1 stored in the first flip-flop, the value stored in the second flip-flop is updated to 1, when the second rising edge of the second clock arrives, the third flip-flop obtains the 1 stored in the second flip-flop, the value stored in the third flip-flop is updated to 1, and the output port of the third flip-flop sends a high level to the reset port of the first flip-flop, and the first flip-flop resets the stored value to 0. When the third rising edge of the second clock arrives, the second flip-flop obtains the 0 stored in the first flip-flop, the value stored in the second flip-flop is updated to 0, when the fourth clock rising edge of the second clock arrives, the third flip-flop obtains the 0 stored in the second flip-flop, the value stored in the third flip-flop is updated to 0, and the output port of the third flip-flop sends a low level to the reset port of the first flip-flop to release the first flip-flop, and a handshake operation is completed.

4. The asynchronous handshake circuit of claim 2 or 3, wherein in the initial state of the asynchronous handshake circuit, if the first flip-flop is an asynchronous low-level effective reset port, the reset port of the first flip-flop is at a high level, and if the first flip-flop is an asynchronous high-level effective reset port, the reset port of the first flip-flop is at a low level; if the value stored in the first flip-flop is 0, it is determined that the first flip-flop is in the handshake initial state, and if the value stored in the first flip-flop is 1, the reset signal of the second clock domain is removed, and then the state of the first flip-flop after two clock periods corresponding to the second clock is determined to be the handshake initial state.

5. The asynchronous handshake circuit of claim 2 or 3, wherein in the initial state of the asynchronous handshake circuit, if the first flip-flop is an asynchronous low-level effective reset port, the reset port of the first flip-flop is at a high level, and if the first flip-flop is an asynchronous high-level effective reset port, the reset port of the first flip-flop is at a low level; in the initial state of the asynchronous handshake circuit, the reset signal of the second clock domain is removed, and then the state of the first flip-flop after two clock periods corresponding to the second clock is determined to be the handshake initial state.

6. The asynchronous handshake circuit of claim 2, wherein the clock frequency of the first clock is greater than or equal to the clock frequency of the second clock, and the time interval at which the first clock generates a single pulse signal is greater than a preset time interval, which is twice the period of the second clock.

7. The asynchronous handshake circuit of claim 1, wherein The asynchronous handshake circuit further comprises a finite state machine connected with the first clock, for generating a single pulse signal based on the first clock and transmitting to a clock port of the first flip-flop.

8. The asynchronous handshake circuit of claim 1, wherein, the reset port of the second flip-flop and the reset port of the third flip-flop are both connected with a second clock reset signal.

9. The asynchronous handshake circuit of claim 8, wherein, the second clock reset signal is set to low at the moment when the second flip-flop and the third flip-flop need to be reset in the initial state or during operation, and is set to high at other moments during operation.

10. An asynchronous circuit, characterized by The asynchronous circuit comprises a data sending circuit, a data receiving circuit and the asynchronous handshake circuit of any one of claims 1-9. The data sending circuit is connected with the first clock, the data receiving circuit is connected with the second clock, and the data sending circuit and the data receiving circuit perform handshake based on the asynchronous handshake circuit.

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