Method for implementing multi-chip high-density connection photolithography

Abstract

The application discloses a multi-chip high-density connection photoetching technology implementation method, a photoetching technology implementation method for multi-chip interconnection, a chip-level chip interconnection method, a mask line manufacturing method and a photoetching device. The multi-chip high-density connection photoetching technology implementation method comprises the following steps: a first mask is selected to be exposed through a first original pattern unit in a first M*N chip group by a second alignment mark, so that the pattern of the first mask is transferred to an exposure area covering the first original pattern unit; the substrate is moved longitudinally by M times of the longitudinal size of the original pattern or transversely by N times of the transverse size of the original pattern to perform alignment exposure, so that the exposure of the corresponding area of other M*N chip groups is completed; other masks are selected to perform exposure on other corresponding pattern units of the first M*N chip group, and the longitudinal movement or transverse movement is repeatedly performed to complete the exposure of the corresponding area of the corresponding pattern units in other M*N chip groups. The scheme realizes multi-chip high-density interconnection.

Description

Technical Field

[0001] This application relates to the field of lithography technology, specifically to a method for implementing multi-chip high-density interconnect lithography technology, a method for implementing multi-chip high-density interconnect lithography technology, a method for implementing lithography technology for multi-chip interconnection, a chip-level chip interconnection method, a method for fabricating mask lines, and lithography equipment. Background Technology

[0002] In modern semiconductor manufacturing, photolithography is a crucial step in realizing high-density integrated circuits. The photolithography process precisely transfers the pattern on a mask onto the photoresist on the silicon wafer surface to form the desired circuit structure. With the continuous increase in the integration density of integrated circuits, the requirements for the critical dimension (CD) are becoming increasingly stringent. In the pattern exposure process of a photolithography machine, the theoretical limit estimate of the critical dimension can be given by Rayleigh's rule for resolution, as shown in equation (1):

[0003] Formula (1)

[0004] in, It refers to the wavelength of the light source used in the lithography machine. It is the numerical aperture of the projection system in a lithography machine used for exposure. It is an adjustment factor dependent on the photolithography process, also known as the Rayleigh constant. This is the minimum size of the graphic. From formula (1), we can see that there are three main ways to reduce the minimum size of the graphic: shortening the exposure wavelength... Increase numerical aperture or reduce Reducing the minimum pattern size through the three methods mentioned above is too difficult and costly. Furthermore, as device dimensions continue to shrink, leakage current problems caused by quantum tunneling become increasingly severe, limiting the feasibility of further reducing the minimum pattern size. Therefore, simply relying on reducing the critical dimensions of the device to increase the number of transistors is no longer feasible.

[0005] To accommodate more transistors, manufacturing larger chips has become extremely important. However, the maximum exposure field size of traditional lithography machines is limited to around 26mm × 33mm, which cannot meet the needs of manufacturing larger chips. While large exposure fields have been achieved in some LCD panel applications, the resulting line sizes are too wide, making it difficult to meet the high-density integration requirements of integrated circuits. Therefore, how to achieve high-density interconnection of multiple chips (such as multiple chips around 26mm × 33mm in size, or 25mm × 32mm) while keeping the exposure field size constant has become a pressing technical problem in lithography. Summary of the Invention

[0006] This application provides a method for implementing high-density interconnection lithography for multiple chips, a method for implementing high-density interconnection lithography for multiple chips, a chip-level chip interconnection method, a method for fabricating mask lines, and lithography equipment. This method enables high-density interconnection of multiple chips while maintaining the same exposure field size, thereby forming a large-size chip and providing lithography technology support for the high-density interconnection and integration of M×N large chips. The specific solution is as follows:

[0007] In a first aspect, embodiments of this application provide a method for implementing multi-chip high-density interconnect lithography technology, used to achieve interconnection of M×N chips, including:

[0008] The substrate to be exposed, which has existing patterned units, is loaded onto the stage of the photolithography equipment, and a first alignment is performed using the first alignment mark on the substrate.

[0009] For the first M×N chip group on the substrate, a first mask is selected, and the first mask is aligned with the first original pattern unit in the first M×N chip group by the second alignment mark on the substrate. Exposure is performed to transfer the pattern of the first mask to the exposure area covering the first original pattern unit.

[0010] The substrate is moved longitudinally by M times the longitudinal dimension of a single original graphic unit, or laterally by N times the lateral dimension of a single original graphic unit. The alignment and exposure steps are repeated to complete the exposure of the exposure area of ​​the graphic unit corresponding to the first original graphic unit in the other M×N chipset on the substrate.

[0011] Select other masks, repeat exposure on the corresponding graphic units other than the first original graphic unit of the first M×N chip group, and repeat vertical movement M times the vertical dimension of a single original graphic unit or horizontal movement N times the horizontal dimension of a single original graphic unit to complete the exposure of the corresponding areas of other corresponding graphic units in other M×N chip groups on the substrate.

[0012] Specifically, for any M×N chipset, the exposure area covering any original graphic unit and the exposure area of ​​the adjacent original graphic unit have overlapping areas; for any M×N chipset, there are no interconnect lines on the outer dicing path of the connected M×N chips that penetrate into the original graphic unit and connect the original graphic unit; M and N are both integers greater than or equal to 1, and at least one of M and N is greater than or equal to 2.

[0013] Secondly, embodiments of this application provide a method for implementing multi-chip high-density interconnect lithography technology, used to achieve interconnection of M×N chips, including:

[0014] The substrate to be exposed, which has existing patterned units, is loaded onto the stage of the photolithography equipment, and a first alignment is performed using the first alignment mark on the substrate.

[0015] For the first M×N chip group on the substrate, a first mask is selected, and the first mask is aligned with the first original pattern unit in the first M×N chip group by the second alignment mark on the substrate. Exposure is performed to transfer the pattern of the first mask to the exposure area covering the first original pattern unit.

[0016] The substrate is moved longitudinally by the sum of the longitudinal dimensions of M original pattern units, or laterally by the sum of the lateral dimensions of N original pattern units. The alignment and exposure steps are repeated to complete the exposure of the exposure area of ​​the pattern unit corresponding to the first original pattern unit in the other M×N chipset on the substrate.

[0017] Select other masks, repeat exposure on the corresponding graphic units other than the first original graphic unit of the first M×N chip group, and repeat vertically move the sum of the vertical dimensions of M original graphic units or horizontally move the sum of the horizontal dimensions of N original graphic units to complete the exposure of the corresponding areas of other corresponding graphic units in other M×N chip groups on the substrate.

[0018] In this M×N chipset, at least some of the original graphic units have different sizes; in any M×N chipset, the exposure area covering any original graphic unit and the exposure area of ​​the adjacent original graphic unit have overlapping areas; in any M×N chipset, there are no interconnect lines extending into the original graphic units and connecting the original graphic units on the dicing path of the connected M×N chips; at least one of M and N is an integer greater than or equal to 2.

[0019] Thirdly, embodiments of this application provide a method for implementing photolithography technology for multi-chip interconnection, including:

[0020] The substrate to be exposed is loaded onto the stage of the photolithography equipment. The substrate to be exposed includes at least a first pattern formed by the previous process and a second pattern adjacent to the first pattern, and there is a scribe line between the first pattern and the second pattern.

[0021] A first exposure is performed using a first mask, transferring a preset pattern on the first mask to a first exposure area on a substrate, wherein the first exposure area at least covers the first pattern;

[0022] A second exposure is performed using a second mask to transfer a preset pattern on the second mask to a second exposure area on a substrate, wherein the second exposure area at least covers the second pattern.

[0023] The first exposure area and the second exposure area have an overlapping area, which is located on the first pattern and / or the scribe line and / or the second pattern.

[0024] Optional, also includes:

[0025] For any two patterned areas of chip cells on the substrate that need to be interconnected, the first and second exposure steps are repeated until the interconnection between all target chip cells on the substrate is completed.

[0026] Fourthly, embodiments of this application provide a chip-level chip interconnection method, characterized in that it includes:

[0027] A substrate is provided on which a semiconductor structure comprising at least two semiconductor chips is formed, each semiconductor chip having at least an intra-chip interconnect, and the semiconductor chips having no inter-chip interconnect;

[0028] The photolithography steps for interconnecting the at least two semiconductor chips are achieved through the photolithography technology implementation method described in either the first or second aspect.

[0029] Fifthly, embodiments of this application provide a method for fabricating mask lines, including:

[0030] A first line, a second line, and a third line are created on a photomask; the first line and the third line are connected, and the second line and the third line are connected.

[0031] Wherein, the first line of the mask is used to expose and form a first line as described in the first aspect in the first exposure area of ​​the substrate; the second line of the mask is used to expose and form a second line as described in the first aspect in the first exposure area of ​​the substrate; and the third line of the mask is used to expose and form a third line as described in the first aspect in the first exposure area of ​​the substrate.

[0032] Sixthly, embodiments of this application provide a photolithography apparatus, including two mask stages, three or four stages, two wafer loading / unloading systems, and two wafer measurement systems.

[0033] Compared with the prior art, this application has the following advantages:

[0034] The method for implementing multi-chip high-density interconnect lithography technology provided in the first aspect of this application involves loading a substrate containing existing patterned units onto the stage of a lithography apparatus, and performing a first alignment using a first alignment mark on the substrate. For a first M×N chip group on the substrate, a first mask is selected, and the first mask is aligned with the first existing patterned unit in the first M×N chip group using a second alignment mark on the substrate. Exposure is then performed, transferring the pattern of the first mask to the exposure area covering the first existing patterned unit. The substrate is then moved longitudinally by M times the longitudinal dimension of a single existing patterned unit, or laterally by N times the lateral dimension of a single existing patterned unit, and the alignment and exposure steps are repeated to complete the patterning of the first mask in other M×N chip groups on the substrate corresponding to the first existing patterned unit. Exposure of the exposure area; then, selecting other masks, repeatedly exposing the corresponding graphic units other than the first original graphic unit of the first M×N chip group, and repeatedly performing vertical movement M times the vertical dimension of a single original graphic unit, or horizontal movement N times the horizontal dimension of a single original graphic unit, thereby completing the exposure of the corresponding areas of other corresponding graphic units in other M×N chip groups on the substrate by other masks; and, for any M×N chip group, there is an overlapping area between the exposure area covering any original graphic unit and the exposure area of ​​the adjacent original graphic unit; for any M×N chip group, there is no interconnect pattern that penetrates into the original graphic unit and connects the original graphic unit on the dicing path of the connected M×N chips; M and N are both integers greater than or equal to 1, and at least one of M and N is greater than or equal to 2. In this way, by using multiple photomasks, high-density interconnection of multiple chips can be achieved without changing the exposure field size, thereby forming a large-size chip. This provides photolithography support for the high-density interconnection and integration of multiple large chips (such as multiple chips with a size of about 26mm × 33mm, or 25mm × 32mm)) of M×N.

[0035] Furthermore, in existing technologies, chip interconnection is mainly achieved through on-board level interconnection. This method typically involves interconnecting chips via a circuit board after packaging, resulting in a complex structure and large size. During use, signals need to be transmitted through long circuit board paths, leading to significant signal delays. Long traces are also susceptible to electromagnetic interference, causing signal distortion. The longer traces and drive circuits also result in larger capacitive loads, inevitably increasing power consumption. Simultaneously, the larger trace and solder joint sizes limit the interconnection density between chips, and the need for larger communication drive circuits further restricts this density. In contrast, the multi-chip high-density interconnection photolithography method provided in this application enables chip-level interconnection. This allows multiple chips to be connected simultaneously during chip manufacturing. During use, the shortened interconnection distance significantly reduces signal transmission time, lowers the risk of signal distortion, improves signal integrity, and reduces parasitic loads, thereby reducing power consumption. Furthermore, this invention directly uses existing high-performance lithography machines (such as DUV lithography machines and EUV lithography machines) to perform chip interconnect lithography, with the smallest line size reaching 0.1um or even a few nm, which can greatly improve the density of chip interconnect lines, ultimately forming a large chip with high-density chip interconnects (such as M×N×25mm×32mm) formed by M×N large chips (such as 25mm×32mm). Attached Figure Description

[0036] Figure 1 This is a structural diagram of an example of the photolithography equipment used in the photolithography technology implementation method provided in the embodiments of this application.

[0037] Figure 2 This is a schematic diagram of an example of mounting a silicon wafer or carrier plate on a substrate in the photolithography technology implementation method provided in the embodiments of this application.

[0038] Figure 3 This is a structural diagram of the lithography equipment based on the EUV light source provided in the embodiments of this application.

[0039] Figure 4 This is a structural diagram of another example of the photolithography equipment used in the implementation method of the photolithography technology provided in the embodiments of this application.

[0040] Figure 5 This is a flowchart of the implementation method of the multi-chip high-density interconnect lithography technology provided in the embodiments of this application.

[0041] Figure 6 This is a schematic diagram of an example of the first M×N chipset in the implementation method of the multi-chip high-density interconnect lithography technology provided in the embodiments of this application.

[0042] Figure 7 This is a schematic diagram illustrating an example of the relative positional relationship between the original mask and the mask selected for exposure in the implementation method of multi-chip high-density interconnect lithography technology provided in this application embodiment, as well as the positional relationship between the exposure area to be formed during exposure and the original pattern unit covered by the exposure area to be formed.

[0043] Figure 8 This is a schematic diagram of an example of the exposure area formed by the substrate being exposed by N times in the lateral step and M times in the vertical step in the implementation method of multi-chip high-density interconnect lithography technology provided in the embodiments of this application.

[0044] Figure 9 This is a schematic diagram of an example of the exposure area formed by the substrate being exposed by N times in the lateral step and M times in the vertical step in the implementation method of multi-chip high-density interconnect lithography technology provided in the embodiments of this application.

[0045] Figure 10 This is a schematic diagram illustrating an example of how multiple M×N chipsets complete inter-chip interconnection in the implementation method of multi-chip high-density interconnection photolithography technology provided in this application embodiment.

[0046] Figure 11 This is a schematic diagram of an example of a target patterning unit in the implementation method of multi-chip high-density interconnect lithography technology provided in the embodiments of this application.

[0047] Figure 12 This is a schematic diagram of an example of the first line, second line, and third line in the implementation method of multi-chip high-density interconnect lithography technology provided in the embodiments of this application.

[0048] Figure 13 This is a schematic diagram of an example of the fourth, fifth, and sixth lines in the implementation method of the multi-chip high-density interconnect lithography technology provided in the embodiments of this application.

[0049] Figure 14 This is a schematic diagram illustrating an example of the overlap between the first exposure region and the second exposure region in the implementation method of multi-chip high-density interconnect lithography technology provided in this application embodiment.

[0050] Figure 15 This is a schematic diagram illustrating an example of a first exposure area including multiple sets of lines and a second exposure area including multiple sets of lines in the implementation of the multi-chip high-density interconnect lithography technology provided in this application embodiment.

[0051] Figure 16 This is a schematic diagram illustrating an example of an implementation of the multi-chip high-density interconnect lithography technology provided in this application, where the overlapping area includes multiple sets of lines.

[0052] Figure 17This is a schematic diagram of an example of an M×N chipset including multiple original patterned units of different sizes in the photolithography technology implementation method for multi-chip high-density interconnection provided in the embodiments of this application.

[0053] Figure 18 This is a schematic diagram of an example of a photolithography technique for implementing high-density interconnection of multiple chips provided in this application, which incorporates existing patterned units. Detailed Implementation

[0054] Many specific details are set forth in the following description to provide a full understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this application; therefore, this application is not limited to the specific embodiments disclosed below.

[0055] It should be noted that the terms "first," "second," "third," etc., in the claims, specification, and drawings of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. Such data are interchangeable where appropriate so that the embodiments of this application described herein can be implemented in a sequence other than that shown or described herein. Furthermore, the terms "comprising," "having," and their variations are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0056] It should be understood that in the embodiments of this application, "at least one" means one or more, and "more than one" means two or more. "And / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. The character " / " generally indicates that the related objects before and after it are in an "or" relationship. "Contains A, B and / or C" means containing any one, two, or three of A, B, and C.

[0057] It should be understood that in the embodiments of this application, "B corresponding to A", "B corresponding to A", "A corresponds to B" or "B corresponds to A" means that B is associated with A, and B can be determined based on A. Determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

[0058] Based on the reasons mentioned in the background art, in order to achieve high-density interconnection of multiple chips while keeping the exposure field size unchanged, thereby forming a large-size chip, this application provides a method for implementing photolithography technology for high-density interconnection of multiple chips, a method for implementing photolithography technology for multi-chip interconnection, and a chip-level chip interconnection method.

[0059] First, the implementation method of photolithography technology for multi-chip high-density interconnection, the implementation method of photolithography technology for multi-chip interconnection, and the application scenarios of chip-level chip interconnection methods provided in the embodiments of this application are introduced:

[0060] The methods provided in this application can be applied to top-layer or second-layer photolithography processes. Top-layer or second-layer photolithography processes are back-end steps in integrated circuit manufacturing, mainly used to form the topmost metal interconnects and contact holes. In the top-layer or second-layer photolithography process, the photolithography technology implementation method for multi-chip high-density interconnection, the photolithography technology implementation method for multi-chip interconnection, and the chip-level chip interconnection method provided in this application can be used to achieve high-density interconnection of multiple chips, thereby forming a large-size chip.

[0061] like Figure 1 The diagram shown is a structural diagram of an example of a photolithography apparatus used in the implementation method of the photolithography technology provided in this application embodiment. The photolithography apparatus includes:

[0062] Light source 100 is used to provide the exposure beam required for photolithography. The light source 100 can be, but is not limited to, a light source generated by a mercury lamp, a light source generated by an excimer laser, or an extreme ultraviolet (EUV) light source. Mercury lamps can emit light of multiple discrete wavelengths, including g-lines (436 nm), i-lines (365 nm), etc., wavelengths suitable for photolithography processes with different resolution requirements. Excimer lasers can generate shorter wavelengths of ultraviolet light, such as KrF (248 nm) and ArF (193 nm), short wavelengths which help improve photolithography resolution and are suitable for fine patterning requirements. The wavelength of the EUV light source is 13.5 nm, much shorter than that of traditional DUV light sources. This allows for photolithography at extremely high resolution, suitable for state-of-the-art semiconductor manufacturing processes. Methods for generating EUV light sources include, but are limited to, converting materials into a plasma state having at least one element with one or more emission lines in the EUV range (e.g., xenon, lithium, or tin).

[0063] Mask 200 is used to provide the preset pattern required for exposure.

[0064] The projection system 300 is used to transfer a preset pattern on the mask 200 onto the substrate 500 to be exposed. The projection system 300 can be a conventional projection system with a reduction ratio of 4 to 10 times or other reduction ratios. Specifically, the reduction ratio of the projection system 300 can be any one of 4, 5, 8, or 10 times, or one of 2.5, 2, 1.25, 1, 0.8, 0.5, 0.4, 0.2, 0.125, or 0.1. The required reduction ratio can be selected according to the size of the original pattern unit produced in the previous layer, the minimum size requirement of the pattern, and the size requirement of the exposure field to be formed (i.e., the first exposure area and the second exposure area). This application does not impose specific restrictions on this.

[0065] The stage 400 is used to mount the substrate 500 to be exposed and to perform stepping on the substrate 500.

[0066] The substrate 500 may be one of a silicon substrate, a germanium substrate, a compound semiconductor substrate, a ceramic substrate, a glass substrate, a quartz substrate, a silicon substrate, or a metal substrate. The substrate may be circular or square.

[0067] like Figure 2 The diagram illustrates an example of mounting a silicon wafer or carrier plate on a substrate in the photolithography implementation method provided in this application. The substrate 500 can be a composite substrate composed of a substrate 503 containing integrated circuits (including silicon substrates, germanium substrates, compound semiconductors, etc.) and a carrier plate 502 (including ceramic carrier plates, glass carrier plates, quartz carrier plates, silicon carrier plates, or metal carrier plates, etc.) supporting the substrate 503. Using the photolithography implementation method provided in this application, KGD (know-good die) chips can be precisely bonded to the carrier plate 502, and the composite substrate can then undergo further high-density interconnection through this invention. Here, a KGD (know-good die) chip refers to an independent chip that has been verified to be functionally normal in wafer-level testing, possessing good functionality and reliability before being integrated into a more complex system.

[0068] The substrate 500 may be a patterned silicon wafer, or a carrier plate or compound semiconductor with metal wiring and / or optical wiring.

[0069] In other words, the photolithography method provided in this application is feasible for patterned silicon wafers, and can also be selected for patterned compound semiconductors or substrates. All can achieve high-density interconnection between multiple patterns based on the same exposure field size, realizing high-density interconnection between compound semiconductors or substrates. Among these, compound semiconductors, like traditional silicon wafers, have the capability to fabricate large-size chips. To achieve high-density interconnection between these chips, bonding techniques (such as direct copper bonding) can be used to fix the chips onto the substrate.

[0070] The substrate of the carrier plate can be a high-hardness, low-deformation substrate. Specifically, the carrier plate can be one of a ceramic carrier plate, a glass carrier plate, a quartz carrier plate, a silicon carrier plate, or a metal carrier plate.

[0071] When using a lithography machine with a large exposure field (e.g., 50 mm × 50 mm), the lithography method provided in this application can achieve high-density interconnection of large substrates at the decimeter level. It should be noted that high-density optical interconnection between chips is a key link in solving communication between chips and between cards. Using the lithography method provided in this application, corresponding optical communication lines can be fabricated, and the fabricated optical communication lines have the advantages of narrow linewidth and high precision.

[0072] The substrate 500 may also be loaded with one or more of the following: a silicon substrate, a germanium substrate, a compound semiconductor substrate, and a carrier plate. The longitudinal dimensions of individual original patterned units existing on the silicon substrate, germanium substrate, and compound semiconductor substrate may be the same or different, and the lateral dimensions of individual original patterned units existing on the silicon substrate, germanium substrate, and compound semiconductor substrate may be the same or different.

[0073] In this way, mounting multiple small silicon wafers or small carrier boards on a large carrier board can improve efficiency. Furthermore, mounting small silicon wafers or small carrier boards of different models on a large carrier board can achieve high-density interconnection of different models of small silicon wafers or small carrier boards in the form of large-size chips.

[0074] When the substrate 500 is a structure on which multiple silicon substrates, multiple germanium substrates, multiple compound semiconductor substrates, or multiple carrier plates are mounted on the substrate 502, the silicon substrates may be the same or different, and / or the germanium substrates may be the same or different, and / or the compound semiconductors may be the same or different, and / or the carrier plates may be the same or different. The silicon substrates, germanium substrates, compound semiconductor substrates, and carrier plates can be placed according to actual needs, and this application does not impose any restrictions on this.

[0075] The size of the carrier plate can be from 40 mm to 4000 mm. For example, the size of the carrier plate can be one of 40 mm, 80 mm, 100 mm, 150 mm, 300 mm, 600 mm, 1200 mm, 2400 mm, 3000 mm, 3600 mm or 4000 mm.

[0076] It should be noted that since the projection lens used in this embodiment is a conventional reduced-magnification projection lens, the lines it produces are finer and the alignment accuracy is higher. In this case, to prevent multiple silicon substrates, germanium substrates, compound semiconductor substrates, and carriers from failing to connect, the silicon substrates, germanium substrates, compound semiconductor substrates, and carriers can be placed with high precision. This effectively avoids the problem of connection failure caused by only aligning a portion of the components while other components cannot be correctly aligned due to changes in their relative positions. Especially when processing silicon substrates, germanium substrates, compound semiconductor substrates, and carriers of different sizes, it is necessary to accurately determine the position of each component and fill the chip-free areas to ensure that the alignment accuracy meets actual requirements and to guarantee the stability of photoresist coating and exposure. If the chip-free areas are not filled, photoresist may seep into them during the photoresist coating process, resulting in uneven surfaces and affecting the quality of subsequent processes.

[0077] exist Figure 1 In the photolithography apparatus shown, the light source 100 forms an exposure beam through an illumination system. The exposure beam passes through the mask 200 and transfers the preset pattern on the mask 200 to the substrate 500 mounted on the stage 400 through a projection system 300. Then, photolithography is performed on the photoresist material to form an exposure field pattern.

[0078] It should be noted that if the light source 100 is an EUV light source, and the projection system 300 is a reflective projection system, such as... Figure 3 The diagram shown is a structural diagram of a lithography device based on an EUV light source provided in an embodiment of this application. Figure 3 In the lithography apparatus shown, the light source 100 forms an exposure beam through an illumination system. The exposure beam passes through the mask 200, and the preset pattern on the mask 200 is reflected onto the substrate 500 mounted on the stage 400 by a reflective projection system 300. Then, photolithography is performed on the photoresist material to form the exposure field pattern. This avoids the problem that extreme ultraviolet (EUV) light is easily absorbed by light-transmitting materials, preventing the exposure beam from reaching the substrate.

[0079] If the light source 100 is a mercury lamp or an excimer laser, the space between the projection system 300 and the substrate 500 is filled with an immersion liquid (such as deionized water). Compared to the traditional photolithography method where the exposure beam directly reaches the silicon wafer surface from the projection system, this embodiment increases the refractive index of the medium by filling with an immersion liquid, thereby increasing the numerical aperture NA of the optical system and reducing the minimum pattern size.

[0080] The existing patterned unit on the substrate 500 can be one or more of the following: integrated circuit pattern, optical path pattern, microfluidic path, metal wiring, and sensor pattern. The integrated circuit pattern can be a single integrated circuit pattern unit. The size of a single integrated circuit pattern unit is less than 26mm × 33mm (e.g., 25mm × 32mm), and the specific size can be determined according to actual needs; no limitation is imposed here.

[0081] The type of integrated circuit may include, but is not limited to, at least one of integrated circuits integrating electrical functions, integrated circuits integrating optical-optoelectronic functions, and integrated circuits integrating sensor functions. In other words, the photolithography technology provided in this application embodiment can be applied to all of the above-mentioned integrated circuits to achieve large-area, high-density interconnection of the chip. The type of integrated circuit can be selected according to actual needs, and this application does not specifically limit it.

[0082] The integrated circuit can be an integrated circuit with or without completed bonding pad (PAD) fabrication. In other words, the photolithography method provided in this application is applicable to integrated circuits with or without bonding pads. It should be noted that initially, some bonding pads may already exist on the chip. These bonding pads are mainly used for internal interconnection or preliminary external connections. However, as the number of chips increases and the interconnection density improves, the existing bonding pads may be insufficient to meet all external connection requirements. Therefore, after completing the high-density free interconnection of M×N chips, bonding pads can be further fabricated. The photolithography method provided in this application can generate a certain number of bonding pads while completing high-density chip interconnection, which not only simplifies the process flow but also reduces the number of pattern fabrication layers, thereby reducing manufacturing costs and time consumption.

[0083] The integrated circuit pattern can be a single-layer integrated circuit pattern or a multi-layer integrated circuit pattern. As 3D integrated circuit technology matures, the photolithography method provided in this application can also be applied to chips with stacked multi-layer integrated circuits. In other words, the method provided in this application can be effectively implemented even under complex structures formed after multi-layer circuit integration.

[0084] In the multi-layer pattern, the materials of the patterns in different layers can be the same or different. In this way, silicon-based, silicon-compound semiconductor, silicon-carbon semiconductor, or silicon-germanium silicon semiconductor can be integrated together to obtain complex large chips.

[0085] The integrated circuits in the existing patterned units on the substrate to be exposed in the photolithography implementation method provided in this application can be integrated circuits that have completed both the front end of line (FEOL) and back end of line (BEOL) processes, and / or integrated circuits that have partially completed both the front end of line (FEOL) and back end of line (BEOL) processes. The specific process step from which to begin can be selected according to actual needs to achieve the desired effect.

[0086] The substrate 500 also includes a primary alignment device 510, which is used to perform preliminary alignment of the substrate. It should be noted that when the substrate 500 does not have a primary alignment device 510, alignment can also be performed by means of the shape of the substrate itself.

[0087] like Figure 4 The diagram shown is a structural diagram of another example of the photolithography equipment used in the implementation method of the photolithography technology provided in this application embodiment. The photolithography equipment includes one stage (e.g., stage 410), two stages (e.g., stages 410, 430), three stages (e.g., stages 410, 420, 430), or four stages (e.g., stages 410, 420, 430, 440). When there are two stages (e.g., stages 410 and 430), both stages are loaded with the silicon substrate, the germanium substrate, the compound semiconductor substrate, or the carrier plate. Figure 4 In the example, stage 410 holds substrate 1500, and stage 430 holds substrate 3500. The two stages alternately move under projection system 310 to complete exposure. Furthermore, when there are two stages, the lithography apparatus is equipped with a separate silicon wafer measurement system 930.

[0088] Furthermore, such as Figure 4 As shown, the photolithography equipment includes two mask stages, one corresponding to mask 210 and the other to mask 220. Each mask stage is equipped with an independent projection system. Figure 4 In the example, the worktable corresponding to mask 210 corresponds to projection system 310, and the worktable corresponding to mask 220 corresponds to projection system 320.

[0089] In the case where the photolithography equipment includes two mask stages and includes one stage (e.g., stage 410), two stages (e.g., stages 410, 430), three stages (e.g., stages 410, 420, 430), or four stages (e.g., stages 410, 420, 430, 440), the one, two, three, or four stages are respectively moved to the projection systems corresponding to the two mask stages (as shown in the attached diagram). Figure 4 Exposure under projection systems 310 and 320.

[0090] Furthermore, such as Figure 4 As shown, when the photolithography equipment includes two mask stages and three stages (such as stage 410, stage 420, and stage 430) or four stages (such as stage 410, stage 420, stage 430, and stage 440), the photolithography equipment further includes two upper and lower silicon wafer systems (respectively attached). Figure 4 (101 and 102 in the middle) and two silicon wafer measurement systems (attached respectively) Figure 4 (Silicon wafer measurement system 930 and silicon wafer measurement system 940).

[0091] In contrast, in the case of only one silicon wafer measurement system (such as silicon wafer measurement system 930), assuming there are three stages (such as stage 410, stage 420, and stage 430), with stage 410 and stage 420 having their wiring in front and stage 430 having its wiring in the back, since there is only one silicon wafer measurement system, the wiring system needs to be bypassed. Stage 410 needs to be moved to the left of silicon wafer measurement system 930 so that stage 420 can be moved to the measurement position. If stage 410 is moved below projection system 320, then stage 420 needs to be moved to the right of projection system 320.

[0092] Using two upper and lower silicon wafer systems (e.g., upper and lower silicon wafer systems 101 and 102) and two silicon wafer measurement systems (e.g., silicon wafer measurement systems 930 and 940), and taking four stages (e.g., stages 410, 420, 430, and 440) as an example, stages 430 and 410 utilize silicon wafer measurement system 930 and upper and lower silicon wafer systems 101, with the wiring system positioned one in front (stage 430) and one behind (stage 410); stages 440 and 420 utilize silicon wafer measurement system 940 and upper and lower silicon wafer systems 102, with the wiring system positioned one in front (stage 420) and one behind (stage 440). Throughout the process, the photomasks (e.g., photomasks 210 and 220) and projection systems (e.g., projection systems 310 and 320) are shared resources. By using reasonable stage rotation and path planning, it can be ensured that each stage can smoothly perform measurement, film loading and unloading preparation, and projection exposure operations without interruption or delay due to path conflicts.

[0093] It is evident that when the lithography equipment includes two mask worktables and three or four stages, and when the lithography equipment includes two upper and lower silicon wafer systems and two silicon wafer measurement systems, mutual interference between the wiring systems can be effectively avoided, thereby improving the flexibility and efficiency of the lithography equipment and ensuring that each stage can smoothly perform measurement, preparation, and projection exposure actions.

[0094] It should be understood that the left, right, front, and back mentioned above are all relative, and in actual operation, the platform runs on platform 10.

[0095] It should be noted that in this embodiment, multiple photomasks are exposed on the same layer of photoresist to achieve various different patterns. In the conventional approach, only one photomask is needed on the same layer of photoresist, eliminating the need for multiple photomasks to achieve various different patterns on a single layer of photoresist.

[0096] The above is an introduction to the photolithography equipment provided in the embodiments of this application.

[0097] It should be noted that the photolithography method provided in this application is mainly used to solve the interconnection between multiple large chips smaller than the exposure field limit of traditional integrated circuits (approximately 26mm*33mm). It enables high-density interconnection of multiple chips while maintaining the same exposure field size, thereby efficiently fabricating chips larger than those fabricated by traditional photolithography methods, or fabricating substrates with higher line density while ensuring a large area compared to traditional substrate fabrication methods. These are the inherent intentions of this application and will not be elaborated upon here.

[0098] The technical solution of this application will be described in detail below through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0099] like Figure 5 The diagram shown is a flowchart of a method for implementing a multi-chip high-density interconnect lithography technology provided in this application embodiment. This method is used to realize the interconnection of M×N chips and includes the following steps S101~S104.

[0100] Step S101: Load the substrate to be exposed, which has the original patterned units, onto the stage of the photolithography equipment, and perform the first alignment using the first alignment mark on the substrate.

[0101] This step is used to initially position the substrate when it is initially loaded onto the stage with the original patterned units.

[0102] The original pattern unit generally refers to a single integrated circuit (e.g., 25mm*32mm) that is slightly smaller than the maximum exposure field size (approximately 26mm*33mm) of a traditional lithography machine (e.g., a DUV (deep ultraviolet) lithography machine). The original pattern unit can be a single-exposure pattern formed using a projection system with a reduction ratio of 4 to 10 times or other ratios. For example, the original pattern unit is a single-exposure pattern formed using a projection system with a reduction ratio of 4 times; another example is a single-exposure pattern formed using a projection system with a reduction ratio of 5 times; yet another example is a single-exposure pattern formed using a projection system with a reduction ratio of 8 times; and yet another example is a single-exposure pattern formed using a projection system with a reduction ratio of 10 times. Taking a reduction ratio of 5 times for the projection system as an example, after synchronous scanning movement of the lithography machine's workpiece stage and mask stage, the maximum exposure field size is generally 26mm×33mm. In this case, the maximum size of the original pattern unit is generally less than or equal to 26mm×33mm.

[0103] It should be noted that the 26mm×33mm mentioned above is a special example. In reality, the original graphic unit is generally slightly smaller than 26mm×33mm, such as 25mm×32mm, etc.

[0104] Optionally, prior to step S101, the implementation method of multi-chip high-density interconnect lithography technology provided in this application embodiment may further include the following steps: using the inherent features of the substrate or a primary alignment device on the substrate (attached) Figure 1 Appendix Figure 2 and appendix Figure 6 The substrate is initially positioned using 510.

[0105] The substrate has a first alignment mark (as shown in the attached image). Figure 6 The alignment mark 520 shown, taking a NIKON lithography machine as an example, can be a laser step alignment mark (LSA) and / or a field image alignment mark (FIA), or an alignment mark designed for the alignment system of the lithography equipment involved in this application. One or more first alignment marks can be provided on the substrate, and the first alignment marks can be provided in the dicing track to avoid affecting the functional areas of the chip.

[0106] Specifically, before photolithography begins, the substrate to be exposed is transferred from the carrier to the stage of the photolithography equipment by a robotic arm or vacuum adsorption system. At this time, the substrate is roughly placed at a certain position on the stage. Then, the substrate is scanned by a high-resolution camera or other sensors installed on the photolithography equipment, and preliminary alignment is performed by the primary alignment device 510 or the shape characteristics of the substrate itself. After that, the substrate is precisely aligned by one or more first alignment marks to prepare for exposure.

[0107] Step S102: For the first M×N chip group on the substrate, select the first mask, align the first mask with the first original pattern unit in the M×N chip group through the second alignment mark on the substrate, perform exposure, and transfer the pattern of the first mask to the exposure area covering the first original pattern unit.

[0108] This step is used to precisely align the first existing pattern unit in the first M×N chip group on the substrate with the first mask after the substrate has been initially positioned.

[0109] An M×N chipset refers to a chip region on the substrate that contains M original pattern units vertically and N original pattern units horizontally. M and N are both integers greater than or equal to 1, and at least one of M and N is greater than or equal to 2. M and N can be one of 1, 2, 3, 4, 5, etc. M and N can be the same or different; this application does not limit the specific values ​​of M and N. For example, to interconnect two chips horizontally, M can be equal to 1 and N equal to 2; to interconnect three chips horizontally, M can be equal to 1 and N equal to 3; to interconnect two chips vertically, M can be equal to 2 and N equal to 1; to interconnect four chips arranged in a 2×2 matrix (i.e., two chips horizontally and two chips vertically), M can be equal to 2 and N equal to 2; to interconnect 12 chips arranged in a 4×3 matrix (i.e., four chips horizontally and three chips vertically), M can be equal to 4 and N equal to 3.

[0110] It should be noted that the substrate may include multiple M×N chip groups, each of which includes original graphic units arranged in an M-row N-column matrix.

[0111] Combined with appendix Figure 10 The substrate includes multiple 4×3 chipsets arranged in a 4x3 matrix, namely 4×3 chipset 101, 4×3 chipset 102, 4×3 chipset 103, and 4×3 chipset 104. It should be understood that... Figure 10 This example is provided for the convenience of illustrating M=4 and N=3, and is not intended to limit this application.

[0112] It should be noted that the colored exposure areas in the accompanying drawings provided in this application are provided for the purpose of making the distinctions clearer and are not intended to limit this application.

[0113] In a specific implementation, the first M×N chipset can be any one of the plurality of M×N chipsets included on the substrate. Generally speaking, the first existing graphic unit is the existing graphic unit at the upper left, upper right, lower left, or lower right corner of the first M×N chipset. For example, the first M×N chipset can be an attached... Figure 10 Any one of 101, 102, 103, and 104 in the above. An M×N chipset can be selected from the substrate as the first M×N chipset according to actual needs.

[0114] like Figure 6 The diagram shown is an example of a first M×N chipset in the implementation method of multi-chip high-density interconnect lithography technology provided in this application. The first M×N chipset may include original patterning units 610, 620, 630, and 640; the first original patterning unit may be original patterning unit 610, 620, 630, or 640. It should be understood that... Figure 6 The example shown is for the convenience of illustrating M=2 and N=2, and is not intended to limit this application.

[0115] It should be noted that the colored exposure areas in the accompanying drawings provided in this application are provided for the purpose of making the distinctions clearer and are not intended to limit this application.

[0116] The substrate has a second alignment mark (as shown in the attached image). Figure 6Similar to the first alignment mark (530 shown), the second alignment mark can be a laser step alignment mark (LSA) and / or a field image alignment mark (FIA), or an alignment mark designed for the alignment system of the lithography equipment involved in this application. One or more second alignment marks can be provided on the substrate, and the second alignment marks can be provided in the dicing track to avoid affecting the functional areas of the chip.

[0117] Specifically, the substrate is moved by controlling the stage to send the area to be exposed on the substrate to the projection system, and the first mask is precisely aligned with the first original graphic unit in the first M×N chip group by one or more second alignment marks on the substrate.

[0118] It should be noted that, because the lithography machine used in this application has a different exposure field size than the lithography machine used to create the original pattern, there is generally an alignment offset problem. Therefore, it is necessary to pre-set the offset distance and align and expose according to the offset position during exposure. That is, before performing exposure, the substrate or the mask selected for performing the exposure (the first mask in step S102) is offset by a preset offset distance. It should be noted that the offset distance can be set in the silicon wafer alignment offset, the mask alignment offset, or a portion can be set for both the silicon wafer and the mask; all of these methods can achieve the desired offset distance.

[0119] In an optional implementation, when the second alignment mark is the alignment mark corresponding to the original graphic unit, the substrate or the mask selected for performing the exposure is preset with a corresponding offset distance. The above-mentioned step of "offsetting the substrate or the mask selected for performing the exposure by the preset offset distance" can be implemented by the following steps: when the mask selected for performing the exposure is loaded onto the mask stage, the mask selected for performing the exposure is offset by the preset offset distance; or the substrate is offset by the preset offset distance.

[0120] In this embodiment, the mask selected for each exposure has a preset offset distance. That is, the first mask selected for exposure in step S102 has a preset offset distance, and the other masks selected for exposure in subsequent steps also have their own preset offset distances. Each of the first mask and the other masks is an independent mask, and the offset distances corresponding to different masks are not necessarily the same.

[0121] In one implementation, the mask selected for the exposure can be offset by a corresponding offset distance when it is loaded onto the mask stage. Specifically, if the mask selected for the exposure is the first mask, it is offset by its corresponding offset distance when loaded onto the mask stage; if the mask selected for the exposure is the second mask among other masks, it is offset by its corresponding offset distance when loaded onto the mask stage; if the mask selected for the exposure is the third mask among other masks, it is offset by its corresponding offset distance when loaded onto the mask stage; and so on.

[0122] In another implementation, after aligning the mask selected for exposure with the corresponding original pattern unit using a second alignment mark on the substrate, the substrate can be biased by a preset offset distance. Specifically, if the mask selected for exposure is the first mask, after aligning the first mask with the first original pattern unit of the first M×N chip group using the second alignment mark on the substrate, the substrate is biased by a preset offset distance; if the mask selected for exposure is the second mask among the other masks, after aligning the second mask with the second original pattern unit of the first M×N chip group using the second alignment mark on the substrate, the substrate is biased by a preset offset distance; if the mask selected for exposure is the third mask among the other masks, after aligning the third mask with the third original pattern unit of the first M×N chip group using the second alignment mark on the substrate, the substrate is biased by a preset offset distance; and so on.

[0123] Thus, by biasing the mask selected for exposure or the substrate, a preset offset distance can be achieved between the mask selected for exposure and the substrate, thereby transferring the pattern on the mask selected for exposure to the exposure area to be exposed.

[0124] In another alternative implementation, where the second alignment mark on the substrate is an alignment mark for the exposure setting to be performed, the set offset distance is 0.

[0125] In another optional implementation, the set offset distance is 0 when the relative positional relationship between the position of the mask pattern of the selected mask in the mask and the position of the mask pattern of the original mask in the original mask is the same as the positional relationship between the exposure area to be formed and the original pattern unit covered by the exposure area to be formed; wherein, the original mask is the mask used to create the original pattern unit.

[0126] In this embodiment, the mask pattern is offset during mask fabrication. Furthermore, the relative positional relationship between the position of the mask pattern of the selected mask and the position of the original mask (which can be determined based on the center of the selected mask relative to the center of the selected mask, and the center of the original mask relative to the center of the original mask) is the same as the positional relationship between the exposure area to be formed and the original pattern units covered by that exposure area (which can be determined based on the center of the exposure area to be formed relative to the center of the original pattern units covered by that exposure area). In this case, when aligning the mask and substrate subsequently, a certain offset already exists between them; therefore, no further offset is required, i.e., the set offset distance is 0.

[0127] like Figure 7 The diagram illustrates an example of the relative positional relationship between the original mask and the mask selected for exposure, and the positional relationship between the exposure area to be formed during exposure and the original pattern unit covered by the exposure area, in the implementation method of multi-chip high-density interconnect lithography technology provided in this application embodiment. Specifically, the center of the mask pattern 203 on the original mask 201 is aligned with the set center of the original mask 201, while the center of the mask pattern 204 on the mask selected for exposure is slightly lower than the set center of the mask 202 (the set centers of masks 201 and 202 follow the same rule according to the lithography machine model). This ensures that, without misalignment, the positional relationship between the exposure area 720 to be formed during exposure and the original pattern unit 620 covered by the exposure area 720 is such that the area 726 of the exposure area 720 corresponding to the original pattern unit 620 overlaps with the original pattern unit 620. That is, the relative positional relationship between the mask pattern 204 and the mask pattern 203 is the same as the positional relationship between the exposure area 720 to be formed during exposure and the original pattern unit 620 covered by the exposure area 720. At this time, the set offset distance is 0.

[0128] Thus, by employing the methods described above, whether through conventional mask fabrication methods or improved mask fabrication methods (mask pattern placement offset), before exposure is performed, the first mask can be aligned with the exposure area of ​​the first mask pattern to be transferred, covering the first original pattern unit, by aligning and offsetting by a preset offset distance. In this way, after exposure is performed, the pattern of the first mask can be transferred to the exposure area covering the first original pattern unit.

[0129] by Figure 6 For example, when the original graphic unit 620 is the first original graphic unit, the graphic of the first mask is transferred to the exposure area 720 covering the first original graphic unit.

[0130] Step S103: Move the substrate longitudinally by M times the longitudinal dimension of a single original pattern unit, or laterally by N times the lateral dimension of a single original pattern unit, and repeat the alignment and exposure steps to complete the exposure of the exposure areas of the pattern units corresponding to the first original pattern unit in the other M×N chipsets on the substrate.

[0131] This step is used to expose the exposure area of ​​the graphic unit corresponding to the first original graphic unit in other M×N chipsets on the substrate.

[0132] It should be noted that the positions of the graphics units corresponding to the first original graphics unit in other M×N chipsets are the same as the positions of the first original graphics unit in the first M×N chipset. For example, if the first original graphics unit is located in the upper left corner of the first M×N chipset, then the graphics units corresponding to the first original graphics unit in other M×N chipsets are located in the upper left corner of those other M×N chipsets; if the first original graphics unit is located in the upper right corner of the first M×N chipset, then the graphics units corresponding to the first original graphics unit in other M×N chipsets are located in the upper right corner of those other M×N chipsets; if the first original graphics unit is located in the lower left corner of the first M×N chipset, then the graphics units corresponding to the first original graphics unit in other M×N chipsets are located in the lower left corner of those other M×N chipsets; if the first original graphics unit is located in the lower right corner of the first M×N chipset, then the graphics units corresponding to the first original graphics unit in other M×N chipsets are located in the lower right corner of those other M×N chipsets.

[0133] It should be noted that the vertical dimension and horizontal dimension of the original graphic unit can be the same or different. For example, the vertical dimension of the original graphic unit is 25mm and the horizontal dimension is 32mm; or the vertical dimension and horizontal dimension of the original graphic unit are both 25mm.

[0134] like Figure 8 The diagram shown is an example of the exposure area formed by N times lateral step exposure and M times vertical step exposure in the implementation method of multi-chip high-density interconnect lithography technology provided in this application embodiment. Figure 8 The example given uses M = 4 and N = 3. Specifically:

[0135] First, a first mask is selected to form an exposure area 207 on the substrate that covers the first original graphic unit 01 in the first 4×3 chipset;

[0136] After exposure in exposure area 207 is completed, the substrate is moved longitudinally by four times the longitudinal dimension of a single original pattern unit. The steps of aligning the substrate with the pattern unit 41 in the second 4×3 chip group (located longitudinally in the first 4×3 chip group and adjacent to the first 4×3 chip group) corresponding to the first original pattern unit 01, offsetting by a preset offset distance, and then exposing are repeated, thereby transferring the first mask pattern to cover the exposure of the pattern unit 41 in the second 4×3 chip group corresponding to the first original pattern unit 01. Region 209; or, move the substrate laterally by 3 times the lateral dimension of a single original pattern unit, and repeat the steps of aligning the substrate with the pattern unit 04 in the third 4×3 chip group that corresponds to the first original pattern unit 01 in the lateral direction of the first 4×3 chip group and adjacent to the first 4×3 chip group by the second alignment mark on the substrate, and offset by a preset offset distance and exposure, thereby transferring the first mask pattern to the exposure area 208 covering the pattern unit 04 in the third 4×3 chip group that corresponds to the first original pattern unit 01;

[0137] After exposure in exposure area 209 is completed, the substrate is moved longitudinally by four times the longitudinal dimension of a single original pattern unit. The steps of aligning the substrate with the pattern unit 81 in the fourth 4×3 chip group (located longitudinally in the second 4×3 chip group and adjacent to the second 4×3 chip group) corresponding to the first original pattern unit 01, offsetting by a preset offset distance, and exposure are repeated, thereby transferring the first mask pattern to the exposure area covering the pattern unit 81 in the fourth 4×3 chip group corresponding to the first original pattern unit 01. Domain 211; or, move the substrate laterally by 3 times the lateral step distance of a single original pattern unit, and repeatedly perform the steps of aligning the substrate with the pattern unit 44 in the fifth 4×3 chip group that is laterally located in the second 4×3 chip group and adjacent to the second 4×3 chip group, and offset by a preset offset distance and exposure, thereby transferring the first mask pattern to the exposure area 210 covering the pattern unit 44 in the fifth 4×3 chip group that is corresponding to the first original pattern unit 01;

[0138] After exposure areas 208, 209, 210 and 211 are exposed, the steps of vertically moving M times the vertical dimension of a single original graphic unit or horizontally moving N times the horizontal dimension of a single original graphic unit, alignment, offsetting by a preset offset distance and exposure are repeated to transfer the graphic of the first mask to the exposure area of ​​the graphic unit corresponding to the first original graphic unit 01 in other 4×3 chipsets.

[0139] Step S104: Select other photomasks, repeat exposure on the corresponding graphic units other than the first original graphic unit of the first M×N chip group, and repeat vertical movement by M times the vertical dimension of a single original graphic unit or horizontal movement by N times the horizontal dimension of a single original graphic unit to complete the exposure of the corresponding areas of other corresponding graphic units in other M×N chip groups on the substrate.

[0140] This step is used to expose the corresponding areas of other masking masks on the first M×N chipset, excluding the first original graphic unit, as well as the corresponding areas of other M×N chipsets, excluding the graphic unit corresponding to the first original graphic unit.

[0141] Other masks refer to independent masks that are different from the first mask. The total number of other masks and the first mask is usually M×N. That is, to achieve a 2×1 chip interconnect, a total of 2 masks are needed; to achieve a 2×2 chip interconnect, a total of 4 masks are needed; to achieve a 3×2 chip interconnect, a total of 6 masks are needed; and to achieve a 4×3 chip interconnect, a total of 12 masks are needed.

[0142] Optionally, the first mask and the other masks are independent, and the second mask among the first mask and the other masks are respectively mounted on the mask stage of different lithography machines.

[0143] Optionally, a lithography apparatus may include multiple mask stages, with the first mask and the second mask respectively mounted on different mask stages of the same lithography apparatus.

[0144] Optionally, a photolithography apparatus may include a mask stage. After the first mask is loaded onto the mask stage and a preset batch of exposures is completed, the first mask is unloaded from the mask stage, and the second mask is loaded onto the mask stage.

[0145] In practical implementation, firstly, select the second mask from other mask templates, and repeat the process for the second original graphic unit of the first M×N chipset (as shown in the attached image). Figure 6 The original graphic unit 640 shown performs exposure to form the corresponding exposure area (as shown in the attached image). Figure 6 As shown in 740), and by repeatedly performing a vertical movement of M times the vertical dimension of a single original graphic unit, or a horizontal movement of N times the horizontal dimension of a single original graphic unit, the second mask is used to expose the area corresponding to the graphic unit in the other M×N chipset on the substrate that corresponds to the second original graphic unit.

[0146] Then, select the third mask from other masks, and repeatedly perform exposure on the third original pattern unit of the first M×N chip group, and repeatedly perform vertical movement M times the vertical dimension of a single original pattern unit, or horizontal movement N times the horizontal dimension of a single original pattern unit, to complete the exposure of the area corresponding to the pattern unit of the third mask in other M×N chip groups on the substrate that corresponds to the third original pattern unit.

[0147] Then, select the fourth mask from other masks, and repeatedly perform exposure on the fourth original pattern unit of the first M×N chip group, and repeatedly perform vertical movement M times the vertical dimension of a single original pattern unit, or horizontal movement N times the horizontal dimension of a single original pattern unit, to complete the exposure of the area corresponding to the pattern unit of the fourth mask in other M×N chip groups on the substrate that corresponds to the fourth original pattern unit.

[0148] ...and so on, until the M×Nth mask in other masks is selected, and the exposure of the M×Nth original pattern unit of the first M×N chip group is repeated, and the vertical dimension of a single original pattern unit is moved by M times, or the horizontal dimension of a single original pattern unit is moved by N times, to complete the exposure of the area corresponding to the pattern unit of the M×Nth original pattern unit in other M×N chip groups on the substrate.

[0149] like Figure 9 The diagram shown is an example of the exposure area formed by N times lateral step exposure and M times vertical step exposure in the implementation method of multi-chip high-density interconnect lithography technology provided in this application embodiment. Figure 9 The example given uses M = 4 and N = 3. Specifically:

[0150] After the first mask is exposed on the substrate, the second mask among the other masks is selected to form an exposure area 216 on the substrate covering the second original pattern unit 11 in the first 4×3 chipset.

[0151] After exposure in exposure area 216 is completed, the substrate is moved longitudinally by four times the longitudinal dimension of a single original pattern unit. The steps of aligning the substrate with the pattern unit 51 corresponding to the second original pattern unit 11 in the second 4×3 chip group (located longitudinally in the first 4×3 chip group and adjacent to the first 4×3 chip group) using the second alignment mark on the substrate, offsetting by a preset offset distance, and then exposing are repeated. This transfers the second mask pattern to cover the exposure of the pattern unit 51 corresponding to the second original pattern unit 11 in the second 4×3 chip group. Region 218; or, move the substrate laterally by 3 times the lateral dimension of a single original pattern unit, and repeat the steps of aligning the substrate with the pattern unit 14 corresponding to the second original pattern unit 11 in the third 4×3 chip group located laterally on the first 4×3 chip group and adjacent to the first 4×3 chip group by the second alignment mark on the substrate, and offset by a preset offset distance and exposure, thereby transferring the second mask pattern to the exposure area 217 covering the pattern unit 14 corresponding to the second original pattern unit 11 in the third 4×3 chip group;

[0152] After exposure in exposure area 218 is completed, the substrate is moved longitudinally by four times the longitudinal dimension of a single original pattern unit. The steps of aligning the substrate with the pattern unit 91 corresponding to the second original pattern unit 11 in the fourth 4×3 chip group (located longitudinally in the second 4×3 chip group and adjacent to the second 4×3 chip group) using the second alignment mark on the substrate, offsetting by a preset offset distance, and then exposing are repeated. This transfers the second mask pattern to cover the exposure of the pattern unit 91 corresponding to the second original pattern unit 11 in the fourth 4×3 chip group. Region 221; or, move the substrate laterally by 3 times the lateral dimension of a single original pattern unit, and repeat the steps of aligning the substrate with the pattern unit 54 in the fifth 4×3 chip group that corresponds to the second original pattern unit 11 in the lateral direction of the second 4×3 chip group and adjacent to the second 4×3 chip group by the second alignment mark on the substrate, and offset by a preset offset distance and exposure, thereby transferring the second mask pattern to the exposure area 219 covering the pattern unit 54 in the fifth 4×3 chip group that corresponds to the second original pattern unit 01;

[0153] After exposure areas 217, 218, 219 and 221 are exposed, the steps of vertically moving M times the vertical dimension of a single original graphic unit or horizontally moving N times the horizontal dimension of a single original graphic unit, alignment, offsetting by a preset offset distance and exposure are repeated to transfer the graphic of the second mask to the exposure area of ​​the graphic unit corresponding to the second original graphic unit 11 in other 4×3 chipsets.

[0154] After the second mask is exposed on the substrate, the third mask among the other masks is selected to form an exposure area 212 on the substrate that covers the third original pattern unit 02 in the first 4×3 chipset.

[0155] After exposure in exposure area 212 is completed, the substrate is moved longitudinally by four times the longitudinal dimension of a single original pattern unit. The steps of aligning the substrate with the pattern unit 42 in the second 4×3 chip group (located longitudinally in the first 4×3 chip group and adjacent to the first 4×3 chip group) corresponding to the third original pattern unit 02, offsetting by a preset offset distance, and then exposing are repeated. This transfers the third mask pattern to cover the exposure of the pattern unit 42 in the second 4×3 chip group corresponding to the third original pattern unit 02. Region 214; or, move the substrate laterally by 3 times the lateral dimension of a single original pattern unit, and repeat the steps of aligning the substrate with the pattern unit 05 corresponding to the third original pattern unit 02 in the third 4×3 chip group located laterally on the first 4×3 chip group and adjacent to the first 4×3 chip group by the second alignment mark on the substrate, and offset by a preset offset distance and exposure, thereby transferring the third mask pattern to the exposure area 213 covering the pattern unit 05 corresponding to the third original pattern unit 02 in the third 4×3 chip group;

[0156] After exposure in exposure area 214 is completed, the substrate is moved longitudinally by four times the longitudinal dimension of a single original pattern unit. The steps of aligning the substrate with the pattern unit 82 in the fourth 4×3 chip group (located longitudinally in the second 4×3 chip group and adjacent to the second 4×3 chip group) corresponding to the third original pattern unit 02, offsetting by a preset offset distance, and then exposing are repeated. This transfers the third mask pattern to cover the exposure of the pattern unit 82 in the fourth 4×3 chip group corresponding to the third original pattern unit 02. Region 220; or, move the substrate laterally by 3 times the lateral dimension of a single original pattern unit, and repeat the steps of aligning the substrate with the pattern unit 45 in the fifth 4×3 chip group that corresponds to the third original pattern unit 02 in the lateral direction of the second 4×3 chip group and adjacent to the second 4×3 chip group by the second alignment mark on the substrate, and offset by a preset offset distance and exposure, thereby transferring the third mask pattern to the exposure area 215 covering the pattern unit 45 in the fifth 4×3 chip group that corresponds to the third original pattern unit 02;

[0157] After exposure areas 213, 214, 215 and 220 are exposed, the steps of vertically moving M times the vertical dimension of a single original graphic unit or horizontally moving N times the horizontal dimension of a single original graphic unit, alignment, offsetting by a preset offset distance and exposure are repeated to transfer the graphic of the third mask to the exposure area of ​​the graphic unit corresponding to the third original graphic unit 02 in other 4×3 chipsets.

[0158] ...and so on, until the 12th mask is selected from other masks, and the exposure of the 12th original pattern unit of the first 4×3 chipset is repeated, and the vertical movement of the original pattern unit is repeated by 4 times or the horizontal movement of the original pattern unit is repeated by 3 times, so as to complete the exposure of the area of ​​the pattern unit corresponding to the 12th original pattern unit in the other 4×3 chipset on the substrate.

[0159] like Figure 10 The diagram shown illustrates an example of how multiple M×N chip groups complete inter-chip interconnection in the implementation method of the multi-chip high-density interconnect lithography technology provided in this application. It can be seen that after selecting 12 independent masks and performing alignment, offset by a preset offset distance, exposure, and vertical stepping of 4 times the vertical dimension of a single original pattern unit or horizontal stepping of 3 times the horizontal dimension of a single original pattern unit, and repeating the alignment, offset, exposure, vertical stepping, or horizontal stepping steps, multiple 4×3 chip groups completing inter-chip interconnection are formed on the substrate, namely 4×3 chip group 101, 4×3 chip group 102, 4×3 chip group 103, and 4×3 chip group 104.

[0160] This completes the interconnection between chips in the first M×N chipset, as well as the interconnection between chips in other M×N chipsets. In other words, it completes the interconnection between chips in multiple M×N chipsets. Furthermore, for any M×N chipset with completed inter-chip interconnections, there is an overlap between the exposure area covering any existing graphic unit and the exposure area of ​​its adjacent existing graphic units, as shown in the attached figure. Figure 6 As shown, there is an overlap region 721 between the exposure area 720 covering the original pattern unit 620 and the exposure area 740 covering the original pattern unit 640 adjacent to the original pattern unit 620. Furthermore, for any M×N chip group with completed inter-chip interconnection, there are no interconnect lines extending into and connecting the original pattern units on the scribe line of the connected M×N chips. The scribe line of the connected M×N chips refers to a narrow area around the edge of the connected M×N chips, mainly used to cut the connected M×N chips off the wafer after manufacturing. In other words, for any M×N chip group with completed inter-chip interconnection, no conductive lines penetrating into and electrically connecting to the M×N chip group will be arranged on its scribe line to protect the M×N chip group from damage that may occur during the scribe process. It should be noted that in this embodiment, the first mask and the other masks are exposed on the same layer of photoresist.

[0161] In this embodiment, the M×N chips are interconnected through the overlapping region. Furthermore, the overlapping region can be located on the existing graphics unit or on the scribe line; this application does not limit the specific location of the overlapping region.

[0162] Optionally, the existing patterned units of the substrate to be exposed may also include target patterned units, which are patterned units that cannot form M×N chip interconnects. To avoid waste, the target patterned unit can be exposed independently.

[0163] When the target pattern unit includes a first target pattern unit and at least one second target pattern unit, each target pattern unit can be exposed independently to avoid waste. The exposure method is as follows: Select a target mask, align the target mask with the first target pattern unit using a second alignment mark on the substrate, and offset it by a preset distance. Perform exposure to transfer the target mask pattern to the first target exposure area corresponding to the first target pattern unit. For each second target pattern unit, move the substrate to the second target pattern unit, repeat the alignment, offset, and exposure process, and transfer the target mask pattern to the second target exposure area corresponding to the second target pattern unit. The target mask is one of the first mask, the other masks, or a mask made for the target pattern unit. The first target exposure area has no interconnect lines extending into the original pattern unit and connecting to it on the scribe line of the first target pattern unit. The second target exposure area has no interconnect lines extending into the original pattern unit and connecting to it on the scribe line of the second target pattern unit.

[0164] Optionally, the dicing paths of the first and second target exposure areas may include measurement patterns for monitoring and evaluating various parameters (such as linewidth, layer thickness, and resistivity) during the manufacturing process. In this embodiment, the target pattern unit may include multiple target pattern units. For example, if the substrate has 13×11 existing pattern units, and chip interconnection in a 4×3 chipset is required, then 3×3 interconnection operations in a 4×3 chipset will be completed. At this point, 35 chips remain on the substrate, and these 35 chips can be exposed independently.

[0165] like Figure 11The diagram shown is an example of a target patterning unit in the implementation method of multi-chip high-density interconnect lithography technology provided in this application embodiment. After completing the inter-chip interconnection of multiple 4×3 chip groups, the substrate also includes multiple target patterning units, namely i1, i2, i3, i4, i5, i6, ... 0j, 1j, 2j, 3j, 4j, 5j, 6j, 7j, ... ij. In this way, each of these multiple target patterning units can be exposed independently.

[0166] In this embodiment, the target mask used only covers the original patterned units after exposure, and there are no interconnecting lines extending into and connecting the original patterned units on the scribe line. That is, the size of the first target exposure area is the same as the size of the first target patterned unit. After the first target exposure area is exposed, no conductive lines penetrating into and electrically connecting to the first target patterned unit will be arranged on the scribe line surrounding the first target patterned unit to protect it from potential damage during the scribe process. Similarly, the size of the second target exposure area is the same as the size of the second target patterned unit. After the second target exposure area is exposed, no conductive lines penetrating into and electrically connecting to the second target patterned unit will be arranged on the scribe line surrounding the second target patterned unit to protect it from potential damage during the scribe process.

[0167] It should be noted that the M×N chip group interconnected on the substrate formed by this method has a different size from the target patterned unit. During dicing, the step distance setting of the cutting tool must be matched accordingly. If necessary, the target patterned unit needs to be diced a second time (small pieces with multiple target patterned units may require further dicing). Unlike the aforementioned longitudinal stepping of M times or lateral stepping of N times, after the first target patterned unit is exposed, the substrate is moved from the first target patterned unit to the second target patterned unit using a freely set step position, performing alignment and exposure steps, thereby achieving independent exposure of the first and second target patterned units respectively.

[0168] In one optional embodiment, there are one or two stages. When there are two stages, each stage is loaded with a substrate to be exposed. When there are two stages, multiple stages can be controlled to move in turn to the projection system to complete the exposure. By using this method of rotating to the projection system for exposure, one stage can perform other preparatory work while one stage is performing exposure, such as loading the substrate or performing preliminary substrate alignment. In one example, if the multiple stages include a first stage and a second stage, the second stage can be controlled to perform wafer loading / unloading and pre-alignment steps while the first stage is performing exposure. Pre-alignment here refers to preliminary alignment using alignment marks on the substrate to be exposed loaded on the second stage. For example, a lithography machine includes stage a and stage b. While stage a is performing alignment and exposure, stage b is controlled to perform wafer loading / unloading and pre-alignment steps. Correspondingly, while stage b is performing alignment and exposure, stage a is controlled to perform wafer loading / unloading and pre-alignment steps. In this way, after the first stage is exposed, the second stage can be started immediately, effectively reducing the time the lithography machine is idle. On the other hand, the time consumed by switching between stages is shorter than the time consumed by substrate replacement and preliminary alignment performed on a single stage, which can achieve a seamless workflow and thus improve lithography efficiency.

[0169] In this embodiment, the overlapping region is the region formed by the overlap of the first and second exposure regions corresponding to adjacent exposure regions of adjacent graphics units in an M×N chipset. The first exposure region may include a first line, a second line, and a third line; the second exposure region may include a fourth line, a fifth line, and a sixth line; the first line and the third line are connected, and the second line is connected to the third line; the fourth line and the sixth line are connected, and the sixth line and the fifth line are connected.

[0170] Wherein, the first line is a line in the first exposure area used to connect the first exposure area and the second exposure area; the fourth line is a line in the second exposure area used to connect the first exposure area and the second exposure area; the second line is a line formed in the overlapping area of ​​the first exposure area after expanding and shrinking the fourth line; the third line is a line in the first exposure area that strengthens the connection between the first exposure area and the second exposure area; the fifth line is a line formed in the overlapping area of ​​the second exposure area after expanding and shrinking the first line; and the sixth line is a line in the second exposure area that strengthens the connection between the first exposure area and the second exposure area.

[0171] It should be noted that the first, second, third, fourth, fifth, and sixth lines here refer to a patterned structure formed on the substrate surface through photolithography. Taking metal wires as an example, the first, second, third, fourth, fifth, and sixth lines refer to the portions not dissolved by the developer; that is, the first, second, third, fourth, fifth, and sixth lines are the portions retaining photoresist, representing a part of the future circuit layout, and do not actually form conductive paths. The actual conductive lines used to transmit current (such as copper wires) are formed through subsequent processes.

[0172] When a positive photoresist is used, the areas exposed to light undergo chemical changes during exposure, making them easier to dissolve in the developer. This means the photoresist in the exposed areas is removed, while the unexposed areas remain. When a negative photoresist is used, the areas exposed to light during exposure cross-link and solidify, becoming more difficult to dissolve in the developer. This means the unexposed photoresist is removed by the developer, while the exposed photoresist remains on the wafer. In this embodiment, when a positive photoresist is used, the mask lines on the corresponding photomasks for the first, second, third, fourth, fifth, and sixth lines are all dark. When a negative photoresist is used, the mask lines on the corresponding photomasks for the first, second, third, fourth, fifth, and sixth lines are all clear.

[0173] The following is through the appendix Figure 12 and attached Figure 13 Introducing lines one through six above:

[0174] like Figure 12 The diagram shown is a schematic representation of an example of the first line, second line, and third line in the implementation method of multi-chip high-density interconnect lithography technology provided in this application embodiment. The area of ​​the first exposure region in the overlapping region is the region formed by the boundary 2036 of the first exposure region and the line 20351 in the first exposure region corresponding to the boundary 2035 of the second exposure region. The first exposure region includes the first line 2021, the second line 2022, and the third line 2034. The second line 2022 is a line formed by expanding and shrinking the fourth line 2011 included in the second exposure region.

[0175] like Figure 13The diagram shown illustrates an example of the fourth, fifth, and sixth lines in the implementation method of the multi-chip high-density interconnect lithography technology provided in this application. The second exposure region within the overlapping region is the area enclosed by the boundary 2035 of the second exposure region and the line 20361 corresponding to the boundary 2036 of the first exposure region in the second exposure region. The second exposure region includes the fourth line 2011, the fifth line 2012, and the sixth line 2033. The fifth line 2012 is formed by expanding and contracting the first line 2021 included in the first exposure region. It can be seen that the second line has an expansion / contraction amount relative to the fourth line, and the fifth line has an expansion / contraction amount relative to the first line. That is, the width of the second line is greater than the width of the fourth line, and the width of the fifth line is greater than the width of the first line. Thus, when the first and second exposure regions are misaligned, the second line will not damage the fourth line, and the fifth line will not damage the first line, thereby avoiding the problem of the first and second exposure regions being unable to interconnect when misaligned. It should be noted that the expansion or contraction of the second line relative to the fourth line is greater than or equal to a preset alignment deviation limit between the first exposure area and the second exposure area; and the expansion or contraction of the fifth line relative to the first line is greater than or equal to the alignment deviation limit. For example, the expansion or contraction of the second line relative to the fourth line and the expansion or contraction of the fifth line relative to the first line can be 1.1 times, 1.2 times, or 1.5 times the preset alignment deviation limit between the first exposure area and the second exposure area.

[0176] like Figure 14 The diagram shown is a schematic representation of an example where the first exposure region and the second exposure region overlap in the implementation method of the multi-chip high-density interconnect lithography technology provided in this application embodiment. Figure 14This includes 14-a and 14-b. 14-a is a schematic diagram when the first and second exposure areas are perfectly aligned; 14-b is a schematic diagram when the first and second exposure areas are misaligned. Figure 203334-1 shows the overlapping portion of the third and sixth lines when the first and second exposure areas are aligned; Figure 203334-2 shows the overlapping portion of the third and sixth lines when the first and second exposure areas are misaligned. It can be seen that the size of Figure 203334-2 is smaller than that of Figure 203334-1. If the fifth line 2012 is not expanded or contracted, and only the original width of the first line 2021 is maintained, then when the first and second exposure areas are misaligned, the first line 2021 will appear outside the area of ​​the fifth line 2012, causing the first line 2021 in the first exposure area to be destroyed. Correspondingly, if the second line 2022 is not expanded or contracted, and only the original width of the fourth line 2011 is maintained, then when the first and second exposure areas are misaligned, the fourth line 2011 will appear outside the area of ​​the second line 2022, causing the fourth line 2011 in the second exposure area to be damaged. By expanding or contracting the second line 2022 and the fifth line 2012, even under misalignment, the fifth line 2012 still has a sufficiently wide unexposed photoresist, thus ensuring that the first line 2021 is within the coverage area of ​​the fifth line 2012. Correspondingly, the second line 2022 also has a sufficiently wide unexposed photoresist, thus ensuring that the fourth line 2011 is also within the coverage area of ​​the second line 2022, avoiding the risk of damaging the lines of the other's exposure area.

[0177] In this embodiment, the second line is set to have a scaling amount relative to the fourth line, and the fifth line is set to have a scaling amount relative to the first line. This avoids the line used to connect the first and second exposure areas being destroyed due to repeated exposure in the overlapping area when the first exposure area and the second exposure area are misaligned.

[0178] It should be noted that the second line is located within the overlapping region and does not extend beyond the boundary of the first exposure region within the overlapping region, and the fifth line is located within the overlapping region and does not extend beyond the boundary of the second exposure region within the overlapping region. (See attached image) Figure 12 and attached Figure 13For example, the second line 2022 does not exceed the boundary 2036 of the first exposure area in the overlapping area, and the fifth line 2012 does not exceed the boundary 2035 of the second exposure area in the overlapping area. That is, the area 20101 outside the boundary 2036 of the first exposure area in the overlapping area does not contain any line patterns from the first exposure area, and area 20101 is opaque; similarly, the area 20201 outside the boundary 2035 of the second exposure area in the overlapping area does not contain any line patterns from the second exposure area, and area 20201 is opaque. Thus, the patterns produced by the exposure of both the first and second exposure areas are within their respective boundaries, with the areas outside the boundaries being opaque, preventing damage to the exposed patterns.

[0179] In one optional embodiment, the first exposure region includes a plurality of first lines, a plurality of second lines, and a plurality of third lines; each pair of adjacent first lines has a first interval, each pair of adjacent second lines has a second interval, and each pair of adjacent third lines has a third interval. The second exposure region includes a plurality of fourth lines, a plurality of fifth lines, and a plurality of sixth lines; each pair of adjacent fourth lines has a fourth interval, each pair of adjacent fifth lines has a fifth interval, and each pair of adjacent sixth lines has a sixth interval.

[0180] like Figure 15 The diagram illustrates an example of a first exposure region comprising multiple sets of lines and a second exposure region comprising multiple sets of lines in an implementation of the multi-chip high-density interconnect lithography technology provided in this application. The first exposure region includes multiple first lines, namely first line 20211, first line 20212, and first line 20213; multiple second lines, namely second line 20221, second line 20222, and second line 20223; and multiple third lines, namely third line 20341, third line 20342, and third line 20343. The second exposure region includes multiple fourth lines, namely fourth line 20111, fourth line 20112, and fourth line 20113; multiple fifth lines, namely fifth line 20121, fifth line 20122, and fifth line 20123; and multiple sixth lines, namely sixth line 20331, sixth line 20332, and sixth line 20333.

[0181] There is a first gap between every two adjacent first lines, a second gap between every two adjacent second lines, and a third gap between every two adjacent third lines. Figure 15For example, the first intervals are 20161 and 20162, and the second intervals are 20181 and 20182. (Due to the appendix...) Figure 15 The second and third lines in the diagram have the same dimensions, and the third intervals are 20181 and 20182 respectively. There is a fourth interval between each pair of adjacent fourth lines, a fifth interval between each pair of adjacent fifth lines, and a sixth interval between each pair of adjacent sixth lines. (See attached diagram.) Figure 15 For example, the fourth intervals are 20151 and 20152, and the fifth intervals are 20171 and 20172. (Due to the appendix...) Figure 15 The fifth and sixth lines in the text have the same size, and the sixth interval is also 20171 and 20172 respectively.

[0182] Spacer regions 2018 and 2017 are light-transmitting areas. This means that the mask areas corresponding to spacer regions 2018 and 2017 are designed as light-transmitting areas to allow the light source to pass through. However, during dry etching, differences in the etching rate occur due to varying pattern densities of the etched structures. In high-density areas (such as dense lines or vias), gaseous reactants are easily "consumed," leading to a decrease in the local reaction rate. Conversely, in low-density areas (such as isolated features), reactants reach the surface more easily, resulting in a faster etching rate. This leads to slower etching in high-density areas and faster etching in low-density areas, resulting in inconsistent minimum critical dimensions and affecting device performance and consistency. To avoid this, spacer regions 2018 and 2017 can also be pattern-filled. This involves adding virtual graphics that do not affect functionality to spacer regions 2018 and 2017, thereby increasing the overall pattern density of spacer regions 2018 and 2017 and mitigating the effects of micro-load.

[0183] When the first exposure area and the second exposure area overlap vertically, the first interval is a horizontal interval, and the second and third intervals are vertical intervals. When the first exposure area and the second exposure area overlap horizontally, the first interval is a vertical interval, and the second and third intervals are horizontal intervals. When the first exposure area and the second exposure area overlap vertically, the fourth interval is a horizontal interval, and the fifth and sixth intervals are vertical intervals. When the first exposure area and the second exposure area overlap horizontally, the fourth interval is a vertical interval, and the fifth and sixth intervals are horizontal intervals. Furthermore, the first interval is greater than or equal to the minimum critical size of the lithography apparatus. The fourth interval is greater than or equal to the minimum critical size of the lithography apparatus.

[0184] When the size of the second line is greater than or equal to the size of the third line, the second interval is greater than or equal to a target value, where the target value is the maximum value among the minimum critical size of the lithography equipment and the alignment deviation limit between the first exposure area and the second exposure area. When the size of the second line is less than the size of the third line, the third interval is greater than or equal to the target value. When the size of the fifth line is greater than or equal to the size of the sixth line, the fifth interval is greater than or equal to the target value. When the size of the fifth line is less than the size of the sixth line, the sixth interval is greater than or equal to the target value. This prevents the influence of misalignment. On the one hand, the third line 2034 of the first exposure area and the sixth line 2033 of the second exposure area may be made thicker and / or longer. When made thicker, if the interval between the second lines is still greater than the target value, and the interval between the fifth lines is greater than the target value, the spacing between the third lines will become smaller. When the misalignment between the first exposure area and the second exposure area is close to the alignment deviation limit, the third line 2034 of the first exposure area and the sixth line 2033 of the second exposure area may overlap unexpectedly, producing additional overlapping patterns.

[0185] To fully utilize the overlapping area, the overlapping area can include a large number of lines. Specifically, the first exposure area includes multiple first line sets, and the second exposure area includes multiple second line sets; each first line set includes multiple first lines, multiple second lines, and multiple third lines; each second line set includes multiple fourth lines, multiple fifth lines, and multiple sixth lines; there is a first set interval between each pair of adjacent first line sets; and there is a second set interval between each pair of adjacent second line sets.

[0186] like Figure 16 The diagram illustrates an example of an implementation of the multi-chip high-density interconnect lithography technology provided in this application, where the overlapping region includes multiple sets of lines. It can be seen that the first exposure region includes multiple sets of first lines, with a first set interval between each pair of adjacent sets of first lines, namely first set interval 20141 and first set interval 20142; the second exposure region includes multiple sets of second lines, with a second set interval between each pair of adjacent sets of second lines, namely second set interval 20241 and second set interval 20242.

[0187] When the first exposure area and the second exposure area overlap vertically, both the first set interval and the second set interval are horizontal intervals. When the first exposure area and the second exposure area overlap horizontally, both the first set interval and the second set interval are vertical intervals.

[0188] Both the first set interval and the second set interval are greater than or equal to the target value. That is, both the first set interval and the second set interval are greater than or equal to the maximum value among the minimum critical size of the lithography equipment and the alignment deviation limit between the first exposure area and the second exposure area.

[0189] It should be noted that there is a difference in the lithography scale between the mask pattern and its actual exposure area on the substrate. The specific values ​​such as the size and spacing of each line need to be determined based on the mask pattern and the actual exposure area on the substrate, which can be determined based on the actual scale difference, and will not be elaborated here. The method for implementing multi-chip high-density interconnect lithography technology provided in the first embodiment of this application loads the substrate to be exposed, which has original pattern units, onto the stage of the lithography equipment, and performs a first alignment using a first alignment mark on the substrate; for a first M×N chip group on the substrate, a first mask is selected, and the first mask is aligned with the first original pattern unit in the first M×N chip group using a second alignment mark on the substrate, and exposure is performed to transfer the first mask pattern to the exposure area covering the first original pattern unit; the substrate is moved vertically by M times the vertical dimension of a single original pattern unit, or horizontally by N times the horizontal dimension of a single original pattern unit, and the alignment and exposure steps are repeated to complete the pattern units of the first mask in other M×N chip groups on the substrate corresponding to the first original pattern unit. The process involves exposing the first M×N chip group's exposure area; then, selecting other masks and repeatedly exposing the corresponding patterned units outside the first original patterned unit of the first M×N chip group, and repeatedly performing a vertical movement of M times the vertical dimension of a single original patterned unit, or a horizontal movement of N times the horizontal dimension of a single original patterned unit, thereby completing the exposure of the corresponding areas of other patterned units in other M×N chip groups on the substrate using other masks; and for any M×N chip group, there is an overlap between the exposure area covering any original patterned unit and the exposure area of ​​its adjacent original patterned unit; for any M×N chip group, there are no interconnect lines extending into the original patterned units and connecting the original patterned units on the scribe lines of the interconnected M×N chips; M and N are both integers greater than or equal to 1, and at least one of M and N is greater than or equal to 2. In this way, using multiple masks, high-density interconnection of multiple chips can be achieved without changing the exposure field size, thereby forming a large-size chip, providing photolithography support for high-density interconnection integration of multiple M×N large chips.

[0190] Furthermore, in existing technologies, chip interconnection is mainly achieved through on-board level interconnection. This method typically involves interconnecting chips via a circuit board after packaging, resulting in a complex structure and large size. During use, signals need to be transmitted through long circuit board paths, leading to significant signal delays. Long traces are also susceptible to electromagnetic interference, causing signal distortion. The longer traces and drive circuits also result in larger capacitive loads, inevitably increasing power consumption. Simultaneously, the larger trace and solder joint sizes limit the interconnection density between chips, and the need for larger communication drive circuits further restricts this density. In contrast, the multi-chip high-density interconnection photolithography method provided in this application enables chip-level interconnection. This allows multiple chips to be connected simultaneously during chip manufacturing. During use, the shortened interconnection distance significantly reduces signal transmission time, lowers the risk of signal distortion, improves signal integrity, and reduces parasitic loads, thereby reducing power consumption. Furthermore, this invention directly uses existing high-performance lithography machines (such as DUV lithography machines and EUV lithography machines) to perform chip interconnect lithography, with the smallest line size reaching 0.1um or even a few nm, which can greatly improve the density of chip interconnect lines, ultimately forming a large chip with high-density chip interconnects (such as M×N×25mm×32mm) formed by M×N large chips (such as 25mm×32mm).

[0191] The second embodiment of this application provides a method for implementing multi-chip high-density interconnect lithography technology, which is used to realize the interconnection of M×N chips.

[0192] Before introducing the implementation method of multi-chip high-density interconnect lithography technology provided in the second embodiment of this application, the application scenario of the implementation method of multi-chip high-density interconnect lithography technology provided in the second embodiment of this application will be introduced first: The second embodiment of this application can integrate different types of chips (such as GPU and high-speed memory) together and support optical communication access. Specifically, firstly, computing chips (such as GPU) and memory chips (such as DRAM) are cut and mounted on a carrier board. The carrier board may contain a portion of pre-designed interconnects for achieving preliminary electrical connections; then, the multi-chip high-density interconnect lithography technology implementation method provided in the second embodiment of this application is used to further interconnect the chips mounted on the carrier board.

[0193] The multi-chip high-density interconnect lithography method provided in the second embodiment of this application interconnects chips of different sizes (such as GPUs and DRAMs), allowing different functional modules to be optimized according to their specific needs and to work collaboratively through efficient interconnect technology. It has at least the following advantages: First, each chip can be optimized for its specific function. For example, a GPU may focus on computationally intensive tasks, while DRAM is designed to provide high-bandwidth memory access, ensuring that each component achieves optimal performance in its assigned task. Second, by interconnecting different types of chips, such as directly connecting a GPU to a cache or DRAM, data transmission latency can be significantly reduced, communication lines increased, and data transmission efficiency improved. Third, it effectively shortens data transmission distance and reduces energy loss caused by long-distance transmission.

[0194] The method for implementing multi-chip high-density interconnect lithography technology provided in the second embodiment of this application specifically includes the following steps: A substrate containing existing patterned units is loaded onto the stage of a lithography apparatus, and a first alignment is performed using a first alignment mark on the substrate; for a first M×N chip group on the substrate, a first mask is selected, and the first mask is aligned with the first existing patterned unit in the first M×N chip group using a second alignment mark on the substrate, and exposure is performed to transfer the pattern of the first mask to the exposure area covering the first existing patterned unit; the substrate is moved longitudinally by the sum of the longitudinal dimensions of M existing patterned units, or laterally by the sum of the lateral dimensions of N existing patterned units, and the alignment and exposure steps are repeated to complete the alignment of the patterned units corresponding to the first existing patterned unit in other M×N chip groups on the substrate. Exposure of the exposure area; selecting other masks, repeatedly exposing the corresponding graphic units other than the first original graphic unit of the first M×N chip group, and repeatedly performing the vertical movement of the sum of the vertical dimensions of M original graphic units or the horizontal movement of the sum of the horizontal dimensions of N original graphic units to complete the exposure of the corresponding areas of other corresponding graphic units in other M×N chip groups on the substrate; wherein, at least some of the original graphic units in the M×N chip group have different sizes; for any M×N chip group, the exposure area covering any original graphic unit and the exposure area of ​​the adjacent original graphic unit have overlapping areas; for any M×N chip group, there are no interconnect lines extending into the original graphic units and connecting the original graphic units on the dicing path of the connected M×N chips; at least M and N are integers greater than or equal to 2.

[0195] The steps described above, namely "loading the substrate containing the original patterned unit onto the stage of the photolithography equipment and performing a first alignment using the first alignment mark on the substrate" and "for the first M×N chip group on the substrate, selecting a first mask and aligning the first mask with the first original patterned unit in the first M×N chip group using the second alignment mark on the substrate, performing exposure, and transferring the pattern of the first mask to the exposure area covering the first original patterned unit," are the same as steps S101 and S102 in the first embodiment of this application, respectively. Please refer to the relevant description of the corresponding steps in the first embodiment of this application, which will not be repeated here.

[0196] The difference from the first embodiment of this application is that the original patterned units on the substrate in the multi-chip high-density interconnect lithography method provided in the first embodiment of this application all have the same size. However, in the second embodiment of this application, the original first patterned unit can be, for example, a GPU, the original second patterned unit can be, for example, a DRAM, and the original third patterned unit can be, for example, a communication module. The original first, second, and third patterned units may have the same or different sizes. That is, the original patterned units in the second embodiment of this application are not all the same size; there are original patterned units with different sizes. Specifically, the vertical dimensions of the original first, second, and third patterned units may be the same or different. In other words, the vertical dimensions of the original first and second patterned units may be the same or different, the vertical dimensions of the original first and third patterned units may be the same or different, and the vertical dimensions of the original second and third patterned units may be the same or different. Accordingly, the original first graphic unit, the original second graphic unit, and the original third graphic unit have the same or different lateral dimensions. That is, the original first graphic unit and the original second graphic unit have the same or different lateral dimensions, the original first graphic unit and the original third graphic unit have the same or different lateral dimensions, and the original second graphic unit and the original third graphic unit have the same or different lateral dimensions. When the original first graphic unit, the original second graphic unit, and the original third graphic unit have different vertical dimensions, after exposing the exposure area of ​​the first original graphic unit in the first M×N chip group using the first mask, the substrate can be aligned with the graphic units corresponding to the first original graphic unit in other M×N chip groups along the vertical direction by stepping the substrate by the sum of the vertical dimensions of M original graphic units.

[0197] like Figure 17The diagram illustrates an example of an M×N chipset comprising multiple original patterned units of different sizes in the photolithography method for implementing high-density interconnection of multiple chips provided in this application. The 2×2 chipset includes original patterned units 610, 620, 630, and 640. After selecting the first mask to complete the exposure of the exposure area covering the original patterned unit 610, the substrate can be moved longitudinally by the sum of the longitudinal dimensions of the original patterned units 610 and 630, thereby exposing the exposure area of ​​the patterned unit corresponding to the original patterned unit 610 in the exposure area longitudinally adjacent to the exposure area 700.

[0198] Accordingly, after the exposure area of ​​the first original graphic unit in the first M×N chip group is completed by the first mask, the substrate can be aligned with the graphic units in other M×N chip groups in the horizontal direction that correspond to the first original graphic unit by stepping the substrate in the horizontal direction by the sum of the horizontal dimensions of N original graphic units.

[0199] Combined with appendix Figure 17 The 2×2 chipset includes original pattern units 610, 620, 630, and 640. After selecting the first mask to complete the exposure of the exposure area covering the original pattern unit 610, the substrate can be laterally moved by the sum of the lateral dimensions of the original pattern units 610 and 620, thereby exposing the exposure area of ​​the pattern unit corresponding to the original pattern unit 610 in the exposure area laterally adjacent to the exposure area 700.

[0200] After the first mask is exposed on the substrate, other masks can be selected to repeatedly expose the corresponding graphic units other than the first original graphic unit of the first M×N chip group, and to repeatedly perform vertical movement by the sum of the vertical dimensions of M original graphic units or horizontal movement by the sum of the horizontal dimensions of N original graphic units to complete the exposure of the corresponding areas of other corresponding graphic units in other M×N chip groups on the substrate. Except that the vertical movement distance is the sum of the vertical dimensions of M original graphic units and the horizontal movement distance is the sum of the horizontal dimensions of N original graphic units, other contents can be referred to the relevant description in the first embodiment of this application, and will not be repeated here. Optionally, the original graphic unit includes a composite original graphic unit, which includes at least two of the original first graphic units, the original second graphic unit, and the graphic units in the original third graphic unit.

[0201] like Figure 18The diagram shown is a schematic of an example of a composite original pattern unit in the photolithography technology implementation method for multi-chip high-density interconnection provided in this application embodiment. Both the original pattern unit 630 and the original pattern unit 640 are composite original pattern units. The original pattern unit 630 includes original pattern unit 6301 and original pattern unit 6302, and the original pattern unit 640 includes original pattern unit 6401 and original pattern unit 6402.

[0202] It should be noted that different graphic unit sizes in embodiments mainly occur when different chips are mounted on the carrier board, and even the chips come from different manufacturers. Taking the simultaneous occurrence of multiple rows and columns (M and N are both greater than or equal to 2) of different graphic unit sizes as an example, the sum of the horizontal dimensions of the aforementioned M original graphic units, or the sum of the vertical dimensions of the N original graphic units, is not necessarily equal and cannot be mechanically added together. For example, if mechanically added together, using... Figure 17 For example, the cumulative vertical dimensions on the left (e.g., 610, 630) are not necessarily equal to the cumulative vertical dimensions on the right (e.g., 620, 640), or the cumulative horizontal dimensions at the top (e.g., 610, 620) are not necessarily equal to the cumulative horizontal dimensions at the bottom (e.g., 630, 640). To overcome this problem, when placing the graphics on the carrier board, it is necessary to plan the dimensions of each original graphic in both the vertical and horizontal directions (e.g., using the dimensions of the larger original graphic units as a reference). When gaps exist, they need to be filled and polished to prevent exposure depth-of-field issues.

[0203] The third embodiment of this application also provides a method for implementing photolithography technology for multi-chip interconnect, comprising the following steps: loading a substrate to be exposed onto the stage of a photolithography apparatus, wherein the substrate to be exposed includes at least a first pattern formed by a previous process and a second pattern adjacent to the first pattern, and a dicing area is provided between the first pattern and the second pattern; performing a first exposure using a first mask, transferring a preset pattern on the first mask to a first exposure area of ​​the substrate, the first exposure area at least covering the first pattern; performing a second exposure using a second mask, transferring a preset pattern on the second mask to a second exposure area of ​​the substrate, the second exposure area at least covering the second pattern; the first exposure area and the second exposure area have an overlapping area; the overlapping area is located on the first pattern and / or the dicing area and / or the second pattern.

[0204] The first and second patterns can be understood as the original pattern units in the implementation method of the multi-chip high-density interconnect photolithography technology provided in the first embodiment of this application. After performing the first exposure using the first mask, the preset pattern on the first mask can be transferred to the first exposure area of ​​the substrate; then, using the second mask, the preset pattern on the second mask can be transferred to the second exposure area on the substrate. The first exposure area at least covers the first pattern, and the second exposure area at least covers the second pattern adjacent to the first pattern. The first exposure area and the second exposure area have an overlapping area. This overlapping area can be located on the first pattern, and / or on the scribe line between the first pattern and the second pattern, and / or on the second pattern, thus realizing the interconnection of the first pattern and the second pattern. In this way, the interconnection of two chips can be realized. When it is necessary to realize the interconnection of more adjacent chips, the implementation method of the photolithography technology for multi-chip interconnection provided in this embodiment of the application can further include the following steps: for the pattern areas of any two chip units on the substrate that need to be interconnected, the steps of the first exposure and the second exposure are repeatedly performed until the exposure of the interconnection between all target chip units on the substrate is completed. All target chip units can be understood as the M×N chip group in the implementation method of the multi-chip high-density interconnect photolithography technology provided in the first embodiment of this application. All target chip units can be some or all of the original patterned units on the substrate, and this application does not impose any restrictions on this. It should be noted that the implementation method of the photolithography technology for multi-chip interconnection provided in the second embodiment of this application can be referred to the foregoing description of the implementation method of the multi-chip high-density interconnect photolithography technology provided in the first embodiment of this application, and will not be repeated here.

[0205] The fourth embodiment of this application also provides a chip-level chip interconnection method, including the following steps:

[0206] A substrate is provided, on which a semiconductor structure including at least two semiconductor chips is formed, each semiconductor chip having an intra-chip interconnect and no inter-chip interconnect; the photolithography step of interconnecting the at least two semiconductor chips is realized by any of the photolithography techniques provided in the first, second, or third embodiments of this application.

[0207] In this embodiment, two, three, four, six, eight, or nine semiconductor chips have been fabricated on the substrate using processes such as photolithography, etching, and deposition. Furthermore, internal metal layers (such as copper interconnects) within each semiconductor chip form intra-chip interconnects, but there are no inter-chip interconnects. The at least two semiconductor chips can be arranged horizontally, vertically, or in a matrix. For example, a semiconductor structure comprising 2×1 semiconductor chips may be formed on the substrate; another example is a semiconductor structure comprising 1×2 semiconductor chips; yet another example is a semiconductor structure comprising 2×3 semiconductor chips. Each semiconductor chip can be a single-exposure patterned area formed using a projection system with a scaling factor of 4 to 10 times or other reduction ratios. For example, each semiconductor chip may be a single-exposure patterned area formed by exposure using a projection system with a 4x reduction ratio; or, for example, each semiconductor chip may be a single-exposure patterned area formed by exposure using a projection system with a 5x reduction ratio; or, for example, each semiconductor chip may be a single-exposure patterned area formed by exposure using a projection system with a 8x reduction ratio; or, for example, each semiconductor chip may be a single-exposure patterned area formed by exposure using a projection system with a 10x reduction ratio. Taking a 5x reduction ratio of the projection system as an example, the maximum size of each semiconductor chip formed is generally 26mm × 33mm. It should be understood that the size of each semiconductor chip formed can also be smaller than 26mm × 33mm, such as 25mm × 32mm, etc., as long as it is smaller than the maximum size. This application does not further limit the specific size of the semiconductor chip. A single semiconductor chip can be understood as the original patterned unit in the implementation method of the multi-chip high-density interconnect lithography technology provided in the first embodiment of this application. With the substrate described above provided, the photolithography steps for interconnecting the at least two semiconductor chips can be implemented by the multi-chip high-density interconnect photolithography technology implementation method provided in the first embodiment of this application, or the multi-chip high-density interconnect photolithography technology implementation method provided in the second embodiment of this application, or the photolithography technology implementation method for multi-chip interconnection provided in the third embodiment of this application.

[0208] It should be noted that the lithography steps for realizing the interconnection between at least two semiconductor chips can refer to the foregoing descriptions of the implementation methods of the multi-chip high-density interconnect lithography technology provided in the first embodiment of this application, the second embodiment of this application, and the third embodiment of this application.

[0209] As can be seen, the chip-level interconnection method provided in this application embodiment can realize high-density interconnection of integrated circuits and provide photolithography technology support for high-density interconnection and integration of multiple large chips.

[0210] The fifth embodiment of this application also provides a method for creating mask lines, including the following steps:

[0211] A first mask line, a second mask line, and a third mask line are fabricated on a mask. The first mask line and the third mask line are connected, and the second mask line is connected to the third mask line. The first mask line is used to expose and form a first line as described in the first embodiment of this application in a first exposure area of ​​the substrate. The second mask line is used to expose and form a second line as described in the first embodiment of this application in the first exposure area of ​​the substrate. The third mask line is used to expose and form a third line as described in the first embodiment of this application in the first exposure area of ​​the substrate.

[0212] The fifth embodiment of this application also provides a photolithography apparatus, including two mask stages, three or four stages, two wafer mounting and dismounting systems, and two wafer measurement systems. The photolithography apparatus has been described in detail above and will not be repeated here.

[0213] Although this application discloses preferred embodiments as described above, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be determined by the scope defined in the claims of this application.

Claims

1. A method for implementing multi-chip high-density interconnect photolithography, used to realize the interconnection of M×N chips, characterized in that, include: The substrate to be exposed, which has existing patterned units, is loaded onto the stage of the photolithography equipment, and a first alignment is performed using the first alignment mark on the substrate. For the first M×N chip group on the substrate, a first mask is selected, and the first mask is aligned with the first original pattern unit in the first M×N chip group by the second alignment mark on the substrate. Exposure is performed to transfer the pattern of the first mask to the exposure area covering the first original pattern unit. The substrate is moved longitudinally by M times the longitudinal dimension of a single original graphic unit, or laterally by N times the lateral dimension of a single original graphic unit. The alignment and exposure steps are repeated to complete the exposure of the exposure area of ​​the graphic unit corresponding to the first original graphic unit in the other M×N chipset on the substrate. Select other masks, repeat exposure on the corresponding graphic units other than the first original graphic unit of the first M×N chip group, and repeat vertical movement M times the vertical dimension of a single original graphic unit or horizontal movement N times the horizontal dimension of a single original graphic unit to complete the exposure of the corresponding areas of other corresponding graphic units in other M×N chip groups on the substrate. Specifically, for any M×N chipset, the exposure area covering any original graphic unit and the exposure area of ​​the adjacent original graphic unit have overlapping areas; for any M×N chipset, there are no interconnect lines on the outer scribe lines of the connected M×N chips that penetrate into the original graphic unit and connect the original graphic unit; M and N are both integers greater than or equal to 1, and at least one of M and N is greater than or equal to 2. The overlapping area is the area formed by the overlap of the first exposure area and the second exposure area corresponding to the adjacent exposure areas of adjacent graphic units in the M×N chipset; the first exposure area includes a first line, a second line and a third line; the second exposure area includes a fourth line, a fifth line and a sixth line; the first line and the third line are connected and the second line is connected to the third line; the fourth line and the sixth line are connected and the sixth line and the fifth line are connected. Wherein, the first line is a line in the first exposure area used to connect the first exposure area and the second exposure area; the fourth line is a line in the second exposure area used to connect the first exposure area and the second exposure area; the second line is a line formed in the overlapping area of ​​the first exposure area after expanding and shrinking the fourth line; the third line is a line in the first exposure area that strengthens the connection between the first exposure area and the second exposure area; the fifth line is a line formed in the overlapping area of ​​the second exposure area after expanding and shrinking the first line; and the sixth line is a line in the second exposure area that strengthens the connection between the first exposure area and the second exposure area.

2. The method according to claim 1, characterized in that, Prior to the exposure process, the following is also included: The substrate or the mask selected for performing the exposure is offset by a preset offset distance.

3. The method according to claim 2, characterized in that, When the second alignment mark is the alignment mark corresponding to the original pattern unit, the substrate or the mask selected for the exposure is preset with a corresponding offset distance. Offsetting the substrate or the mask selected for the exposure by the preset offset distance includes: When the mask selected for the exposure is loaded onto the mask stage, the mask selected for the exposure is offset by a preset offset distance; or The substrate is biased by a preset offset distance.

4. The method according to claim 2, characterized in that, When the second alignment mark is an alignment mark for the exposure setting to be performed, the preset offset distance is 0.

5. The method according to claim 2, characterized in that, When the relative positional relationship between the position of the mask pattern of the selected mask in the mask and the position of the mask pattern of the original mask in the original mask is the same as the positional relationship between the exposure area to be formed and the original pattern unit covered by the exposure area to be formed, the preset offset distance is 0. The original mask is the mask used to create the original graphic unit.

6. The method according to claim 1, characterized in that, Also includes: The expansion or contraction of the second line relative to the fourth line is greater than or equal to the alignment deviation limit between the first exposure area and the second exposure area; Furthermore, the expansion or contraction of the fifth line relative to the first line is greater than or equal to the alignment deviation limit value.

7. The method according to claim 1, characterized in that, Also includes: The first exposure area includes a plurality of first lines, a plurality of second lines, and a plurality of third lines; there is a first interval between each pair of adjacent first lines, a second interval between each pair of adjacent second lines, and a third interval between each pair of adjacent third lines.

8. The method according to claim 7, characterized in that, When the first exposure area and the second exposure area overlap vertically, the first interval is a horizontal interval, and the second interval and the third interval are vertical intervals.

9. The method according to claim 7, characterized in that, When the first exposure area and the second exposure area overlap laterally, the first interval is a vertical interval, and the second interval and the third interval are horizontal intervals.

10. The method according to any one of claims 7 to 9, characterized in that, The first interval is greater than or equal to the minimum critical dimension of the lithography equipment.

11. The method according to any one of claims 7 to 9, characterized in that, When the size of the second line is greater than or equal to the size of the third line, the second interval is greater than or equal to a target value, the target value being the maximum value among the minimum critical size of the lithography equipment and the alignment deviation limit between the first exposure area and the second exposure area.

12. The method according to any one of claims 7 to 9, characterized in that, When the size of the second line is smaller than the size of the third line, the third interval is greater than or equal to the target value.

13. The method according to claim 1, characterized in that, Also includes: The second exposure area includes a plurality of fourth lines, a plurality of fifth lines, and a plurality of sixth lines; there is a fourth interval between each pair of adjacent fourth lines, a fifth interval between each pair of adjacent fifth lines, and a sixth interval between each pair of adjacent sixth lines.

14. The method according to claim 13, characterized in that, When the first exposure area and the second exposure area overlap vertically, the fourth interval is a horizontal interval, and the fifth interval and the sixth interval are vertical intervals.

15. The method according to claim 13, characterized in that, When the first exposure area and the second exposure area overlap laterally, the fourth interval is a vertical interval, and the fifth interval and the sixth interval are horizontal intervals.

16. The method according to any one of claims 13 to 15, characterized in that, The fourth interval is greater than or equal to the minimum critical dimension of the lithography equipment.

17. The method according to any one of claims 13 to 15, characterized in that, When the size of the fifth line is greater than or equal to the size of the sixth line, the fifth interval is greater than or equal to the target value.

18. The method according to any one of claims 13 to 15, characterized in that, When the size of the fifth line is smaller than the size of the sixth line, the sixth interval is greater than or equal to the target value.

19. The method according to claim 1, characterized in that, The first exposure area includes multiple first line sets, and the second exposure area includes multiple second line sets; each first line set includes multiple first lines, multiple second lines, and multiple third lines; each second line set includes multiple fourth lines, multiple fifth lines, and multiple sixth lines; there is a first set interval between each two adjacent first line sets; there is a second set interval between each two adjacent second line sets.

20. The method according to claim 19, characterized in that, When the first exposure area and the second exposure area overlap vertically, both the first set interval and the second set interval are horizontal intervals.

21. The method according to claim 19, characterized in that, When the first exposure area and the second exposure area overlap laterally, both the first set interval and the second set interval are vertical intervals.

22. The method according to any one of claims 19 to 21, characterized in that, Both the first set interval and the second set interval are greater than or equal to the target value.

23. The method of claim 1, characterized in that, The original patterned units of the substrate to be exposed include target patterned units, which are patterned units that cannot form M×N chip interconnects.

24. The method according to claim 23, characterized in that, The target graphic unit includes a first target graphic unit and at least one second target graphic unit, and further includes: A target mask is selected, and the target mask is aligned with the first target pattern unit by a second alignment mark on the substrate, and offset by a preset offset distance. Exposure is then performed to transfer the target mask pattern to the first target exposure area corresponding to the first target pattern unit. The target mask is one of the first mask, the other masks, or a mask made for the target pattern unit. The first target exposure area has no interconnect lines on the scribe line of the first target pattern unit that penetrate into the original pattern unit and connect to the original pattern unit. For each of the second target patterning units, the substrate is moved to the second target patterning unit, and alignment, biasing, and exposure are repeatedly performed to transfer the target mask pattern to the second target exposure area corresponding to the second target patterning unit; the second target exposure area has no interconnection pattern that penetrates into the original patterning unit and connects to the original patterning unit on the dicing path of the second target patterning unit.

25. A method for implementing multi-chip high-density interconnect photolithography, used to realize the interconnection of M×N chips, characterized in that, include: The substrate to be exposed, which has existing patterned units, is loaded onto the stage of the photolithography equipment, and a first alignment is performed using the first alignment mark on the substrate. For the first M×N chip group on the substrate, a first mask is selected, and the first mask is aligned with the first original pattern unit in the first M×N chip group by the second alignment mark on the substrate. Exposure is performed to transfer the pattern of the first mask to the exposure area covering the first original pattern unit. The substrate is moved longitudinally by the sum of the longitudinal dimensions of M original pattern units, or laterally by the sum of the lateral dimensions of N original pattern units. The alignment and exposure steps are repeated to complete the exposure of the exposure area of ​​the pattern unit corresponding to the first original pattern unit in the other M×N chipset on the substrate. Select other masks, repeat exposure on the corresponding graphic units other than the first original graphic unit of the first M×N chip group, and repeat vertically move the sum of the vertical dimensions of M original graphic units or horizontally move the sum of the horizontal dimensions of N original graphic units to complete the exposure of the corresponding areas of other corresponding graphic units in other M×N chip groups on the substrate. In this M×N chipset, at least some of the original patterned units have different sizes; in any M×N chipset, the exposure area covering any original patterned unit and the exposure area of ​​the adjacent original patterned unit have overlapping areas; in any M×N chipset, there are no interconnect lines extending into the original patterned units and connecting the original patterned units on the dicing paths of the connected M×N chips; at least one of M and N is an integer greater than or equal to 2. The overlapping area is the area formed by the overlap of the first exposure area and the second exposure area corresponding to the adjacent exposure areas of adjacent graphic units in the M×N chipset; the first exposure area includes a first line, a second line and a third line; the second exposure area includes a fourth line, a fifth line and a sixth line; the first line and the third line are connected and the second line is connected to the third line; the fourth line and the sixth line are connected and the sixth line and the fifth line are connected. Wherein, the first line is a line in the first exposure area used to connect the first exposure area and the second exposure area; the fourth line is a line in the second exposure area used to connect the first exposure area and the second exposure area; the second line is a line formed in the overlapping area of ​​the first exposure area after expanding and shrinking the fourth line; the third line is a line in the first exposure area that strengthens the connection between the first exposure area and the second exposure area; the fifth line is a line formed in the overlapping area of ​​the second exposure area after expanding and shrinking the first line; and the sixth line is a line in the second exposure area that strengthens the connection between the first exposure area and the second exposure area.

26. A method for implementing photolithography technology for multi-chip interconnection, characterized in that, include: The substrate to be exposed is loaded onto the stage of the photolithography equipment. The substrate to be exposed includes at least a first pattern formed by the previous process and a second pattern adjacent to the first pattern, and there is a scribe line between the first pattern and the second pattern. A first exposure is performed using a first mask to transfer a preset pattern on the first mask to a first exposure area on a substrate, wherein the first exposure area at least covers the first pattern. A second exposure is performed using a second mask to transfer a preset pattern on the second mask to a second exposure area on a substrate, wherein the second exposure area at least covers the second pattern. The first exposure area and the second exposure area have an overlapping area, which is located on the first pattern and / or the scribe line and / or the second pattern; The first exposure area includes a first line, a second line, and a third line; the second exposure area includes a fourth line, a fifth line, and a sixth line; the first line and the third line are connected, and the second line is connected to the third line; the fourth line and the sixth line are connected, and the sixth line and the fifth line are connected. Wherein, the first line is a line in the first exposure area used to connect the first exposure area and the second exposure area; the fourth line is a line in the second exposure area used to connect the first exposure area and the second exposure area; the second line is a line formed in the overlapping area of ​​the first exposure area after expanding and shrinking the fourth line; the third line is a line in the first exposure area that strengthens the connection between the first exposure area and the second exposure area; the fifth line is a line formed in the overlapping area of ​​the second exposure area after expanding and shrinking the first line; and the sixth line is a line in the second exposure area that strengthens the connection between the first exposure area and the second exposure area.

27. The method for implementing photolithography technology for multi-chip interconnect according to claim 26, characterized in that, Also includes: For any two patterned areas of chip cells on the substrate that need to be interconnected, the first and second exposure steps are repeated until the interconnection between all target chip cells on the substrate is completed.

28. A chip-level chip interconnection method, characterized in that, include; A substrate is provided on which a semiconductor structure comprising at least two semiconductor chips is formed, each semiconductor chip having at least an intra-chip interconnect, and the semiconductor chips having no inter-chip interconnect; The photolithography steps for interconnecting the at least two semiconductor chips are achieved by the photolithography technique described in any one of claims 1-27.

Images