Floating point multiplication method and floating point multiplication circuit

Abstract

The application provides a floating-point multiplication method and a floating-point multiplication circuit, and relates to the technical field of processors. The method comprises the following steps: obtaining a first exponent of a first floating-point number and a second exponent of a second floating-point number; obtaining a to-be-shifted parameter for performing a to-be-shifted operation on a decimal part of a product of the first floating-point number and the second floating-point number according to the first exponent and the second exponent; the to-be-shifted parameter comprises a shift direction and a shift bit number; in the process of obtaining a shift result of the product according to the to-be-shifted parameter, overflow information of a decimal part of the shift result is obtained according to the to-be-shifted parameter; the overflow information comprises overflow or no overflow; and the exponent of the shift result is adjusted according to the overflow information to obtain a multiplication result of the first floating-point number and the second floating-point number. The method has the advantage that the floating-point multiplication period is short.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of processors, and particularly relates to a floating-point multiplication method and a floating-point multiplication circuit. BACKGROUND

[0002] When performing multiplication on floating-point numbers, in order to ensure that the decimal part does not overflow, the decimal part of the product needs to be shifted, and when the decimal part is shifted, the exponent will also change. After the decimal part of the product is shifted, the exponent may overflow the exponent range of the floating-point number, in which case the exponent needs to be handled by carrying.

[0003] In the related art, after obtaining the product of floating-point numbers, a shift operation is performed on the product, and then the value of the highest bit of the shift result is analyzed, and it is determined whether the exponent needs to be carried according to the analysis result.

[0004] However, this method needs to first obtain the shift result of the product, then determine the shift strategy according to the shift result, and then perform exponent shifting according to the shift strategy. This method has low processing efficiency and results in a long operation period of multiplication. SUMMARY

[0005] Embodiments of the present application provide a floating-point multiplication method and a floating-point multiplication circuit to solve the problems of low multiplication efficiency and long period in the prior art.

[0006] In a first aspect, an embodiment of the present application provides a floating-point multiplication method, including: obtaining a first exponent of a first floating-point number and a second exponent of a second floating-point number; obtaining a to-be-shifted parameter for performing a to-be-shifted operation on the decimal part of the product of the first floating-point number and the second floating-point number according to the first exponent and the second exponent; the to-be-shifted parameter includes a shift direction and a shift bit number; in the process of obtaining a shift result of the product according to the to-be-shifted parameter, obtaining overflow information of the decimal part of the shift result according to the to-be-shifted parameter; the overflow information includes overflow or no overflow; adjusting the exponent of the shift result according to the overflow information to obtain a multiplication result of the first floating-point number and the floating-point number.

[0007] In a second aspect, the embodiments of the present application provide a floating-point multiplication circuit, comprising an overflow information obtaining unit, and a to-be-shifted parameter obtaining unit and an exponent adjusting unit connected with the overflow information obtaining unit; the to-be-shifted parameter obtaining unit is configured to obtain a first exponent of a first floating-point number and a second exponent of a second floating-point number; and according to the first exponent and the second exponent, a to-be-shifted parameter for performing a to-be-shifted operation on a decimal part of a product of the first floating-point number and the second floating-point number is obtained; the to-be-shifted parameter comprises a shift direction and a shift bit number; the overflow information obtaining unit is configured to, in a process of obtaining a shift result of the product according to the to-be-shifted parameter, obtain overflow information of a decimal part of the shift result according to the to-be-shifted parameter; the overflow information comprises overflow or no overflow; and the exponent adjusting unit is configured to adjust an exponent of the shift result according to the overflow information, to obtain a multiplication result of the first floating-point number and the floating-point number.

[0008] In a third aspect, the embodiments of the present application further provide a floating-point multiplication device, comprising: a first obtaining module configured to obtain a first exponent of a first floating-point number and a second exponent of a second floating-point number; a second obtaining module configured to obtain, according to the first exponent and the second exponent, a to-be-shifted parameter for performing a to-be-shifted operation on a decimal part of a product of the first floating-point number and the second floating-point number; the to-be-shifted parameter comprises a shift direction and a shift bit number; a third obtaining module configured to, in a process of obtaining a shift result of the product according to the to-be-shifted parameter, obtain overflow information of a decimal part of the shift result according to the to-be-shifted parameter; the overflow information comprises overflow or no overflow; and an exponent adjusting module configured to adjust an exponent of the shift result according to the overflow information, to obtain a multiplication result of the first floating-point number and the floating-point number.

[0009] In a fourth aspect, the embodiments of the present application further provide an electronic device, comprising a processor; a memory for storing instructions executable by the processor; and the processor is configured to execute the instructions to implement the method of the first aspect.

[0010] In a fifth aspect, the embodiments of the present application further provide a computer-readable storage medium, when instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the method of the first aspect.

[0011] In the embodiment of the present application, the first exponent of the first floating-point number and the second exponent of the second floating-point number are obtained; in the process of obtaining the product of the first floating-point number and the second floating-point number, the to-be-shifted parameter for performing the to-be-shifted operation on the decimal part of the product is obtained according to the first exponent and the second exponent; the to-be-shifted parameter includes the shift direction and the shift bit number; in the process of obtaining the shift result of the shift operation on the decimal part of the product according to the to-be-shifted operation parameter, the overflow information of the decimal part of the shift result is obtained, the exponent of the shift result is adjusted according to the overflow information, and the multiplication result of the first floating-point number and the floating-point number is obtained. Compared with the method in the related art that the shift result is obtained, and then it is judged whether the exponent carry is needed according to the detection result of the highest value of the shift result, the embodiment reduces the processing time of the exponent carry and reduces the operation period of the floating-point number multiplication operation.

[0012] The above description is only a summary of the technical solutions of the present application. In order to more clearly understand the technical means of the present application, the content of the specification can be implemented, and in order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the following specific embodiments of the present application are described. BRIEF DESCRIPTION OF DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0014] Figure 1 is a floating-point number multiplication method application scenario provided by the embodiment of the present application;

[0015] Figure 2 is a floating-point number multiplication method step flowchart provided by the embodiment of the present application;

[0016] Figure 3 is a floating-point number multiplication method step flowchart provided by the embodiment of the present application;

[0017] Figure 4 is a flowchart for obtaining a floating-point number product provided by the related art;

[0018] Figure 5 is a flowchart for obtaining a floating-point number product provided by the embodiment of the present application;

[0019] Figure 6 is a flowchart for obtaining a floating-point number product provided by the embodiment of the present application;

[0020] Figure 7is a floating point multiplication method step flow chart provided by the embodiment of the application;

[0021] Figure 8 is a floating point multiplication method step flow chart provided by the embodiment of the application;

[0022] Figure 9 is a floating point multiplication method step flow chart provided by the embodiment of the application;

[0023] Figure 10 is a floating point multiplication circuit schematic diagram provided by the embodiment of the application;

[0024] Figure 11 is a shift information acquisition circuit schematic diagram provided by the embodiment of the application;

[0025] Figure 12 is an index carry information acquisition circuit schematic diagram provided by the embodiment of the application;

[0026] Figure 13 is a floating point multiplication device block diagram provided by the embodiment of the application;

[0027] Figure 14 is an electronic device block diagram provided by the embodiment of the application;

[0028] Figure 15 is another electronic device block diagram provided by another embodiment of the application. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the application will be clearly and completely described below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are some of the embodiments of the application, rather than all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the application.

[0030] The terms "first", "second", etc. in this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally a class, not limited to the number of objects, for example, the first object can be one or more. In addition, the term "and / or" in the application file is used to describe the relationship between the associated objects, which means that there can be three relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects. The term "multiple" in the embodiments of the application means two or more, and other quantifiers are similar.

[0031] Figure 1 is an application scenario diagram of a floating-point multiplication method provided by an embodiment of the application, referring to Figure 1 The floating-point multiplication instruction is a commonly used instruction in a processor, which can be used to instruct the first floating-point number and the second floating-point number to perform multiplication, and then obtain the product between the first floating-point number and the second floating-point number.

[0032] In the multiplication process, the clock frequency is very high, and correspondingly, the time of each operation period is very short, and the operation process of the floating-point multiplication is relatively complex, which leads to the fact that usually multiple periods are needed to complete the floating-point multiplication. For example, in the related art, in some processor architectures, the multiplication between half-precision floating-point numbers, the multiplication between single-precision floating-point numbers, and the multiplication between double-precision floating-point numbers all need three periods.

[0033] Further, the floating-point number usually includes a sign part, an exponent part and a mantissa part, and the floating-point multiplication can be represented by the following formula:

[0034]

[0035] Among them, is the first floating-point number, is the second floating-point number, is the product between the first floating-point number and the second floating-point number. According to the above formula, the floating-point multiplication is to multiply the values of the first floating-point number and the second floating-point number.

[0036] Specifically, the sign values of the first floating-point number and the second floating-point number are multiplied, the exponent values of the first floating-point number and the second floating-point number are multiplied, and the decimal values of the first floating-point number and the second floating-point number are multiplied, thereby obtaining the product of the first floating-point number and the second floating-point number, and then the product is converted into a binary floating-point number representation. Further, the sign value multiplication is an exclusive OR operation on the binary sign parts of the first floating-point number and the second floating-point number; the exponent value multiplication is an addition operation on the binary exponent parts of the first floating-point number and the second floating-point number; and the decimal value multiplication is a multiplication operation on the binary decimal parts of the first floating-point number and the second floating-point number.

[0037] Based on the above multiplication processing procedure, the value range of the result obtained by multiplying the decimal parts of the two floating-point numbers should be [0, 4). If both of the two floating-point numbers are normalized numbers, the value range of the result of the multiplication of the decimal parts should be [1, 4), and if the actual result obtained by multiplying the binary decimal parts of the two floating-point numbers is between [2, 4), the mantissa part of the product of the two floating-point numbers needs to be right-shifted, and the exponent part of the product of the two floating-point numbers needs to be incremented by 1.

[0038] If both of the two floating-point numbers are non-normalized numbers, the actual result obtained by multiplying the binary decimal parts of the two floating-point numbers is between [0, 1).

[0039] Based on the above multiplication processing procedure, the value range of the exponent part of the multiplication result should be If the exponent part is greater than the upper limit value of the floating-point number exponent , the result overflows to infinity; if the exponent part is less than the lower limit value of the floating-point number exponent , the decimal part of the product needs to be left-shifted, and the exponent part of the product needs to be decremented. That is, after obtaining the product of the two floating-point numbers, the decimal part of the product needs to be shifted according to the shift bit number and the shift direction.

[0040] If the value of the exponent part of the result obtained by multiplying the exponent parts of the two floating-point numbers is in , and the result of the multiplication of the decimal parts is in , the decimal part of the multiplication result needs to be left-shifted, and the exponent value is decremented after the left shift.

[0041] In the related art, the product of the two floating-point numbers is usually calculated first, and then the product is analyzed for shifting to determine whether to left-shift or right-shift, and the product is left-shifted or right-shifted according to the determination result to obtain a shift result, and then it is analyzed whether the highest bit of the shift result is 1, and if it is 1, it is determined that the shift result overflows, and the exponent is incremented by 1. However, this method has a long processing period.

[0042] To solve the problems in the related art, the embodiment of the present application provides a floating-point multiplication method, which comprises the following steps: obtaining a first exponent of a first floating-point number and a second exponent of a second floating-point number; obtaining a to-be-shifted parameter for performing a to-be-shifted operation on a decimal part of a product of the first floating-point number and the second floating-point number according to the first exponent and the second exponent; the to-be-shifted parameter comprises a shift direction and a shift bit number; in the process of obtaining a shift result of the product according to the to-be-shifted parameter, obtaining overflow information of the shift result decimal part according to the to-be-shifted parameter; the overflow information comprises overflow or no overflow; and adjusting an exponent of the shift result according to the overflow information to obtain a multiplication result of the first floating-point number and the second floating-point number. The embodiment reduces the processing time of the exponent carry and reduces the operation period of the floating-point multiplication operation.

[0043] The floating-point multiplication method provided by the embodiment of the present application will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0044] Figure 2 is a step flowchart of the floating-point multiplication method provided by the embodiment of the present application, as shown in the figure, the method can comprise the following steps: Figure 2

[0045] Step 101, obtaining a first exponent of a first floating-point number and a second exponent of a second floating-point number.

[0046] The first floating-point number and the second floating-point number are floating-point numbers to be subjected to multiplication operation. The binary representation of the floating-point number comprises three parts, namely a sign part (sign), an exponent part (exp) and a mantissa part (frac). The calculation method and value range of each part of the floating-point number will be described by way of example as follows:

[0047] The exponent part exp of the floating-point number can be normalized according to the following formula to obtain the normalized result of the exponent part exp of the floating-point number :

[0048]

[0049] According to the expression, if the exponent exp of the floating-point number is 0, the normalized result of the exponent is 1; if the exponent exp of the floating-point number is not 0, the normalized result of the exponent is exp. In this step, the first exponent of the first floating-point number is obtained, which comprises: obtaining the normalized result of the exponent exp of the first floating-point number

[0050] ​​​​Determine a first exponent of the first floating-point number. Obtain a second exponent of the second floating-point number, including obtaining a normalized result of an exponent exp of the second floating-point number , the normalized result of the exponent of the second floating-point number Determine a second exponent of the second floating-point number.

[0051] In step 102, according to the first exponent and the second exponent, obtain a shift parameter for a shift operation on a decimal part of a product of the first floating-point number and the second floating-point number.

[0052] The shift parameter includes a shift direction and a shift bit number.

[0053] For example, the shift bit number can include a left shift bit number and / or a right shift bit number, and the shift direction includes left shift or right shift.

[0054] For example, the shift parameter can be obtained according to the first exponent and the second exponent in a process of obtaining the product of the first floating-point number and the second floating-point number.

[0055] For example, a first number of leading zeros of the first floating-point number and a second number of leading zeros of the second floating-point number can be obtained, and a left shift bit number can be obtained according to the first exponent, the second exponent, the first number of leading zeros and the second number of leading zeros; and a right shift bit number can be obtained according to the first exponent and the second exponent.

[0056] In step 103, in a process of obtaining a shift result of the product according to the shift parameter, obtain overflow information of a decimal part of the shift result according to the shift parameter.

[0057] The overflow information includes overflow or no overflow.

[0058] According to the shift parameter, perform a shift operation on the product to obtain a shift result.

[0059] For example, the shift operation includes a left shift operation, the shift direction in the shift operation parameter is left shift, and the shift bit number is a left shift bit number. An initial shift mask with the highest bit being 1 can be obtained, and a shift mask can be obtained by performing a shift operation on the initial shift mask according to the shift operation parameter in a process of obtaining the product. A logical AND operation is performed on the shift mask and the shift result of the product to obtain overflow information corresponding to the left shift operation.

[0060] For example, the shift operation includes a right shift operation, the shift direction in the shift operation parameter is right shift, and the shift bit number is a right shift bit number. According to the right shift bit number, overflow information corresponding to the right shift operation is obtained.

[0061] Step 104, according to the overflow information, adjusting the exponent of the shift result to obtain the multiplication result of the first floating-point number and the floating-point number.

[0062] For example, if the overflow information is that the decimal part of the shift result overflows, or the third exponent of the product is not all 1, the third exponent of the product is incremented by 1 to perform the exponent carry; if the overflow information is no overflow, or the third exponent is all 1, the third exponent is maintained unchanged.

[0063] When the decimal part of the floating-point number is multiplied, the carry of the exponent is generated, and the carry needs to be detected during the left shift operation and the right shift operation. In the related art, the product of the floating-point numbers is first obtained, and then the product is left shifted or right shifted to obtain a shift result, and then it is determined whether the highest bit of the shift result is 1. If the highest bit is 1, it is determined that the shift result overflows, and then the exponent of the shift result is incremented. However, this method needs to obtain the product first, then shift the product, and then analyze the value of the highest bit of the shift result. This processing method is slow, which leads to a long floating-point multiplication period.

[0064] In the embodiment of the present application, the first exponent of the first floating-point number and the second exponent of the second floating-point number are obtained. In the process of obtaining the product of the first floating-point number and the second floating-point number, the shift parameter for the decimal part of the product is obtained according to the first exponent and the second exponent. The shift parameter includes the shift direction and the shift bit number. In the process of obtaining the shift result of the decimal part of the product according to the shift parameter, the overflow information of the decimal part of the shift result is obtained, and the exponent of the shift result is adjusted according to the overflow information to obtain the multiplication result of the first floating-point number and the floating-point number. Compared with the method of obtaining the shift result and then determining whether the exponent needs to be incremented according to the detection result of the highest bit value of the shift result in the related art, the embodiment reduces the processing time of the exponent carry and reduces the operation period of the floating-point multiplication.

[0065] Referring to Figure 3 The floating-point multiplication method of the embodiment can further include the following steps:

[0066] Step 201, obtaining the first exponent of the first floating-point number and the second exponent of the second floating-point number.

[0067] The method of this step has been described in the foregoing step 101, which will not be repeated here.

[0068] Step 202, obtaining the shift parameter for the decimal part of the product according to the first exponent and the second exponent.

[0069] The shift parameter includes the shift direction and the shift bit number.

[0070] The method of this step has been described in the foregoing step 102, and will not be repeated here.

[0071] In step 203, in the process of obtaining the shift result of the product according to the to-be-shifted parameter, in the case where the shift direction is left shift and the shift bit number includes the left shift number, an initial mask is obtained.

[0072] The value of the highest bit of the initial mask is 1, and the values of the other bits are 0.

[0073] For example, the first bit number of the decimal part of the first floating-point number and the second bit number of the decimal part of the second floating-point number are obtained, and the third bit number of the decimal part of the product of the first floating-point number and the second floating-point number is obtained according to the first bit number and the second bit number. An initial mask with a bit number equal to the third bit number and a value of 1 in the highest bit is constructed.

[0074] For example, in the case where the shift direction is left shift, the initial mask is obtained according to the following method :

[0075]

[0076] wherein, is a hot bit constant, and is obtained After that, the decimal part of the product is ANDed with the initial mask, and then is reduced to determine whether the exponent needs to be incremented.

[0077] The floating-point number decimal part bit width, is equal to the bit width of the decimal part of the product. The floating-point number decimal part bit width is related to the floating-point number type, and the corresponding relationship between the floating-point number type and the decimal part bit width is shown in Table 1:

[0078]

[0079] wherein, f64, f32 and f16 respectively represent double-precision floating-point numbers, single-precision floating-point numbers and half-precision floating-point numbers.

[0080] According to the expression of the initial mask, the bit number of the initial mask is equal to , and the value of the highest bit is 1.

[0081] In step 204, the value of the highest bit of the initial mask is shifted right by the left shift number to obtain a shift mask.

[0082] For example, the initial mask is 10000000000000000000, and the left shift number is 2, so that the shift mask obtained after the shift is 00100000000000000000.

[0083] For example, the first floating-point number and the second floating-point number are of the same floating-point type, and an exponent sum of the first exponent and the second exponent is obtained, as well as a preset exponent bias value corresponding to the floating-point type of the first floating-point number and the second floating-point number; an exponent difference value between the exponent sum and the preset exponent bias value is obtained, and the exponent difference value is determined as the third exponent.

[0084] For example, step 204 can include the following sub-steps:

[0085] Sub-step A1: obtaining, according to the first exponent and the second exponent, a third exponent of the product.

[0086] For example, the first floating-point number and the second floating-point number are of the same floating-point type, and an exponent sum of the first exponent and the second exponent is obtained, as well as a preset exponent bias value corresponding to the floating-point type of the first floating-point number and the second floating-point number; an exponent difference value between the exponent sum and the preset exponent bias value is obtained, and the exponent difference value is determined as the third exponent.

[0087] For example, the third exponent can be obtained by the following method :

[0088]

[0089] wherein, the first exponent is, the second exponent is, the preset exponent bias value corresponds to the floating-point type of the first floating-point number and the second floating-point number.

[0090] Sub-step A2: if the third exponent is equal to zero, then according to the first shift value, the value of the highest bit of the initial mask is shifted right to obtain a shifted mask.

[0091] wherein, the first shift value is equal to the sum of the left shift number and 1.

[0092] For example, if the third exponent is equal to zero, the value of the highest bit of the initial mask can be shifted according to the left shift number, and then the shifted value is shifted right by 1 bit to obtain the shifted mask; or the value of the highest bit of the initial mask can be first shifted right by 1 bit, and then shifted according to the left shift number to obtain the shifted mask; or the value of the highest bit of the initial mask can be directly shifted right according to the first shift value to obtain the shifted mask.

[0093] For example, the shifted mask can be obtained by the following method :

[0094]

[0095] According to the expression, if the third exponent of the product is equal to 0, the initial mask right shift Then, the initial mask is right shifted by 1 bit.

[0096] In sub-step A3, if the third index is not equal to zero, the initial mask is right shifted by the number of left shifts to obtain a shifted mask.

[0097] In this embodiment, if the third index is equal to zero, the initial mask is right shifted by 1 bit after being shifted by the number of left shifts to obtain a shifted mask, otherwise, the initial mask is directly shifted by the number of left shifts to obtain a shifted mask. Based on the shifted mask, subsequent overflow analysis can be performed to ensure the accuracy of the obtained overflow information.

[0098] In step 205, the shifted mask and the product are ANDed to obtain an AND result.

[0099] For example, the AND result can be obtained according to the following method: .

[0100] For example, the number of bits of the shifted mask is equal to the number of bits of the decimal part of the product; step 205 can include the following sub-steps:

[0101] In sub-step B1, the shifted mask and the product are ANDed to obtain an initial AND result.

[0102] The shifted mask and the product are both in binary format, and the shifted mask and the product are ANDed bit by bit to obtain the initial AND result.

[0103] For example, the shifted mask is 00100000000000000000, and the product is 11100000001010000000, and the initial AND result obtained by ANDing the two is 1.

[0104] In sub-step B2, the data from the highest bit to the first bit of the initial AND result is intercepted to obtain an AND result.

[0105] The total number of bits from the highest bit to the first bit of the initial AND result is equal to the exponent width of the preset floating-point type.

[0106] When the product is left shifted, the maximum value of the number of left shifts is equal to the exponent width In this embodiment, instead of analyzing all the bits of the initial AND result, part of the data is intercepted, and the intercepted part of the data is determined as the AND result.

[0107] In this step, the AND result is obtained by intercepting from the high bit to the low bit of the initial AND result. For example, the AND result can be obtained according to the following method :

[0108]

[0109] wherein, the number of bits corresponding to the high bit is the number of bits corresponding to the low bit.

[0110] In this embodiment, the initial mask and the product are subjected to an AND operation to obtain an initial AND operation result; the maximum value of the left shift number is equal to the mantissa width, so the data from the highest bit to the first bit of the initial AND operation result is intercepted to obtain an AND operation result. In this way, the effective part of the initial AND operation result that can reflect the overflow information is retained, and the data useless for the overflow information judgment is cut off, thereby reducing the amount of data to be processed and improving the processing efficiency.

[0111] In step 206, the overflow information of the decimal part of the shift result is obtained according to the AND operation result.

[0112] In an example, an OR reduction operation is performed on the AND operation result to obtain an OR reduction operation result, and the overflow information is obtained according to the OR reduction operation result.

[0113] For example, the product is 00.1100, the initial mask constructed is 100000, the shift direction of the product is left shift, and the left shift number is 2, so the initial mask is right shifted by two bits to obtain a shift mask 001000, and the AND operation is performed on the shift mask and the product to obtain an AND operation result 001000.

[0114] The OR reduction operation is performed on the AND operation result 001000 to obtain a result 1, indicating that the overflow information corresponding to the left shift operation is overflow; and the product 00.1100 is left shifted by two bits, and the result is 11.0000, so the shift result is overflow. It can be known from this embodiment that according to the method of this embodiment, the overflow information of the shift result of the product can be accurately obtained.

[0115] In this embodiment, the initial mask is obtained, the value of the highest bit of the initial mask is 1, and the values of the other bits are 0. In the process of obtaining the product, the value of the highest bit of the initial mask is left shifted according to the left shift number to obtain a shift mask, and then the AND operation is performed on the shift mask and the product to obtain an AND operation result. According to the AND operation result, the overflow information of the shift result corresponding to the left shift operation can be accurately obtained.

[0116] ​In addition, the embodiment obtains the overflow information in the process of obtaining the product, and does not need to obtain the overflow information by performing a shift operation on the product and then analyzing whether the value of the highest bit of the shift result is 1. In other words, the method of obtaining the overflow information in the embodiment can be executed in parallel with the method of obtaining the product, thereby shortening the time of obtaining the overflow information, and further shortening the time of performing the exponential carry based on the overflow information, and shortening the operation period of the floating-point multiplication operation.

[0117] Step 206 includes sub-step C1 to sub-step C2:

[0118] Sub-step C1, performing an OR or NOR operation on the AND operation result to obtain an OR or NOR operation result.

[0119] For example, the OR or NOR operation result is obtained according to the following method: :

[0120]

[0121] In the formula,.orR represents the OR or NOR operation.

[0122] Sub-step C2, obtaining the overflow information of the decimal part of the shift result according to the OR or NOR operation result.

[0123] The overflow information obtained in this sub-step is the overflow information corresponding to the decimal part of the shift result after left shift.

[0124] In the embodiment, the OR or NOR operation is performed on the AND operation result to obtain the OR or NOR operation result. The AND operation result can include data of multiple bits, and only in the case of overflow, the AND operation result includes a bit with a value of 1, and the number of bits is the same as the number of bits equal to 1 in the shift code. Conversely, in the case of no overflow, the data of each bit of the AND operation result is 0. The OR or NOR operation can determine whether the AND operation result includes a value of 1, and therefore, in the embodiment, the overflow information of the product can be quickly and accurately obtained according to the OR or NOR operation result of the OR or NOR operation performed on the AND operation result.

[0125] For example, sub-step C2 can include the following sub-steps:

[0126] Sub-step C21, obtaining a third exponent of the product according to the first exponent and the second exponent.

[0127] Sub-step C22, obtaining first overflow information of the shift result according to the third exponent.

[0128] For example, sub-step C22 can include sub-step C221 to sub-step C223:

[0129] In sub-step C221, a first number of leading zeros of the first floating-point number and a second number of leading zeros of the second floating-point number are obtained.

[0130] For example, if the first exponent of the first floating-point number is equal to zero, a first splicing result obtained by splicing zero and the mantissa of the first floating-point number is obtained, and the number of leading zeros of the first splicing result is determined as the first number of leading zeros of the first floating-point number; if the first exponent of the first floating-point number is not equal to zero, the first number of leading zeros of the first floating-point number is determined as zero. The splicing operation of 0 and the mantissa of the first floating-point number is , and the obtained splicing result is .

[0131] If the second exponent of the second floating-point number is equal to zero, a second splicing result obtained by splicing zero and the mantissa of the second floating-point number is obtained, and the number of leading zeros of the second splicing result is determined as the second number of leading zeros of the second floating-point number; if the second exponent of the second floating-point number is not equal to zero, the second number of leading zeros of the second floating-point number is determined as zero. The splicing operation of 0 and the mantissa of the second floating-point number is , and the obtained splicing result is .

[0132] In sub-step C222, a third number of leading zeros of the product is obtained according to the first number of leading zeros and the second number of leading zeros.

[0133] For example, an OR operation is performed on the first number of leading zeros and the second number of leading zeros to obtain the third number of leading zeros; or an addition operation is performed on the first number of leading zeros and the second number of leading zeros to obtain the third number of leading zeros.

[0134] In sub-step C223, first overflow information of a shift operation on the decimal part of the product is obtained according to a comparison result of the third exponent and the third number of leading zeros.

[0135] For example, if the third exponent is less than the third number of leading zeros, it is determined that the first overflow information is no overflow; otherwise, it is determined that the first overflow information is overflow.

[0136] For example, the first overflow information is obtained according to the following method :

[0137]

[0138] According to the expression, if the third exponent is less than the third number of leading zeros , it is determined that the first overflow information is no overflow; otherwise, it is determined that the first overflow information is overflow. In the expression, the third number of leading zeros is determined as the number of leading zeros of the product of the first number of leading zeros and the second number of leading zeros. ​​The condition that will not overflow is calculated for left shift operation when calculating the shift value. In the processing, 1 bit is needed to record the case that multiplication of the decimal part will not cause overflow when left shift operation is performed.

[0139] In the embodiment, the first leading zero number of the first floating point number and the second leading zero number of the second floating point number are obtained, and the third leading zero number of the product is obtained according to the first leading zero number and the second leading zero number. The embodiment does not need to obtain the product between the first floating point number and the second floating point number in advance, and the third leading zero number is obtained by performing leading zero detection on the product, thereby shortening the period of obtaining the third leading zero. The third exponent is reduced by 1 for each left shift, and if the product is shifted according to the number of left shifts when the third exponent is less than the third leading zero number, overflow will occur, otherwise overflow will not occur. According to the third exponent and the number of the third leading zero, the first overflow information obtained by analyzing the exponent can be quickly and accurately obtained.

[0140] In sub-step C23, if the result of the or reduction operation is 1 and the first overflow information is overflow, it is determined that the overflow information of the decimal part of the shift result of the left shift is overflow.

[0141] The first overflow information is the overflow information obtained according to the exponent of the product.

[0142] In sub-step C24, if the result of the or reduction operation is 0 or the first overflow information is no overflow, it is determined that the overflow information of the decimal part of the shift result is no overflow.

[0143] The overflow information is the overflow information of the decimal part of the shift result of the left shift.

[0144] For example, the overflow information of the product can be obtained according to the following method :

[0145]

[0146] In the embodiment, the first overflow information of the shift result of the shift operation on the decimal part of the product is obtained according to the third exponent. If the result of the or reduction operation is 1, it is determined that the overflow information determined according to the shift mask is overflow. If the result of the or reduction operation is 1 and the first overflow information is overflow, it can be accurately determined that the overflow information of the shift result of the product is overflow. If the result of the or reduction operation is 0 or the first overflow information is no overflow, it can be accurately determined that the overflow information of the shift result of the product is no overflow. Otherwise, through the double judgment of the result of the or reduction operation analysis and the first overflow information, it can be accurately determined that the overflow information of the shift result of the product is overflow.

[0147] Step 207: In the process of obtaining the shift result of the product based on the shift parameter to be shifted, if the shift direction includes right shift and the number of shifts includes right shift value, and the value of the highest bit of the fractional part of the product is equal to 1 and the number of right shifts is equal to 1, then it is determined that the fractional part of the right shift result has overflowed.

[0148] The algorithm compares the right shift bit with 1, performs a bitwise AND operation between the comparison result and the highest-order bit of the product's fractional part, and obtains the overflow information of the fractional part of the right shift result. The comparison result includes whether the right shift bit is equal to or not equal to 1.

[0149] Step 208: If the value of the highest bit of the fractional part of the product is equal to 0, or the number of bits shifted to the right is not equal to 1, then it is determined that the fractional part of the shift result will not overflow.

[0150] If the right shift is equal to 1, that is... If the highest bit of the fractional part of the product is 1, the result of the AND operation is 1; otherwise, the result is 0. In this embodiment, based on the comparison result of whether the right shift bit is 1 and the AND operation of the highest bit of the fractional part of the product, the overflow information of the fractional part of the shifted result can be obtained quickly and accurately.

[0151] Carry detection during right shift: a carry can only be made to the exponent if the shift is 1 bit to the right. Equal to 0, A carry-over to the exponent is only possible if the result after shifting right by one bit is greater than 1, and the result after shifting right by two bits or more is also possible. After the shift, the value is less than 1, so it's impossible to carry over to the exponent. For example, overflow information can be obtained using the following method. :

[0152]

[0153] in, This represents the value of the highest digit of the fractional part of the product. Equal to 1 means Greater than 2; otherwise, it means No more than 2.

[0154] According to this expression, the first product... Number of bits and right shift ( Perform a logical AND operation. If the result is 1, it means dMul is greater than 2, and the right shift is equal to 1. In this case, it indicates product overflow. If the highest bit of the fractional part of the product is not equal to 1, it indicates... If not greater than 2, then No overflow.

[0155] In the case of a right shift, shift detection is performed; a carry-over to the exponent is only possible if the shift is 1 bit to the right. This is because the condition for a right shift operation is the third exponent of the product. Therefore, when shifted to the right, the third exponent of the product... A carry-over to the exponent occurs only if the product equals 0 and the right shift is 1. However, if the right shift is greater than or equal to 2, the product... After shifting two bits to the right, the result is less than 1, so it's impossible to carry over to the exponent. Therefore, if the number of bits to shift is not equal to 1, then... No overflow.

[0156] In other words, if the value of the highest bit of the fractional part of the product is not equal to 1, or the number of bits to be shifted is not equal to 1, then the overflow information is determined to be non-overflow.

[0157] For each right shift, the third exponent of the product increases by 1, increasing from negative to 0. In this embodiment, a bitwise AND operation is performed between the right shift value and the highest bit of the fractional part of the product. If the right shift value is 1, the highest bit of the fractional part is 1, and the third exponent of the product is 0, then the shift result will overflow if the shift is 1 bit to the right; otherwise, the shift result will not overflow. Based on this embodiment, overflow information can be accurately obtained when the shift direction is right and the shift number is the right shift value.

[0158] Step 209: If the overflow information is no overflow, or if all the digits of the third exponent of the product are 1, then keep the exponent unchanged.

[0159] Example: Retrieving overflow information The methods may include:

[0160]

[0161] Based on this expression, determine whether the product satisfies the left shift condition. If the left shift condition is met, and the overflow information corresponding to the left shift operation is overflow, then the product's overflow information is determined to be overflow. If the left shift condition is not met, and the overflow information corresponding to the right shift operation is overflow, then the product's overflow information is determined to be overflow. Otherwise, the product's overflow information is determined to be non-overflow.

[0162] Step 210: If the overflow information is overflow and at least one bit in the third exponent of the product is equal to 0, then perform a further operation on the exponent.

[0163] Example, based on value selection or At the same time, special cases should be considered, such as This is the carry-over result when all numbers are 1. For example, the carry-over result can be obtained using the following method:

[0164]

[0165] In the embodiment, if the overflow information is not overflow, or the value of each digit in the third exponent of the product is 1, it indicates that the third exponent will overflow to infinity if there is a carry, and thus the exponent is kept unchanged. If the overflow information is overflow, and the value of at least one digit in the third exponent of the product is equal to 0, it indicates that the decimal part of the product shifting result overflows, and the third exponent has room for carry, and thus the exponent is incremented. Based on the embodiment, the carry of the exponent of the product can be accurately processed, and the entire processing process does not need to be based on the shifting result of the product, and the carry analysis of the exponent can be processed in parallel with the process of obtaining the product, which shortens the processing time and reduces the operation period of the floating-point multiplication operation.

[0166] The method further includes the following steps:

[0167] In step 210, a first mantissa of the first floating-point number and a second mantissa of the second floating-point number are obtained.

[0168] In step 211, a first partial product is obtained according to the first mantissa and the second mantissa.

[0169] For example, the first partial product of the first mantissa and the second mantissa can be obtained by using the Booth encoding method. For example, the first partial product of the first mantissa and the second mantissa can be obtained by using the Radix-4 method.

[0170] In step 212, the first partial product is compressed to obtain a first compression result, and a second partial product of the first implicit bit of the first floating-point number and the second implicit bit of the second floating-point number is obtained in the process of compressing the first partial product.

[0171] For example, the partial product is compressed by using a carry-save adder (CSA).

[0172] In step 213, a product of the first floating-point number and the second floating-point number is obtained according to the first compression result and the second partial product.

[0173] After the partial product is generated by using the Booth encoding, the CSA can be used to compress all the partial products into two partial products, and then the two compressed partial products are added to obtain the product of the first floating-point number and the second floating-point number.

[0174] The method for obtaining the product of the floating-point numbers in the related art is as follows Figure 4As shown, when slow Booth encoding is performed, timing optimization is performed, the calculation of implicit bits needs to be reduced by exponent bits or reduced, and the result of each partial product is affected by implicit bits, so the time of partial product generation is slow, which causes the CSA compression to start slowly.

[0175] In the embodiment, with reference to Figure 4 , the implicit bits are removed to generate partial products directly to start CSA compression, and the CSA compression needs multiple stages to complete. The implicit bits are calculated and added to two partial products of implicit bits at the same time as the CSA compression, and the partial products are combined together after the CSA compression for several stages to continue the compression. Thus, timing optimization during Booth encoding can be realized.

[0176] For example, with reference to Figure 5 Taking f64 as an example, the fractional part is 53 bits, and the mantissa part is 52 bits. If the fractional part is directly subjected to fast Booth encoding, 27 partial products are generated. If the mantissa part is subjected to Booth encoding first, 27 partial products are also generated, and the subsequent implicit bits are added to two partial products, a total of 29 partial products.

[0177] In the embodiment, a first mantissa of a first floating point number and a second mantissa of a second floating point number are obtained, a first partial product is obtained according to the first mantissa and the second mantissa, the first partial product is compressed to obtain a first compression result, and in the process of compressing the first partial product, a first implicit bit of the first floating point number and a second implicit bit of the second floating point number are obtained to obtain a second partial product. According to the first compression result and the second partial product, a product of the first floating point number and the second floating point number is obtained. In the process of compression, the implicit bits are calculated and added to two partial products of implicit bits, and the partial products are combined together after compression to continue the compression. Thus, the time of obtaining the product can be shortened, and the operation period of the floating point multiplication operation is shortened.

[0178] Figure 5 and Figure 6 In the compression process shown, the CSA is a CSA3_2 compressor that compresses three operands into two operands. In the embodiment, a one-level CSA4_2 compressor is used to replace the CSA3_2 compressor for compression processing in the process of the last four partial products, to realize timing optimization.

[0179] According to Figure 6 the embodiment shown, the time of the optimized fast Booth encoding during the calculation of the product of the double-precision floating point number is longer than the time of the one-level CSA3_2. The embodiment has positive benefits in timing, and realizes timing optimization of obtaining the product of the floating point number.

[0180] For example, the fractional parts of the first and second floating-point numbers can be directly multiplied using the multiplication sign "*", and then the product can be output to the synthesizer for optimization.

[0181] Figure 7 This is a flowchart illustrating the specific steps of a floating-point multiplication method provided in an embodiment of this application, as follows: Figure 7 As shown, the method may include:

[0182] Step S1: Perform sign processing on the first sign of the first floating-point number and the second sign of the second floating-point number to obtain the sign result.

[0183] The sign of the product is obtained using the following formula. .

[0184] Step S2: Perform sign processing on the first exponent of the first floating-point number and the second exponent of the second floating-point number to obtain the exponent of the product of the first floating-point number and the second floating-point number before shift processing.

[0185] Step S3: Calculate the fractional part of the product of the first floating-point number and the second floating-point number to be shifted.

[0186] For example, the shifted value of the product of the first and second floating-point numbers can be obtained according to the following formula:

[0187]

[0188]

[0189]

[0190] in, and These are the left shift number and the right shift number, respectively; truncate the left shift number. From the number of digits ( The data up to the least significant bit is used as Extract the right-shifted bits. From the number of digits ( The data up to the least significant bit is used as If the determined shift direction is leftward, then the final shift number is... ,otherwise, .

[0191] Step S4: Obtain the decimal product of the first floating-point number and the second floating-point number.

[0192] Step S5: Obtain the special result of multiplication operation on the special number when the first floating-point number and / or the second floating-point number are special numbers.

[0193] The steps S1 to S5 can be processed in parallel, so that the processing implementation can be saved, and the processing period of the floating-point multiplication operation is reduced.

[0194] Optionally, the first exponent of the first floating-point number and the second exponent of the second floating-point number are obtained, and in the process of calculating the product of the first floating-point number and the second floating-point number, a to-be-shifted parameter for performing a shift operation on the fractional part of the product is obtained according to the first exponent and the second exponent; the to-be-shifted parameter comprises a shift bit number and a shift direction; and the shift operation is performed on the fractional part of the product according to the shift bit number and the shift direction, to obtain the multiplication result of the first floating-point number and the second floating-point number.

[0195] Optionally, the to-be-shifted parameter for performing the shift operation on the fractional part of the product according to the first exponent and the second exponent comprises: obtaining a third exponent of the product according to the first exponent of the first floating-point number and the second exponent of the second floating-point number; and obtaining a shift bit number corresponding to the fractional part of the product according to the third exponent.

[0196] Optionally, in a case where the shift bit number comprises a left shift bit number, the shift bit number corresponding to the fractional part of the product according to the third exponent comprises: obtaining a first leading zero quantity of the first floating-point number and a second leading zero quantity of the second floating-point number; performing an or operation on the first leading zero quantity and the second leading zero quantity to obtain a third leading zero quantity; and obtaining the left shift bit number corresponding to the fractional part of the product according to the third exponent and the third leading zero quantity.

[0197] Optionally, the left shift bit number corresponding to the fractional part of the product according to the third exponent and the third leading zero quantity comprises: if the third leading zero quantity is less than the third exponent, the third leading zero quantity is determined as the left shift bit number; and if the third leading zero quantity is greater than or equal to the third exponent, a difference between the third exponent and a first preset exponent is determined as the left shift bit number.

[0198] Optionally, the first leading zero quantity of the first floating-point number and the second leading zero quantity of the second floating-point number are obtained, comprising: if the first exponent of the first floating-point number is equal to zero, a first splicing result obtained by splicing zero and a mantissa of the first floating-point number is obtained, and a leading zero quantity of the first splicing result is determined as the first leading zero quantity of the first floating-point number; if the first exponent of the first floating-point number is not equal to zero, the first leading zero quantity of the first floating-point number is determined as zero; if the second exponent of the second floating-point number is equal to zero, a second splicing result obtained by splicing zero and a mantissa of the second floating-point number is obtained, and a leading zero quantity of the second splicing result is determined as the second leading zero quantity of the second floating-point number; and if the second exponent of the second floating-point number is not equal to zero, the second leading zero quantity of the second floating-point number is determined as zero.

[0199] Optionally, in the case that the shift number includes a right shift number, the shift number corresponding to the decimal part of the product is obtained according to the third index, including: determining the difference between the second preset index and the third index as the right shift number corresponding to the decimal part of the product.

[0200] Optionally, the to-be-shifted parameter for the shift operation on the decimal part of the product is obtained according to the first index and the second index, including: obtaining the third index of the product according to the first index of the first floating-point number and the second index of the second floating-point number; if the third index is greater than zero, determining that the shift direction is left shift; if the third index is less than or equal to zero, determining that the shift direction is right shift.

[0201] Optionally, the first index of the first floating-point number and the second index of the second floating-point number are obtained, including: if the first floating-point number and the second floating-point number both belong to the first digital type, obtaining the first index of the first floating-point number and the second index of the second floating-point number; wherein the first digital type includes other digital types except the second digital type, and the second digital type includes: zero, non-number, and infinite number.

[0202] Optionally, the method further includes: if the first floating-point number and / or the second floating-point number belongs to the second digital type, obtaining the multiplication result of the first floating-point number and the second floating-point number according to the multiplication operation strategy corresponding to the second digital type; the second digital type includes: zero, non-number, and infinite number; wherein the multiplication operation strategy includes: if the first floating-point number and / or the second floating-point number is non-number, determining that the multiplication result of the first floating-point number and the second floating-point number is equal to a preset value; if the first floating-point number and the second floating-point number are both zero, or one of the first floating-point number and the second floating-point number is zero and the other is a digital type other than non-number and infinite, determining that the multiplication result of the first floating-point number and the second floating-point number is equal to zero; if the first floating-point number and the second floating-point number are both infinite numbers, or one of the first floating-point number and the second floating-point number is infinite and the other is a digital type other than non-number and zero, determining that the multiplication result of the first floating-point number and the second floating-point number is equal to infinite.

[0203] Optionally, the first index of the first floating-point number is obtained, including: obtaining a first initial index of the first floating-point number; if the first initial index is equal to zero, determining that the first index of the first floating-point number is equal to 1; if the first initial index is not equal to zero, determining that the first index of the first floating-point number is equal to the first initial index; the second index of the second floating-point number is obtained, including: obtaining a second initial index of the second floating-point number; if the second initial index is equal to zero, determining that the second index of the second floating-point number is equal to 1; if the second initial index is not equal to zero, determining that the second index of the second floating-point number is equal to the first initial index.

[0204] Step S6, according to the value to be shifted and the decimal multiplication result, carry detection is performed.

[0205] According to the method of any one of the preceding embodiments, according to the value to be shifted and the decimal multiplication result, carry detection is performed.

[0206] Step S7, according to the carry detection result and the exponent before the product is subjected to the shift processing, first exponent carry processing is performed.

[0207] Step S8, according to the value to be shifted and the decimal multiplication result, decimal shift is performed.

[0208] Steps S6 to S8 can be processed in parallel, thereby processing implementation can be saved and the processing period of the floating-point multiplication operation can be reduced.

[0209] The method of carry detection is as described in any one of the preceding embodiments, which will not be repeated here.

[0210] Step S9, after the decimal shift, mantissa rounding is performed to obtain the mantissa of the product.

[0211] Step S10, according to the first exponent carry processing and the decimal rounding result, second exponent carry processing is performed on the result after the mantissa rounding to obtain the exponent of the product after the shift operation.

[0212] Step S11, according to the sign, the exponent and the mantissa of the product, the mantissa, the product of the first floating-point number and the second floating-point number is obtained, which is the normal result.

[0213] Step S12, according to the mantissa of the product, the mantissa rounding result and the special result, the identification bit is obtained.

[0214] Step S13, according to the normal result and the special result, the final multiplication result of the first floating-point number and the second floating-point number is obtained.

[0215] Optionally, a shift result of the product of the first floating-point number and the second floating-point number is obtained; the shift result is a result of a shift operation on a decimal part of the product; a mantissa rounding operation is performed on the shift result to obtain a mantissa rounding result of the shift result; in the process of the mantissa rounding operation, a first judgment result of whether a mantissa of the shift result satisfies a first preset rounding condition is obtained; if the first judgment result is that the mantissa satisfies the first preset rounding condition, a target mantissa of a multiplication result of the first floating-point number and the second floating-point number is obtained according to the mantissa rounding result.

[0216] Optionally, the first judgment result of whether the mantissa satisfies the first preset rounding condition is obtained, including: obtaining a first parameter of the shift result; the first parameter includes at least one of the following: a value of the first reserved bit of the shift result, a value of the first rounding bit, and a value of the first sticky bit; and the first judgment result of whether the mantissa satisfies the first preset rounding condition is obtained according to the first parameter.

[0217] Optionally, in the case where the shift operation includes a right shift operation, the value of the first sticky bit is obtained, including: obtaining a shift mask; data of the shift mask from a second position to a lowest bit of the shift mask is 1, and data of other bits of the shift mask is 0; a total number of bits from the second position to the lowest bit of the shift mask is equal to a right shift number of the decimal part of the product subjected to the right shift operation; obtaining first data from a third position of the decimal part of the product to a lowest bit of the product; and a total number of bits from the third position to the lowest bit of the product is equal to a difference between the total width corresponding to the preset floating-point number type and 1.

[0218] The shift mask and the first data are subjected to an AND operation to obtain an AND operation result; and the AND operation result is subjected to an OR reduction operation to obtain the value of the first sticky bit corresponding to the right shift operation.

[0219] Optionally, the shift result is subjected to a mantissa rounding operation to obtain a mantissa rounding result of the shift result, including: the preset mantissa is subjected to the mantissa rounding operation to obtain the mantissa rounding result of the shift result; wherein, if the shift result satisfies a first condition, the preset mantissa includes: data of the shift result from a fourth position to a lowest bit; and a total number of bits from the fourth position to the lowest bit of the shift result is equal to a sum of a mantissa bit width corresponding to the preset floating-point number type and 1; and the first condition includes: the shift operation is a left shift operation, the decimal part of the product overflows, and the exponent of the product is not equal to 0; if the shift result does not satisfy the first condition, the preset mantissa includes: a zero padding result of data of the shift result from a fifth position to a lowest bit subjected to a low-bit zero padding operation; and a total number of bits from the fifth position to the lowest bit of the shift result is equal to the mantissa bit width corresponding to the preset floating-point number type.

[0220] Optionally, the shift result is subjected to a mantissa rounding operation to obtain a mantissa rounding result of the shift result, including: data of the preset mantissa from a highest bit to a sixth position is subjected to a plus 1 operation to obtain the mantissa rounding result of the shift result; wherein, a total number of bits from the highest bit of the preset mantissa to the sixth position is equal to a mantissa width of the preset floating-point number type.

[0221] Optionally, the method further includes: if the first judgment result is that the mantissa does not satisfy the first preset rounding condition, obtaining a target mantissa of a multiplication result of the first floating-point number and the second floating-point number according to the preset mantissa.

[0222] Optionally, the method further comprises: obtaining overflow information of the exponent of the shift result; if the overflow information is not overflow, and the first determination result is that the mantissa does not satisfy the first preset rounding condition, the method further comprises: determining the data from the highest bit to the sixth bit of the preset mantissa as the target mantissa of the multiplication result of the first floating-point number and the second floating-point number; and the total number of bits between the highest bit and the sixth bit of the preset mantissa is equal to the mantissa width of the preset floating-point number type.

[0223] Optionally, the method further comprises: obtaining overflow information of the exponent of the shift result; if the overflow information is not overflow, and the first determination result is that the mantissa satisfies the first preset rounding condition, the method further comprises: obtaining the target mantissa of the multiplication result of the first floating-point number and the second floating-point number according to the mantissa rounding result, comprising: determining the mantissa rounding result as the target mantissa of the multiplication result.

[0224] Optionally, the method further comprises: obtaining the overflow information of the exponent of the shift result; if the overflow information is overflow, the preset target mantissa is determined as the target mantissa of the multiplication result; wherein if the preset rounding mode is a rounding mode other than the rounding mode to zero, the rounding mode for positive numbers to down, and the rounding mode for negative numbers to up, the total number of bits of the preset target mantissa is equal to the mantissa bit width corresponding to the preset floating-point number type, and each bit value is 0; if the preset rounding mode is the rounding mode to zero, the rounding mode for positive numbers to down, or the rounding mode for negative numbers to up, the total number of bits of the preset target mantissa is equal to the mantissa bit width corresponding to the preset floating-point number type, and each bit value is 1.

[0225] Optionally, the method further comprises: obtaining the exponent of the shift result, and performing an exponent carry operation on the exponent of the shift result to obtain an exponent carry result; in the process of performing the exponent carry operation, obtaining a second determination result of whether the exponent of the shift result satisfies a first preset carry condition; if the second determination result is that the exponent satisfies the first preset carry condition, obtaining the target exponent of the multiplication result of the first floating-point number and the second floating-point number according to the exponent carry result; if the second determination result is that the exponent does not satisfy the first preset carry condition, obtaining the target exponent of the multiplication result of the first floating-point number and the second floating-point number according to the exponent.

[0226] Optionally, the second determination result of whether the exponent of the shift result satisfies the first preset carry condition comprises: if the mantissa of the shift result satisfies the first preset rounding condition, and the value of each bit of the preset mantissa of the shift result from the highest bit to the sixth bit is 1, it is determined that the second determination result is that the exponent of the shift result satisfies the first preset carry condition; the total number of bits between the highest bit and the sixth bit of the preset mantissa is equal to the mantissa width of the preset floating-point number type; if the mantissa of the shift result does not satisfy the first preset rounding condition, or the value of any bit of the preset mantissa of the shift result from the highest bit to the sixth bit is 0, it is determined that the second determination result is that the exponent of the shift result does not satisfy the first preset carry condition.

[0227] Optionally, the method further comprises: obtaining overflow information of the exponent of the shift result; if the overflow information is an overflow, determining the preset target exponent as the target exponent of the multiplication result; wherein if the preset rounding mode is a rounding mode other than the rounding to zero mode, rounding down for positive numbers and rounding up for negative numbers, the preset target exponent is an exponent with a total bit number equal to the exponent bit width of the preset floating-point number and each bit value being equal to 1; if the preset rounding mode is the rounding to zero mode, rounding down for positive numbers or rounding up for negative numbers, the preset target exponent is an exponent with a total bit number equal to the exponent bit width of the preset floating-point number, the value of the lowest bit being 0 and the values of the other bits being 1.

[0228] Optionally, the method further comprises: obtaining overflow information of the exponent of the shift result; if the overflow information is not an overflow and the second determination result is that the exponent satisfies the first preset carry condition, obtaining the multiplication result of the first floating-point number and the second floating-point number according to the exponent carry result, including: determining the exponent carry result as the target exponent of the multiplication result; if the overflow information is not an overflow and the second determination result is that the exponent does not satisfy the first preset carry condition, obtaining the multiplication result of the first floating-point number and the second floating-point number according to the exponent, including: determining the exponent of the shift result as the target exponent of the multiplication result.

[0229] Optionally, the method further comprises: obtaining overflow information of the exponent of the shift result; if the overflow information of the exponent is an overflow, determining the sign bit of the multiplication result as an overflow; if the shift result satisfies any one of the second conditions, determining the sign bit of the multiplication result as an inaccuracy; the second conditions include: the overflow information is an overflow, the shift result first rounding bit, and the value of the first sticky bit is 1; if the exponent of the product is equal to 0 and the exponent of the shift result does not satisfy the preset second carry condition and the shift result satisfies any one of the second conditions, determining the sign bit of the multiplication result as an underflow.

[0230] Optionally, the method further comprises: if the values of the exponent from the highest bit to the first bit are all 1 and the exponent satisfies the third condition, determining the overflow information as an overflow; the third condition includes: the value of the lowest bit of the exponent is 1 or the exponent satisfies the first preset carry condition; if the shift result does not satisfy the third condition, determining that the exponent of the shift result does not satisfy the preset second carry condition, and the third condition includes: the data of the preset tail number of the shift result from the highest bit to the sixth bit are all 1, the value of the second reserved bit of the shift result is 1, and the tail number of the shift result satisfies the second preset rounding condition.

[0231] Optionally, the method further comprises: obtaining a second parameter of the shift result; the second parameter comprises at least one of: a value of a second reserved bit of the shift result, a value of a second rounding bit, and a value of a second sticky bit; obtaining a third judgment result of whether the mantissa satisfies a second preset rounding condition according to the second parameter; the value of the second reserved bit is a value of the preset mantissa at a seventh position; a position interval between the seventh position and a lowest bit of the mantissa is equal to a sum of a mantissa bit width of the preset floating-point number type and 1; the value of the second rounding bit is a value of the preset mantissa at an eighth position; a total bit number from the eighth position to the lowest bit of the preset mantissa is equal to the mantissa bit width of the preset floating-point number type; in a case where the shift operation is left shift, the value of the second sticky bit is an or reduction operation result of data of the preset mantissa from a ninth position to the lowest bit; a total bit number from the ninth position to the lowest bit of the preset mantissa is equal to a difference between the mantissa bit width of the preset floating-point number type and 1; in a case where the shift operation is right shift, the value of the second sticky bit is equal to a value of a first sticky bit corresponding to the right shift operation.

[0232] By the embodiment, the long processing period problem caused by serial processing of each part of the floating-point number is avoided, and the method for obtaining the shift value in step S6 can be implemented by referring to any method in the foregoing embodiments. In the related art, three periods are required to calculate the product of the half-precision floating-point number, the product of the single-precision floating-point number, and the product of the double-precision floating-point number. Based on the embodiment, the processing time can be shortened, and the operation period of the half-precision floating-point number product and the single-precision floating-point number product can be shortened to two. For the multiplication operation of the double-precision floating-point number, the operation can be completed in a half period of the third period, that is, based on the embodiment, the number of periods of the floating-point multiplication operation can be shortened.

[0233] In one embodiment, referring to Figure 8 For the multiplication operation of the double-precision floating-point number (f64), the operation can be processed in three periods. The first period is used to perform steps S1 to S5 in parallel and store the processing results in the corresponding register 1. The second period is used to obtain the data of steps S6 to S8 and store the data in the corresponding register 2. Steps S9 to S13 are performed in the third period. Based on the method of the embodiment, the result is calculated in a half period of the third period, and the data can be bypassed to other functional units for fast wake-up.

[0234] Continuing to refer to Figure 8 The decimal multiplication is implemented by using the fast Booth and set compression method, the partial product is stored in the register 1, the partial product is added to obtain the product, and then the decimal shift operation of step S8 is performed on the product. The set compression method is the carry-saved adder (CSA) method.

[0235] In one embodiment, referring to Figure 9 For multiplication of half-precision floating-point numbers (f16) and single-precision floating-point numbers (f32), the operation period can be shortened to two periods. The first period is used to perform steps S1-S5 in parallel and store the processing results in the respective corresponding registers Reg; and the second period is used to perform steps S6-S13. Based on the method of the embodiment, the second period is completed in half a period, and the data can be bypassed to other functional units for fast wake-up.

[0236] In combination with Figure 8 and Figure 9 , the difference between the two processing methods is that Figure 9 The embodiment can calculate the product of floating-point numbers by multiplication, Figure 8 The embodiment shown in the figure obtains the product of floating-point numbers by the fast Booth and CSA compression method.

[0237] It should be noted that f64 can also be implemented by the two-period processing method shown in Figure 9 f32 and f16 can also be implemented by the three-period processing method shown in Figure 8 .

[0238] The embodiment optimizes the timing of the floating-point multiplication calculation method, designs a pipeline, and reduces the floating-point multiplication calculation period of f32 and f16 in the processor to two periods, and f64 to three periods, and all can support fast wake-up. The embodiment can shorten the calculation period of floating-point multiplication, improve the performance of the processor in executing floating-point multiplication instructions, and is not limited to the processor, but also can improve the calculation performance in other calculation fields that require floating-point multiplication.

[0239] For example, based on the method of the embodiment, in the application scenario of half-precision floating-point multiplication and single-precision floating-point multiplication based on a CPU processor, the period of floating-point multiplication in the related art is reduced from 3 to 2, and the total period is reduced by 33.3%.

[0240] Referring to Figure 10The embodiment provides a floating point multiplication circuit, which comprises an overflow information acquisition unit 302, and a to-be-shifted parameter acquisition unit 301 and an index adjustment unit 303 connected with the overflow information acquisition unit 302; the to-be-shifted parameter acquisition unit 301 is used for acquiring a first index of a first floating point number and a second index of a second floating point number; and the to-be-shifted parameter acquisition unit 301 is further used for acquiring a to-be-shifted parameter for performing a to-be-shifted operation on a decimal part of a product of the first floating point number and the second floating point number according to the first index and the second index; the to-be-shifted parameter comprises a shift direction and a shift bit number; the overflow information acquisition unit 302 is used for acquiring overflow information of a shift result of the shift operation on the decimal part of the product according to the to-be-shifted operation parameter; the overflow information comprises overflow or no overflow; and the index adjustment unit 303 is used for adjusting an index of the shift result according to the overflow information, so as to obtain a multiplication result of the first floating point number and the second floating point number.

[0241] With reference to Figure 11 In the case that the shift direction is left shift and the shift bit number comprises a left shift bit number, the overflow information acquisition unit comprises a shift mask acquisition unit, the shift mask acquisition unit is used for acquiring an initial mask, and the initial mask is shifted right by a value of a highest bit of the initial mask according to the left shift bit number, so as to obtain a shift mask; the value of the highest bit of the initial mask is 1, and the values of other bits are 0; a first AND operation subunit is used for performing AND operation on the shift mask and the product, so as to obtain an AND operation result; and a left shift operation overflow information acquisition subunit is used for acquiring overflow information of the decimal part of the left shift result according to the AND operation result.

[0242] Optionally, the left shift operation overflow information acquisition subunit comprises a first overflow information acquisition subunit, and a second AND operation subunit connected with the first overflow information acquisition subunit.

[0243] The first overflow information acquisition subunit is used for acquiring a first number of leading zeros of the first floating point number and a second number of leading zeros of the second floating point number, and acquiring a third number of leading zeros of the product according to the first number of leading zeros and the second number of leading zeros; the first overflow information acquisition subunit is further used for acquiring a third index of the product according to the first index and the second index, and acquiring first overflow information of the shift result according to a comparison result of the third index and the third number of leading zeros; and the second AND operation subunit is used for determining that the overflow information of the decimal part of the left shift result is overflow if the or reduction operation result is 1 and the first overflow information is overflow; and determining that the overflow information of the decimal part of the left shift result is no overflow if the or reduction operation result is 0 or the first overflow information is no overflow.

[0244] With reference to Figure 11The second AND operation subunit obtains the first overflow information leftShiftNoOverFlow and the result of the OR and reduction operation dMulShiftMask, and performs an AND operation to obtain the overflow information corresponding to the left shift operation leftShiftOverFlow.

[0245] In the case of right shift, the shift bit number includes the right shift number, and the overflow information obtaining unit includes a third AND operation subunit. If the value of the highest bit of the product decimal part is equal to 1 and the right shift number is equal to 1, the third AND operation subunit determines that the decimal part of the right shift result overflows. If the value of the highest bit of the product decimal part is equal to 0 or the right shift number is not equal to 1, the third AND operation subunit determines that the decimal part of the right shift result does not overflow.

[0246] Referring to Figure 11 The third AND operation subunit obtains the right shift value (shiftBits==1) and the value of the highest bit of the product decimal part (dMul(2*decimlWidth-1)), and performs an AND operation to obtain the overflow information corresponding to the right shift operation rightShiftOverFlow.

[0247] Referring to Figure 12 The exponent adjusting unit includes a first OR operation subunit and a first multiplexer (MUX) connected to the first OR operation subunit. If the overflow information is no overflow or the values of all bits in the third exponent of the product are equal to 1, the first OR operation subunit determines that the product overflows. If the overflow information is overflow and the value of at least one bit in the third exponent of the product is equal to 0, the first OR operation subunit determines that the product does not overflow. If the overflow information is no overflow or the values of all bits in the third exponent of the product are equal to 1, the first multiplexer keeps the exponent unchanged. If the overflow information is overflow and the value of at least one bit in the third exponent of the product is equal to 0, the first multiplexer performs a carry operation on the exponent.

[0248] Referring to Figure 13The embodiment of the application provides a floating point multiplication device, and the device 40 comprises: a first obtaining module 401, which is used for obtaining a first exponent of a first floating point and a second exponent of a second floating point; a second obtaining module 402, which is used for obtaining a to-be-shifted parameter for performing a to-be-shifted operation on a decimal part of a product of the first floating point and the second floating point according to the first exponent and the second exponent; the to-be-shifted parameter comprises a shift direction and a shift bit number; a third obtaining module 403, which is used for obtaining overflow information of a decimal part of a shift result according to the to-be-shifted parameter in a process of obtaining the shift result of the product according to the to-be-shifted parameter; the overflow information comprises overflow or no overflow; and an exponent adjusting module 404, which is used for adjusting the exponent of the shift result according to the overflow information, so as to obtain a multiplication result of the first floating point and the second floating point.

[0249] Optionally, in the case that the shift direction is left shift, the shift bit number comprises a left shift number; the third obtaining module 403 is further used for: obtaining an initial mask; the highest bit of the initial mask is 1, and the other bits are 0; shifting the value of the highest bit of the initial mask to the right according to the left shift number, so as to obtain a shift mask; performing an AND operation on the shift mask and the product, so as to obtain an AND operation result; and obtaining the overflow information of the decimal part of the shift result according to the AND operation result.

[0250] Optionally, the third obtaining module 403 is further used for: performing an OR reduction operation on the AND operation result, so as to obtain an OR reduction operation result; and obtaining the overflow information of the decimal part of the shift result according to the OR reduction operation result.

[0251] Optionally, the third obtaining module 403 is further used for: obtaining a third exponent of the product according to the first exponent and the second exponent; obtaining first overflow information of the shift result according to the third exponent; if the OR reduction operation result is 1 and the first overflow information is overflow, determining that the overflow information of the decimal part of the shift result is overflow; and if the OR reduction operation result is 0 or the first overflow information is no overflow, determining that the overflow information of the decimal part of the shift result is no overflow.

[0252] Optionally, the third obtaining module 403 is further used for: obtaining a first number of leading zeros of the first floating point and a second number of leading zeros of the second floating point; obtaining a third number of leading zeros of the product according to the first number of leading zeros and the second number of leading zeros; and obtaining the first overflow information of the shift result according to a comparison result of the third exponent and the third number of leading zeros.

[0253] Optionally, the mantissa of the initial mask is equal to the number of bits of the decimal part of the product; optionally, the third obtaining module 403 is further configured to: perform an AND operation on the shifted mask and the product to obtain an initial AND operation result; and obtain an AND operation result by intercepting data from the highest bit to the first bit of the initial AND operation result, wherein the total number of bits from the highest bit to the first bit of the initial AND operation result is equal to the width of the mantissa of the preset floating-point number type.

[0254] Optionally, the third obtaining module 403 is further configured to: obtain a third exponent of the product according to the first exponent and the second exponent; if the third exponent is equal to zero, perform right shifting on the value of the highest bit of the initial mask according to a first shift value to obtain the shifted mask; the first shift value is equal to the sum of the left shift number and 1; if the third exponent is not equal to zero, perform right shifting on the value of the highest bit of the initial mask according to the left shift number to obtain the shifted mask.

[0255] Optionally, in the case that the shift direction includes right shifting and the shift number includes the right shift number, the third obtaining module 403 is further configured to: if the value of the highest bit of the decimal part of the product is equal to 1 and the right shift number is equal to 1, determine that the decimal part of the shift result overflows; if the value of the highest bit of the decimal part of the product is equal to 0 or the right shift number is not equal to 1, determine that the decimal part of the shift result does not overflow.

[0256] Optionally, the exponent adjusting module is further configured to: if the overflow information is no overflow or the value of each bit of the third exponent of the product is 1, keep the exponent unchanged; if the overflow information is overflow and the value of at least one bit of the third exponent of the product is equal to 0, perform a carry operation on the exponent.

[0257] Optionally, the apparatus 40 further includes: a fourth obtaining module configured to obtain a first mantissa of the first floating-point number and a second mantissa of the second floating-point number; a fifth obtaining module configured to obtain a first partial product according to the first mantissa and the second mantissa; a sixth obtaining module configured to obtain a first compressed result by compressing the first partial product, and obtain a second partial product of a first implicit bit of the first floating-point number and a second implicit bit of the second floating-point number in the process of compressing the first partial product; and a compression module configured to obtain the product of the first floating-point number and the second floating-point number according to the first compressed result and the second partial product.

[0258] In summary, in the embodiment of the present application, it is not necessary to determine whether the exponent needs to be incremented according to the detection result of the value of the highest bit of the shift result after obtaining the product of the first floating-point number and the second floating-point number and performing the shift operation on the product, compared with the method in the related art that first obtains the product, then performs the shift operation on the product, determines whether the value of the highest bit of the shift result is 1, and determines whether the exponent needs to be incremented according to the determination result. The embodiment reduces the processing time of the exponent increment and the operation period of the floating-point number multiplication operation.

[0259] Figure 14 FIG. 5 is a block diagram of an electronic device 500 according to an example embodiment. The electronic device 500 can be, for example, a mobile phone, a computer, a digital broadcasting terminal, a message transmitting / receiving device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0260] Referring to Figure 14 The electronic device 500 can include one or more of the following components: a processing component 502, a memory 504, a power supply component 506, a multimedia component 508, an audio component 510, an input / output (I / O) interface 512, a sensor component 514, and a communication component 516.

[0261] The processing component 502 usually controls overall operations of the electronic device 500, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 502 can include one or more processors 520 to execute instructions to complete all or part of steps of the above-described methods. The memory 504 is used to store various types of data to support operations of the electronic device 500. The memory 504 can be implemented by any type of volatile or nonvolatile storage devices or a combination thereof. The power supply component 506 supplies power for various components of the electronic device 500. The power supply component 506 can include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 500.

[0262] The multimedia component 508 includes a screen to provide an output interface between the electronic device 500 and a user. The audio component 510 is used to output and / or input audio signals. The received audio signals can be further stored in the memory 504 or transmitted via the communication component 516. The I / O interface 512 provides an interface between the processing component 502 and peripheral interface modules.

[0263] The sensor component 514 includes one or more sensors to provide state evaluation of various aspects for the electronic device 500. The sensor component 514 can include a proximity sensor configured to detect the presence of a nearby object without any physical contact. The communication component 516 is used to facilitate wired or wireless communication between the electronic device 500 and other devices. The electronic device 500 can access a wireless network based on a communication standard. In an example embodiment, the communication component 516 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In an example embodiment, the electronic device 500 is used to implement a floating-point multiplication method provided by the embodiments.

[0264] In an example embodiment, a non-transitory computer readable storage medium including instructions, such as the memory 504 including instructions, is also provided, which can be executed by the processor 520 of the electronic device 500 to complete the above method. For example, the non-transitory storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, and an optical data storage device, etc.

[0265] Figure 15 is a block diagram of an electronic device 600 according to an example embodiment. For example, the electronic device 600 can be provided as a server. Referring to Figure 15 , the electronic device 600 includes a processing component 622, which further includes one or more processors, and a memory resource represented by a memory 632, for storing instructions executable by the processing component 622, such as an application program. The application program stored in the memory 632 can include one or more than one module each corresponding to a set of instructions. In addition, the processing component 622 is configured to execute the instructions to perform a floating point multiplication method provided by the embodiments of the present application.

[0266] The electronic device 600 can also include a power supply component 626 configured to perform power management of the electronic device 600, a wired or wireless network interface 650 configured to connect the electronic device 600 to a network, and an input / output (I / O) interface 658. The electronic device 600 can operate based on an operating system stored in the memory 632, such as Windows ServerTM, Mac OS XTM, UnixTM, LinuxTM, FreeBSDTM or the like.

[0267] The embodiments of the present application also provide a computer program product including a computer program, which when executed by a processor implements a floating point multiplication method.

[0268] Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims.

Claims

1. A floating-point multiplication circuit, characterized in that, The overflow information acquisition unit is connected with the to-be-shifted parameter acquisition unit and the index adjustment unit. The to-be-shifted parameter acquisition unit is configured to acquire a first index of the first floating-point number and a second index of the second floating-point number. The to-be-shifted parameter acquisition unit is further configured to acquire, according to the first index and the second index, a to-be-shifted parameter for performing a to-be-shifted operation on a decimal part of a product of the first floating-point number and the second floating-point number; the to-be-shifted parameter comprises a shift direction and a shift bit number. The overflow information acquisition unit is configured to acquire, according to the to-be-shifted parameter, overflow information of a decimal part of a shift result of the product in a process of acquiring the shift result according to the to-be-shifted parameter; the overflow information comprises overflow or no overflow. The index adjustment unit is configured to adjust, according to the overflow information, an index of the shift result, to obtain a multiplication result of the first floating-point number and the second floating-point number. In a case where the shift direction is left shift and the shift bit number comprises a left shift number, the overflow information acquisition unit comprises a shift mask acquisition subunit, a first AND operation subunit connected with the shift mask acquisition subunit, and a left shift operation overflow information acquisition subunit connected with the first AND operation subunit; the shift mask acquisition subunit is configured to acquire an initial mask, and shift a value of a highest bit of the initial mask to the right according to the left shift number, to obtain a shift mask; the value of the highest bit of the initial mask is 1, and values of other bits are 0; the first AND operation subunit is configured to perform AND operation on the shift mask and the product, to obtain an AND operation result; and the left shift operation overflow information acquisition subunit is configured to acquire, according to the AND operation result, the overflow information of the decimal part of the shift result.

2. The circuit of claim 1, wherein, In a case where the shift direction comprises right shift and the shift bit number comprises a right shift number, the overflow information acquisition unit comprises: A third AND operation subunit is configured to determine that the decimal part of the shift result overflows, if a value of a highest bit of the decimal part of the product is equal to 1 and the right shift number is equal to 1. The third AND operation subunit is further configured to determine that the decimal part of the shift result does not overflow, if the value of the highest bit of the decimal part of the product is equal to 0 or the right shift number is not equal to 1.

3. The circuit of claim 1, wherein, The index adjustment unit comprises a first OR operation subunit and a first multiplexer connected with the first OR operation subunit. The first OR operation subunit is configured to determine that the product overflows, if the overflow information is no overflow or values of all bits in a third index of the product are equal to 1. The first OR operation subunit is further configured to determine that the product does not overflow, if the overflow information is overflow and at least one bit in the third index of the product is equal to 0. The first multiplexer is configured to keep the index unchanged, if the overflow information is no overflow or the values of all bits in the third index of the product are equal to 1. The first multiplexer is further configured to perform a carry operation on the exponents if the overflow information is overflow and a value of at least one bit in a third exponent of the product is equal to 0.

4. The circuit of claim 1, wherein, The left shift operation overflow information obtaining subunit is further configured to: perform an or reduction operation on the and operation result to obtain an or reduction operation result; obtain overflow information of a decimal part of the shift result according to the or reduction operation result.

5. The circuit of claim 4, wherein, The left shift operation overflow information obtaining subunit is further configured to: obtain a third exponent of the product according to the first exponent and the second exponent; obtain first overflow information of the shift result according to the third exponent; if the or reduction operation result is 1 and the first overflow information is overflow, determine that the overflow information of the decimal part of the shift result is overflow; if the or reduction operation result is 0 or the first overflow information is not overflow, determine that the overflow information of the decimal part of the shift result is not overflow.

6. The circuit of claim 5, wherein, The left shift operation overflow information obtaining subunit is further configured to: obtain a first number of leading zeros of the first floating-point number and a second number of leading zeros of the second floating-point number; obtain a third number of leading zeros of the product according to the first number of leading zeros and the second number of leading zeros; obtain first overflow information of the shift result according to a comparison result of the third exponent and the third number of leading zeros.

7. The circuit of claim 1, wherein, The first and operation subunit is further configured to: perform an and operation on the shift mask and the product to obtain an initial and operation result; obtain the and operation result by intercepting data from a highest bit to a first bit in the initial and operation result; wherein a total number of bits from the highest bit to the first bit in the initial and operation result is equal to a width of a mantissa of a preset floating-point number type.

8. The circuit of claim 1, wherein, The shift mask obtaining subunit is further configured to: obtain a third exponent of the product according to the first exponent and the second exponent; if the third exponent is equal to 0, perform a right shift on a value of a highest bit of the initial mask according to a first shift value to obtain the shift mask; the first shift value is equal to a sum of the left shift number and 1; if the third exponent is not equal to 0, perform a right shift on the value of the highest bit of the initial mask according to the left shift number to obtain the shift mask.

9. The circuit of claim 1, wherein, The overflow information obtaining unit is further configured to: obtain a first mantissa of the first floating-point number and a second mantissa of the second floating-point number; obtain a first partial product according to the first mantissa and the second mantissa; perform compression on the first partial product to obtain a first compression result, and obtain a second partial product of a first implicit bit of the first floating-point number and a second implicit bit of the second floating-point number in the process of performing the compression on the first partial product; obtain the product of the first floating-point number and the second floating-point number according to the first compression result and the second partial product.

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