Data enhancement and yield analysis method and system for multi-defect pattern wafer map

Abstract

The application discloses a kind of data enhancement and yield analysis methods, system for multi-defect pattern wafer map, belong to integrated circuit manufacturing detection technical field. Obtain original multi-defect pattern wafer map, construct data set after amplification quantity;Extract multi-scale feature of wafer map, form defect feature by feature pyramid fusion, then generate position-sensitive defect activation feature map using defect activation module, aggregate as defect feature matrix after normalization;Each row of feature vector of the matrix is output simultaneously by three independent prediction heads Defect type probability, confidence score and die level mask, based on dynamic convolution calculation instance segmentation mask and implement confidence re-score, complete model training by dichotomous matching and combination loss;Finally, based on segmentation result, calculate defect count yield and spatial distribution yield.The application solves the technical problems of integrated circuit manufacturing, such as multi-defect wafer map data scarcity, insufficient automated analysis and single traditional detection function.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit manufacturing detection, and particularly relates to a data enhancement and yield analysis method and system for a multi-defect pattern wafer map. BACKGROUND

[0002] Chip probe testing is the final test for evaluating the performance and function of each chip after the wafer goes through the entire manufacturing process. The failure mode in the chip probe testing process is called bin, and the failure and abnormality of a certain link on the production line will lead to a certain specific defect pattern. A spatial pattern formed by gathering multiple failed dies in space is called Gross Failure Area (GFA), which can also be referred to as a defect pattern. The classification, positioning and counting of wafer map defects are very important for determining the failure fast backtracking corresponding process and improving the yield in integrated circuit manufacturing.

[0003] Currently, some works use machine learning methods to automatically classify wafer map defects. For example, a wafer image recognition method, device, equipment and application (CN115841663A) uses DBSCAN and OPTICS algorithms to denoise the wafer map, and then inputs the convolutional neural network for classification. The output only has the type information of the defect, and lacks a yield analysis integrated system for wafer map defect classification, positioning and counting. For another example, a wafer surface defect visual detection method and system (CN117808809B) and a machine learning assisted wafer manufacturing process evaluation and abnormality detection method (CN118887208B) use image segmentation algorithms to segment the internal micro-defects of the dies in the scanning electron microscope images. The algorithms used have high complexity, consume large computing resources, and cannot analyze the yield from the wafer level.

[0004] As a key technology in machine learning, data augmentation can not only significantly increase the number of wafer map data, but more importantly, it can enhance the diversity and coverage of the data, making the trained model better adapt to the various forms of defects in the actual production environment, thereby improving the accuracy and practicality of the defect detection algorithm. Instance segmentation algorithm, as a core technology in the field of computer vision, aims to detect each object instance in the image and generate an accurate pixel-level segmentation mask for it, which can accurately distinguish different individuals of the same type in complex scenes. Various representative methods have emerged in this field: Mask R-CNN based on two-stage detection framework realizes high-precision segmentation through region proposal network and mask prediction branch; YOLACT and SOLOv2 algorithms based on single-stage detection significantly improve the inference speed while ensuring segmentation quality; and emerging algorithms such as Mask2Former based on Transformer architecture further improve the segmentation performance in complex scenes. With its outstanding ability in target detection, positioning and pixel-level classification, data-driven instance segmentation technology provides an ideal solution for wafer defect detection. By training a specialized wafer map defect segmentation model, it can accurately identify various types of defects on the wafer surface (such as scratches, edge rings, etc.), accurately locate the spatial position of the defect area, and automatically count the number and distribution of different types of defects in each wafer. This automated defect detection and quantitative analysis capability not only enables accurate calculation of wafer yield, but also provides important data support and decision-making basis for integrated circuit manufacturing process parameter optimization, equipment maintenance strategy formulation, and continuous improvement of production processes.

[0005] However, the wafer map data in the prior art relies heavily on manual annotation, and labeled multi-defect wafer map data is extremely scarce; defect analysis and yield calculation still mainly rely on the experience and subjective judgment of yield engineers, with low automation; existing machine learning-based wafer map defect detection methods have single functions, only output type information, lack of integrated yield analysis systematic solutions for defect classification, positioning and counting, lack of key defect location and wafer quantity information affected by corresponding defects, and thus cannot comprehensively analyze the root cause and process location of failure, cannot quantitatively calculate the yield impact, and cannot meet the complete needs in actual production. SUMMARY

[0006] To solve the above problems, the present application proposes a data augmentation and yield analysis method and system for multi-defect pattern wafer map, which increases the number and diversity of wafer map data and realizes accurate detection and segmentation of multi-type, multi-area and complex overlapping relationship defects.

[0007] The technical solution adopted by the present application is as follows:

[0008] In a first aspect, the present application provides a data enhancement and yield analysis method for multi-defect pattern wafer map, comprising the following steps:

[0009] (1) generating a multi-defect pattern wafer map from integrated circuit test log visualization, and expanding the number of multi-defect pattern wafer maps in the form of defect pattern combination through an adaptive data enhancement algorithm to construct a data set;

[0010] (2) extracting multi-scale features of the wafer map, fusing the features through a feature pyramid to form defect features, and generating a position-sensitive defect activation feature map through a defect activation module; aggregating the defect features using the normalized defect activation feature map to obtain an aggregated defect feature matrix;

[0011] (3) generating a segmentation result including defect type probability, confidence score and die-level mask through three independent prediction heads for each row of feature vectors in the defect feature matrix, calculating an instance segmentation mask based on the die-level mask and dynamic convolution, and re-scoring the confidence score based on the defect type probability, and training the model based on the instance segmentation mask and the re-scored confidence score result;

[0012] (4) generating an instance segmentation mask and a re-scored confidence score result based on the trained model, calculating the ratio of the number of qualified dies to the total number of dies to obtain a defect count yield result, and introducing a defect position and size weight function based on the defect count to quantify the impact of spatial distribution on yield, and calculating the spatial distribution yield.

[0013] Further, in step (1), the defect pattern combination includes:

[0014] (1.1) loading the original wafer map and defect annotation, and setting the number of synthetic samples N k , k = 1, 2, …, K; K represents the total number of defect types;

[0015] (1.2) randomly combining i defect patterns of different types, and randomly selecting an overlap rate parameter between the defect patterns based on a preset probability distribution;

[0016] (1.3) extracting geometric transformation mapping rules to translate, rotate or scale the defect patterns so that the superimposed patterns meet the overlap rate requirement;

[0017] (1.4) superimposing the defect patterns according to the predefined bin code priority rule to generate a composite defect pattern;

[0018] (1.5) injecting random noise defects based on a preset probability distribution;

[0019] (1.6) saving the synthetic image and annotation, and iterating until all N k decreases to 0.

[0020] Further, the overlap rate parameter is an intersection over union, and the value range is 0.2-0.8.

[0021] Further, in step (1.6), if the defect pattern type randomly combined in the current iteration contains the kth defect pattern, then N k is reduced by 1, otherwise N k remains unchanged.

[0022] Further, the calculation process of the defect feature includes:

[0023] Extracting multi-scale features of the wafer map, respectively denoted as shallow features C3, middle features C4 and high features C5;

[0024] Performing a global average pooling operation on the high features C5 using different sizes of pooling kernels, and generating a first pyramid feature through convolution operation after splicing the pooling results;

[0025] Adding the middle features C4 through convolution operation to the first pyramid feature after upsampling to generate a second pyramid feature;

[0026] Adding the shallow features C3 through convolution operation to the second pyramid feature after upsampling to generate a third pyramid feature;

[0027] Splicing the third pyramid feature, the second pyramid feature after upsampling and the first pyramid feature after upsampling, and fusing through convolution operation, and adding coordinate features to the fusion result before forming a defect feature through convolution.

[0028] Further, in step (2), the wafer map is taken as input, and the Swin Transformer backbone network is used to extract the third to fifth stage features as the wafer map shallow features, middle features and high features.

[0029] Further, the calculation process of the defect activation module includes:

[0030] Encoding the defect feature through four groups of continuous 3x3 convolution layers, each group of convolution layers gradually extracting local features and separately processed through Sigmoid activation function;

[0031] Splicing the four groups of activation results to obtain a position-sensitive defect activation feature map.

[0032] Further, the formulas of instance segmentation mask and confidence score re-evaluation are as follows:

[0033] ;

[0034] ;

[0035] wherein, and represents the instance segmentation mask and confidence re-score result corresponding to the i-th row of feature vectors, represents the die-level mask corresponding to the i-th row of feature vectors, represents three 3x3 convolutional layers, represents the defect feature, represents the d-th dimension, and D represents the total predicted dimension, represents the mask branch feature, represents the d-th dimension, represents the confidence score corresponding to the i-th row of feature vectors, represents the maximum predicted probability corresponding to the i-th row of feature vectors.

[0036] Further, the calculation formula of the spatial distribution yield is:

[0037] ;

[0038] ;

[0039] wherein, represents the spatial distribution yield, represents the impact value of the j-th defect, represents the center coordinates of the j-th defect instance, represents the area of the j-th defect instance, represents the total number of dies on the wafer, represents the number of instances of the i-th type of defect, and K represents the total number of defect types, represents the defect impact function considering position and size, represents the area size of the defect, represents the position weight function, represents the size impact adjustment parameter, is the reference defect area.

[0040] In a second aspect, the present application provides a data enhancement and yield analysis system for multi-defect pattern wafer maps, which is used to implement the above-mentioned data enhancement and yield analysis method for multi-defect pattern wafer maps.

[0041] The present application has the following beneficial effects:

[0042] The present application systematically solves the technical problems of data scarcity, insufficient automation analysis and single traditional detection function in integrated circuit manufacturing through an adaptive data enhancement mechanism, multi-scale feature fusion, a position-sensitive defect activation module and dual yield quantitative calculation of fused spatial distribution and size weight. Specifically, the present application first generates multi-defect combined patterns in accordance with the real distribution in a defect pattern combination manner through an adaptive data enhancement algorithm, significantly improving data diversity and scale; then uses a multi-scale feature extraction network and feature pyramid fusion technology to combine a continuous convolution chain to enhance the position sensitivity of defects, accurately capturing complex defects in wafer maps with multi-scale, high overlap and fuzzy boundaries; in the segmentation stage, a dynamic mask generation and confidence score re-scoring mechanism is introduced to realize high-precision calculation of classification, positioning and counting; finally, a defect position and size weight function is introduced on the basis of defect counting to quantify the influence of spatial distribution on yield, converting the detection result into a root cause analysis closed loop that can guide process optimization. BRIEF DESCRIPTION OF DRAWINGS

[0043] Figure 1 A method flowchart of the present application;

[0044] Figure 2 A multi-defect pattern wafer map data enhancement flowchart of the present application;

[0045] Figure 3 A defect activation module structure diagram of the present application;

[0046] Figure 4 A defect classification, positioning, segmentation and yield quantitative analysis overall model architecture diagram of the present application;

[0047] Figure 5 A multi-bin multi-GFA wafer map data set schematic diagram in an embodiment of the present application;

[0048] Figure 6 A segmentation visualization result diagram of different methods in an embodiment of the present application. DETAILED DESCRIPTION

[0049] The present application will be further described and explained with the specific embodiments. The embodiments are only exemplary and do not circumscribe the scope of the present disclosure. The technical features of each embodiment of the present application can be combined accordingly without conflict.

[0050] The accompanying drawings are merely illustrative and are not necessarily drawn to scale. Some of the block diagrams shown in the drawings are functional entities, which do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0051] The flowchart shown in the drawing is only an exemplary illustration and does not necessarily include all the steps. For example, some steps can be further decomposed, and some steps can be combined or partially combined, so the actual execution order can be changed according to the actual situation.

[0052] The present application proposes a data enhancement and yield analysis method for multi-defect pattern wafer map, to realize adaptive data enhancement of multi-defect wafer map and yield analysis integration of defect classification, positioning and counting. The overall model architecture of defect classification, positioning and segmentation and yield quantitative analysis adopted is as shown in Figure 4 The multi-scale features of the wafer map are extracted, the defect features are formed through feature pyramid fusion, and the position-sensitive defect activation feature map is generated by using the defect activation module; the defect features are aggregated by using the normalized defect activation feature map to obtain the aggregated defect feature matrix; each row of feature vectors in the defect feature matrix generates a segmentation result through three independent prediction heads, including defect type probability, confidence score and die-level mask, the instance segmentation mask is calculated according to the die-level mask and dynamic convolution, and the confidence score is re-scored according to the defect type probability.

[0053] As shown in Figure 1 The data enhancement and yield analysis method for multi-defect pattern wafer map mainly includes the following steps:

[0054] (1) The wafer map is converted from integrated circuit test log visualization, and the number of multi-defect pattern wafer maps is expanded by using adaptive data enhancement algorithm to construct the data set.

[0055] In this embodiment, first, the original test log data containing chip position coordinates, test results and failure mode (bin code) information is extracted from the integrated circuit test equipment, then the chip coordinate information in the test log is accurately mapped to the pixel position of the two-dimensional wafer plane according to the physical layout specification and chip arrangement of the wafer, a one-to-one correspondence between the chip physical position and the image coordinate system is established, then different types of test failure modes are converted into corresponding pixel values or color identifiers through a predefined coding rule, wherein the qualified chips are usually displayed as background color, and different failure types are distinguished by different identification colors, finally, based on the established coordinate mapping relationship and failure mode coding scheme, the corresponding pixel value is filled for each chip position in the two-dimensional image matrix, and boundary processing, color adjustment and size standardization and other visualization optimization operations are performed, finally a standardized multi-defect pattern wafer map (Wafer Bin Map, WBM) is generated, thereby converting the originally discrete text stored test data into a visual two-dimensional image representation, providing a visual data basis for subsequent defect mode recognition, spatial distribution analysis and yield calculation.

[0056] Due to the extreme scarcity of labeled multi-defect pattern wafer map data, the present application proposes a multi-defect pattern wafer map adaptive data enhancement algorithm, which significantly increases the number and diversity of training data through intelligent defect pattern synthesis strategies, as shown in Figure 2 The specific implementation process of the algorithm includes the following key steps:

[0057] (1) Data initialization and requirement setting: load the original wafer map and its corresponding defect annotation information, and set the number of synthesized samples required for K types of defect patterns according to the distribution of each type of defect pattern , k = 1, 2, …, K.

[0058] (2) Random combination of defect patterns: based on the pre-defined combination rules, randomly extract i (for example, 2-4) different types of defect patterns from the existing defect pattern library, and randomly select the overlap rate parameters between the defect patterns according to the pre-set probability distribution function, such as the intersection-over-union ratio.

[0059] (3) Geometric transformation constraint mapping: under the premise of meeting the constraints of each defect type characteristics, randomly extract applicable geometric transformation mapping rules (including translation, rotation, scaling, etc. Operation), so that the superimposed composite pattern meets the pre-set overlap rate requirement.

[0060] (4) Priority-driven pattern superposition: according to the pre-defined bin code priority rule, spatially superimpose and synthesize multiple defect patterns to generate composite defect patterns that conform to the real data distribution. Here, the pre-defined bin code priority rule is to mark the bin code and color to which the overlapping area belongs.

[0061] (5) Random noise defect injection: randomly extract the noise defect proportion according to the pre-set probability distribution, and add random scattered defects conforming to the actual production characteristics to the synthesized image.

[0062] (6) Data saving and iteration control: save the newly synthesized wafer map and its complete defect annotation information, and record key parameters such as overlap rate and random defect proportion; if the randomly selected defect pattern in step (2) contains type k, then execute the counter decrement operation , when some decreases to 0, the synthesis cycle of this type is terminated, and the entire cycle is ended when all decreases to 0, and a multi-defect pattern wafer map with uniform defect pattern type distribution is obtained.

[0063] (2) Feature extraction and feature fusion are performed on the wafer map to obtain the feature map F, which is input into the defect activation module to obtain the defect activation feature map A. The specific operation process is as follows:

[0064] (1) Feature extraction and fusion: Due to the large difference in shape and size between the defects in the multi-defect pattern wafer map, high overlap rate, weak internal consistency of the defects, discontinuity, unclear boundary, and long distance dependence problem, it is crucial to construct a robust feature expression. Compared with the ResNet commonly used in the prior art, which can only extract features within a local receptive field, the Swin Transformer (sliding window transformer) with stronger global modeling capability is used as the feature extraction backbone network in the present application to extract C3, C4 and C5 layer features for further fusion.

[0065] (2) Multi-scale feature fusion:

[0066] As shown in Figure 4 , a feature pyramid P5, P4 and P3 is constructed:

[0067]

[0068]

[0069]

[0070] wherein, is a pyramid pooling module, and is used to enhance the receptive field; is a global average pooling, is a different pooling kernel size, is a convolution, is an up-sampling, is a splicing, and then the multi-scale features after fusion are:

[0071]

[0072] The wafer map defects have a position-sensitive characteristic, i.e. the type of the defect is highly related to the position on the wafer, so a coordinate feature is further added to enhance the position perception, wherein , is a normalized absolute coordinate, and finally the feature map is fused to obtain a defect feature F, which has a dimension of :

[0073]

[0074] Here, D is a preset dimension.

[0075] (3) Defect activation module:

[0076] As shown in Figure 3 , 4 groups of 3x3 convolution are used to capture local patterns, and then passed through a Sigmoid activation function , which allows multiple regions to be activated, equivalent to 4 different "perspectives" for each defect to observe and aggregate features, learn different activation patterns, so that the model can more comprehensively and richly represent the defect pattern of fracture discontinuity, and the calculation process is as follows:

[0077]

[0078]

[0079] wherein, represents the gth group of activation results, and the dimension is , represents the gth group of continuous 3x3 convolution layers, in this embodiment, four groups of continuous 3x3 convolution layers are used, which means that four 3x3 convolution kernels are stacked in order, and a sigmoid activation function is stacked after each 3x3 convolution kernel. This process does not require an explicit query vector, but directly generates a defect activation map A from the defect feature F.

[0080] (Three) using normalized defect activation feature map to aggregate defect features F, and then through three independent prediction heads, the final segmentation result is obtained, including defect type probability, confidence score and grain level mask, according to the grain level mask and dynamic convolution calculation instance segmentation mask, and according to the defect type probability, the confidence is re-scored. The specific operation process is as follows:

[0081] (1) Feature aggregation: normalized defect activation feature map equivalent to a kind of spatial attention mechanism, increase the weight of defect feature, strengthen the model's attention to each part of the discontinuous defect, get the aggregated defect feature matrix :

[0082]

[0083] wherein, represents the value of the hth row and the wth column in the defect activation map A, and the superscript T represents transposition. Each row of the defect feature matrix will output the defect type probability, the confidence score and the grain level mask simultaneously through three independent prediction heads.

[0084] (2) Prediction head: based on the i th defect feature , through three independent linear layers, respectively generate classification prediction probability , confidence , mask core prediction , the calculation process is as follows:

[0085]

[0086]

[0087]

[0088] wherein, , is the projection matrix and bias of the classification linear layer, , is the projection matrix and bias of the confidence linear layer, , is the projection matrix and bias of the mask kernel linear layer, represents a Sigmoid activation function, represents a softmax function.

[0089] (3) Defect mask generation and post-processing: first, the defect feature F is further encoded through a 3-layer stacked 3x3 convolution to obtain a mask feature of defect instance perception , and then the segmentation mask of each defect instance is calculated through dynamic convolution:

[0090]

[0091] wherein, is the dth channel of the mask branch feature, is the dth channel of the mask kernel, and the final mask can be further obtained through binarization and up-sampling operations.

[0092] In the segmentation task of wafer map defects, the traditional method directly uses the classification score as the final confidence, which will lead to inconsistency between the classification confidence and the segmentation quality. A defect may be correctly classified (high classification score), but the mask prediction quality is poor (the intersection over union with the true label is low), and vice versa. Some defects have good segmentation quality, but the classification confidence is not high, so the confidence needs to be re-scored:

[0093]

[0094] wherein, is the prediction type, is the prediction probability of type c, is the confidence re-scoring result corresponding to the ith feature.

[0095] (4) Model training:

[0096] The application adopts an end-to-end training strategy for target detection / instance segmentation, the core of which is bipartite matching and combined loss function. Bipartite matching refers to that, during training, the model does not assign multiple anchor boxes to each real target, but uses the Hungarian algorithm for one-time optimal one-to-one matching. The matching basis is a cost function that combines classification confidence and segmentation mask similarity (Dice coefficient). This ensures that each predicted instance is matched with only one real target, and vice versa.

[0097] Combined loss refers to that, after matching, the model is optimized by a weighted combined loss function, which includes four parts:

[0098] Focal Loss (Focal Loss): used for classification, to solve the imbalance problem between foreground and background types.

[0099] Dice Loss and pixel-level binary cross-entropy: jointly used as segmentation loss to solve the serious imbalance problem of foreground-background pixels in the mask.

[0100] IoU-aware target loss: aligns the IoU (intersection over union) of the predicted bounding box and the real bounding box predicted by the model, improving the consistency of classification and segmentation quality.

[0101] This training strategy ensures that the defect instance activation mapping can learn discriminative defect feature representation, and at the same time realizes end-to-end prediction without NMS (Non-Maximum Suppression) through bipartite matching, significantly improving the inference efficiency.

[0102] The specific implementation process of the loss function can be realized according to the common knowledge of those skilled in the art, and other loss functions can also be replaced or added, which will not be described in detail.

[0103] (4) Based on the segmentation result, the influence of each defect on yield is quantitatively calculated.

[0104] The wafer map defect segmentation result obtained in the above step contains the type, location, and number of dies affected by the defect of all defects in the wafer map, so that the yield can be quantitatively calculated :

[0105]

[0106] wherein, is the total number of chips on the wafer, is the number of qualified chips, is the number of chips affected by the i-th type of defect, and K is the total number of defect types.

[0107] Different positions of defects have different impacts on the function of chips, and a yield model considering the spatial distribution of defects is introduced , quantifying the actual impact of defects in different areas of the wafer, by analyzing the spatial aggregation pattern of defects, systematic failures of specific manufacturing equipment or process steps can be identified. For example, the aggregation of defects in the edge area may point to the problem of the glue coating equipment, while the radial distribution of defects may imply the abnormality of the spin coating process. The calculation process is as follows:

[0108]

[0109] wherein, is the number of instances of the i-th type of defect, is the center coordinate of the j-th defect instance, is the area of the j-th defect instance, is the defect impact function considering position and size.

[0110] Defect impact function considering position and size One form of the defect impact function considering position and size is a regional weight function:

[0111]

[0112] wherein, is the area size of the defect, is the position weight function, which is determined according to the position of the defect on the wafer returns the corresponding weight coefficient; is the size impact adjustment parameter, which controls the contribution of the defect area to the impact function, the greater the value, the more significant the adjustment effect of the size on the impact; is the reference defect area, which is used to normalize the defect size, and is usually the average or median of the defect area in the data set, so that defects of different sizes are comparable.

[0113] In addition, the root cause of the defect can be further qualitatively analyzed, and the corresponding process problem in the manufacturing process can be traced back to improve.

[0114] In one specific implementation of the present application, the root cause of the defect can also be qualitatively analyzed according to the defect identification result, and the corresponding process problem in the manufacturing process can be traced back to improve. This process first identifies the potential process root cause by analyzing the spatial distribution characteristics of the defects: when the defects show a central aggregation distribution, it usually points to the uniformity problem of the etching or ion implantation process; when the defects are mainly distributed in the edge of the wafer, it is often related to the improper control of the edge effect of the glue coating, developing or cleaning process; when the defects show a radial or sectorial distribution, it may imply abnormal spin coating process parameters or mechanical problems of the wafer transmission system.

[0115] Secondly, the process traceability is conducted combined with the geometric features of the defects: linear defects are usually related to scratches, etching stripes or photolithography alignment problems; block defects may be caused by particle contamination, mask defects or local process abnormalities; ring defects often point to the rotation speed control of the spin coating process or the pressure distribution problem of the chemical mechanical polishing.

[0116] Further, by statistically analyzing the frequency and trend of defects in different batches, different equipment and different time periods, the problem equipment and abnormal process steps can be accurately located, such as the repeatability defects of a photolithography machine, the contamination problems caused by a specific chemical batch or the process drift caused by equipment aging.

[0117] Finally, based on the multi-dimensional root cause analysis results, targeted improvement measures can be developed: adjusting process parameter settings, optimizing equipment maintenance plans, improving environmental control strategies or updating job instruction books, so as to realize closed-loop management from defect detection to process improvement and continuously improve the stability and yield level of the manufacturing process.

[0118] The present application verifies the experimental results. Since there is no publicly available wafer map data set with segmentation labels in the academic and industrial communities, this embodiment uses 772 multi-failure mode multi-defect wafer map data collected from an advanced process production line, each wafer map contains 665 dies, and is scaled to a resolution of 64x64 after visualization conversion from test logs, and is labeled by experienced yield engineers, a total of 18 defect types are labeled, Figure 5 Ten examples are shown in FIG. 10, which are arc-shaped defects, beetle-like defects, honeycomb-shaped defects, center defects, ring defects, pure edge block defects, edge ring defects, photolithography defects, block defects, and near-full defects.

[0119] The above data set is expanded to 1000 instances per defect class by an adaptive data augmentation algorithm, and 2-4 defect patterns can exist simultaneously per wafer map, the combination rules, overlap rate, geometric transformation mapping rules, superposition priority rules, and random defect proportion all follow the original data distribution, and finally 18668 wafer maps are synthesized, which are divided into training set, validation set and test set in the ratio of 8:1:1. The experimental environment used in this embodiment: CPU is 16-core Intel(R) Xeon(R) Platinum 8352V, main frequency is 2.10GHz, memory size is 120GB, operating system is Ubuntu 20.04; GPU uses NVIDIA RTX 2080Ti, video memory is 11GB, single floating point precision computing power is 13.45TFLOPS; Python version is 3.8, Cuda version is 11.8, and training and testing are based on deep learning framework PyTorch 2.2.2.

[0120] The performance of the method provided by the present application and other classical instance segmentation algorithms in the application of multi-defect wafer map segmentation is compared in this embodiment example: due to the large difference between the wafer map and the traditional image, the feature extraction backbone network of this embodiment uses a randomly initialized swin-tiny-patch2-window4-64 model, that is, a Swin Transformer model with a patch size of 2x2, a window size of 4x4, and an input image resolution of 64x64, 4 groups of 3x3 convolution and The activation function is used as a defect activation module, and the AdamW optimizer is used for training, with an initial learning rate of 5x10 -5 , a weight decay of 0.0001, a training round of 100, a batch size of 16, and a preset number of defect activation mappings of 100.

[0121] To evaluate the performance of the technical solution of the present application, the present method is compared with the best traditional image instance segmentation algorithm under the same conditions, including Mask R-CNN based on a two-stage detection framework, which realizes high-precision segmentation through a region proposal network and a mask prediction branch, and Mask2Former based on a Transformer architecture, which further improves the segmentation performance in complex scenes through an attention mechanism. The evaluation index is mAP (mean Average Precision, average precision mean), which is defined as follows:

[0122]

[0123]

[0124] Among them, mAP refers to the average precision of all types when IoU changes from 0.5 to 0.95; mAP 50 , mAP S , mAP M , and mAP L represent the segmentation accuracy of the model on small area defects, medium area defects, and large area defects, respectively.

[0125] Table 1 shows the comparison results of the present method and the existing segmentation method, and the results show that the present method is better than other models in all evaluation indexes, and the mAP is improved by 6.2% compared with the suboptimal model.

[0126] Table 1 Performance comparison of the present method and the classical instance segmentation method (%)

[0127]

[0128] The embodiment also shows 3 groups of visual representative results of using different methods to segment wafer map defects respectively, as shown in Figure 6 It can be seen from the above that the method of the present application can accurately segment defects with multiple scales, multiple morphologies, high overlaps, discontinuous fractures, weak internal consistency and unclear boundaries, obtain type, location and defect grain number information, and realize integrated wafer map defect classification, positioning, segmentation and yield quantitative analysis.

[0129] Table 2 shows the performance comparison results of the segmentation model in the present application before and after data enhancement. It can be seen that the wafer map data enhancement proposed in the present application can significantly improve the wafer map defect segmentation performance. This is because the enhanced data set not only significantly expands the sample size, but also comprehensively covers the complexity of the defect pattern, the spatial distribution characteristics and the combination mode, thereby providing rich and real learning samples for the segmentation model training.

[0130] Table 2 Performance comparison of the method of the present application before and after using data enhancement (%)

[0131]

[0132] Based on the same inventive concept, in the present embodiment, a data enhancement and yield analysis system for a multi-defect pattern wafer map for realizing the above method is also provided, comprising:

[0133] A multi-defect pattern wafer map collection and enhancement module, which generates a multi-defect pattern wafer map from integrated circuit test log visualization, and expands the number of multi-defect pattern wafer maps in the form of defect pattern combinations through an adaptive data enhancement algorithm to construct a data set;

[0134] A feature extraction and activation module, which is used to extract multi-scale features of the wafer map, form defect features through feature pyramid fusion, and generate a location-sensitive defect activation feature map through a defect activation module; and aggregate defect features by using the normalized defect activation feature map to obtain an aggregated defect feature matrix;

[0135] A segmentation module, which is used to generate a segmentation result including a defect type probability, a confidence score and a grain-level mask through three independent prediction heads for each row of feature vectors in the defect feature matrix, calculate an instance segmentation mask according to the grain-level mask and dynamic convolution, and re-score the confidence according to the defect type probability;

[0136] A training module, which trains the model by using the data set constructed by the multi-defect pattern wafer map collection and enhancement module;

[0137] The yield analysis module calculates a proportion of a number of qualified crystal grains to a total number of crystal grains to obtain a defect count yield result according to the instance segmentation mask and the confidence rescore result generated by the trained model, and introduces a defect position and size weight function on the basis of the defect count to quantify an influence of spatial distribution on the yield, and calculates a spatial distribution yield.

[0138] For the system embodiment, since it basically corresponds to the method embodiment, the relevant part is described in the method embodiment, and the implementation method of the remaining modules is not described here. The system embodiment described above is only illustrative, wherein the units described as separate components can or can not be physically separated, and the components displayed as units can or can not be physical units, that is, they can be located in one place or distributed on multiple network units. Part or all of the modules can be selected to achieve the purpose of the present application according to actual needs. Those skilled in the art can understand and implement it without creative labor.

[0139] The system embodiment of the present application can be applied to any device with data processing capability, which can be a device or apparatus such as a computer. The system embodiment can be realized by software, hardware or a combination of software and hardware. Taking software realization as an example, as a logical device, it is formed by reading the corresponding computer program instructions in the non-volatile memory into the memory and running by the processor of the device with data processing capability.

[0140] The above-described embodiments only express several implementation manners of the present application, which are described in detail, but cannot be understood as a limitation on the scope of the present application. Those skilled in the art can make some modifications and improvements without departing from the concept of the present application, which are all within the protection scope of the present application.

Claims

1. A data enhancement and yield analysis method for wafer patterns with multiple defects, characterized in that, The method comprises the following steps: (1) generating a multi-defect pattern wafer map from integrated circuit test log visualization, and expanding the number of multi-defect pattern wafer maps in a defect pattern combination manner through an adaptive data enhancement algorithm to construct a data set; (2) extracting multi-scale features of the wafer map, fusing the features through a feature pyramid to form defect features, and generating a position-sensitive defect activation feature map through a defect activation module; aggregating the defect features by using the normalized defect activation feature map to obtain an aggregated defect feature matrix; (3) each row of feature vectors in the defect feature matrix generates a segmentation result through three independent prediction heads, including defect type probability, confidence score and die-level mask, calculates an instance segmentation mask according to the die-level mask and dynamic convolution, and re-scores the confidence according to the defect type probability, and completes model training through binary matching and combined loss; (4) generating an instance segmentation mask and a confidence re-score result based on the trained model, calculating the proportion of the number of qualified dies to the total number of dies to obtain a defect count yield result, and introducing a defect position and size weight function based on the defect count to quantify the influence of spatial distribution on yield, and calculating the spatial distribution yield.

2. The data augmentation and yield analysis method for multi-defect pattern wafer map according to claim 1, wherein, In step (1), the defect pattern combination manner comprises: (1.1) Load the original wafer map and defect annotation, set the number of synthetic samples N of K-class defect patterns k , k = 1, 2, …, K; K represents the total number of defect types; (1.2) randomly combining i defect patterns of different types, and randomly selecting an overlap rate parameter between the defect patterns based on a preset probability distribution; (1.3) extracting a geometric transformation mapping rule to translate, rotate or scale the defect patterns, so that the superimposed pattern meets the overlap rate requirement; (1.4) superimposing the defect patterns according to a predefined bin code priority rule to generate a composite defect pattern; (1.5) injecting random noise defects based on a preset probability distribution; (1.6) save the synthetic image and the annotation, iterate until all N k decreased to 0.

3. The method of data augmentation and yield analysis for multi-defect pattern wafer maps of claim 2, wherein, The overlap rate parameter is an intersection-over-union ratio, and the value range is 0.2-0.

8.

4. The data augmentation and yield analysis method for multi-defect pattern wafer map oriented pattern according to claim 2, wherein, In step (1.6), if the defect pattern type randomly combined in the current iteration contains the kth defect pattern type, then N k is reduced by 1, otherwise N k remains unchanged.

5. The data augmentation and yield analysis method for multi-defect pattern wafer map oriented pattern according to claim 1, wherein, The calculation process of the defect features comprises: extracting multi-scale features of the wafer map, and denoting the features as shallow features C3, middle features C4 and high features C5 respectively; performing a global average pooling operation on the high features C5 using different sizes of pooling kernels, concatenating the pooling results, and generating a first pyramid feature through convolution operation; adding the middle features C4 through convolution operation to the up-sampled first pyramid feature to generate a second pyramid feature; adding the shallow features C3 through convolution operation to the up-sampled second pyramid feature to generate a third pyramid feature; concatenating the third pyramid feature, the up-sampled second pyramid feature and the up-sampled first pyramid feature, fusing them through convolution operation, adding coordinate features to the fusion result, and then forming the defect features through convolution.

6. The data augmentation and yield analysis method for multi-defect pattern wafer map oriented graphs of claim 5, wherein, In step (2), the wafer map is taken as input, and the Swin Transformer backbone network is used to extract features at the third to fifth stages as the shallow features, the middle features and the high features of the wafer map respectively.

7. The data augmentation and yield analysis method for multi-defect pattern wafer maps of claim 1, wherein, The calculation process of the defect activation module comprises: encoding the defect features through four groups of consecutive 3x3 convolution layers, each group of convolution layers gradually extracting local features and being processed through a Sigmoid activation function separately; concatenating the four groups of activation results to obtain a position-sensitive defect activation feature map.

8. The data augmentation and yield analysis method for multi-defect pattern wafer maps of claim 1, wherein, The formula of instance segmentation mask and confidence rescore is as follows: ； ； wherein, and denotes the instance segmentation mask and confidence rescore result corresponding to the i-th row feature vector in the defect feature matrix, denotes the die-level mask corresponding to the i-th row feature vector in the defect feature matrix, denotes three 3x3 convolutional layers, denotes the defect feature, denotes the d-th dimension in, D denotes the total predicted dimension, denotes the mask branch feature, denotes the d-th dimension in, denotes the confidence score corresponding to the i-th row feature vector in the defect feature matrix, denotes the maximum predicted probability corresponding to the i-th row feature vector in the defect feature matrix.

9. The data augmentation and yield analysis method for multi-defect pattern wafer maps of claim 1, wherein, The formula of spatial distribution yield is as follows: ； ； wherein, represents a spatial distribution yield, represents an impact value of the jth defect, represents a center coordinate of the jth defect instance, represents an area of the jth defect instance, represents a total number of dies on a wafer, represents a number of instances of the ith defect type, K represents a total number of defect types, represents a defect impact function considering position and size, represents an area size of a defect, represents a position weight function, represents a size impact adjustment parameter, is a reference defect area.

10. A data augmentation and yield analysis system for multiple-defect pattern wafer maps for implementing the data augmentation and yield analysis method for multiple-defect pattern wafer maps of claim 1, characterized by, The system comprises: A multi-defect pattern wafer map collection and enhancement module which generates multi-defect pattern wafer maps from integrated circuit test log visualization and expands the number of multi-defect pattern wafer maps in the form of defect pattern combinations through an adaptive data enhancement algorithm to construct a data set; A feature extraction and activation module which is used to extract multi-scale features of wafer maps, form defect features through feature pyramid fusion, and generate position-sensitive defect activation feature maps through a defect activation module; the normalized defect activation feature maps are used to aggregate defect features to obtain an aggregated defect feature matrix; A segmentation module which is used to generate segmentation results including defect type probability, confidence score and die-level mask through three independent prediction heads for each row of feature vectors in the defect feature matrix, calculate instance segmentation masks according to the die-level mask and dynamic convolution, and rescore the confidence score according to the defect type probability; A training module which trains the model using the data set constructed by the multi-defect pattern wafer map collection and enhancement module; A yield analysis module which calculates the ratio of the number of qualified dies to the total number of dies to obtain defect count yield results according to the instance segmentation mask and confidence rescore results generated by the trained model, and introduces a defect position and size weight function on the basis of defect count to quantify the influence of spatial distribution on yield and calculate the spatial distribution yield.

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