Refresh rate adjustment circuit and display panel

Abstract

The application provides a refresh rate adjusting circuit and a display panel. A refresh starting module is arranged to output a starting signal to a gate drive circuit, so that the gate drive circuit can output a scanning signal again based on the starting signal in addition to the default scanning signal output, thereby improving the refresh rate of the pixel row corresponding to the gate drive circuit. Meanwhile, a refresh ending module is arranged to stop the improvement of the refresh rate, that is, the refresh rate improvement area is selected by the refresh starting module and the refresh ending module, so that the selection of the refresh rate improvement of the area in the picture can be made according to actual needs. In order to realize the reset of the re-refresh, a refresh reset module is arranged, so that the complete steps of starting, transferring and ending in the re-refresh process are realized, the refresh rate improvement of the partial area in the display picture is realized, and the setting of different refresh rates of different areas in the display picture is realized.

Description

Technical Field

[0001] This invention relates to the field of displays, and more particularly to a refresh rate adjustment circuit and a display panel. Background Technology

[0002] Traditional monitors can only operate at a fixed global refresh rate, such as 60Hz or 120Hz. As the requirements for display quality have increased, some monitors have been equipped with adaptive refresh technology, which dynamically adjusts the refresh rate by recognizing different display scenarios. However, this method can only achieve a uniform refresh rate change across the entire screen. When there are both static and dynamic areas in the display screen, adaptive refresh technology can only refresh at a high frame rate based on the dynamic areas, causing the static areas to also refresh at a high frame rate, resulting in wasted power. Summary of the Invention

[0003] The main objective of this invention is to propose a refresh rate adjustment circuit and a display panel, which aims to solve the problem in the prior art that it is impossible to refresh different areas of the display screen at different refresh rates.

[0004] To achieve the above objectives, the present invention provides a refresh rate adjustment circuit, which is connected to a gate drive circuit; the refresh rate adjustment circuit includes a refresh start module, a refresh reset module, and a refresh end module.

[0005] The refresh start module is connected to the input terminal of the gate drive circuit, the refresh reset module is connected to the reset terminal of the gate drive circuit, and the output terminal of the gate drive circuit is connected to the input terminal of the next gate drive circuit through the refresh end module; wherein:

[0006] For a target refresh area containing at least one row of consecutive pixels, the refresh start module corresponding to the first row of pixels in the target refresh area is used to send a start signal to the corresponding gate drive circuit so that the gate drive circuit outputs a gate drive signal.

[0007] The refresh end module corresponding to the last row of pixels in the target refresh area is used to disconnect the output terminal of the gate driving circuit from the input terminal of the next gate driving circuit.

[0008] The refresh reset module corresponding to the last row of pixels in the target refresh area is used to trigger a reset of the corresponding gate drive circuit.

[0009] Optionally, the refresh starting module comprises a first charging unit and a first signal sending unit; a control end of the first charging unit is connected with an input end of the gate drive circuit, a charging end of the first charging unit is connected with a first signal line, a control end of the first signal sending unit is connected with the first charging unit, an input end of the first signal sending unit is connected with the first signal line, and an output end of the first signal sending unit is connected with the input end of the gate drive circuit; wherein:

[0010] The first charging unit is configured to charge when an input signal at the input end of the gate drive circuit and the first signal at the first signal line are both active, and to provide a conduction signal to the first signal sending unit after the charging is completed.

[0011] The first signal sending unit is configured to send a starting signal to the corresponding gate drive circuit when the first charging unit provides the conduction signal and the first signal at the first signal line is active.

[0012] Optionally, the first charging unit comprises a first switch tube and a first capacitor; wherein:

[0013] A control end of the first switch tube is connected with the input end of the gate drive circuit, an input end of the first switch tube is connected with the first signal line, an output end of the first switch tube is connected with a first end of the first capacitor, a second end of the first capacitor is connected with a low-voltage signal line, and the output end of the first switch tube is further connected with a control end of the first signal sending unit.

[0014] Optionally, the first signal sending unit comprises a second switch tube; wherein:

[0015] A control end of the second switch tube, as a control end of the first signal sending unit, is connected with the first charging unit, an input end of the second switch tube is connected with the first signal line, and an output end of the second switch tube is connected with the input end of the gate drive circuit.

[0016] Optionally, the refresh rate adjusting circuit further comprises an isolation module, and the isolation module comprises a seventh switch tube; wherein:

[0017] A control end of the seventh switch tube is connected with a second signal line, an input end of the seventh switch tube is connected with a first signal line, and an output end of the seventh switch tube is connected with a charging end of the first charging unit and a charging end of the first signal sending unit respectively; wherein, a fourth signal on the second signal line indicates that the seventh switch tube is turned off after the starting signal is sent.

[0018] Optionally, the refresh reset module comprises a second charging unit and a second signal sending unit; a control end of the second charging unit is connected with the first signal line, an input end of the second charging unit is connected with an output end of the gate drive circuit, a control end of the second signal sending unit is connected with the second charging unit, an input end of the second signal sending unit is connected with the first signal line, and an output end of the second signal sending unit is connected with a reset end of the gate drive circuit.

[0019] Optionally, the second charging unit comprises a third switch tube, a fourth switch tube, a fifth switch tube and a second capacitor; wherein:

[0020] a control end of the third switch tube is connected with the first signal line, an input end of the third switch tube is connected with an output end of the gate drive circuit, an output end of the third switch tube is connected with a control end and an input end of the fourth switch tube, an output end of the fourth switch tube is connected with a first end of the second capacitor, the first end of the second capacitor is also connected with a control end of the second signal sending unit, a second end of the second capacitor is connected with a low-voltage signal line, the output end of the fourth switch tube is also connected with an output end of the fifth switch tube, an input end of the fifth switch tube is connected with the low-voltage signal line, and a control end of the fifth switch tube is connected with an input end of the gate drive circuit.

[0021] Optionally, the second signal sending unit comprises a sixth switch tube; wherein:

[0022] a control end of the sixth switch tube, as a control end of the second signal sending unit, is connected with the second charging unit, an input end of the sixth switch tube is connected with the first signal line, and an output end of the sixth switch tube is connected with a reset end of the gate drive circuit.

[0023] Optionally, the refresh end module comprises an eighth switch tube; wherein:

[0024] a control end of the eighth switch tube is connected with a third signal line, an input end of the eighth switch tube is connected with an output end of the gate drive circuit, and an output end of the eighth switch tube is connected with an input end of a next gate drive circuit.

[0025] In addition, in order to achieve the above-mentioned purpose, the application further provides a display panel, which comprises the refresh rate adjusting circuit and the gate drive circuit as described above.

[0026] The application provides a refresh rate adjusting circuit and a display panel. The application provides a refresh rate adjusting circuit and a display panel. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only show some embodiments of the application, and for those skilled in the art, other drawings can also be obtained from the structures shown in these drawings without any creative effort.

[0028] Figure 1 The functional module diagram of the embodiment of the refresh rate adjusting circuit of the application;

[0029] Figure 2 The circuit structure diagram of the embodiment of the refresh rate adjusting circuit of the application;

[0030] Figure 3 The circuit structure diagram of another embodiment of the refresh rate adjusting circuit of the application;

[0031] Figure 4 Fig. 1 is a schematic diagram of the overall structure of the refresh rate adjusting circuit according to the present application;

[0032] Figure 5 Fig. 2 is a signal waveform diagram of the refresh rate adjusting circuit according to the present application.

[0033] The implementation, functional features and advantages of the present application will be further described with reference to the accompanying drawings.

[0034] Explanation of reference numerals:

[0035] DETAILED DESCRIPTION

[0036] It should be understood that the specific embodiments described herein merely set forth preferred combinations of components and / or other features, and that the scope of the application is not limited to these embodiments. Numerous variations and modifications from the descriptions and illustrations herein will be readily apparent to those of ordinary skill in the art.

[0037] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0038] It should be noted that all directional indications, such as up, down, left, right, front, back, etc., are only used to explain the relative position relationship, movement condition, etc. between components in a certain posture (as shown in the drawings), and if the certain posture changes, the directional indications will also change accordingly.

[0039] In addition, the description of "first", "second", etc. in the present application is only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features with "first", "second" can explicitly or implicitly include at least one of the features. In addition, the technical solutions of each embodiment can be combined with each other, but it must be based on the realization of those of ordinary skill in the art, and when the combination of technical solutions contradicts each other or cannot be realized, it should be considered that the combination of technical solutions does not exist, and is not within the scope of protection required by the present application.

[0040] The present application provides a refresh rate adjusting circuit applied to a display panel, please refer to Figure 1 , Figure 1A function module diagram of an embodiment of the refresh rate adjusting circuit of the present application is shown in the figure. In this embodiment, the refresh rate adjusting circuit is connected with the gate drive circuit 400; the refresh rate adjusting circuit comprises a refresh start module 100, a refresh reset module 200 and a refresh end module 300.

[0041] The refresh start module 100 is connected with the input end of the gate drive circuit 400, the refresh reset module 200 is connected with the reset end in the gate drive circuit 400, and the output end of the gate drive circuit 400 is connected with the input end of the next gate drive circuit 400 through the refresh end module 300; wherein:

[0042] For a target refresh area comprising at least one continuous pixel row, the first pixel row in the target refresh area corresponds to the refresh start module 100, which is used to send a start signal to the corresponding gate drive circuit 400, so as to make the gate drive circuit 400 output a gate drive signal.

[0043] The last pixel row in the target refresh area corresponds to the refresh end module 300, which is used to disconnect the connection between the output end of the gate drive circuit 400 and the input end of the next gate drive circuit 400.

[0044] The last pixel row in the target refresh area corresponds to the refresh reset module 200, which is used to trigger the reset of the corresponding gate drive circuit 400.

[0045] The gate drive circuit 400 is a main circuit for outputting a scanning signal; the specific structure of the gate drive circuit 400 can be set based on actual needs, such as 4T1C (4 TFTs+1 capacitor), 8T1C (8 TFTs+1 capacitor) and the like; in this embodiment and subsequent embodiments, 4T1C is taken as an example for description, and other types of gate drive circuits 400 can be analogously implemented, which will not be described in detail.

[0046] The structure of the gate drive circuit 400 will be described first. The gate drive circuit 400 comprises a first drive switch tube TD1, a second drive switch tube TD2, a third drive switch tube TD3, a fourth drive switch tube TD4 and a first drive capacitor CD1; wherein:

[0047] The control end of the first driving switch tube TD1 is connected with the output end of the previous row of the gate driving circuit 400 as the input end of the gate driving circuit 400, the input end of the first driving switch tube TD1 is connected with the first / two clock signal line, the output end of the first driving switch tube TD1 is connected with the control end of the second driving switch tube TD2, the input end of the second driving switch tube TD2 is connected with the second / one clock signal line, the output end of the second driving switch tube TD2 is the output end of the gate driving circuit 400, and the first driving capacitor CD1 is connected between the control end and the output end of the second driving switch tube TD2; the output end of the third driving switch tube TD3 is connected with the control end of the second driving switch tube TD2, the control end of the third driving switch tube TD3 is connected with the output end of the next row of the gate driving circuit 400, the input end of the third driving switch tube TD3 is connected with the low-voltage signal line, the control end of the fourth driving switch tube TD4 is connected with the output end of the next row of the gate driving circuit 400, the input end of the fourth driving switch tube TD4 is connected with the low-voltage signal line, and the output end of the fourth driving switch tube TD4 is connected with the output end of the second driving switch tube TD2.

[0048] The first clock signal line and the second clock signal line are opposite in time sequence, and the first clock signal line and the second clock signal line of the adjacent rows of the gate driving circuit 400 are opposite; for example, the input end of the first driving switch tube TD1 of the first row of the gate driving circuit 400 is connected with the first clock signal line, and the input end of the second driving switch tube TD2 is connected with the second clock signal line, so that the input end of the first driving switch tube TD1 of the second row of the gate driving circuit 400 is connected with the second clock signal line, and the input end of the second driving switch tube TD2 is connected with the first clock signal line.

[0049] The control end of the first driving switch tube TD1 is the input end of the gate driving circuit 400, the output end of the second driving switch tube TD2 is the output end of the gate driving circuit 400, and the control end of the third driving switch is the reset end of the gate driving circuit 400; it should be noted that when the gate driving circuit 400 outputs a signal, the second driving switch tube TD2 directly outputs the signal to the pixel row, but in the embodiment, the refresh end module 300 is additionally provided, and the output end of the second driving switch tube TD2 is connected to the input end of the next row of the gate driving circuit 400 through the refresh end module 300.

[0050] It can be understood that one gate driving circuit 400 is responsible for the pixel driving of one row of pixels; in the embodiment, the refresh rate adjusting circuit is correspondingly provided for the gate driving circuit 400.

[0051] The target refresh region is a display region that needs to be refreshed again; it can be understood that the gate driving circuit 400 itself can realize complete scanning, which is referred to as general scanning; the role of the refresh rate adjusting circuit in the embodiment is to control the gate driving circuit 400 in the target refresh region to scan again within the same frame on the basis of the gate driving circuit 400 realizing general scanning, so that the refresh rate of the gate driving circuit 400 in the target refresh region is increased, and the number of times of refreshing again within one frame can be set based on actual needs; while the refresh rate of the gate driving circuit 400 outside the target refresh region is still the refresh rate of general scanning, so that different regions in the display picture have different refresh rates, based on which, when there are dynamic regions and static regions in the display picture, for example, the upper half of the picture is a video playing region and the lower half is a video introduction region, the refresh rate of general scanning can be set to be relatively low to meet the low refresh rate of the video introduction region and save power, and at the same time, the pixel row where the video playing region is located is taken as the target refresh region, and the refresh rate thereof is increased by using the method of the application to meet the high refresh rate requirement of the video playing, and the application can meet the high refresh rate and low refresh rate requirements in the display picture at the same time.

[0052] The refresh starting module 100 is a module for setting the starting row of the target refresh region, and the input end of the gate driving circuit 400 is used to trigger the output of the charging and scanning signals of the gate driving circuit 400; specifically, the refresh of the gate driving circuit 400 is triggered by sending a starting signal; therefore, by setting the refresh starting module 100 connected with the input end of the gate driving circuit 400, the purpose of outputting the scanning signal of the gate driving circuit 400 again can be realized, and the refresh of the gate driving circuit 400 can be realized.

[0053] When the refresh starting module 100 triggers the gate drive circuit 400 to refresh again, the gate drive circuit 400 outputs the scanning signal again; at the same time, based on the original structure of the gate drive circuit 400, the refresh of the next row of gate drive circuits 400 can be automatically triggered, and the subsequent gate drive circuits 400 are refreshed in turn; in actual application, only part of the gate drive circuits 400 need to be refreshed, that is, only the gate drive circuits 400 in the target refresh area need to be refreshed, therefore, in order to avoid the subsequent gate drive circuits 400 from being refreshed, the refresh ending module 300 is arranged in the embodiment, the refresh ending module 300 is arranged between the output end of the current row of gate drive circuits 400 and the input end of the next row of gate drive circuits 400, the connection between the output end of the gate drive circuit 400 and the input end of the next gate drive circuit 400 is disconnected through the refresh ending module 300, so that the scanning signal of the current row of gate drive circuits 400 cannot be transmitted to the next row, and therefore the refresh of the next gate drive circuit 400 cannot be triggered, the refresh is stopped, therefore, the end row of the target refresh area can be set through the refresh ending module 300; the refresh starting module 100 and the refresh ending module 300 are used to position the gate drive circuit 400 corresponding to the target refresh area in the embodiment.

[0054] It can be understood that the gate drive circuit 400 needs to be reset through the scanning signal of the next row, and for the last row of pixel rows in the target refresh area, the next gate drive circuit 400 will not be refreshed, and therefore the gate drive circuit 400 corresponding to the last row of pixel rows cannot be reset, therefore, the refresh reset module 200 is arranged in the embodiment, the refresh reset module 200 is connected with the reset end of the gate drive circuit 400, and the reset of the gate drive circuit 400 corresponding to the last row of pixel rows is triggered through the refresh reset module 200, so that the reset of all the gate drive circuits 400 performing the refresh is realized.

[0055] The embodiment sets the refresh starting module 100 to output a starting signal to the gate drive circuit 400, so that the gate drive circuit 400 can output the scanning signal again based on the starting signal in addition to the default scanning signal output, thereby improving the refresh rate of the pixel row corresponding to the gate drive circuit 400. Meanwhile, the refresh ending module 300 is set to stop the improvement of the refresh rate, that is, the refresh rate improvement area is selected by the refresh starting module 100 and the refresh ending module 300. Therefore, the selection of the refresh rate improvement of the area in the picture can be made according to the actual needs. In order to realize the reset of the re-refresh, the refresh reset module 200 is set, so as to realize the complete steps of starting, transmitting and ending in the re-refresh process, realize the refresh rate improvement of part of the display picture, and realize the setting of different refresh rates of different areas in the display picture.

[0056] Further, the refresh starting module 100 comprises a first charging unit and a first signal sending unit. The control end of the first charging unit is connected with the input end of the gate drive circuit 400, the charging end of the first charging unit is connected with a first signal line, the control end of the first signal sending unit is connected with the first charging unit, the input end of the first signal sending unit is connected with the first signal line, and the output end of the first signal sending unit is connected with the input end of the gate drive circuit 400.

[0057] The first charging unit is configured to charge when the input signal of the input end of the gate drive circuit 400 and the first signal of the first signal line are simultaneously effective, and provide a conduction signal for the first signal sending unit after the charging is completed.

[0058] The first signal sending unit is configured to send a starting signal to the corresponding gate drive circuit 400 when the first charging unit provides a conduction signal and the first signal of the first signal is effective.

[0059] The refresh starting module 100 needs to start the re-refresh of the first row of pixels in the target refresh area. Therefore, how to locate the first row of pixels in the target refresh area is a difficulty. All the gate drive circuits 400 can be provided with a refresh rate adjusting circuit. Therefore, if the re-refresh needs to be selected for a specific gate drive circuit 400, a signal line can be set for each gate drive circuit 400, and the signal line of the gate drive circuit 400 corresponding to the first row of pixels in the target refresh area sends a starting signal to the gate drive circuit 400, so as to realize the re-refresh trigger of the first row of gate drive circuits 400. However, this way is too high in cost and complex in setting. For example, if 1080 rows of pixels are included, 1080 signal lines need to be set, which is difficult to realize in practical application.

[0060] The embodiment provides a more convenient way of starting re-refresh of the first row of pixel rows in the target refresh area, in the embodiment, only the first signal line is arranged, all refresh starting modules 100 corresponding to the rows are connected with the first signal line, and re-refresh of the first row of pixel rows in the target refresh area is triggered based on the first signal line.

[0061] The first charging unit is used for positioning the first row of pixel rows in the target refresh area; and the first signal sending unit is used for specifically sending the starting signal.

[0062] The first charging unit is connected with the input end of the gate driving circuit 400 and the first signal line; when the input signal of the gate driving circuit 400 and the first signal of the first signal line are simultaneously effective, the first charging unit charges; it can be understood that the input signal of the gate driving circuit 400 is effective, that is, the input end of the gate driving circuit 400 receives the scanning signal output by the previous row of gate driving circuits 400, based on the principle of line-by-line scanning, when the input signal is effective, only the input signal corresponding to this row is effective in all pixel rows, and the input signals corresponding to other pixel rows are all ineffective, therefore, the positioning of the first row of pixel rows in the target refresh area can be realized through the effectiveness of the input signal; thus, in the embodiment, after the first row of pixel rows in the target refresh area is determined, the moment when the input signal corresponding to the first row of pixel rows is effective can be determined, and the first signal line is controlled to output the effective first signal at the moment when the input signal is effective, so that only the first charging unit corresponding to the first row of pixel rows in the target refresh area charges in all rows, and then only the first charging unit corresponding to the first row of pixel rows in the target refresh area is in a charging completion state.

[0063] After the first row of pixel rows in the target refresh area is positioned through the first charging unit, the gate driving circuit 400 of the row can be controlled to re-refresh through the first signal sending unit; the effective first signal is sent through the first signal line again, since the first signal sending unit needs the power support of the first charging unit, only the first row of pixel rows in the target refresh area can output the starting signal; thus, the re-refresh trigger of the first row of pixel rows in the target refresh area is realized, and only one new signal line needs to be arranged.

[0064] Further, in the following, refer to Figure 2 The first charging unit includes a first switch tube T1 and a first capacitor C1; wherein:

[0065] The control end of the first switch tube T1 is connected with the input end of the gate drive circuit 400, the input end of the first switch tube T1 is connected with the first signal line, the output end of the first switch tube T1 is connected with the first end of the first capacitor C1, and the second end of the first capacitor C1 is connected with the low-voltage signal line; and the output end of the first switch tube T1 is also connected with the control end of the first signal sending unit.

[0066] The switch tube in the application is taken as an example of TFT, and in actual application, a specific type of switch tube can be set based on actual needs.

[0067] When the input signal of the previous pixel row is valid, the first switch tube T1 is turned on, at this time, if the first signal of the first signal line is valid, the first signal reaches the first capacitor C1 through the first switch tube T1, so as to realize the charging of the first capacitor C1; if the first signal of the first signal line is invalid, the corresponding first capacitor C1 will not be charged.

[0068] The first capacitor C1 that realizes the charging can provide a high-level voltage through the first end of the first capacitor C1 after the charging is completed, and the first capacitor C1 that is not charged cannot provide a high-level voltage; the high-level voltage through the first end of the first capacitor C1 realizes the positioning of the first pixel row in the target refresh area.

[0069] Further, the first signal sending unit comprises a second switch tube T2; wherein:

[0070] The control end of the second switch tube T2, as the control end of the first signal sending unit, is connected with the first charging unit, the input end of the second switch tube T2 is connected with the first signal line, and the output end of the second switch tube T2 is connected with the input end of the gate drive circuit 400.

[0071] When the control end of the second switch tube T2 is high, the second switch tube T2 is turned on, if the first signal line outputs a valid first signal, the first signal can be output to the gate drive circuit 400 as a start signal through the second switch tube T2, so as to realize the re-refreshing of the gate drive circuit 400; if the first signal of the first signal line is invalid, the second switch tube T2 remains in the turned-on state, but does not output the start signal.

[0072] When the control end of the second switch tube T2 is low, the second switch tube T2 is turned off, and the output of the start signal cannot be realized.

[0073] Further, the refresh reset module 200 comprises a second charging unit and a second signal sending unit; a control end of the second charging unit is connected with the first signal line, an input end of the second charging unit is connected with an output end of the gate drive circuit 400, so a control end of the second signal sending unit is connected with the second charging unit, an input end of the second signal sending unit is connected with the first signal line, and an output end of the second signal sending unit is connected with a reset end of the gate drive circuit 400.

[0074] In this embodiment, the last row of the target refresh area is positioned by using the uniqueness of the gate drive circuit 400 when outputting the scanning signal.

[0075] It can be understood that when the gate drive circuit 400 outputs the scanning signal, only the row has the scanning signal output in all the pixel rows, so the second charging unit charges when the scanning signal output by the corresponding gate drive circuit 400 is valid and the first signal of the first signal line is valid, so that the last row of the target refresh area can be positioned.

[0076] After the last row of the target refresh area is positioned by the second charging unit, the gate drive circuit 400 of the row can be reset by the second signal sending unit; the first signal of the first signal line is sent again, and since the second signal sending unit needs the power support of the second charging unit, only the last row of the target refresh area can be reset; thus, the reset of the last row of the target refresh area is realized.

[0077] It should be noted that since the refresh reset module 200 and the refresh start module 100 both need the valid first signal to realize the function, when the refresh reset module triggers the reset, the refresh start module 100 will be triggered again; in order to avoid this problem, the first row and the last row of the target refresh area can be located in different rows with different parity, for example, the first row is located in an odd row, and the last row is located in an even row; since the first clock signal and the second clock signal in the two adjacent gate drive circuits 400 are opposite in time sequence, when the last row of the refresh reset module 200 triggers the reset, the first driving transistor TD1 of the gate drive circuit 400 corresponding to the first row of the refresh start module 100 has a low-level clock signal, and cannot realize the output of the scanning signal, so that the trigger of the re-refresh can be avoided; in other embodiments, a signal line can also be set for the refresh reset module 200, that is, the first signal line of the refresh reset module 200 is replaced by a second signal line, so that the refresh reset module 200 and the refresh start module 100 are controlled by different signal lines.

[0078] Further, the second charging unit comprises a third switch tube T3, a fourth switch tube T4, a fifth switch tube T5 and a second capacitor C2; wherein:

[0079] The control end of the third switch tube T3 is connected with the first signal line, the input end of the third switch tube T3 is connected with the output end of the gate drive circuit 400, the output end of the third switch tube T3 is connected with the control end and the input end of the fourth switch tube T4, the output end of the fourth switch tube T4 is connected with the first end of the second capacitor C2, the first end of the second capacitor C2 is also connected with the control end of the second signal sending unit, the second end of the second capacitor C2 is connected with a low-voltage signal line, the output end of the fourth switch tube T4 is also connected with the output end of the fifth switch tube T5, the input end of the fifth switch tube T5 is connected with the low-voltage signal line, and the control end of the fifth switch tube T5 is connected with the input end of the gate drive circuit 400.

[0080] When the first signal is valid, the third switch tube T3 is turned on, at this time, the gate drive circuit 400 outputs a scanning signal, then the scanning signal passes through the third switch tube T3, triggers the fourth switch tube T4 to be turned on, and reaches the second capacitor C2, so that the charging of the second capacitor C2 is realized; if the first signal is invalid, the third switch tube T3 will not be turned on, and the second capacitor C2 will not be charged.

[0081] After the second capacitor C2 realizing charging is charged, the first end of the second capacitor C2 can provide a high-level voltage, and the second capacitor C2 which is not charged cannot provide a high-level voltage; the high-level voltage of the first end of the second capacitor C2 realizes the positioning of the last row in the target refresh area.

[0082] Meanwhile, when the input signal of the input end of the gate drive circuit 400 is valid, the fifth switch tube T5 is turned on, so that the second capacitor C2 is discharged and the reset state is released.

[0083] The fourth switch tube T4 is used to avoid the voltage output of the second capacitor C2 to the scanning line, and the fourth switch tube T4 can also be replaced by other unidirectional devices, such as a diode.

[0084] Further, the second signal sending unit comprises a sixth switch tube T6; wherein:

[0085] The control end of the sixth switch tube T6 as the control end of the second signal sending unit is connected with the second charging unit, the input end of the sixth switch tube T6 is connected with the first signal line, and the output end of the sixth switch tube T6 is connected with the reset end of the gate drive circuit 400.

[0086] When the control end of the sixth switch tube T6 is high level, the sixth switch tube T6 is turned on, if the first signal line outputs the valid first signal, the first signal can be output as a reset signal to the gate drive circuit 400 through the sixth switch tube T6, so as to realize the reset of the gate drive circuit 400; if the first signal of the first signal line is invalid, the sixth switch tube T6 remains in the on state, but does not output the reset signal.

[0087] When the control end of the sixth switch tube T6 is low level, the sixth switch tube T6 is turned off, and the output of the reset signal cannot be realized.

[0088] Further, referring to Figure 3 , the refresh rate adjusting circuit further comprises an isolation module, the isolation module comprises a seventh switch tube T7; wherein:

[0089] The control end of the seventh switch tube T7 is connected with the second signal line, the input end of the seventh switch tube T7 is connected with the first signal line, and the output end of the seventh switch tube T7 is connected with the charging end of the first charging unit and the charging end of the first signal sending unit respectively; wherein the fourth signal on the second signal line indicates that the seventh switch tube T7 is turned off after the sending of the start signal.

[0090] It can be understood that in the same target refresh area, the start of the first row and the reset of the last row both need to be triggered through the first signal line; at the same time, when multiple target refresh areas appear, multiple target refresh areas all need the first signal line to realize triggering, therefore, the validity of the first signal will cause mis-triggering; as known from the foregoing description, when there is only one target refresh area, the first row and the last row can be set in different odd and even rows to avoid mis-triggering, but when there are multiple target refresh areas, even if they are set in this way, multiple target refresh areas have multiple last rows, therefore, the last row will occupy odd and even rows, and mis-triggering of the refresh start module 100 will always occur.

[0091] In order to avoid this problem, an isolation module is arranged in the embodiment to isolate the first signal line.

[0092] Firstly, for a single target refresh area, the first row and the last row thereof are still set in different odd and even rows; and for two different target refresh areas, since there are two times of charging of the first capacitor C1, the validity of the first signal is required twice, and the latter first signal will also cause mis-triggering of the former, therefore, the two first rows are set in different odd and even rows.

[0093] After the charging is completed, the first row of the two target refresh areas is triggered to refresh again by a valid first signal at the same time, and after the first row refresh again is completed, the seventh switch tube T7 is controlled to be turned off, at this time, the first signal will not cause the first row to be triggered again; and the refresh reset module 200 of the last row of the target refresh area can also be reset at the same time; after the last row of the target refresh area is reset, the seventh switch tube T7 is controlled to be turned on, so that subsequent can trigger refresh again based on the need.

[0094] Further, the refresh end module 300 comprises an eighth switch tube; wherein:

[0095] The control end of the eighth switch tube is connected with the third signal line, the input end of the eighth switch tube is connected with the output end of the gate drive circuit 400, and the output end of the eighth switch tube is connected with the input end of the next gate drive circuit 400.

[0096] When the last row of the target refresh area outputs the scanning signal by the gate drive circuit 400, the third signal line outputs the third signal indicating the turn-off, such as low level, at this time, the eighth switch tube is turned off, the scanning signal cannot be transmitted to the next row through the eighth switch tube, and the next row cannot refresh again.

[0097] When the other row gate drive circuit 400 outputs the scanning signal, the third signal line outputs the third signal indicating the turn-on, such as high level, at this time, the eighth switch tube is turned on, the scanning signal is transmitted to the next row through the eighth switch tube, and the next row starts to refresh.

[0098] The overall implementation process of the present application is described as follows:

[0099] Referring to Figure 4 , the refresh rate adjusting circuit and the gate drive circuit 400 jointly constitute a GDL (Gate Driver Line, gate drive module) for a row of pixel rows; and the first clock signal line CLK1, the second clock signal line CLK2, the first signal line DATA, the second signal line SY and the third signal line SW are connected through the corresponding interfaces; referring to Figure 5 , Figure 5 The left waveform is the waveform during general refresh, and the right waveform is the waveform during refresh again.

[0100] 1. General refresh:

[0101] The scanning signal Gn-1 output by the previous row triggers the first drive switch tube TD1 to be turned on, the first drive switch tube TD1 charges the first drive capacitor CD1 through the clock signal, and then triggers the second drive switch tube TD2 to be turned on, and outputs the scanning signal Gn;

[0102] The next line of output scan signal Gn+1 triggers the third drive switch TD3 and the fourth drive switch TD4 to turn on, and the first drive capacitor CD1 resets, and the scan signal resets.

[0103] 2. Single target refresh area re-refresh:

[0104] The first line of the target refresh area: the scan signal output by the last line Gn-1 triggers the gate drive circuit 400 to output the scan signal Gn; at the same time, the first signal line outputs an effective first signal, the first switch T1 turns on, and the first signal reaches the first capacitor C1 through the first switch T1, realizing the charging of the first capacitor C1;

[0105] The last line of the target refresh area: when the gate drive circuit 400 outputs the scan signal of the current line, the first signal line outputs an effective first signal, the third switch T3 and the fourth switch T4 turn on, and the scan signal charges the second capacitor C2;

[0106] The first line of the target refresh area: when the first line of the target refresh area needs to trigger re-refresh, the first signal line outputs an effective first signal, and the first signal is output to the gate drive circuit 400 as a start signal through the second switch T2, triggering the re-refresh of the gate drive circuit 400, i.e. outputting the scan signal again; then, trigger the re-refresh of the next line of the gate drive circuit 400 until the last line of the target refresh area;

[0107] The last line of the target refresh area: the third signal line outputs a third signal indicating that the third signal is turned off, and the eighth switch is turned off, so that the scan signal cannot be output to the next line of the gate drive circuit 400; at the same time, the first signal line outputs an effective first signal, and the first signal reaches the control end of the third drive switch TD3 and the fourth drive switch TD4 through the sixth switch T6, triggering the reset of the gate drive circuit 400;

[0108] 3. Multiple target refresh area re-refresh:

[0109] The processes of each target refresh area are the same as those of the single target refresh area.

[0110] However, the first line of each target refresh area triggers re-refresh at the same time, and after the re-refresh of the first line of each target refresh area is completed, the seventh switch T7 is controlled to turn off, and until the reset of the last line of the target refresh area is completed, the seventh switch T7 is controlled to turn on.

[0111] The application also protects a display panel, which comprises a refresh rate adjusting circuit and a gate driving circuit, the structure of the refresh rate adjusting circuit can refer to the above-mentioned embodiments, which will not be repeated here. Naturally, since the display panel of the present embodiment adopts the technical solution of the above-mentioned refresh rate adjusting circuit, the display panel has all the beneficial effects of the above-mentioned refresh rate adjusting circuit.

[0112] It should be noted that in this paper, the term "including", "containing" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or system including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or includes elements inherent to such process, method, article or system. Without more limitations, the element defined by the sentence "including a" does not exclude the existence of other identical elements in the process, method, article or system including the element. The above-mentioned embodiment number of the application is only for description, not representing the advantages and disadvantages of the embodiments.

[0113] The above is only the preferred embodiment of the application, and does not limit the patent scope of the application, and any equivalent structure or equivalent process transformation using the content of the application specification and drawings, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the application.

Claims

1. A refresh rate adjustment circuit, characterized in that, The refresh rate adjustment circuit is connected to the gate drive circuit; the refresh rate adjustment circuit includes a refresh start module, a refresh reset module, and a refresh end module. The refresh start module is connected to the input terminal of the gate drive circuit, the refresh reset module is connected to the reset terminal of the gate drive circuit, and the output terminal of the gate drive circuit is connected to the input terminal of the next gate drive circuit through the refresh end module; wherein: For a target refresh area containing at least one row of consecutive pixels, the refresh start module corresponding to the first row of pixels in the target refresh area is used to send a start signal to the corresponding gate drive circuit so that the gate drive circuit outputs a gate drive signal. The refresh end module corresponding to the last row of pixels in the target refresh area is used to disconnect the output terminal of the gate driving circuit from the input terminal of the next gate driving circuit. The refresh reset module corresponding to the last row of pixels in the target refresh area is used to trigger a reset of the corresponding gate drive circuit.

2. The refresh rate adjustment circuit as described in claim 1, characterized in that, The refresh startup module includes a first charging unit and a first signal transmitting unit; the control terminal of the first charging unit is connected to the input terminal of the gate driving circuit, the charging terminal of the first charging unit is connected to a first signal line, the control terminal of the first signal transmitting unit is connected to the first charging unit, the input terminal of the first signal transmitting unit is connected to the first signal line, and the output terminal of the first signal transmitting unit is connected to the input terminal of the gate driving circuit; wherein: The first charging unit is used to charge the first signal transmitting unit when the input signal at the input terminal of the gate driving circuit and the first signal of the first signal line are both valid, and to provide a conduction signal to the first signal transmitting unit after charging is completed. The first signal transmitting unit is configured to send a start signal to the corresponding gate driving circuit when the first charging unit provides a conduction signal and the first signal of the first signal line is valid.

3. The refresh rate adjustment circuit as described in claim 2, characterized in that, The first charging unit includes a first switching transistor and a first capacitor; wherein: The control terminal of the first switching transistor is connected to the input terminal of the gate driving circuit, the input terminal of the first switching transistor is connected to the first signal line, the output terminal of the first switching transistor is connected to the first terminal of the first capacitor, and the second terminal of the first capacitor is connected to the low-voltage signal line; the output terminal of the first switching transistor is also connected to the control terminal of the first signal transmitting unit.

4. The refresh rate adjustment circuit as described in claim 2, characterized in that, The first signal transmitting unit includes a second switching transistor; wherein: The control terminal of the second switch is connected to the first charging unit as the control terminal of the first signal transmitting unit, the input terminal of the second switch is connected to the first signal line, and the output terminal of the second switch is connected to the input terminal of the gate driving circuit.

5. The refresh rate adjustment circuit as described in claim 1, characterized in that, The refresh reset module includes a second charging unit and a second signal transmitting unit; the control terminal of the second charging unit is connected to the first signal line, the input terminal of the second charging unit is connected to the output terminal of the gate driving circuit, so the control terminal of the second signal transmitting unit is connected to the second charging unit, the input terminal of the second signal transmitting unit is connected to the first signal line, and the output terminal of the second signal transmitting unit is connected to the reset terminal of the gate driving circuit.

6. The refresh rate adjustment circuit as described in claim 5, characterized in that, The second charging unit includes a third switch, a fourth switch, a fifth switch, and a second capacitor; wherein: The control terminal of the third switch is connected to the first signal line, the input terminal of the third switch is connected to the output terminal of the gate drive circuit, the output terminal of the third switch is connected to the control terminal and the input terminal of the fourth switch, the output terminal of the fourth switch is connected to the first terminal of the second capacitor, the first terminal of the second capacitor is also connected to the control terminal of the second signal transmitting unit, the second terminal of the second capacitor is connected to the low-voltage signal line, the output terminal of the fourth switch is also connected to the output terminal of the fifth switch, the input terminal of the fifth switch is connected to the low-voltage signal line, and the control terminal of the fifth switch is connected to the input terminal of the gate drive circuit.

7. The refresh rate adjustment circuit as described in claim 5, characterized in that, The second signal transmitting unit includes a sixth switching transistor; wherein: The control terminal of the sixth switch is connected to the second charging unit as the control terminal of the second signal transmitting unit. The input terminal of the sixth switch is connected to the first signal line, and the output terminal of the sixth switch is connected to the reset terminal of the gate driving circuit.

8. The refresh rate adjustment circuit as described in any one of claims 2 to 4, characterized in that, The refresh rate adjustment circuit further includes an isolation module, which includes a seventh switching transistor; wherein: The control terminal of the seventh switch is connected to the second signal line, the input terminal of the seventh switch is connected to the first signal line, and the output terminal of the seventh switch is connected to the charging terminal of the first charging unit and the input terminal of the first signal transmitting unit, respectively; wherein, the fourth signal on the second signal line indicates that the seventh switch is turned off after the start signal is sent.

9. The refresh rate adjustment circuit as described in claim 1, characterized in that, The refresh completion module includes an eighth switch transistor; wherein: The control terminal of the eighth switch is connected to the third signal line, the input terminal of the eighth switch is connected to the output terminal of the gate drive circuit, and the output terminal of the eighth switch is connected to the input terminal of the next gate drive circuit.

10. A display panel, characterized in that, The display panel includes a refresh rate adjustment circuit and a gate drive circuit as described in any one of claims 1 to 9.

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