Semiconductor element with top supporting layer and preparation method thereof

Abstract

The invention provides a semiconductor element and a preparation method thereof. The semiconductor element comprises a substrate; the bottom electrode is positioned on the substrate and comprises a container-shaped outline; and a top support layer overhung over the substrate and connected to the bottom electrode. A thickness ratio of a thickness of the top support layer to a thickness of the bottom electrode is between about 3.0% and about 8.0%.

Description

Technical Field

[0001] This application claims priority to U.S. patent application No. 18 / 625,497 (i.e., the priority date is "April 3, 2024"), the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device with a top support layer and a method for manufacturing the same. Background Art

[0003] Semiconductor components are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor components continue to shrink in size to meet the ever-increasing demand for computing power. However, various problems arise during the miniaturization process, and these problems are increasing. Consequently, challenges remain in improving quality, yield, performance, and reliability, while reducing complexity.

[0004] The above description of “prior art” merely provides background technology, does not admit that the above description of “prior art” reveals the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the Invention

[0005] One aspect of the present disclosure provides a semiconductor device comprising a substrate; a bottom electrode disposed on the substrate and having a container-shaped profile; and a top support layer overhanging the substrate and connected to the bottom electrode. A thickness ratio of the top support layer to a thickness of the bottom electrode is between approximately 3.0% and approximately 8.0%.

[0006] Another aspect of the present disclosure provides a semiconductor device comprising a substrate; a bottom electrode comprising a bottom portion located above the substrate and extending parallel to a top surface of the substrate, a first wall portion extending upward from the bottom portion, and a second wall portion extending upward from the bottom portion and away from the first wall portion; a first supporting layer located above the substrate and surrounding the first and second wall portions; a second supporting layer located above the first supporting layer and surrounding the first and second wall portions; and a third supporting layer located above the second supporting layer and surrounding the second wall portion. A thickness ratio of a thickness of the top supporting layer to a thickness of the bottom electrode is between approximately 3.0% and approximately 8.0%.

[0007] Another aspect of the present disclosure provides a method for fabricating a semiconductor device, comprising: forming a landing area on a substrate; sequentially forming a first supporting layer, a first material layer, a second supporting layer, a top material layer, a third supporting layer, and a bottom mask layer on the landing area; forming a first recess through the bottom mask layer, the third supporting layer, the top material layer, the second supporting layer, the first material layer, and the first supporting layer to expose the landing area; conformally forming a bottom electrode material layer on the bottom mask layer and the first recess, forming a sacrificial material to fill the first recess, and performing a planarization process to expose the bottom mask layer; performing a first etching process to selectively remove the bottom mask layer; performing a second etching process to selectively remove the bottom electrode material layer above the third supporting layer to convert the bottom electrode material layer into a bottom electrode; and performing a third etching process to remove the sacrificial material. During the first etching process, the etch rate ratio of the bottom mask layer to the third supporting layer is greater than 1000. During the second etching process, an etching rate ratio of the bottom electrode material layer to the third supporting layer is greater than 100.

[0008] Due to the design of the semiconductor device disclosed herein, the high etch selectivity of the first and second etching processes can significantly reduce the consumption of the third supporting layer (or top supporting layer). Therefore, the remaining thickness of the third supporting layer can be increased. Consequently, the performance of the semiconductor device can be improved. Furthermore, by doping different material layers with different dopants, the bottom of the first recess can be widened. Consequently, the performance of the semiconductor device can be improved.

[0009] The above has outlined the technical features and advantages of the present disclosure in a fairly broad manner, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that form the subject of the claims of the present disclosure will be described below. It should be understood by those skilled in the art to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used quite easily to modify or design other structures or processes to achieve the same purposes as the present disclosure. It should also be understood by those skilled in the art to which the present disclosure belongs that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] A more complete understanding of the present disclosure may be obtained by referring to the detailed description and claims when considered in conjunction with the drawings, wherein like reference characters represent like elements throughout the drawings, and:

[0011] Figure 1 According to one embodiment of the present disclosure, a method for manufacturing a semiconductor device is shown in the form of a flow chart.

[0012] Figures 2 to 5A cross-sectional schematic diagram showing a partial process of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 6 yes Figure 5 A top view of the middle semiconductor element.

[0014] Figures 7 to 13 A cross-sectional schematic diagram showing a partial process of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0015] Figure 14 yes Figure 13 A top view of the middle semiconductor element.

[0016] Figures 15 to 19 A cross-sectional schematic diagram showing a partial process of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0017] Figures 20 to 33 A cross-sectional schematic diagram shows a process for manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0018] The description of the accompanying drawings is as follows:

[0019] 1A: Semiconductor components

[0020] 1B: Semiconductor components

[0021] 10: Method

[0022] 101: Substrate

[0023] 101: Top surface

[0024] 102: Landing Area

[0025] 102T: Top surface

[0026] 103: Insulation layer

[0027] 104: First support layer

[0028] 104T: Top surface

[0029] 105: First material layer

[0030] 105T: Top surface

[0031] 106: Second material layer

[0032] 107: Second support layer

[0033] 107T: Top surface

[0034] 108: Top material layer

[0035] 108T1: Top surface

[0036] 108T2: Top surface

[0037] 109: The third support layer

[0038] 109T: Top surface

[0039] 111: Bottom electrode

[0040] 111A: First wall portion

[0041] 111B: Second wall portion

[0042] 111C: bottom part

[0043] 111M: bottom electrode material layer

[0044] 111T1: Top surface

[0045] 111T2: Top surface

[0046] 112: Dielectric layer

[0047] 113: Top electrode

[0048] 114: Ground layer

[0049] 137: Sacrificial Materials

[0050] 151: Bottom mask layer

[0051] 151T: Top surface

[0052] 161: First mask layer

[0053] CD1: Dimensions

[0054] CD2: Dimensions

[0055] CD3: Dimensions

[0056] CD4: Dimensions

[0057] CDR: Dimensions

[0058] D1': size

[0059] D2': size

[0060] D3': Dimensions

[0061] E1: Space

[0062] E2: Space

[0063] E3: Space

[0064] h1: thickness

[0065] h2: thickness

[0066] h3: thickness

[0067] h4: thickness

[0068] h6: thickness

[0069] J1: Truncation area

[0070] P1: Part 1

[0071] P1': lower part

[0072] P1": lower part

[0073] P2: Part 2

[0074] P2': middle part

[0075] P2”: middle part

[0076] P3: Part 3

[0077] P3': higher part

[0078] P3”: higher part

[0079] P4: Part 4

[0080] R1: First depression

[0081] R2: Second depression

[0082] RA: First Region

[0083] RB: Second zone

[0084] S11: Steps

[0085] S13: Steps

[0086] S15: Steps

[0087] SW1: First inner wall

[0088] SW1': Second inner wall

[0089] SW2: Third inner wall

[0090] SW2': Fourth inner wall

[0091] SW3: Fifth inner wall

[0092] SW3': Sixth inner wall

[0093] W1: width

[0094] W2: width

[0095] W3: Width

[0096] Z: Direction DETAILED DESCRIPTION

[0097] The following disclosure provides many different embodiments or examples to implement different components of the embodiments of the present disclosure. The following describes specific examples of components and their arrangements to simplify the embodiments of the present disclosure. Of course, these are only examples and should not be used to limit the scope of the embodiments of the present disclosure. For example, when the description refers to a first component being formed "on" or "up" a second component, it may include an embodiment in which the first component is in direct contact with the second component, and it may also include an embodiment in which there are other components formed between the two without direct contact. In addition, the present disclosure may repeat reference symbols and / or marks in different embodiments. These repetitions are for the purpose of simplicity and clarity and are not used to define the relationship between the different embodiments and / or structures discussed.

[0098] Additionally, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like are used to facilitate describing the relationship of one element or component to another element or component as depicted in the drawings. These spatially relative terms are intended to encompass different orientations of the element in use or operation other than the orientation depicted in the drawings. The element may be oriented differently (rotated 90 degrees or at other orientations), and the spatially relative adjectives used therein should be interpreted accordingly.

[0099] It will be understood that when an element or layer is referred to as being “connected” or “coupled” to another element or layer, it can be directly connected or coupled to the other element or layer or intervening elements or layers may be present.

[0100] It should be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. Unless otherwise specified, these terms are used only to distinguish one element from another. Thus, for example, a first element, a first component, or a first part discussed below may be referred to as a second element, a second component, or a second part without departing from the teachings of the present disclosure.

[0101] Unless the context indicates otherwise, terms like "same," "equal," "planar," or "coplanar" used herein when referring to an orientation, layout, position, shape, size, quantity, or other measurement do not necessarily mean exactly the same orientation, layout, position, shape, size, quantity, or other measurement, but are intended to encompass nearly identical orientations, layouts, positions, shapes, sizes, quantities, or other measurements within an acceptable range of variation, for example, due to manufacturing processes. The term "substantially" may be used herein to reflect this meaning. For example, items described as "substantially the same," "substantially equal," or "substantially planar" may be exactly the same, equal, or planar, or may be the same, equal, or planar within an acceptable range of variation, for example, due to manufacturing processes.

[0102] In the present disclosure, a semiconductor element generally refers to an element that can function by utilizing semiconductor characteristics, and electro-optical elements, light-emitting display elements, semiconductor circuits, and electronic elements are all included in the category of semiconductor elements.

[0103] It should be noted that in the description of the present disclosure, above or up corresponds to the arrow direction of direction Z, and below or down corresponds to the arrow direction opposite to direction Z.

[0104] Figure 1 According to some embodiments of the present disclosure, a method 10 for manufacturing a semiconductor device 1A is shown in the form of a flow chart. Figures 2 to 5 A cross-sectional schematic diagram shows a partial process of manufacturing a semiconductor device 1A according to an embodiment of the present disclosure. Figure 6 yes Figure 5 A top view of the middle semiconductor element.

[0105] Reference Figures 1 to 6 In step S11, a substrate 101 can be provided, a plurality of landing areas 102 can be formed on the substrate 101, a first supporting layer 104 (also called a bottom supporting layer), a first material layer 105, a second supporting layer 107 (also called an intermediate supporting layer), a top material layer 108, and a third supporting layer 109 (also called a top supporting layer) can be sequentially formed on the landing areas 102, and a plurality of first recesses R1 can be formed to expose the landing areas 102.

[0106] Reference Figure 2A substrate 101 may be provided. An insulating layer 103 may be formed on the substrate 101, and the landing areas 102 may be formed in the insulating layer 103. For example, one landing area 102 may be formed on a first area RA of the substrate 101, and another landing area 102 may be formed on a second area RB different from the first area RA. In some embodiments, a planarization process such as chemical mechanical planarization (CMP) may be performed on the insulating layer 103 and the landing areas 102.

[0107] The substrate 101 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The substrate 101 may include an elemental semiconductor, including single crystal, polycrystalline, or amorphous forms of silicon or germanium; a compound semiconductor material, including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor material, including at least one of silicon, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; or a combination of the foregoing. In some embodiments, the alloy semiconductor substrate may be a silicon alloy having a gradient silicon feature, wherein the Si and metal composition changes from one ratio at one location of the gradient silicon feature to another ratio at another location of the gradient silicon feature. For example, the alloy semiconductor substrate may be a SiGe alloy having a gradient SiGe feature, wherein the Si and Ge composition changes from one ratio at one location of the gradient SiGe feature to another ratio at another location of the gradient SiGe feature. In another embodiment, the SiGe alloy is formed on a silicon substrate. In some embodiments, another material in contact with the SiGe alloy may mechanically strain the SiGe alloy.

[0108] In some embodiments, substrate 101 may have a multilayer structure, or substrate 101 may include a multilayer compound semiconductor structure. In some embodiments, substrate 101 may include a semiconductor element, an electronic component, an electronic part, or a combination thereof. In some embodiments, substrate 101 may include a transistor or a functional unit of a transistor.

[0109] In some embodiments, the landing area 102 may include a conductive material such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (e.g., titanium nitride), transition metal aluminides, doped polysilicon, polycrystalline silicon germanium, polycrystalline germanium, or combinations thereof.

[0110] Reference Figure 3 The first supporting layer 104 may extend over the insulating layer 103 and the landing area 102. In some embodiments, the material of the first supporting layer 104 may include silicon nitride (SiN). Alternatively, the material of the first supporting layer 104 may be another suitable material, such as an insulating material.

[0111] Reference Figure 3 , a first material layer 105 may be formed on the first support layer 104. In some embodiments, the first material layer 105 may be doped with a P-type dopant. For example, the first material layer 105 may be doped with boron, indium, gallium, or other suitable dopants. In some embodiments, the first material layer 105 may include polysilicon doped with a P-type dopant. In some embodiments, when the first material layer 105 is doped with boron, the concentration of the boron dopant in the first material layer 105 may be 5E14 atoms / cm 3 to about 5E15 atoms / cm 3 In some embodiments, the first material layer 105 may include borophosphosilicate glass. In some embodiments, the dopant concentration in the first material layer 105 may gradually decrease along the direction Z away from the first support layer 104. The first material layer 105 may be in direct contact with the first support layer 104. In some embodiments, the thickness of the first material layer 105 may be less than 800 nm.

[0112] Reference Figure 3 A second supporting layer 107 may be formed on the first material layer 105. The material of the second supporting layer 107 may be the same as that of the first supporting layer 104. In some embodiments, the material of the second supporting layer 107 may include silicon nitride.

[0113] Reference Figure 3 , a top material layer 108 (also referred to as a third material layer) can be formed on the second supporting layer 107. In some embodiments, the top material layer 108 may include, for example, silicon oxide. In some embodiments, the manufacturing technology of the top material layer 108 may include, for example, chemical vapor deposition (CVD) using tetraethyl orthosilicate (TEOS), or other applicable deposition processes. In some embodiments, the thickness of the top material layer 108 may be less than the thickness of the first material layer 105. The top material layer 108 may be in direct contact with the second supporting layer 107. The top material layer 108 has a top surface 108T1.

[0114] Reference Figure 3, a third supporting layer 109 may be formed on the top surface 108T1 of the top material layer 108. The material of the third supporting layer 109 may be the same as the material of the first supporting layer 104 or the material of the second supporting layer 107. In some embodiments, the material of the third supporting layer 109 includes silicon nitride. In some embodiments, the total thickness of the stack of the first supporting layer 104, the first material layer 105, the second supporting layer 107, the top material layer 108, and the third supporting layer 109 may be in a range of 0.8 μm to approximately 1.2 μm.

[0115] Reference Figure 4 A bottom mask layer 151 may be formed on the third supporting layer 109. In some embodiments, the bottom mask layer 151 may serve as a hard mask for forming the first recess R1. In some embodiments, the bottom mask layer 151 may include polysilicon or other suitable materials having etching selectivity to silicon oxide and silicon nitride. In some embodiments, the bottom mask layer 151 may be fabricated using, for example, chemical vapor deposition or other suitable deposition processes. A first mask layer 161 may be formed on the bottom mask layer 151. In some embodiments, the first mask layer 161 may be a photoresist layer and may include a pattern of the first recess R1.

[0116] Reference Figure 5 , the first recesses R1 can be formed on the substrate 101 by performing a dry etching process using the first mask layer 161 as a mask. In some embodiments, the dry etching process may include applying plasma, such as fluorine-based plasma or fluorine-containing plasma. In some embodiments, each first recess R1 can pass through the first support layer 104, the first material layer 105, the second support layer 107, the top material layer 108, and the third support layer 109. The landing area 102 can be exposed through the first recess R1. In some embodiments, a cleaning process can be performed to remove residues generated during the dry etching process. In some embodiments, as Figure 6 As shown, the first recesses R1 can be arranged in a staggered array. The position of each first recess R1 corresponds to the position of one of the landing areas 102. In some embodiments, the first recesses R1 can include a tapered profile toward the substrate 101. In other words, the width of the first recesses R1 can gradually decrease toward the substrate 101. In some embodiments, the aspect ratio of the first recesses R1 can be greater than 35. In some embodiments, the top surface 102T of the landing area 102 can be partially exposed through the first recesses R1. That is, the first supporting layer 104 can cover a portion of the landing area 102.

[0117] It should be noted that the non-uniform morphology of the bottom mask layer 151 may be caused by the loading effect of the dry etching process.

[0118] Figures 7 to 13 A cross-sectional schematic diagram shows a partial process of manufacturing a semiconductor device 1A according to an embodiment of the present disclosure. Figure 14 yes Figure 13 A top view of the middle semiconductor element. Figures 15 to 19 A cross-sectional schematic diagram shows a partial process of manufacturing a semiconductor device 1A according to an embodiment of the present disclosure.

[0119] Reference Figure 1 and Figures 7 to 12 In step S13, a bottom electrode material layer 111M can be conformally formed on the first recesses R1 and the bottom mask layer 151, a sacrificial material 137 can be formed to fill the first recesses R1, the bottom mask layer 151 can be removed, a portion of the bottom electrode material layer 111M can be removed to form a plurality of bottom electrodes 111 in the first recesses R1, and the sacrificial material 137 can be removed.

[0120] Reference Figure 7 , the bottom electrode material layer 111M can be formed in the first recess R1 so that the bottom electrode material layer 111M has a container-shaped profile. In the present disclosure, the term "container-shaped" or "shaped as a container" can refer to an object having a bottom and a sidewall portion extending from the bottom, and a portion of the space above the bottom is at least partially laterally surrounded by the sidewall portion. The bottom electrode material layer 111M can conform to the profile of the first recess R1. In some embodiments, the bottom electrode material layer 111M can further cover the top surface 151T of the bottom mask layer 151 and the top surface 102T of the landing area 102. In some embodiments, the bottom electrode material layer 111M may include titanium nitride (TiN), titanium silicon nitride (TiSiN), or a combination of the foregoing. In some embodiments, the bottom electrode material layer 111M may be formed by blanket deposition, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other applicable deposition processes.

[0121] Reference Figure 8, a sacrificial material 137 may be formed on the substrate 101 and fill the first recess R1. In some embodiments, the sacrificial material 137 may completely cover the bottom electrode material layer 111M. In some embodiments, the sacrificial material 137 may include a material having an etching selectivity to the bottom electrode material layer 111M. In some embodiments, the sacrificial material 137 may include a material having an etching selectivity to the bottom electrode material layer 111M and the bottom mask layer 151. In some embodiments, the sacrificial material 137 may include an oxide, such as silicon oxide. In some embodiments, the sacrificial material 137 may include a photoresist. In some embodiments, the manufacturing technology of the sacrificial material 137 may include a deposition process, such as a CVD process, a PVD process, an ALD process, or a spin coating process.

[0122] Reference Figure 9 , a planarization process such as chemical mechanical polishing (CMP) can be performed until the bottom mask layer 151 is exposed to remove excess material and provide a substantially flat surface for subsequent processing steps. During the planarization process, portions of the bottom electrode material layer 111M, the bottom mask layer 151, and the sacrificial material 137 can be removed. The sacrificial material 137 can be divided into a plurality of portions within the first recess R1, respectively. After the planarization process, the bottom electrode material layer 111M can be divided into a plurality of portions located above each landing area 102. For example, a portion of the bottom electrode material layer 111M can be formed above the first region RA, and another portion of the bottom electrode material layer 111M can be formed above the second region RB. Each portion of the bottom electrode material layer 111M can have a container-shaped profile.

[0123] Reference Figure 10 , a first etching process may be performed to selectively remove the bottom mask layer 151. In some embodiments, the first etching process may be a gas etching process. In some embodiments, the first etching process may use free radicals (e.g., hydrogen radicals or fluorine radicals) to remove the bottom mask layer 151. In some embodiments, the ions of the first etching process may be filtered. In some embodiments, the reaction gas of the first etching process may include, for example, ammonia, hydrogen fluoride, fluorine, nitrogen trifluoride and / or hydrogen. In some embodiments, the first etching process may include a carrier gas such as nitrogen and / or argon. In some embodiments, the process temperature of the first etching process may be between approximately 20°C and approximately 120°C.

[0124] In some embodiments, during the first etching process, the etch rate ratio of the bottom mask layer 151 to the third supporting layer 109 may be greater than 1000. In some embodiments, during the first etching process, the etch rate ratio of the doped polysilicon to the silicon nitride may be greater than 1000. It should be noted that due to the high etching selectivity of the first etching process, the consumption of the third supporting layer 109 may be significantly reduced.

[0125] Reference Figure 11 A second etching process may be performed to remove the bottom electrode material layer 111M above the third supporting layer 109. After the second etching process, the remaining bottom electrode material layer 111M may be referred to as the bottom electrodes 111. The bottom electrodes 111 may have a container-shaped profile. In some embodiments, the top surface 111T1 of the bottom electrode 111 and the top surface 109T of the third supporting layer 109 may be substantially coplanar.

[0126] In some embodiments, the second etching process may be a gas etching process. In some embodiments, the second etching process may use free radicals (e.g., hydrogen radicals or fluorine radicals) to remove the exposed bottom electrode material layer 111M. In some embodiments, the ions of the second etching process may be filtered. In some embodiments, the reaction gas of the second etching process may include, for example, ammonia, hydrogen fluoride, fluorine, nitrogen trifluoride and / or hydrogen. In some embodiments, the second etching process may include a carrier gas such as nitrogen and / or argon. In some embodiments, the process temperature of the second etching process may be between approximately 250°C and approximately 350°C.

[0127] In some embodiments, during the second etching process, the etching rate ratio of the bottom electrode material layer 111M to the third supporting layer 109 may be greater than 100. In some embodiments, during the second etching process, the etching rate ratio of tungsten to silicon nitride may be greater than 100. It should be noted that due to the high etching selectivity of the second etching process, the consumption of the third supporting layer 109 may be significantly reduced.

[0128] In some embodiments, after the first and second etching processes, the thickness loss of the third supporting layer 109 can be less than about 50%, about 45%, about 40%, about 35%, or about 30%. The thickness loss of the third supporting layer 109 can be calculated by dividing the thickness of the third supporting layer 109 before the first etching process by the thickness of the third supporting layer 109 after the second etching process. In some embodiments, after the first and second etching processes, the thickness loss of the third supporting layer 109 can be less than about 40 nm, about 35 nm, about 30 nm, or about 25 nm. In some embodiments, after the first and second etching processes, the thickness h6 of the third supporting layer 109 can be greater than about 40 nm, about 45 nm, about 50 nm, about 55 nm, or about 60 nm.

[0129] In some embodiments, the first etching process and the second etching process may be performed in the same processing chamber.

[0130] Reference Figure 12 , a third etching process may be performed to completely remove the sacrificial material 137. In some embodiments, during the third etching process, the etching selectivity of the sacrificial material 137 relative to the bottom electrode 111 may be relatively high. Therefore, the sacrificial material 137 may be removed by the etching process while substantially preserving the bottom electrode 111. In some embodiments, the third etching process may be a wet etching process. In some embodiments, the third etching process may include dilute hydrofluoric acid.

[0131] Reference Figure 1 and Figures 13 to 19 In step S15, the third support layer 109 and the bottom electrodes 111 can be partially removed to expose the top material layer 108 in the truncation area J1, the top material layer 108 and the first material layer 105 can be removed, a dielectric layer 112 can be formed to cover the bottom electrodes 111, a top electrode 113 can be formed to cover the dielectric layer 112, and a ground layer 114 can be formed to cover the top electrode 113.

[0132] Reference Figure 13 , a truncation region J1 can be defined by a lithography process, wherein the truncation region J1 is connected to at least two first recesses R1. In some embodiments, each truncation region J1 is connected to three first recesses R1, such as Figure 14As shown. Furthermore, an etching process can be performed to remove a portion of the top material layer 108, a portion of the third supporting layer 109, and a portion of the bottom electrode 111 above the cutoff region J1. In some embodiments, the etching process can be stopped at a location within the top material layer 108, or in other words, the etching process can be stopped at a location above the top surface 107T of the second supporting layer 107. After such an etching process, the remaining portion of the top material layer 108 in the cutoff region J1 has a top surface 108T2 that is lower than the top surface 108T1 of the top material layer 108 outside the cutoff region J1. In some embodiments, a cleaning process can be performed to remove residues generated during the etching process.

[0133] In some embodiments, after the etching process, the bottom electrode 111 may include a first wall portion 111A extending upward and adjacent to the truncation region J1, a second wall portion 111B extending upward and away from one side of the first wall portion 111A, and a bottom portion 111C located above the landing area 102 and extending parallel to the top surface 101T of the substrate 101. In some embodiments, a dimension CDR between the first wall portion 111A and the second wall portion 111B may taper toward the bottom portion 111C.

[0134] The first wall portion 111A may have a top surface 111T2 that is lower than the top surface 108T1 of the top material layer 108. The top surface 111T2 may be lower than the top surface 111T1 of the second wall portion 111B. In some embodiments, the top surface 111T2 of the first wall portion 111A and the top surface 108T2 of the top material layer 108 at the truncation region J1 may be substantially coplanar.

[0135] In some embodiments, a thickness ratio of the thickness h6 of the third supporting layer 109 to the thickness h4 of the bottom electrode 111 can be between about 3.0% and about 8.0% or between about 3.3% and about 7.5%. In some embodiments, the thickness h4 of the bottom electrode 111 can be in a range of 0.8 μm to about 1.2 μm.

[0136] Reference Figure 15, the top material layer 108 can be removed by a removal process. In some embodiments, the removal process can include applying NF3 and H2 on the third material layer 108, accompanied by the application of plasma. The etching rate of the removal process for Si can be significantly greater than the etching rate for SiN, for example, about 2000:1. In addition, the aforementioned etching recipe is an effective process when the target layer to be etched can be partially covered by SiN. After the removal process is performed, the third support layer 109 can remain attached to (adhered to) the bottom electrode 111 and overhang above the second support layer 107. In some embodiments, the third support layer 109 can be connected to the second wall portion 111B of the bottom electrode 111.

[0137] A top surface 107T of the second supporting layer 107 may be exposed, and an empty space E1 may be formed between the second supporting layer 107 and the third supporting layer 109 .

[0138] After the removal process, a punch-through process may be performed to remove a portion of the second support layer 107 in the cut-off region J1 (eg, Figure 13 As shown in FIG. 1 , a second recess R2 may be formed in the second supporting layer 107 , and the top surface 105T of the first material layer 105 may be exposed through the second recess R2 . The second recess R2 may be located between the first wall portions 111A of the bottom electrode 111 .

[0139] Reference Figure 16 , the first material layer 105 can be removed by a removal process. In some embodiments, the removal process can include applying NF3 and H2 on the first material layer 105, accompanied by the application of plasma. Such a removal process can have a significantly greater etching rate for Si than for SiN, for example, about 2000:1. After the removal process, the second support layer 107 can remain attached to the bottom electrode 111 and overhang the first support layer 104. In some embodiments, the etching chemicals are applied via Figure 15 The second recess R2 is shown as being formed therein. In some embodiments, the second supporting layer 107 may be connected to the second wall portion 111B and the first wall portion 111A of the bottom electrode 111. The top surface 104T of the first supporting layer 104 may be exposed. An empty space E2 may be formed between the first supporting layer 104 and the second supporting layer 107. An empty space E3 may be formed between the first wall portion 111A of the bottom electrode 111.

[0140] In summary, the first material layer 105 and the top material layer 108 are removed. The first support layer 104, the second support layer 107, the third support layer 109, and the bottom electrode 111 remain in place.

[0141] Reference Figure 17 , a dielectric layer 112 can be conformally formed to cover the surfaces of the third supporting layer 109, the second supporting layer 107, the first supporting layer 104, and the bottom electrode 111. In some embodiments, the dielectric layer 112 can include a single layer or multiple layers. In some embodiments, the dielectric layer 112 can include SiO2, a dielectric material with a high dielectric constant (high-k), such as ZrO2, HfO2, TiO2, AlO, or a combination of the foregoing. For example, the dielectric layer 112 can be a three-layer structure including two layers of aluminum oxide and a layer of zirconium oxide disposed therebetween. In addition, in some embodiments, the fabrication technique of the dielectric layer 112 can include a conformal deposition process, such as a CVD process, a PVD process, or an ALD process.

[0142] Reference Figure 18 , a top electrode 113 can be conformally formed to cover the dielectric layer 112. In some embodiments, the top electrode 113 can include titanium nitride (TiN), titanium silicon nitride (TiSiN), or a combination thereof. In some embodiments, the top electrode 113 can be formed using a conformal deposition process such as a CVD process, a PVD process, or an ALD process.

[0143] Reference Figure 19 A ground layer 114 may be formed on the top electrode 113 and fill the empty space E1, the empty space E2, the empty space E3, and the first recess R1. In some embodiments, the ground layer 114 is doped with polysilicon, polysilicon germanium, polycrystalline germanium, or a combination thereof. In some embodiments, the ground layer 114 may be doped with a P-type dopant or an N-type dopant. The P-type dopant may include boron, indium, or gallium. The N-type dopant may include phosphorus, arsenic, antimony, or bismuth. In some embodiments, the fabrication technique of the ground layer 114 may include, for example, a CVD process or other applicable deposition process.

[0144] In some embodiments, an annealing process may be performed to activate the ground layer 114. The temperature of the annealing process may be between about 800° C. and about 1250° C. The annealing process may have a process duration between about 1 millisecond and about 500 milliseconds. The annealing process may be, for example, rapid thermal annealing, laser spike annealing, or flash lamp annealing.

[0145] Figures 20 to 33 A cross-sectional schematic diagram shows a process for manufacturing a semiconductor device 1B according to another embodiment of the present disclosure.

[0146] Reference Figure 20 , you can use something like Figure 2 and Figure 3 The substrate 101, the landing areas 102, the insulating layer 103, and the first supporting layer 104 are formed by the steps shown, and their description is not repeated here.

[0147] A first material layer 105 may be formed on the first support layer 104, wherein the first material layer 105 may be doped with an N-type dopant. For example, the first material layer 105 may be doped with phosphorus, arsenic, antimony, bismuth, or other suitable dopants. In some embodiments, the first material layer 105 may include polysilicon doped with an N-type dopant. The first material layer 105 may have a first thickness h1. In some embodiments, the first thickness h1 of the first material layer 105 may be less than 400 nm. In some embodiments, when the first material layer 105 is doped with phosphorus, the concentration of the phosphorus dopant in the first material layer 105 may be 5E14 atoms / cm 3 to about 5E15 atoms / cm 3 within the range.

[0148] A second material layer 106 may be formed over the first material layer 105. The second material layer 106 may have a second thickness h2. In some embodiments, the second thickness h2 of the second material layer 106 may be less than the first thickness h1 of the first material layer 105. In some embodiments, the second thickness h2 of the second material layer 106 may be less than 200 nm. In some embodiments, the second material layer 106 may include undoped polysilicon (which may be referred to as intrinsic polysilicon), i.e., having no significant dopants therein. The second material layer 106 may be in direct contact with the first material layer 105.

[0149] A second supporting layer 107 may be formed on the second material layer 106. The material of the second supporting layer 107 may be the same as that of the first supporting layer 104. In some embodiments, the material of the second supporting layer 107 may include silicon nitride.

[0150] A top material layer 108 may be formed on the second supporting layer 107, wherein the top material layer 108 may be doped with a P-type dopant. For example, the top material layer 108 may be doped with boron, indium, gallium, or other suitable dopants. The top material layer 108 may have a third thickness h3. In some embodiments, the third thickness h3 of the top material layer 108 may be greater than the first thickness h1 of the first material layer 105. In some embodiments, the third thickness h3 of the top material layer 108 may be greater than the second thickness h2 of the second material layer 106. In some embodiments, the third thickness h3 of the top material layer 108 may be less than 500 nm. In some embodiments, the sum of the first thickness h1 of the first material layer 105 and the second thickness h2 of the second material layer 106 is greater than the third thickness h3 of the top material layer 108.

[0151] In some embodiments, the top material layer 108 may include polysilicon doped with a P-type dopant. In some embodiments, when the top material layer 108 is doped with boron, the concentration of the boron dopant in the top material layer 108 is between 5E14 atoms / cm 3 to about 5E15 atoms / cm 3 The top material layer 108 may be in direct contact with the second support layer 107. The top material layer 108 has a top surface 108T1.

[0152] You can use something like Figure 3 and Figure 4 The third supporting layer 109, the bottom mask layer 151, and the first mask layer 161 are formed by the steps shown, and their description is not repeated here.

[0153] Reference Figure 21 , a plurality of first recesses R1 can be formed on the substrate 101 by performing a dry etching process. In some embodiments, the dry etching process may include applying plasma, such as fluorine-based plasma or fluorine-containing plasma. In some embodiments, each first recess R1 may pass through the first support layer 104, the first material layer 105, the second material layer 106, the second support layer 107, the top material layer 108, and the third support layer 109. The landing area 102 can be exposed through the first recess R1. In some embodiments, the position of the first recess R1 can be defined by one or more lithography operations, and a cleaning process can be performed to remove residues generated in the dry etching process. In some embodiments, the first recesses R1 can be configured in a staggered array (such as Figure 6 As shown in FIG. 1 , the position of each first recess R1 may correspond to the position of a landing area 102 .

[0154] In some embodiments, the aspect ratio of the first recess R1 may be greater than 35. The first recess R1 may include a first portion P1 laterally surrounded by the first material layer 105, a second portion P2 laterally surrounded by the second material layer 106, a third portion P3 laterally surrounded by the third material layer 108, and a fourth portion P4 laterally surrounded by the first supporting layer 104. The third portion P3 may be located above the second portion P2, the second portion P2 may be located above the first portion P1, and the first portion P1 may be located above the fourth portion P4.

[0155] The dry etching process can etch the first material layer 105 at a higher rate than the second material layer 106 during the dry etching process. Furthermore, the dry etching process can etch the second material layer 106 at a higher rate than the third material layer 108 during the dry etching process. Specifically, by doping the first material layer 105 with a predetermined concentration of N-type dopants, the lateral etching rate of the first material layer 105 during the dry etching process can be increased. Conversely, by doping the third material layer 108 with a predetermined concentration of P-type dopants, the lateral etching rate of the third material layer 108 during the dry etching process can be reduced.

[0156] In a comparative embodiment, a recess (not shown) having a high aspect ratio and a narrower bottom dimension (relative to the top dimension) can result in a lower capacitance of a capacitor further formed in the recess. Conversely, doping the first material layer 105 and the third material layer 108 with different types of dopants and providing the second material layer 106 without significant doping between the first material layer 105 and the third material layer 108 can widen the bottom of the first recess R1. This improvement in the profile of the first recess R1 can enhance the performance of the semiconductor element 1A.

[0157] Specifically, dimension CD1 of first portion P1 may be greater than dimension CD2 of second portion P2. In some embodiments, dimension CD2 of second portion P2 may be greater than dimension CD3 of third portion P3. In some embodiments, dimension CD1 of first portion P1 may be greater than dimension CD4 of fourth portion P4. In some embodiments, dimension CD1 may be greater than dimension CD2 or dimension CD3. The aforementioned ranges of dopant concentration in the material layers are designed to achieve desired values ​​for dimensions CD1, CD2, and CD3, wherein the difference between CD1 and CD3 is within a predetermined range.

[0158] In some alternative embodiments, dimension CD1 may be comparable to dimension CD2, and dimension CD2 may be comparable to dimension CD3.

[0159] In some embodiments, the top surface 102T of the landing area 102 may be exposed through the fourth portion P4 of the first recess R1 . The first supporting layer 104 may cover a portion of the landing area 102 .

[0160] Reference Figure 22 , you can use something like Figure 7 The bottom electrode material layer 111M is formed by the steps shown, and the description thereof will not be repeated here.

[0161] Reference Figure 23 , you can use something like Figure 8 The sacrificial material 137 is formed by the steps shown in the figure, and its description is not repeated here.

[0162] Reference Figure 24 , you can use something like Figure 9 The planarization process is performed by the steps shown in the figure, and the description thereof will not be repeated here.

[0163] Reference Figure 25 , you can use something like Figure 10 The bottom mask layer 151 is removed by the steps shown, and its description is not repeated here.

[0164] Reference Figure 26 , you can use something like Figure 11 The bottom electrode 111 is formed by the steps shown in the figure, and the description thereof will not be repeated here.

[0165] Reference Figure 27 , you can use something like Figure 12 The sacrificial material 137 is removed by the steps shown, and its description is not repeated here.

[0166] Reference Figure 28 , you can use something like Figure 13 and Figure 14 The steps shown cause the truncation region J1 to be recessed, and a description thereof will not be repeated here. After the truncation region J1 is recessed, a first recess R1 may be defined by the bottom electrode 111. In some embodiments, the first recess R1 may include a lower portion P1', a middle portion P2', and an upper portion P3'. The lower portion P1' may have a first width W1 measured from the first inner sidewall SW1 of the lower portion P1' to the second inner sidewall SW1' of the lower portion P1', the middle portion P2' may have a second width W2 measured from the third inner sidewall SW2 of the middle portion P2' to the fourth inner sidewall SW2' of the middle portion P2', and the upper portion P3' may have a third width W3 measured from the fifth inner sidewall SW3 of the upper portion P3' to the sixth inner sidewall SW3' of the upper portion P3'.

[0167] In some embodiments, the first width W1 may be greater than the second width W2. In some embodiments, the second width W2 may be greater than the third width W3. In some embodiments, the first width W1 may be greater than the second width W2 or the third width W3.

[0168] In some alternative embodiments, the third width W3 may be comparable to the second width W2 , and the second width W2 may be comparable to the first width W1 .

[0169] In some embodiments, a thickness ratio of the thickness h6 of the third supporting layer 109 to the thickness h4 of the bottom electrode 111 can be between about 3.0% and about 8.0% or between about 3.3% and about 7.5%. In some embodiments, the thickness h4 of the bottom electrode 111 can be in a range of 0.8 μm to about 1.2 μm.

[0170] Referring to Figure 29 The top material layer 108 can be removed and a second recess R2 can be formed using steps similar to those shown in Figure 15 , which are not repeated here.

[0171] Referring to Figure 30 The first material layer 105 and the second material layer 106 can be removed by a removal process. In some embodiments, the removal process can include applying NF3 and H2 over the first material layer 105 and the second material layer 106, with application of a plasma. Such a removal process can have a significantly greater etch rate for Si than for SiN, e.g., about 2000: 1. After the removal process is performed, the second support layer 107 can remain attached to the bottom electrode 111 and overhang the first support layer 104. In some embodiments, the etch chemistry enters via the second recess R2 shown in Figure 29 In some embodiments, the second support layer 107 can be connected to the second wall portion 111B and the first wall portion 111A of the bottom electrode 111. A top surface 104T of the first support layer 104 can be exposed. An empty space E2 can be formed between the first support layer 104 and the second support layer 107. An empty space E3 can be formed between the first wall portion 111A of the bottom electrode 111.

[0172] In summary, the first material layer 105, the second material layer 106, and the top material layer 108 are removed. The first support layer 104, the second support layer 107, the third support layer 109, and the bottom electrode 111 remain in place.

[0173] Referring to Figure 31 The dielectric layer 112 can be formed using steps similar to those shown in Figure 17 , which are not repeated here.

[0174] Referring to Figure 32 The dielectric layer 112 can be formed using steps similar to those shown in Figure 18The top electrode 113 is formed by the steps shown in the figure, and its description is not repeated here. After the top electrode 113 is formed, the first recess R1 can be defined by the top electrode 113. In some embodiments, the first recess R1 may include a lower portion P1", a middle portion P2", and an upper portion P3". In some embodiments, the first recess R1 may have a dimension D1' at the level of the lower portion P1", a dimension D2' at the level of the middle portion P2", and a dimension D3' at the level of the upper portion P3". In some embodiments, the dimension D1' may be greater than the dimension D2'. In some embodiments, the dimension D2' may be greater than the dimension D3'. In some embodiments, the dimension D1' may be greater than the dimension D2' or the dimension D3'. The dimensions D1', D2', and D3' are the maximum lateral widths of the empty space corresponding to the first recess R1.

[0175] In some embodiments, dimension D1 ′ may be comparable to dimension D2 ′, and dimension D2 ′ may be comparable to dimension D3 ′.

[0176] Reference Figure 33 , you can use something like Figure 19 The ground layer 114 is formed by the process shown in FIG. 1 , and its description is not repeated here.

[0177] One aspect of the present disclosure provides a semiconductor device comprising a substrate; a bottom electrode disposed on the substrate and comprising a container-shaped profile; and a top support layer overhanging the substrate and connected to the bottom electrode. A thickness ratio of the top support layer to a thickness of the bottom electrode is between approximately 3.0% and approximately 8.0%.

[0178] Another aspect of the present disclosure provides a semiconductor device comprising a substrate; a bottom electrode comprising a bottom portion located above the substrate and extending parallel to a top surface of the substrate, a first wall portion extending upward from the bottom portion, and a second wall portion extending upward from the bottom portion and away from the first wall portion; a first supporting layer located above the substrate and surrounding the first and second wall portions; a second supporting layer located above the first supporting layer and surrounding the first and second wall portions; and a third supporting layer located above the second supporting layer and surrounding the second wall portion. A thickness ratio of a thickness of the top supporting layer to a thickness of the bottom electrode is between approximately 3.0% and approximately 8.0%.

[0179] Yet another aspect of the present disclosure provides a method for preparing a semiconductor element, comprising: forming a landing area on a substrate; sequentially forming a first supporting layer, a first material layer, a second supporting layer, a top material layer, a third supporting layer, and a bottom mask layer on the landing area; forming a first recess, passing through the bottom mask layer, the third supporting layer, the top material layer, the second supporting layer, the first material layer, and the first supporting layer and exposing the landing area; conformally forming a bottom electrode material layer on the bottom mask layer and the first recess, forming a sacrificial material to fill the first recess, and performing a planarization process to expose the bottom mask layer; performing a first etching process to selectively remove the bottom mask layer; performing a second etching process to selectively remove the bottom electrode material layer above the third supporting layer to convert the bottom electrode material layer into a bottom electrode; and performing a third etching process to remove the sacrificial material. During the first etching process, an etching rate ratio of the bottom mask layer to the third supporting layer is greater than 1000. During the second etching process, an etching rate ratio of the bottom electrode material layer to the third supporting layer is greater than 100.

[0180] Due to the design of the semiconductor device disclosed herein, the high etch selectivity of the first and second etching processes can significantly reduce the consumption of the third supporting layer 109 (or top supporting layer). Therefore, the remaining thickness of the third supporting layer 109 can be increased. Consequently, the performance of the semiconductor device can be improved. Furthermore, by doping the different material layers 105, 106, and 108 with different dopants, the bottom of the first recess R1 can be widened. Consequently, the performance of the semiconductor device can be improved.

[0181] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations may be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the above processes may be implemented in different ways, and many of the above processes may be replaced by other processes or combinations thereof.

[0182] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machines, manufacture, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future developed processes, machines, manufacture, compositions of matter, means, methods, or steps that function the same as or achieve substantially the same results as the corresponding embodiments described herein may be used in accordance with this disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps are intended to be encompassed by the claims of this application.

Claims

1. A semiconductor device comprising: a substrate; a bottom electrode disposed on the substrate and comprising a container-shaped profile; as well as a top support layer overhanging the substrate and connected to the bottom electrode, A thickness ratio of a thickness of the top supporting layer to a thickness of the bottom electrode is between about 3.0% and about 8.0%.

2. The semiconductor device according to claim 1, wherein the bottom electrode comprises: a bottom portion positioned on the substrate and extending parallel to a top surface of the substrate; a first wall portion extending upwardly from the bottom portion; as well as A second wall portion extends upward from the bottom portion and away from the first wall portion. The semiconductor element as claimed in claim 2 , wherein the top supporting layer is connected to the second wall portion. 4 . The semiconductor device as claimed in claim 3 , wherein a top surface of the first wall portion is lower than a top surface of the second wall portion. 5 . The semiconductor device as claimed in claim 4 , wherein a dimension between the first wall portion and the second wall portion tapers toward the bottom portion. 6 . The semiconductor device as claimed in claim 1 , further comprising a bottom supporting layer located below and away from the top supporting layer, wherein the bottom supporting layer laterally surrounds the bottom electrode. 7 . The semiconductor device of claim 6 , further comprising a middle supporting layer located between the bottom supporting layer and the top supporting layer, wherein the middle supporting layer is away from both the bottom supporting layer and the top supporting layer and laterally surrounds the bottom electrode. 8 . The semiconductor device of claim 7 , further comprising a dielectric layer conformally covering the bottom electrode, the bottom supporting layer, the middle supporting layer, and the top supporting layer. 9 . The semiconductor device as claimed in claim 8 , further comprising a top electrode conformally covering the dielectric layer. 10 . The semiconductor device as claimed in claim 9 , further comprising a ground layer located on the top electrode.

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