High-power-density MOS power module application circuit

Abstract

The invention discloses a high-power-density MOS (Metal Oxide Semiconductor) power module application circuit. According to the invention, source electrode current data of each parallel MOS tube in the main power module is acquired in real time through a micro sampling resistor, and the source electrode current data is converted by the signal processing and transmission module and then is transmitted to a control chip of the driving and control module through an SPI interface. And after the control chip analyzes the current deviation, the driving adjustment execution module dynamically adjusts the grid voltage parameter of the driving chip, so that the problem of non-uniform current distribution caused by manufacturing difference or temperature change of MOS (Metal Oxide Semiconductor) tubes is effectively improved, and abnormal loss caused by long-term overload operation of individual devices is reduced. The service life of a core power device is directly prolonged by improving the current distribution uniformity; through the real-time adjustment of the dynamic current sharing module, the current shared by each MOS tube tends to be consistent, thereby avoiding the local overload phenomenon, reducing the damage risk of the device caused by unbalanced load, and reducing the frequency of maintenance or replacement of the module due to the device fault.

Description

Technical Field

[0001] The present invention belongs to the technical field of MOS module circuits, and in particular relates to a high power density MOS power module application circuit. Background Art

[0002] MOS power module application circuits are high-efficiency power conversion and control circuits based on metal oxide semiconductor field-effect transistors (MOSFETs). They are widely used in industrial automation, new energy, electric vehicles, power supplies, and motor drives. By integrating multiple MOSFET chips into a module, these circuits achieve precise control of current, voltage, and power. They offer advantages such as low on-resistance, fast switching speeds, minimal heat loss, and high reliability. MOS power modules typically include gate drive circuits, thermal management modules, and protection circuits, effectively improving overall system efficiency and stability. In practical applications, MOS power modules can implement various power conversion modes, such as AC / DC, DC / DC, and DC / AC, meeting high-performance requirements under various loads and operating conditions. With the introduction of wide-bandgap semiconductor materials (such as SiC and GaN), MOS power module application circuits are continuously evolving toward higher efficiency, smaller size, and improved thermal performance.

[0003] However, in the existing technology, the current distribution of parallel MOS tubes mainly relies on the consistency of the devices themselves and the matching of static parameters, and lacks a dynamic and real-time current detection and adjustment mechanism. This can easily lead to uneven current distribution due to manufacturing differences or temperature changes, causing some devices to be overloaded for a long time and accelerate aging. At the same time, it is difficult to quickly suppress abnormal current concentration when the load suddenly changes, affecting the operating stability of the power module. Summary of the Invention

[0004] The purpose of the present invention is to provide a high power density MOS power module application circuit in order to solve the above-mentioned problems.

[0005] The technical solution adopted by the present invention is as follows: a high power density MOS power module application circuit, comprising a circuit body, wherein a system body is arranged inside the circuit body; The system body includes: a main power module, a drive and control module, a dynamic current sharing module, an intelligent thermal management module, an input and output filter module and an auxiliary power supply module; The dynamic current sharing module is internally provided with a current signal acquisition module, a signal processing and transmission module, a control decision module and a drive adjustment execution module; The source control terminal of the main power module is connected to the driver chip of the drive and control module, the drain main terminal is connected to the output end of the input and output filter module, and the source main terminal is connected to the input end of the input and output filter module; The sampling resistor of the dynamic current balancing module is connected in series to the source of the MOS tube of the main power module, and the signal is transmitted to the control chip of the drive and control module, and the adjustment instruction is returned to the drive chip; The NTC of the intelligent thermal management module is connected to the main power module substrate, and the signal is transmitted to the control chip, and the heat dissipation component is controlled by the control chip output; The auxiliary power supply module supplies power to the drive and control module, the dynamic current sharing module, and the intelligent thermal management module; the two ends of the input and output filter modules are connected to the external power supply and the load respectively.

[0006] In a preferred embodiment, the main power module is internally equipped with a DBC substrate, SiC MOSFET array, source / drain copper foil, main terminals, and control terminals. The DBC substrate, made of highly thermally conductive material and ≤0.3mm thick, serves as the integrated carrier for the power devices. SiC MOSFETs are arranged in parallel on the substrate, with each group consisting of ≥4 SiC MOSFETs, each with an on-resistance ≤5mΩ and a withstand voltage of 1200V. The drain is connected to the substrate's drain copper foil, and the source is connected to the source copper foil. The source copper foil leads to the control terminal for transmitting small-signal control commands, while the drain copper foil leads to the main terminal, serving as a high-current input and output interface. The MOSFET body diode is directly used for freewheeling, reducing the number of external components.

[0007] In a preferred embodiment, the drive and control module is internally equipped with a high-frequency driver chip, a control chip, and a protection circuit. The high-frequency driver chip is a model that supports high-frequency switching, provides ±4A drive current, has a rise / fall time of <10ns, and is directly connected to the MOS transistor gate. The control chip uses a DSP with an integrated PWM generator, which can dynamically adjust the dead time to prevent bridge arm shoot-through. The protection circuit includes a Vds monitoring unit, a Vgs clamp circuit, overcurrent detection thresholds, and overtemperature detection thresholds, triggering the driver shutdown within 5μs in the event of an abnormality.

[0008] In a preferred embodiment, the current signal acquisition module is internally provided with a micro-sampling resistor and a high-precision differential op amp. The micro-sampling resistor is designed to be low-resistance, with a single resistor value of ≤1mΩ. It is connected in series with the source of each parallel MOS tube and converts the MOS tube's current signal into a voltage signal through the principle of resistor voltage division. The high-precision differential op amp uses a high common-mode rejection ratio model, such as the AD8210. Its function is to amplify the weak voltage signal output by the sampling resistor, with a gain design of ≥100 times. At the same time, the differential input structure effectively suppresses common-mode noise in the circuit, ensuring the accuracy of signal acquisition.

[0009] In a preferred embodiment, the signal processing and transmission module is internally provided with a low-pass filter, an analog-to-digital converter, and a communication interface. The cutoff frequency of the low-pass filter is set to 10kHz to filter out high-frequency noise such as di / dt interference generated during the high-frequency switching of the MOS tube, thereby avoiding signal distortion. The analog-to-digital converter uses a 16-bit high-precision model, such as the ADS8320, with a resolution of ≤0.1mV, which can convert the filtered analog voltage signal into a digital quantity for subsequent digital processing. The communication interface uses the SPI protocol with a communication rate of ≥10MHz, which is responsible for quickly transmitting the digital current signal after analog-to-digital conversion to the control chip to ensure real-time data.

[0010] In a preferred embodiment, the control decision module dynamically generates the current sharing adjustment instruction through real-time current data calculation and closed-loop control algorithm. The specific process is as follows: the control chip (such as DSP) synchronously reads the current values ​​I1, I2, ..., I of all parallel MOS tubes at a sampling frequency of 10kHz. n (n is the number of MOS tubes in parallel), first calculate the average current I of the current cycle avg =(I1+I2+…+I n ) / n, as the current sharing target; then for each MOS tube, calculate its current deviation e i =I i -I avg , and calculate the maximum absolute deviation e max =max{∣e1∣,∣e2∣,…,∣e n ∣}. If e max >5% I avg (i.e. triggering the current sharing adjustment threshold), the PI control algorithm is activated: the proportional link (P) quickly responds to the deviation, the integral link (I) eliminates the steady-state error, and the final output adjustment value Δui is used to correct the driving parameters of the i-th MOS tube (such as gate voltage or turn-on delay). The adjustment logic is: for e i >0 (large current) MOS tube, Δu i is negative (reduce gate voltage or increase delay); for e i <0 (small current) MOS tube, Δu i is positive (increase gate voltage or reduce delay), until e max ≤3% I avg Stop adjusting when The formula for precise regulation of dynamic current sharing by the PI control algorithm is: Where: Δu i (k) represents the drive adjustment value of the i-th MOS tube in the k-th control cycle (unit: V or ns); Kp Represents the proportionality coefficient (dimensionless), which determines the response speed to the current deviation; K i Indicates the integral coefficient (unit: V -1 ·s -1 or ns -1 ·s -1 ), used to eliminate steady-state errors; e i (k) represents the current deviation of the i-th MOS tube in the k-th cycle (e i (k)=I i (k)-I avg (k), unit: A); T s Control period (i.e. sampling interval, here 0.1ms).

[0011] In a preferred embodiment, the drive adjustment execution module (12) is internally provided with a drive chip, a digital-to-analog converter, and a parameter adjustment unit. The drive chip is a high-frequency drive model, such as UCC27714, and its function is to receive the adjustment instruction output by the control chip and transmit the instruction to the digital-to-analog converter. The digital-to-analog converter converts the digital adjustment instruction into an analog signal for adjusting the drive parameters of the MOS tube. The parameter adjustment unit includes a gate voltage adjustment circuit and a delay adjustment circuit. The gate voltage adjustment range is ±0.5V, and the conduction capability of the MOS tube can be adjusted by changing the gate drive voltage; the delay adjustment range is ±20ns, and the turn-on time of the MOS tube can be changed by adjusting the turn-on delay time. In terms of current deviation, if the current of a MOS tube is too large, the parameter adjustment unit is used to reduce its gate voltage or increase the turn-on delay; if the current is too small, the gate voltage is increased or the turn-on delay is reduced to achieve current balance.

[0012] In a preferred embodiment, the intelligent thermal management module is internally equipped with an NTC thermistor, a double-sided liquid cooling radiator, a liquid cooling pump, and a fan. The NTC thermistors, with a response time of <100ms, are located in key locations on the DBC substrate, such as below the MOS transistors and at the edge of the copper foil. They monitor the module's temperature in real time. The double-sided liquid cooling radiator consists of microchannels on its upper and lower surfaces, with a channel width of 0.5mm and a spacing of 1mm. The cooling medium is deionized water. The liquid cooling pump has an adjustable speed, regulating the cooling medium flow rate. The fan works in conjunction with the liquid cooling system, with its speed varying with temperature demand. Temperature data is transmitted via wires to the control chip, which serves as a basis for adjusting the cooling strategy.

[0013] In a preferred embodiment, the input / output filter module is internally equipped with an input-side capacitor bank, an output-side inductor and capacitor bank, and an optimized wiring structure. The input-side capacitor bank consists of low-ESR ceramic capacitors in parallel with aluminum electrolytic capacitors to suppress input voltage ripple; the output-side inductor and capacitor bank includes a high-frequency inductor and film capacitor in series to filter out switching frequency multiplication noise. The optimized wiring structure physically separates the input / output terminals, with vertical wiring of the power and control circuits to reduce electromagnetic coupling interference.

[0014] In a preferred embodiment, the auxiliary power module is internally equipped with a flyback switching power supply, multiple isolated outputs, and protection circuitry. The flyback switching power supply input is 48V, which is converted to multiple low-voltage power supplies via a high-frequency transformer. The multiple isolated outputs utilize independent windings to ensure that each power supply circuit does not interfere with each other. The protection circuitry includes overcurrent protection and undervoltage lockout, automatically shutting off the output to protect downstream circuits when the input voltage fluctuates or the load current is abnormal.

[0015] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are: 1. In this invention, a micro-sampling resistor collects real-time source current data from each parallel-connected MOS transistor in the main power module. After conversion by a signal processing and transmission module, the data is transmitted to the control chip of the drive and control module via an SPI interface. After the control chip analyzes the current deviation, the drive adjustment execution module dynamically adjusts the gate voltage parameters of the driver chip. This effectively improves the uneven current distribution caused by MOS transistor manufacturing variations or temperature changes, significantly improves the current distribution uniformity of multiple parallel MOS transistors, and reduces the abnormal loss of individual devices caused by long-term overload operation.

[0016] 2. In this invention, the improved current distribution uniformity directly extends the service life of core power devices. Without the dynamic current balancing module, some MOS transistors would bear higher loads due to current concentration, which could accelerate aging and even premature failure. With the real-time adjustment of the dynamic current balancing module, the current shared by each MOS transistor tends to be consistent, avoiding local overloads and reducing the risk of device damage caused by uneven loads, thereby reducing the frequency of module repair or replacement due to device failures.

[0017] 3. In this invention, the real-time adjustment capability of the dynamic current balancing module enhances the operational stability of the power module under different operating conditions. When the load changes suddenly, the current of each MOS tube will fluctuate instantaneously. The dynamic current balancing module can quickly detect the current deviation and adjust the drive parameters to suppress abnormal current concentration. Under different operating conditions such as light load and heavy load, it can also balance the current distribution by continuously optimizing the drive parameters, reducing the additional losses caused by current imbalance, and ensuring the stable operation of the module under various operating conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a schematic diagram of the main structure of the circuit of the present invention; Figure 2 This is a block diagram of the main system of the present invention; Figure 3 This is a system block diagram of the dynamic current sharing module in the present invention.

[0019] Markings in the figure: 1-circuit main body, 2-system main body, 3-main power module, 4-drive and control module, 5-dynamic current sharing module, 6-intelligent thermal management module, 7-input and output filtering module, 8-auxiliary power supply module, 9-current signal acquisition module, 10-signal processing and transmission module, 11-control decision module, 12-drive adjustment execution module. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0021] Reference Figure 1-3 A high power density MOS power module application circuit includes a circuit body 1, wherein a system body 2 is provided inside the circuit body 1; The system body 2 includes: a main power module 3, a drive and control module 4, a dynamic current sharing module 5, an intelligent thermal management module 6, an input and output filter module 7 and an auxiliary power supply module 8; The dynamic current sharing module 5 is internally provided with a current signal acquisition module 9, a signal processing and transmission module 10, a control decision module 11 and a drive adjustment execution module 12; The source copper foil control terminal of the main power module 3 is connected to the gate output terminal of the high-frequency driver chip of the drive and control module 4 through a wire. The drain main terminal is directly electrically connected to the input terminal of the output-side inductor and capacitor group of the input-output filter module 7. The source main terminal is connected to the output terminal of the input-side capacitor group of the input-output filter module 7. The micro sampling resistor of the current signal acquisition module of the dynamic current balancing module 5 is connected in series between the source and source copper foil of the parallel MOS tube of the main power module 3. The SPI communication interface of the signal processing and transmission module is connected to the SPI input pin of the control chip of the drive and control module 4 through a data line. The output end of the digital-to-analog converter of the drive adjustment execution module is connected to the gate voltage adjustment input pin of the high-frequency drive chip of the drive and control module 4 through a signal line. The NTC thermistor signal output line of the intelligent thermal management module 6 is soldered to the bottom of the MOS tube and the edge of the copper foil of the DBC substrate in the main power module 3. The other end of the signal transmission line is connected to the analog input pin of the control chip of the drive and control module 4. The control signal line of the liquid cooling pump and fan is connected to the PWM output pin of the control chip of the drive and control module 4. The 3.3V output end of the auxiliary power supply module 8 is connected to the power supply pin of the control chip of the drive and control module 4 and the power supply pin of the dynamic current equalizing module 5 control decision module DSP, the 5V output end is connected to the power supply pin of the signal processing and transmission module ADC of the dynamic current equalizing module 5 and the power supply pin of the NTC signal conditioning circuit in the intelligent thermal management module 6, and the 15V output end is connected to the power supply pin of the high-frequency drive chip of the drive and control module 4 and the power supply pin of the digital-to-analog converter of the drive adjustment execution module of the dynamic current equalizing module 5; the input end of the input side capacitor group of the input and output filter module 7 is connected to the external power bus, and the output end of the output side inductor and capacitor group is connected to the load bus.

[0022] The main power module 3 is internally equipped with a DBC substrate, SiC MOSFET array, source / drain copper foil, main terminals, and control terminals. The DBC substrate, made of highly thermally conductive material and ≤0.3mm thick, serves as the integrated carrier for the power devices. SiC MOSFETs are arranged in parallel on the substrate, with each group consisting of ≥4 SiC MOSFETs. Each SiC MOSFET has an on-resistance of ≤5mΩ and a withstand voltage of 1200V. The drain is connected to the substrate's drain copper foil, and the source is connected to the source copper foil. The source copper foil leads to the control terminal for transmitting small-signal control commands, while the drain copper foil leads to the main terminal, serving as a high-current input and output interface. The MOSFET body diode is directly used for freewheeling, reducing the number of external components.

[0023] The drive and control module 4 houses a high-frequency driver chip, a control chip, and a protection circuit. The high-frequency driver chip, a model that supports high-frequency switching, provides ±4A drive current, rise / fall times <10ns, and is directly connected to the MOS transistor gate. The control chip utilizes a DSP with an integrated PWM generator, dynamically adjusting the dead time to prevent bridge arm shoot-through. The protection circuit includes a Vds monitoring unit, a Vgs clamping circuit, overcurrent detection thresholds, and overtemperature detection thresholds. In the event of an abnormality, the driver shuts down within 5μs.

[0024] The current signal acquisition module 9 is internally equipped with a micro-sampling resistor and a high-precision differential op amp. The micro-sampling resistor is designed to be low-resistance, with a single resistor value of ≤1mΩ. It is connected in series with the source of each parallel MOS transistor and converts the MOS transistor's current signal into a voltage signal through the principle of resistor voltage division. The high-precision differential op amp, using a high common-mode rejection ratio (CMRR) model such as the AD8210, amplifies the weak voltage signal output by the sampling resistor. Its gain is designed to be ≥100x. Its differential input structure effectively suppresses common-mode noise in the circuit, ensuring accurate signal acquisition.

[0025] The signal processing and transmission module 10 is internally equipped with a low-pass filter, an analog-to-digital converter, and a communication interface. The low-pass filter has a cutoff frequency of 10kHz, which is used to filter out high-frequency noise such as di / dt interference generated during the high-frequency switching of the MOS tube to prevent signal distortion. The analog-to-digital converter uses a 16-bit high-precision model, such as the ADS8320, with a resolution of ≤0.1mV. It can convert the filtered analog voltage signal into a digital quantity for subsequent digital processing. The communication interface uses the SPI protocol with a communication rate of ≥10MHz. It is responsible for quickly transmitting the digital current signal after analog-to-digital conversion to the control chip to ensure real-time data.

[0026] The control decision module 11 dynamically generates the current sharing adjustment instruction through real-time current data calculation and closed-loop control algorithm. The specific process is as follows: the control chip synchronously reads the current values ​​I1, I2, ..., I of all parallel MOS tubes at a sampling frequency of 10kHz. n , first calculate the average current I of the current cycle avg =(I1+I2+…+I n ) / n, as the current sharing target; then for each MOS tube, calculate its current deviation e i =I i -I avg , and calculate the maximum absolute deviation e max =max{∣e1∣,∣e2∣,…,∣e n ∣}. If e max >5% I avg , then the PI control algorithm is started: the proportional link quickly responds to the deviation, the integral link eliminates the steady-state error, and the final output adjustment value Δui is used to correct the driving parameters of the i-th MOS tube. The adjustment logic is: for e i MOS tube >0, Δu i is negative; for e i MOS tube <0, Δu i is positive until e max ≤3% I avg Stop adjusting when The formula for precise regulation of dynamic current sharing by the PI control algorithm is: Where: Δu i (k) represents the driving adjustment value of the i-th MOS tube in the k-th control cycle; K p Represents the proportional coefficient, which determines the response speed to the current deviation; K i Represents the integral coefficient, which is used to eliminate steady-state errors; e i (k) represents the current deviation of the i-th MOS tube in the k-th cycle; T s Control cycle.

[0027] The drive adjustment execution module 12 is internally equipped with a driver chip, a digital-to-analog converter, and a parameter adjustment unit. The driver chip uses a high-frequency driver model, such as the UCC27714. Its function is to receive adjustment instructions output by the control chip and pass the instructions to the digital-to-analog converter. The digital-to-analog converter converts the digital adjustment instructions into analog signals, which are used to adjust the drive parameters of the MOS tube. The parameter adjustment unit includes a gate voltage adjustment circuit and a delay adjustment circuit. The gate voltage adjustment range is ±0.5V, which can adjust the conduction capability of the MOS tube by changing the gate drive voltage; the delay adjustment range is ±20ns, which can change the turn-on time of the MOS tube by adjusting the turn-on delay time. In response to current deviation, if the current of a MOS tube is too high, the parameter adjustment unit reduces its gate voltage or increases the turn-on delay; if the current is too low, the gate voltage is increased or the turn-on delay is reduced to achieve current balance.

[0028] Intelligent thermal management module 6 is equipped with an NTC thermistor, a double-sided liquid cooling radiator, a liquid cooling pump, and a fan. The NTC thermistors, with a response time of less than 100ms, are located in key locations on the DBC substrate, such as below the MOS transistors and at the edge of the copper foil. They monitor module temperature in real time. The double-sided liquid cooling radiator consists of microchannels on the upper and lower surfaces, with a channel width of 0.5mm and a spacing of 1mm. The cooling medium is deionized water. The liquid cooling pump has an adjustable speed, regulating the cooling medium flow. The fan works in conjunction with the liquid cooling system, with its speed varying with temperature demand. Temperature data is transmitted via wires to the control chip, which serves as a basis for adjusting the cooling strategy.

[0029] The input / output filter module 7 is internally equipped with an input-side capacitor bank, an output-side inductor and capacitor bank, and an optimized wiring structure. The input-side capacitor bank consists of low-ESR ceramic capacitors in parallel with aluminum electrolytic capacitors to suppress input voltage ripple. The output-side inductor and capacitor bank consists of a high-frequency inductor and a film capacitor in series to filter out switching frequency multiplication noise. The optimized wiring structure physically separates the input / output terminals, and the power circuit and control circuit are wired vertically to reduce electromagnetic coupling interference.

[0030] The auxiliary power module 8 houses a flyback switching power supply, multiple isolated outputs, and protection circuitry. The flyback switching power supply takes a 48V input, which is converted to multiple low-voltage power supplies via a high-frequency transformer. The multiple isolated outputs utilize independent windings to ensure that each power supply circuit does not interfere with each other. The protection circuitry includes overcurrent protection and undervoltage lockout, automatically shutting off the output to protect downstream circuitry when the input voltage fluctuates or the load current is abnormal.

[0031] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprises" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also other elements that are not explicitly listed, or also includes elements that are inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device that includes the element.

[0032] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A high power density MOS power module application circuit, characterized by: It comprises a circuit main body (1), wherein a system main body (2) is arranged inside the circuit main body (1); The system body (2) includes: a main power module (3), a drive and control module (4), a dynamic current sharing module (5), an intelligent thermal management module (6), an input and output filter module (7) and an auxiliary power supply module (8); The dynamic current balancing module (5) is internally provided with a current signal acquisition module (9), a signal processing and transmission module (10), a control decision module (11) and a drive adjustment execution module (12); The source control terminal of the main power module (3) is connected to the driver chip of the drive and control module (4), the drain main terminal is connected to the output end of the input / output filter module (7), and the source main terminal is connected to the input end of the input / output filter module (7); The sampling resistor of the dynamic current balancing module (5) is connected in series to the source of the MOS tube of the main power module (3), and the signal is transmitted to the control chip of the driving and control module (4), and the adjustment instruction is sent back to the driving chip; The NTC of the intelligent thermal management module (6) is connected to the main power module (3) substrate, and the signal is transmitted to the control chip, and the heat dissipation component is controlled by the output of the control chip; The auxiliary power supply module (8) supplies power to the drive and control module (4), the dynamic current sharing module (5), and the intelligent thermal management module (6); and the two ends of the input and output filter module (7) are connected to an external power supply and a load, respectively.

2. The high power density MOS power module application circuit according to claim 1, wherein: The main power module (3) is internally provided with a DBC substrate, a SiC MOSFET array, a source / drain copper foil, a main terminal and a control terminal.

3. The high power density MOS power module application circuit according to claim 1, wherein: The driving and control module (4) is internally provided with a high-frequency driving chip, a control chip, and a protection circuit.

4. The high power density MOS power module application circuit according to claim 1, wherein: The current signal acquisition module (9) is internally provided with a micro sampling resistor and a high-precision differential operational amplifier.

5. The high power density MOS power module application circuit according to claim 1, wherein: The signal processing and transmission module (10) is internally provided with a low-pass filter, an analog-to-digital converter, and a communication interface.

6. The high power density MOS power module application circuit according to claim 1, wherein: The control decision module (11) dynamically generates a current sharing adjustment instruction through real-time current data calculation and a closed-loop control algorithm. The formula for the precise adjustment of the dynamic current sharing by the PI control algorithm of the control decision module (11) is: Where: Δu i (k) represents the drive adjustment value of the i-th MOS tube in the k-th control cycle (unit: V or ns); K p Represents the proportional coefficient, which determines the response speed to the current deviation; K i Indicates the integral coefficient, unit: V -1 ·s -1 or ns -1 ·s -1 , used to eliminate steady-state errors; e i (k) represents the current deviation of the i-th MOS tube in the k-th cycle, e i (k) = I i (k)-I avg (k), unit: A; T s The control period, that is, the sampling interval, is 0.1ms here.

7. The high power density MOS power module application circuit according to claim 1, characterized in that: The drive adjustment execution module (12) is internally provided with a drive chip, a digital-to-analog converter, and a parameter adjustment unit.

8. The high power density MOS power module application circuit according to claim 1, wherein: The intelligent thermal management module (6) is internally provided with an NTC thermistor, a double-sided liquid cooling radiator, a liquid cooling pump, and a fan.

9. The high power density MOS power module application circuit according to claim 1, wherein: The input-output filter module (7) is internally provided with an input-side capacitor group, an output-side inductor-capacitor group, and an optimized wiring structure.

10. The high power density MOS power module application circuit according to claim 1, characterized in that: The auxiliary power supply module (8) is internally provided with a flyback switching power supply, multi-channel isolation outputs, and a protection circuit.

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