High-temperature-stability band-gap reference circuit with full MOS (Metal Oxide Semiconductor) structure

Abstract

The invention provides a high-temperature stability band-gap reference circuit of a full MOS structure. The circuit is applied to the field of integrated circuit design and comprises a negative temperature coefficient voltage generation circuit and a positive temperature coefficient current / voltage generation circuit which are connected. The negative temperature coefficient voltage generating circuit comprises a first MOS (Metal Oxide Semiconductor) tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube and a sixth MOS tube; the first MOS tube, the second MOS tube, the third MOS tube, the fourth MOS tube, the fifth MOS tube and the sixth MOS tube work in a sub-threshold region; the positive temperature coefficient current / voltage generating circuit comprises a differential pair module, a first resistor, a second resistor, a current mirror module and a high-gain operational amplifier, the differential pair module comprises a tenth MOS transistor and an eleventh MOS transistor, and the current mirror module comprises a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a fourteenth MOS transistor and a fifteenth MOS transistor. The temperature stability is improved; and the static power consumption is reduced.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to a high-temperature-stability bandgap reference circuit with a full-MOS structure. Background Art

[0002] Bandgap reference (BGR) circuits play a crucial role in analog and mixed-signal integrated circuit design. They provide a highly stable DC voltage over a wide temperature range, power supply voltage fluctuations, and process variations. They are essential for the proper operation of functional modules such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), phase-locked loops (PLLs), and various low-dropout (LDO) voltage regulators. The commonly known principle for achieving temperature-independence is to compensate for the negative temperature coefficient (CTAT) and the positive temperature coefficient (PTAT) by appropriately weighting their summation. The ideal output voltage, VREF, can be expressed as VREF = VCTAT + K* VPTAT, where K is a constant. When the temperature drift of VCTAT and VPTAT is precisely offset, VREF theoretically achieves zero temperature coefficient.

[0003] In existing technology, the most mature and widely adopted solution is to use bipolar junction transistors (BJTs). The CTAT voltage is typically directly derived from the BJT's base-emitter voltage, VBE. VBE has an excellent, predictable, and linear negative temperature coefficient. The PTAT voltage is typically generated by the base-emitter voltage difference (ΔVBE) between two BJTs operating at different current densities. ΔVBE is naturally proportional to absolute temperature.

[0004] Although this traditional BJT-based bandgap reference circuit can achieve high precision, it has the following inherent and difficult-to-overcome defects: 1. Poor process compatibility and high cost: The standard digital CMOS process flow does not include high-quality BJTs. In order to integrate BJTs, a more complex BiCMOS process with more photolithography masks must be used, which significantly increases the manufacturing cost and design complexity of the chip. If the inherent parasitic BJT is used in the standard CMOS process, its performance (such as the current gain β value) is often poor and consistency is difficult to guarantee. 2. High power consumption: As a current-driven device, the BJT requires a relatively considerable base current and collector quiescent current for normal operation, which makes the overall power consumption of the traditional BJT bandgap reference circuit difficult to meet the stringent requirements of current portable devices, Internet of Things devices, and other ultra-low power applications.

[0005] Therefore, how to design a bandgap reference circuit with simple structure, ultra-low power consumption and high precision (low temperature drift) characteristics under standard and low-cost CMOS process is a technical problem to be solved in the field. SUMMARY

[0006] To solve the above technical problems, the application provides a full-MOS-structure high-temperature-stability bandgap reference circuit, which comprises a negative temperature coefficient voltage generating circuit and a positive temperature coefficient current / voltage generating circuit, and the negative temperature coefficient voltage generating circuit and the positive temperature coefficient voltage generating circuit are connected.

[0007] The negative temperature coefficient voltage generating circuit comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube and a sixth MOS tube, and the first MOS tube, the second MOS tube, the third MOS tube, the fourth MOS tube, the fifth MOS tube and the sixth MOS tube work in a sub-threshold region.

[0008] The positive temperature coefficient current / voltage generating circuit comprises a differential pair module, a first resistor, a second resistor, a current mirror module and a high-gain operational amplifier, the differential pair module comprises a tenth MOS tube and an eleventh MOS tube, and the current mirror module comprises a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a fourteenth MOS tube and a fifteenth MOS tube.

[0009] Optionally, the source of the first MOS tube is connected with the gate of the second MOS tube, the drain and the gate of the first MOS tube are grounded, the source of the second MOS tube is connected with the source of the third MOS tube, the drain of the second MOS tube is connected with the drain of the fourth MOS tube, the drain of the third MOS tube is connected with the drain of the fifth MOS tube, the source of the fourth MOS tube is grounded, the gate of the fourth MOS tube is connected with the gate of the fifth MOS tube, the source of the fifth MOS tube is connected with the drain of the sixth MOS tube, the gate of the sixth MOS tube is connected with the drain of the sixth MOS tube, and the source of the sixth MOS tube is grounded.

[0010] Optionally, the source of the seventh MOS is connected to a power supply voltage, the gate of the seventh MOS is connected to the gate of the fourteenth MOS and the gate of the fifteenth MOS, the drain of the seventh MOS is connected to the drain of the eighth MOS, the gate of the eighth MOS is connected to the gate of the ninth MOS, the source of the eighth MOS is grounded, the drain of the ninth MOS is connected to the gate of the twelfth MOS, the source of the ninth MOS is grounded, the source of the tenth MOS is connected to the source of the eleventh MOS, the gate of the tenth MOS is connected to the gate of the third MOS, the drain of the tenth MOS is connected to the drain of the twelfth MOS, the gate of the twelfth MOS is connected to the gate of the thirteenth MOS, the source of the twelfth MOS is grounded, the drain of the eleventh MOS is connected to the drain of the thirteenth MOS, the source of the thirteenth MOS is grounded, the gate of the eleventh MOS is connected to the positive input of the high-gain operational amplifier, the source of the fourteenth MOS is connected to a power supply voltage, the drain of the fourteenth MOS is connected to the source of the tenth MOS and the source of the eleventh MOS, the source of the fifteenth MOS is connected to a power supply voltage, the drain of the fifteenth MOS is connected to the source of the sixteenth MOS, the drain of the sixteenth MOS is connected to the first end of the first resistor, the second end of the first resistor is connected to the negative input of the high-gain operational amplifier, the first end of the second resistor is connected to the first end of the first resistor, and the second end of the second resistor is grounded.

[0011] Optionally, the high-gain operational amplifier comprises a seventeenth MOS, an eighteenth MOS, a nineteenth MOS, a twentieth MOS, a twenty-first MOS, a twenty-second MOS, a twenty-third MOS, a twenty-fourth MOS, a twenty-fifth MOS, a twenty-sixth MOS, and a first capacitor.

[0012] Optionally, the source of the seventeenth MOS is connected to a power supply voltage, the drain of the seventeenth MOS is connected to the source of the twenty-second MOS, the source of the eighteenth MOS is connected to a power supply voltage, the drain of the eighteenth MOS is connected to the source of the twenty-first MOS, the source of the nineteenth MOS is connected to a power supply voltage, the gate of the nineteenth MOS is connected to the gate of the twentieth MOS, the drain of the nineteenth MOS is connected to the drain of the twenty-first MOS, the source of the twentieth MOS is connected to a power supply voltage, the drain of the twentieth MOS is connected to the drain of the twenty-second MOS, the gate of the twenty-first MOS is connected to the gate of the twenty-second MOS, the source of the twenty-first MOS is connected to the drain of the twenty-third MOS, the source of the twenty-second MOS is connected to the drain of the twenty-fourth MOS, the gate of the twenty-third MOS is connected to the gate of the twenty-fourth MOS, the source of the twenty-third MOS is connected to ground, the source of the twenty-fourth MOS is connected to ground, the source of the twenty-fifth MOS is connected to a power supply voltage, the gate of the twenty-fifth MOS is connected to the drain of the twentieth MOS and the drain of the twenty-second MOS, the drain of the twenty-fifth MOS is connected to the drain of the twenty-sixth MOS, the source of the twenty-sixth MOS is connected to ground, the first end of the first capacitor is connected to the gate of the twenty-fifth MOS, and the second end of the first capacitor is connected to the drain of the twenty-fifth MOS.

[0013] Optionally, in the sub-threshold region, the drain current of the MOS satisfies the following formula:

[0014]

[0015] wherein, is the drain current, is the gate-source voltage, is the ratio of the channel width to the channel length of the MOS, , is the ideal factor, is the electron mobility or the hole mobility, is the unit-area gate-oxide capacitance, is the thermal voltage, is the Boltzmann constant, is the absolute temperature, is the electron charge.

[0016] The application provides a high-temperature stability bandgap reference circuit of a full MOS structure, which comprises a negative temperature coefficient voltage generating circuit and a positive temperature coefficient current / voltage generating circuit, and the negative temperature coefficient voltage generating circuit and the positive temperature coefficient voltage generating circuit are connected; the negative temperature coefficient voltage generating circuit comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube and a sixth MOS tube, and the first MOS tube, the second MOS tube, the third MOS tube, the fourth MOS tube, the fifth MOS tube and the sixth MOS tube work in a sub-threshold region; the positive temperature coefficient current / voltage generating circuit comprises a differential pair module, a first resistor, a second resistor, a current mirror module and a high-gain operational amplifier, the differential pair module comprises a tenth MOS tube and an eleventh MOS tube, and the current mirror module comprises a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a fourteenth MOS tube and a fifteenth MOS tube. The bandgap reference circuit improves the temperature stability of a system and reduces static power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0017] The drawings incorporated in and forming a part of the specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the application.

[0018] Figure 1 A high-temperature stability bandgap reference circuit of a full MOS structure provided by the embodiment of the application;

[0019] Figure 2 A high-gain operational amplifier provided by the embodiment of the application;

[0020] Figure 3 A change trend graph of a reference voltage of the bandgap reference circuit provided by the embodiment of the application in a temperature range of-40°C to 100°C;

[0021] Figure 4 A total current consumption graph of the bandgap reference circuit provided by the embodiment of the application in a temperature range of-40°C to 100°C;

[0022] Figure 5 A characteristic graph of an output reference voltage changing with a power supply voltage provided by the embodiment of the application;

[0023] Figure 6 A relationship graph of a static current changing with a power supply voltage provided by the embodiment of the application.

[0024] Through the above drawings, the specific embodiments of the application have been shown, and will be described in more detail hereinafter. The drawings and the written description are not intended to limit the scope of the concept of the application in any way, but to illustrate the concept of the application for those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application and the manner how the technical solutions solve the above technical problems will be described in detail below with specific embodiments. The specific embodiments below can be combined with each other, and the same or similar concepts or processes can not be described repeatedly in some embodiments. The embodiments of the present application will be described below with reference to the drawings.

[0026] The terms "first", "second", "third", "fourth" and the like in the description, claims, and drawings of the present application, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the use of the terms so termed is interchangeable under appropriate circumstances such that the embodiments of the application described herein are, for example, capable of orderly execution or performance with variations in the sequence of operations or with the addition or omission of intermediate operations.

[0027] In the embodiments of the present application, the words "exemplary" and "for example" are used to mean serving as an example, instance, or illustration, at 5 2 least. Any implementation described herein as "exemplary" or "for example" is not necessarily to be construed as preferred or advantageous over other implementations. The

[0028] The technical solutions in the embodiments of the present application and the manner how the technical solutions solve the above technical problems will be described in detail below with specific embodiments. The specific embodiments below can be combined with each other, and the same or similar concepts or processes can not be described repeatedly in some embodiments. The embodiments of the present application will be described below with reference to the drawings.

[0029] Figure 1 A schematic diagram of a high-temperature-stability bandgap reference circuit with full-MOS structure according to an embodiment of the present application is shown in FIG. 1, which includes a negative-temperature-coefficient voltage generating circuit and a positive-temperature-coefficient current / voltage generating circuit, and the negative-temperature-coefficient voltage generating circuit and the positive-temperature-coefficient voltage generating circuit are connected. Figure 1 The negative-temperature-coefficient voltage generating circuit includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, and a sixth MOS transistor M6, wherein the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5, and the sixth MOS transistor M6 work in a sub-threshold region.

[0030] The negative-temperature-coefficient voltage generating circuit includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, and a sixth MOS transistor M6, wherein the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5, and the sixth MOS transistor M6 work in a sub-threshold region.

[0031] Specifically, the source of the first MOS transistor M1 is connected with the gate of the second MOS transistor M2, the drain and the gate of the first MOS transistor M1 are grounded, the source of the second MOS transistor M2 and the source of the third MOS transistor M3 are connected, the drain of the second MOS transistor M2 and the drain of the fourth MOS transistor M4 are connected, the drain of the third MOS transistor M3 and the drain of the fifth MOS transistor M5 are connected, the source of the fourth MOS transistor M4 is grounded, the gate of the fourth MOS transistor M4 and the gate of the fifth MOS transistor M5 are connected, the source of the fifth MOS transistor M5 and the drain of the sixth MOS transistor M6 are connected, the gate of the sixth MOS transistor M6 and the drain of the sixth MOS transistor M6 are connected, and the source of the sixth MOS transistor M6 is grounded.

[0032] It can be understood that the negative temperature coefficient voltage generating circuit utilizes the exponential I-V characteristic of the sub-threshold region MOS transistor to realize the high linearity and negative temperature coefficient CTAT voltage output. The working principle is as follows:

[0033] In the sub-threshold region, the relationship between the drain current of the MOS transistor and the gate-source voltage is:

[0034]

[0035] wherein, is the drain current, is the gate-source voltage, is the ratio of the channel width to the channel length of the MOS transistor, , is the ideal factor, is the electron mobility or the hole mobility, is the unit area gate oxide layer capacitance, is the thermal voltage, is the Boltzmann constant, is the absolute temperature, is the electronic charge. From the above formula, it can be obtained that:

[0036]

[0037] Therefore, Figure 1 VOUT1 in the above formula is:

[0038]

[0039] wherein, is the gate voltage of M2, and are the gate-source voltages of M2 and M3 respectively, and from the above formula, it can be obtained that:

[0040]

[0041] wherein, is the drain current of M1, the drain current of M2, the ratio of channel width to channel length of M1, the ratio of channel width to channel length of M2.

[0042] According to Kirchhoff's voltage law, we have:

[0043]

[0044] where, the gate-source voltage of M4, the gate-source voltage of M5, the gate-source voltage of M6.

[0045] Thus we have:

[0046]

[0047] where, the drain current of M4, the drain current of M5, the drain current of M6, the ratio of channel width to channel length of M4, the ratio of channel width to channel length of M5, the ratio of channel width to channel length of M6.

[0048] Simplifying, we have:

[0049]

[0050] Since , we assume is very small, the drain current of M5 is:

[0051]

[0052] where, the bias current, , The coefficient is a quadratic function of temperature. As the temperature rises, the drain current and significantly increase, and because , decreases. The increase of and the decrease of result in a significant drop in output voltage, so VOUT1 has a CTAT characteristic without using any BJT transistor.

[0053] The positive temperature coefficient current / voltage generating circuit comprises a differential pair module, a first resistor R1, a second resistor R2, a current mirror module and a high-gain operational amplifier, the differential pair module comprises a tenth MOS transistor M10 and an eleventh MOS transistor M11, and the current mirror module comprises a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, a fourteenth MOS transistor M14 and a fifteenth MOS transistor M15.

[0054] Specifically, the source of the seventh MOS transistor M7 is connected to a power supply voltage, the gate of the seventh MOS transistor M7 is connected to the gate of the fourteenth MOS transistor M14 and the gate of the fifteenth MOS transistor M15, the drain of the seventh MOS transistor M7 is connected to the drain of the eighth MOS transistor M8, the gate of the eighth MOS transistor M8 is connected to the gate of the ninth MOS transistor M9, the source of the eighth MOS transistor M8 is grounded, the drain of the ninth MOS transistor M9 is connected to the gate of the twelfth MOS transistor M12, the source of the ninth MOS transistor M9 is grounded, the source of the tenth MOS transistor M10 is connected to the source of the eleventh MOS transistor M11, the gate of the tenth MOS transistor M10 is connected to the gate of the third MOS transistor M3, the drain of the tenth MOS transistor M10 is connected to the drain of the twelfth MOS transistor M12, the gate of the twelfth MOS transistor M12 is connected to the gate of the thirteenth MOS transistor M13, the source of the twelfth MOS transistor M12 is grounded, the drain of the eleventh MOS transistor M11 is connected to the drain of the thirteenth MOS transistor M13, the source of the thirteenth MOS transistor M13 is grounded, the gate of the eleventh MOS transistor M11 is connected to the positive input terminal of the high-gain operational amplifier A1, the source of the fourteenth MOS transistor M14 is connected to the power supply voltage, the drain of the fourteenth MOS transistor M14 is connected to the source of the tenth MOS transistor M10 and the source of the eleventh MOS transistor M11, the source of the fifteenth MOS transistor M15 is connected to the power supply voltage, the drain of the fifteenth MOS transistor M15 is connected to the source of the sixteenth MOS transistor M16, the drain of the sixteenth MOS transistor M16 is connected to the first end of the first resistor R1, the second end of the first resistor R1 is connected to the negative input terminal of the high-gain operational amplifier A1, the first end of the second resistor R2 is connected to the first end of the first resistor R1, and the second end of the second resistor R2 is grounded.

[0055] Figure 2 A high-gain operational amplifier schematic diagram provided for the embodiment of the application is shown in Figure 2 The high-gain operational amplifier A1 comprises a seventeenth MOS transistor M17, an eighteenth MOS transistor M18, a nineteenth MOS transistor M19, a twentieth MOS transistor M20, a twenty-first MOS transistor M21, a twenty-second MOS transistor M22, a twenty-third MOS transistor M23, a twenty-fourth MOS transistor M24, a twenty-fifth MOS transistor M25, a twenty-sixth MOS transistor M26 and a first capacitor C1.

[0056] The source of the seventeenth MOS transistor M17 is connected to the power supply voltage, the drain of the seventeenth MOS transistor M17 is connected to the source of the twenty-second MOS transistor M22, the source of the eighteenth MOS transistor M18 is connected to the power supply voltage, the drain of the eighteenth MOS transistor M18 is connected to the source of the twenty-first MOS transistor M21, the source of the nineteenth MOS transistor M19 is connected to the power supply voltage, the gate of the nineteenth MOS transistor M19 is connected to the gate of the twentieth MOS transistor M20, the drain of the nineteenth MOS transistor M19 is connected to the drain of the twenty-first MOS transistor M21, the source of the twentieth MOS transistor M20 is connected to the power supply voltage, the drain of the twentieth MOS transistor M20 is connected to the drain of the twenty-second MOS transistor M22, the gate of the twenty-first MOS transistor M21 is connected to the gate of the twenty-second MOS transistor M22, the source of the twenty-first MOS transistor M21 is connected to the drain of the twenty-third MOS transistor M23, the source of the twenty-second MOS transistor M23 is connected to the drain of the twenty-fourth MOS transistor M24, the gate of the twenty-third MOS transistor M23 is connected to the gate of the twenty-fourth MOS transistor M24, the source of the twenty-third MOS transistor M23 is connected to ground, the source of the twenty-fourth MOS transistor M24 is connected to ground, the source of the twenty-fifth MOS transistor M25 is connected to the power supply voltage, the gate of the twenty-fifth MOS transistor M25 is connected to the drain of the twentieth MOS transistor M20 and the drain of the twenty-second MOS transistor M22, the drain of the twenty-fifth MOS transistor M25 is connected to the drain of the twenty-sixth MOS transistor M26, the source of the twenty-sixth MOS transistor M26 is connected to ground, the first end of the first capacitor C1 is connected to the gate of the twenty-fifth MOS transistor M25, and the second end of the first capacitor C1 is connected to the drain of the twenty-fifth MOS transistor M25.

[0057] It can be understood that the differential pair module generates a PTAT voltage VOUT2, which increases with temperature. Assuming that the gate voltage of M10 is V in , then:

[0058]

[0059]

[0060]

[0061] wherein, VGS10 is the gate-source voltage of M10, VGS11 is the gate-source voltage of M11, IM9 is the drain current of M9, IM10 is the drain current of M10, IM11 is the drain current of M11, IM12 is the drain current of M12, W0 / L0 is the ratio of the channel width to the channel length of M0, W11 / L11 is the ratio of the channel width to the channel length of M11.

[0062] The expression:

[0063]

[0064] From the expression, has PTAT characteristics, and if has a positive temperature coefficient, the circuit is more sensitive to temperature changes. High gain operational amplifier A1 constitutes a high gain negative feedback loop, forcing the resistance series branch middle node voltage equal to V OUT , so as to accurately convert the PTAT voltage into PTAT current I PTAT :

[0065]

[0066] Again through the current mirror (M7, M14, M15), M14 copied In parallel with the constant current source I, it becomes part of the total current of the differential pair. M7 copied Through the current mirror M8, M9, thereby affecting the current of the active load, at this time has a positive temperature coefficient, further improving the sensitivity of the PTAT circuit to temperature.

[0067] The amplifier A1 used for the PTAT voltage circuit is realized by the two-stage Miller compensation amplifier shown in Figure 2 . Among them, the first stage is composed of transistors M17-M24, and the second stage is composed of transistors M25 and M26. Frequency compensation is performed by capacitor C1.

[0068] Temperature compensation and zero temperature coefficient are realized, CTAT voltage and PTAT current / voltage are combined by cascading the circuit structure, and the output end realizes accurate cancellation of positive and negative temperature coefficient components. By adjusting the current mirror ratio, the MOS tube size ratio and the values of resistors R1 and R2, the temperature coefficient of the output reference voltage can be flexibly adjusted to approach zero in a wide temperature range.

[0069] Figure 3 The reference voltage of the bandgap reference circuit provided by the embodiment of the present application has a variation trend in the temperature range of-40°C to 100°C, as shown in Figure 3 , the maximum voltage change is only 0.85mV, the reference voltage is extremely insensitive to temperature changes, the temperature drift is extremely small, and a highly stable reference voltage can be provided in a wide temperature range. The temperature coefficients of the circuit under different process angles (TT, SS, FF) are 5.01, 8.91, and 14.77ppm / °C, respectively, which has good process robustness and high reliability.

[0070] Figure 4 ​The total current consumption graph of the bandgap reference circuit provided by the embodiment of the present application in the temperature range of -40°C to 100°C is shown in FIG. 2. Figure 4 As shown in the graph, the curve shows that the current consumption changes little in the whole temperature range and is basically maintained at about 2 μA, which indicates that the bandgap reference circuit has extremely low power consumption and good temperature robustness.

[0071] Figure 5 The characteristic graph of the output reference voltage provided by the embodiment of the present application changing with the power supply voltage is shown in FIG. 3. Figure 5 As shown in the graph, the reference voltage is almost constant, which shows extremely high power supply rejection ratio (PSR), and can output stable reference voltage even in the case of power supply voltage fluctuation, which meets the strict requirement of high-precision system on power supply noise suppression.

[0072] Figure 6 The relationship graph of the quiescent current provided by the embodiment of the present application changing with the power supply voltage is shown in FIG. 4. Figure 6 As shown in the graph, with the power supply voltage rising from 1.5 V to 1.8 V, the current only has a slight increase (1.6 μA to 2.1 μA), which indicates that the circuit has good adaptability to the change of power supply voltage and can maintain low power consumption operation in a wide power supply voltage range, which improves the power supply compatibility of the system.

[0073] The application provides a high-temperature stability bandgap reference circuit with a full MOS structure, which integrates a negative temperature coefficient (CTAT) voltage generating circuit, a positive temperature coefficient (PTAT) current / voltage generating circuit and a high-gain operational amplifier, all of which are made of standard CMOS processes, and has a simple structure and is easy to integrate.Compared with a traditional bandgap reference scheme relying on a BJT, the application has ultra-low power consumption and high precision, all core devices work in a sub-threshold region, the static power consumption is greatly reduced, and the application is suitable for a system on chip (SoC) and a portable application scene which are sensitive to energy consumption.Meanwhile, by accurately designing MOS tube size ratios and bias currents, optimal linear combination of CTAT and PTAT components is realized, the temperature coefficient of an output reference voltage is extremely low, and high precision can be kept in a wide temperature range of -40 DEG C to + 125 DEG C.The application has strong process compatibility and low cost, the circuit is completely based on MOS transistors, does not need a BJT, is compatible with a standard digital CMOS process, does not need additional masks and special process steps, significantly reduces chip manufacturing cost and design complexity, and is convenient for large-scale integration.The application has strong temperature compensation capability and high output stability, a negative feedback loop formed by the high-gain operational amplifier A1 accurately converts the PTAT voltage into a PTAT current, and feeds back to a differential pair bias path, and the temperature sensitivity and compensation capability are further enhanced.The finally output reference voltage shows extremely high stability and reliability under temperature, process and power voltage fluctuation.The application has a flexible structure, is easy to adjust and expand, the temperature coefficient of the output voltage can be flexibly adjusted by adjusting current mirror ratios, resistance division ratios and MOS tube sizes, different application scenarios are met, and diversified demands of reference sources are met.The circuit structure is modularized, and is convenient for integration with high-precision analog modules such as an LDO, an ADC and a DAC.

[0074] Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the application be limited only by the scope of the claims, including any appropriate amendments thereof, and that there be accounted to patent freedoms relating to apparent disclosure of the application which is inherent to its disclosure. The specification and examples are to be considered exemplary only, with the true scope and spirit of the application indicated by the following claims.

[0075] It is to be understood that the application is not limited to the precise construction here described and as shown in the attached drawings, and that various modifications and changes can be made by those skilled in the art without departing from the scope of the application. The scope of the application is to be determined only by the appended claims.

Claims

1. A high temperature stability bandgap reference circuit with a full MOS structure, characterized in that: include: A negative temperature coefficient voltage generating circuit and a positive temperature coefficient current / voltage generating circuit, wherein the negative temperature coefficient voltage generating circuit and the positive temperature coefficient voltage generating circuit are connected; The negative temperature coefficient voltage generating circuit includes: a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor and a sixth MOS transistor, wherein the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor and the sixth MOS transistor operate in a subthreshold region; The positive temperature coefficient current / voltage generating circuit includes: a differential pair module, a first resistor, a second resistor, a current mirror module and a high-gain operational amplifier. The differential pair module includes: a tenth MOS transistor and an eleventh MOS transistor. The current mirror module includes: a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a fourteenth MOS transistor and a fifteenth MOS transistor.

2. The high temperature stability bandgap reference circuit of the full MOS structure according to claim 1, characterized in that: The source of the first MOS transistor is connected to the gate of the second MOS transistor, the drain and gate of the first MOS transistor are grounded, the source of the second MOS transistor is connected to the source of the third MOS transistor, the drain of the second MOS transistor is connected to the drain of the fourth MOS transistor, the drain of the third MOS transistor is connected to the drain of the fifth MOS transistor, the source of the fourth MOS transistor is grounded, the gate of the fourth MOS transistor is connected to the gate of the fifth MOS transistor, the source of the fifth MOS transistor is connected to the drain of the sixth MOS transistor, the gate of the sixth MOS transistor is connected to the drain of the sixth MOS transistor, and the source of the sixth MOS transistor is grounded.

3. The high temperature stability bandgap reference circuit of the full MOS structure according to claim 1, characterized in that: The source of the seventh MOS tube is connected to the power supply voltage, the gate of the seventh MOS tube is connected to the gate of the fourteenth MOS tube and the gate of the fifteenth MOS tube, the drain of the seventh MOS tube is connected to the drain of the eighth MOS tube, the gate of the eighth MOS tube is connected to the gate of the ninth MOS tube, the source of the eighth MOS tube is grounded, the drain of the ninth MOS tube is connected to the gate of the twelfth MOS tube, the source of the ninth MOS tube is grounded, the source of the tenth MOS tube is connected to the source of the eleventh MOS tube, the gate of the tenth MOS tube is connected to the gate of the third MOS tube, the drain of the tenth MOS tube is connected to the drain of the twelfth MOS tube, the gate of the twelfth MOS tube is connected to the gate of the thirteenth MOS tube, and the The source of the second MOS transistor is grounded, the drain of the eleventh MOS transistor is connected to the drain of the thirteenth MOS transistor, the source of the thirteenth MOS transistor is grounded, the gate of the eleventh MOS transistor is connected to the positive input terminal of the high-gain operational amplifier, the source of the fourteenth MOS transistor is connected to the power supply voltage, the drain of the fourteenth MOS transistor is connected to the sources of the tenth and eleventh MOS transistors, the source of the fifteenth MOS transistor is connected to the power supply voltage, the drain of the fifteenth MOS transistor is connected to the source of the sixteenth MOS transistor, the drain of the sixteenth MOS transistor is connected to the first end of the first resistor, the second end of the first resistor is connected to the negative input terminal of the high-gain operational amplifier, the first end of the second resistor is connected to the first end of the first resistor, and the second end of the second resistor is grounded.

4. The high temperature stability bandgap reference circuit of the full MOS structure according to claim 1, characterized in that: The high-gain operational amplifier includes: a seventeenth MOS tube, an eighteenth MOS tube, a nineteenth MOS tube, a twentieth MOS tube, a twenty-first MOS tube, a twenty-second MOS tube, a twenty-third MOS tube, a twenty-fourth MOS tube, a twenty-fifth MOS tube, a twenty-sixth MOS tube and a first capacitor.

5. The high temperature stability bandgap reference circuit of the full MOS structure according to claim 4, characterized in that: The source of the seventeenth MOS transistor is connected to the power supply voltage, the drain of the seventeenth MOS transistor is connected to the source of the twenty-second MOS transistor, the source of the eighteenth MOS transistor is connected to the power supply voltage, the drain of the eighteenth MOS transistor is connected to the source of the twenty-first MOS transistor, the source of the nineteenth MOS transistor is connected to the power supply voltage, the gate of the nineteenth MOS transistor is connected to the gate of the twentieth MOS transistor, the drain of the nineteenth MOS transistor is connected to the drain of the twenty-first MOS transistor, the source of the twentieth MOS transistor is connected to the power supply voltage, the drain of the twentieth MOS transistor is connected to the drain of the twenty-second MOS transistor, the gate of the twenty-first MOS transistor is connected to the gate of the twenty-second MOS transistor, the source of the twenty-first MOS transistor is connected to the gate of the twenty-second MOS transistor The drain of the 23rd MOS transistor is connected to the drain of the 24th MOS transistor, the gate of the 23rd MOS transistor is connected to the gate of the 24th MOS transistor, the source of the 23rd MOS transistor is grounded, the source of the 24th MOS transistor is grounded, the source of the 25th MOS transistor is connected to the power supply voltage, the gate of the 25th MOS transistor is connected to the drain of the 20th MOS transistor and the drain of the 22nd MOS transistor, the drain of the 25th MOS transistor is connected to the drain of the 26th MOS transistor, the source of the 26th MOS transistor is grounded, the first end of the first capacitor is connected to the gate of the 25th MOS transistor, and the second end of the first capacitor is connected to the drain of the 25th MOS transistor.

6. The high temperature stability bandgap reference circuit of the full MOS structure according to claim 1, characterized in that: In the subthreshold region, the relationship between the drain current and the gate-source voltage of the MOS tube satisfies the following formula: ； in, is the drain current, is the gate-source voltage, is the ratio of the MOS tube channel width to the channel length, , is the ideal factor, is the electron mobility or hole mobility, is the gate oxide capacitance per unit area, is the thermal voltage, is the Boltzmann constant, is the absolute temperature, is the charge of the electron.

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