Efficient flash memory management method, device and equipment based on table lookup algorithm

Abstract

The present application relates to a high-efficiency flash memory management method, device and equipment based on a lookup table algorithm, which maps write cache programming commands issued by a chip bus through three configured lookup tables in stages, indexes corresponding programming groups in a lookup table manner during execution of programming, uses programming group indexes to return corresponding programming addresses and programming data, reduces programming time of the same cache size to 2 / 3 of that of a traditional scheme, thereby speeding up the entire write cache programming process of the flash memory, realizing more efficient write management operation on a large-capacity flash memory, saving chip resources and write time, and improving the overall performance of the flash memory.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of computer data access, and relates to an efficient flash memory management method, device and equipment based on a lookup table algorithm. BACKGROUND

[0002] Flash memory is an important non-volatile memory. With the rapid development of artificial intelligence applications, the demand for flash memory is rapidly increasing, which puts forward higher requirements for flash memory in the era of artificial intelligence. Not only does flash memory need to have larger storage space, but also needs to have faster read and write speeds. Therefore, it is necessary to develop more efficient flash memory read and write management means to improve the overall performance of flash memory. However, in the traditional flash memory read and write management means, the common management method is based on a flash translation layer (FTL). The FTL is responsible for mapping the logical address of the host to the physical address of the flash memory, and performs operations such as wear leveling and garbage collection. There is also a management means represented by SPI flash memory, which sends a write command through an SPI bus, writes data to a cache area first, and then writes it to the actual storage location. However, these traditional means have deficiencies in overall performance: the garbage collection process of the FTL can cause write amplification, increase the amount of actual data written, and reduce write performance; the cache management mechanism of the SPI flash memory is complex in maintaining consistency between the cache and the actual storage, and is prone to cache data loss due to unexpected power failure, which is difficult to meet the stringent performance requirements of large capacity and high read and write speed of flash memory in the era of artificial intelligence. SUMMARY

[0003] In view of the problems in the above-mentioned traditional technology, the present application provides an efficient flash memory management method based on a lookup table algorithm, an efficient flash memory management device based on a lookup table algorithm, and a computer device, which can more efficiently manage large-capacity flash memory, save chip resources and write time, and improve the overall performance of flash memory.

[0004] To achieve the above-mentioned purpose, the embodiments of the present application adopt the following technical solutions:

[0005] On the one hand, an efficient flash memory management method based on a lookup table algorithm is provided, comprising the steps of:

[0006] obtaining a write cache programming command issued by a chip bus;

[0007] mapping programming data to be written to flash memory to a lookup table one according to the programming address of the write cache programming command; the lookup table one is used to map the write cache programming command to the real storage space of the flash memory;

[0008] mapping the programming data in the lookup table one that needs to be programmed to the real storage space of the flash memory into the programming group in the lookup table two; the lookup table two is used for mapping the data that needs to be programmed to the real storage space into the programming group;

[0009] mapping the programming group in the lookup table two into the programming group index that needs to be programmed in the lookup table three; the lookup table three is used for indexing the programming address and the data in the programming process;

[0010] according to the programming times of the write cache programming command, looking up the lookup table three, indexing the programming group in the lookup table two through the matched programming operation information, and according to the hit programming group index, looking up the programming address and the programming data in the lookup table one;

[0011] according to the hit programming address, programming the hit programming data into the corresponding real storage space in parallel.

[0012] In another aspect, the application further provides a high-efficiency flash memory management device based on a lookup table algorithm, comprising:

[0013] a command acquisition module, configured to acquire a write cache programming command issued by a chip bus;

[0014] a command mapping module, configured to map programming data to be written into a flash memory into a lookup table one according to a programming address of the write cache programming command; the lookup table one is used for mapping the write cache programming command into a real storage space of the flash memory;

[0015] a programming group mapping module, configured to map programming data in the lookup table one that needs to be programmed to the real storage space of the flash memory into the programming group in the lookup table two; the lookup table two is used for mapping the data that needs to be programmed to the real storage space into the programming group;

[0016] a programming index mapping module, configured to map the programming group in the lookup table two into the programming group index that needs to be programmed in the lookup table three; the lookup table three is used for indexing the programming address and the data in the programming process;

[0017] a lookup index module, configured to according to the programming times of the write cache programming command, look up the lookup table three, index the programming group in the lookup table two through the matched programming operation information, and according to the hit programming group index, look up the programming address and the programming data in the lookup table one;

[0018] a write programming module, configured to according to the hit programming address, program the hit programming data into the corresponding real storage space in parallel.

[0019] In another aspect, the application further provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the high-efficiency flash memory management method based on a lookup table algorithm when executing the computer program.

[0020] One of the above technical solutions has the following advantages and beneficial effects:

[0021] The above high-efficiency flash memory management method, device and equipment based on the table lookup algorithm gradually map the write cache programming commands issued by the chip bus through the three configured lookup tables, index the corresponding programming groups in the table lookup manner in the programming process, use the programming group index to return the corresponding programming address and programming data, reduce the programming time of the same cache size to 2 / 3 of the traditional scheme, thereby accelerating the entire write cache programming process of the flash memory, realizing more efficient write management operation on the large-capacity flash memory, saving the chip resources and write time, and improving the overall performance of the flash memory. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0023] Figure 1 A flowchart of the high-efficiency flash memory management method based on the table lookup algorithm in one embodiment;

[0024] Figure 2 A flowchart of the write cache programming algorithm in one embodiment;

[0025] Figure 3 A mapping diagram of the WB_C2M_LUT lookup table in one embodiment;

[0026] Figure 4 A mapping diagram of the WB_M2G_LUT lookup table in one embodiment;

[0027] Figure 5 A mapping diagram of the WB_T2P_LUT lookup table in one embodiment;

[0028] Figure 6 A diagram of the table lookup index in the programming process in one embodiment;

[0029] Figure 7 A flowchart of the multi-sector erase algorithm in one embodiment;

[0030] Figure 8 A mapping diagram of the SERS_EN_LUT lookup table in one embodiment;

[0031] Figure 9 A diagram of the SERS_ADDR_P pointer update in one embodiment;

[0032] Figure 10 Figure 1 is a diagram illustrating a multi-sector erase address index for one embodiment;

[0033] Figure 11 Figure 2 is a block diagram of a module for an efficient flash management device based on a lookup table algorithm for one embodiment. DETAILED DESCRIPTION

[0034] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not intended to limit the present application. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms used in the specification of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0035] It should be noted that the term "embodiment" mentioned herein means that the specific features, structures or characteristics described in connection with the embodiment can be included in at least one embodiment of the present application. The phrase is shown at various places in the specification does not necessarily refer to the same embodiment, nor is it independent or alternative to other embodiments. Those skilled in the art can understand that the embodiments described herein can be combined with other embodiments. The term "and / or" used herein refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0036] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0037] In one embodiment, as shown in Figure 1 a method for efficient flash management based on a lookup table algorithm can include the following steps S10 to S20:

[0038] S10, obtaining a write cache programming command issued by a chip bus;

[0039] S12, mapping programming data to be written into the flash memory to a lookup table one according to the programming address of the write cache programming command; the lookup table one is used to map the write cache programming command to the real storage space of the flash memory;

[0040] S14, mapping the programming data in the lookup table one that needs to be programmed to the real storage body of the flash memory to a programming group in the lookup table two; the lookup table two is used to map the data that needs to be programmed to the real storage space to the programming group;

[0041] S16, mapping the programming group in the lookup table two to the programming group index in the lookup table three which needs to be programmed; the lookup table three is used to index the programming address and data during programming;

[0042] S18, according to the programming times of the write cache programming command, looking up the lookup table three, and then according to the hit programming group index, indexing the programming address and programming data in the lookup table one through the matching programming operation information in the lookup table two;

[0043] S20, according to the hit programming address, programming the hit programming data to the corresponding real memory bank in parallel.

[0044] It can be understood that the parallel flash memory chip can accelerate the whole write cache programming process of the flash memory by configuring three lookup tables when performing write cache programming (taking 32 words as an example, and the same is similar for other word lengths). The lookup table one is used to map the write cache programming command issued by the chip bus to the real memory space of the flash memory; the lookup table two is used to map the data needed to be programmed to the real memory space into the programming group according to the demand (such as the demand for parallel programming, if 4 memory banks need to be programmed in parallel, then 4 groups are divided); the lookup table three is used to index the programming address and data during programming. When the flash memory chip performs write cache programming of the real memory space, the above three lookup tables are retrieved to shorten the data arrangement time, and the programming time is reduced through the programming group. Based on this, the write cache programming algorithm flow can be as shown in Figure 2 .

[0045] It should be noted that the purpose of the lookup table is mainly to change the traditional single memory bank programming mode to multiple memory bank parallel programming, so that the programming time of the same size memory space can be greatly reduced. In addition, the operation of the lookup table can be operated in parallel, and the time consumption is less, compared with the reduction of the programming time, the time consumption of the lookup table is small enough to be ignored, therefore, the embodiment adopts the following new two-stage processing logic design: the command stage is "command >> lookup table one >> lookup table two >> lookup table three", and the programming stage is "lookup table three >> lookup table two >> lookup table one".

[0046] Specifically, when the chip bus issues the write cache programming command, according to the programming address of the write cache programming command, the corresponding programming data is mapped to the lookup table one (denoted as WB_C2M_LUT lookup table), as shown in Figure 3As shown. Here, taking the storage bank 32-bit width and the chip bus 16-bit width as an example (in order to align the bit width, two 16-bit command data need to be saved for one lookup table address), the write cache programming command of the chip bus maps the programming data carried according to the programming address to the WB_C2M_LUT lookup table, and sets the to-be-programmed flag of the highest bit of the real storage space in the WB_C2M_LUT lookup table to 1 (to inform the subsequent lookup table to avoid repeated saving).

[0047] Then, the lookup table two (which can be recorded as WB_M2G_LUT lookup table) maps the programming data that need to be programmed to the real storage space to a programming group according to the information in the WB_C2M_LUT lookup table. As shown, Figure 4 Taking the simultaneous programming of four groups of real storage banks of the flash memory as an example, the corresponding programming data that need to be programmed to the real storage bank are mapped to the programming group in the WB_M2G_LUT lookup table, and the to-be-programmed flag of the highest bit of the real storage bank is set to 1 according to the mapping relationship.

[0048] The programming data are mapped to the programming group index (such as the WB_M2G_LUT index that need to be programmed) in the lookup table three (which can be recorded as WB_T2P_LUT lookup table) according to the programming group in the WB_M2G_LUT lookup table, for example, Figure 5 As shown, the index with the high four bits not being 0 in the WB_M2G_LUT lookup table is mapped to the WB_T2P_LUT lookup table, and the programming times are added by one.

[0049] When performing programming, first, the programming times indicated by the write cache programming command are used to start the lookup table in the WB_T2P_LUT lookup table, the index is used to obtain the programming group corresponding to the programming times in the WB_M2G_LUT lookup table, and finally the programming group index hit by the lookup table is used to obtain the real programming address and programming data in the WB_C2M_LUT lookup table, to perform the simultaneous write programming of four groups of real storage banks. The flow of the lookup table index in the programming process is as shown in Figure 6 .

[0050] The above high-efficiency flash memory management method based on the lookup table algorithm maps the write cache programming command issued by the chip bus through three configured lookup tables in stages, indexes the corresponding programming group in the lookup table during the programming process, uses the programming group index to return the corresponding programming address and programming data, reduces the programming time of the same cache size to 2 / 3 of the traditional scheme, thereby speeding up the whole write cache programming process of the flash memory, realizing the more efficient write management operation of the large-capacity flash memory, saving the chip resources and the write time, and improving the overall performance of the flash memory.

[0051] In one embodiment, the high-efficiency flash memory management method based on the table lookup algorithm described above can further include the following steps:

[0052] Obtaining a multi-sector erase command issued by a chip bus;

[0053] According to the sector address in the multi-sector erase command, setting the valid bit in the lookup table A to 1; the valid bit is used as an erase sector address index;

[0054] According to the sector address in the multi-sector erase command, updating the dynamic pointer P so that the dynamic pointer P always points to the smallest sector address in the multi-sector erase command; the initial value of the dynamic pointer P is the invalid pointer 2048;

[0055] According to the number of erases indicated by the multi-sector erase command, starting from the starting address of the dynamic pointer P to perform erasing;

[0056] When the updated erase sector address in the lookup table A is smaller than the value of the current dynamic pointer P, updating the value of the dynamic pointer P to the next valid erase sector address index in the lookup table A;

[0057] When the dynamic pointer P cannot find the next valid erase sector address index in the lookup table A, the sector erasing ends.

[0058] It can be understood that when the parallel flash memory chip performs multi-sector erasing, the embodiment reduces the chip resource usage amount during the execution of the multi-sector erase command through the configuration of a lookup table A and a dynamic pointer mechanism, as shown in Figure 7 The lookup table A is used to record the sectors that need to be erased during the multi-sector erasing process, and the dynamic pointer P is set to dynamically find the sector address corresponding to the sector that needs to be erased according to the lookup table A during the execution of the real erasing. When the parallel flash memory chip performs real storage space erasing, the lookup table A guides the jumping of the dynamic pointer P to obtain the sector address required for real erasing, thereby reducing the usage amount of chip resources during the multi-sector erasing process.

[0059] Specifically, when multi-sector erasing of the flash memory needs to be processed, the chip bus sets the valid bit in the lookup table A (which can be denoted as SERS_EN_LUT lookup table) to 1 according to the sector address in the multi-sector erase command when issuing the multi-sector erase command, and the valid bit is used as an erase sector address index. As shown in Figure 8 Taking a 2G bit flash memory chip as an example, the SERS_EN_LUT lookup table updates the valid bit according to the received valid multi-sector erase command.

[0060] While the SERS_EN_LUT lookup table is being updated, a dynamic pointer P (which can be denoted as SERS_ADDR_P pointer) is also updated synchronously according to the data in the SERS_EN_LUT lookup table. As shown in Figure 9 , the initial value of the SERS_ADDR_P pointer is an invalid pointer 2048, and when the updated erase sector address in the SERS_EN_LUT lookup table is smaller than the value of the current SERS_ADDR_P pointer, the SERS_ADDR_P pointer is updated.

[0061] When performing erasing, erasing is performed from the starting address of the SERS_ADDR_P pointer according to the number of erasing times indicated by the multi-sector erasing command, and in the process of erasing, when the SERS_ADDR_P pointer finds the next valid erase address, if the next valid erase address is found, the SERS_ADDR_P pointer stops at the valid erase sector address index in the SERS_EN_LUT lookup table, so as to erase the next sector, as shown in Figure 10 .

[0062] In this embodiment, when performing multi-sector erasing, the chip resources required for multi-sector erasing of the flash memory are saved by means of table lookup and dynamic pointer mechanism, and the chip resources used in multi-sector erasing are reduced by 90% (taking a 2Gbit flash memory chip as an example). For example, if there are 100 sector addresses occupying 10 bits, the conventional method needs 100 10=1000 bits, and the above-mentioned efficient flash memory management method based on table lookup algorithm adopts a pointer method and only needs a 10-bit pointer and a 100-bit SERS_EN_LUT lookup table. This method only needs 100+10=110 bits, which greatly saves resources, thereby significantly improving the write performance of the flash memory chip and making the flash memory chip obtain higher performance and lower power consumption.

[0063] It should be understood that although each step in the above-mentioned flow Figure 1 is displayed in sequence according to the arrow, these steps are not necessarily executed in sequence according to the arrow. Unless otherwise specified herein, the execution of these steps has no strict sequence limitation, and these steps can be executed in other sequences. Moreover, at least part of the steps in the above-mentioned flow Figure 1 may include multiple sub-steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of these sub-steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least part of other steps or sub-steps or stages of other steps.

[0064] In one embodiment, asFigure 11 As shown, the high-efficiency flash memory management device based on the table lookup algorithm also includes a command acquisition module 11, a command mapping module 13, a programming group mapping module 15, a programming index mapping module 17, a table lookup index module 19, and a write programming module 21. The command acquisition module 11 is configured to acquire the write cache programming command issued by the chip bus. The command mapping module 13 is configured to map the programming data to be written into the flash memory to a lookup table 1 according to the programming address of the write cache programming command. The lookup table 1 is configured to map the write cache programming command to the real storage space of the flash memory. The programming group mapping module 15 is configured to map the programming data in the lookup table 1 that needs to be programmed into the real storage bank of the flash memory to a programming group in a lookup table 2. The lookup table 2 is configured to map the data that needs to be programmed into the real storage space to the programming group. The programming index mapping module 17 is configured to map the programming group in the lookup table 2 to a programming group index that needs to be programmed in a lookup table 3. The lookup table 3 is configured to index the programming address and the data in the programming process. The table lookup index module 19 is configured to perform table lookup in the lookup table 3 according to the programming times of the write cache programming command, index the programming group in the lookup table 2 through the matching programming operation information, and then index the programming address and the programming data in the lookup table 1 according to the hit programming group index. The write programming module 21 is configured to program the hit programming data into the corresponding real storage bank according to the hit programming address.

[0065] The high-efficiency flash memory management device based on the table lookup algorithm described above maps the write cache programming command issued by the chip bus through three configured lookup tables in stages, indexes the corresponding programming group in the table lookup manner in the programming process, uses the programming group index to return the corresponding programming address and the programming data, reduces the programming time of the same cache size to 2 / 3 of the traditional scheme, thereby accelerating the entire write cache programming process of the flash memory, realizing more efficient write management operation on the large-capacity flash memory, saving the chip resources and the write time, and improving the overall performance of the flash memory.

[0066] In one embodiment, the command obtaining module 11 is further configured to obtain a multi-sector erase command issued by the chip bus; the high-efficiency flash memory management device based on the table lookup algorithm can further comprise: an erase mapping module configured to set an effective bit in the lookup table A to 1 according to a sector address in the multi-sector erase command; the effective bit is used as an erase sector address index. A pointer updating module configured to update a dynamic pointer P according to the sector address in the multi-sector erase command, so that the dynamic pointer P always points to the smallest sector address in the multi-sector erase command; the initial value of the dynamic pointer P is an invalid pointer 2048. A sector erasing module configured to perform erasing from the starting address of the dynamic pointer P according to the number of erasing indicated by the multi-sector erase command. When the updated erase sector address in the lookup table A is smaller than the value of the current dynamic pointer P, the pointer updating module updates the value of the dynamic pointer P to the next effective erase sector address index in the lookup table A; when the dynamic pointer P cannot find the next effective erase sector address index in the lookup table A, the sector erasing ends.

[0067] It can be understood that the explanations and descriptions of the features of the above high-efficiency flash memory management device based on the table lookup algorithm can be understood in the same way by referring to the corresponding explanations and descriptions in the above embodiments of the high-efficiency flash memory management method based on the table lookup algorithm. Each module in the above high-efficiency flash memory management device based on the table lookup algorithm can be realized by software, hardware, or a combination thereof. The above components can be embedded in or independent of a device with data processing function in hardware form, or stored in the memory of the above device in software form, so that the processor can call and execute the operations corresponding to each module. The above device can be, but is not limited to, various computers in the prior art.

[0068] In one embodiment, a computer device is also provided, comprising a memory and a processor, the memory stores a computer program, and the processor implements the following processing steps when executing the computer program: obtaining a write cache programming command issued by the chip bus; mapping programming data to be written into the flash memory to a lookup table I according to a programming address of the write cache programming command; the lookup table I is used to map the write cache programming command to the real storage space of the flash memory; mapping the programming data in the lookup table I that needs to be programmed into the real storage bank of the flash memory to a programming group in a lookup table II; the lookup table II is used to map the data that needs to be programmed into the real storage space to a programming group; mapping the programming group in the lookup table II to a programming group index that needs to be programmed in a lookup table III; the lookup table III is used to index the programming address and data during programming; according to the number of programming times of the write cache programming command, looking up the lookup table III, and then according to the hit programming group index, mapping the programming address and the programming data in the lookup table I; and programming the hit programming data to the corresponding real storage bank according to the hit programming address.

[0069] In one embodiment, the processor, when executing the computer program, can also implement the steps or sub-steps added in each embodiment of the high-efficiency flash memory management method based on the table lookup algorithm.

[0070] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by a computer program instructing related hardware, and the computer program can be stored in a non-volatile computer readable storage medium. When the computer program is executed, it can include the processes of the above-mentioned embodiments. Any reference to memory, storage, database or other medium used in each embodiment of the present application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus dynamic random access memory (Rambus DRAM, RDRAM for short) and interface dynamic random access memory (DRDRAM).

[0071] Any combination of the technical features of the above embodiments can be made. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, but as long as the combination of the technical features does not exist, it should be considered as the scope of the present application.

[0072] The above embodiments only express several embodiments of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of protection. It should be noted that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of protection of the present application.

Claims

1. A high-efficiency flash memory management method based on a table lookup algorithm, characterized in that, Including the following steps: Obtain the write cache programming command issued by the chip bus; The programming data to be written to the flash memory is mapped to lookup table one according to the programming address of the write cache programming command; lookup table one is used to map the write cache programming command to the actual storage space of the flash memory; The programming data that needs to be programmed into the actual storage in the flash memory in lookup table 1 is mapped to the programming group in lookup table 2; lookup table 2 is used to map the data that needs to be programmed into the actual storage space to the programming group; Map the programming group in lookup table 2 to the programming group index in lookup table 3 that needs to be programmed; Lookup Table 3 is used to index programming addresses and data during the programming process; Based on the number of programming commands written to the cache, the system looks up the code in lookup table three. After indexing the programming group in lookup table two through the matching programming operation information, the system indexes the programming address and programming data in lookup table one based on the matched programming group. Based on the matched programming address, the matched programming data is programmed in parallel into the corresponding physical memory.

2. The efficient flash memory management method based on table lookup algorithm according to claim 1, characterized in that, It also includes the following steps: Obtain multi-sector erase commands issued by the chip bus; Based on the sector address in the multi-sector erase command, set the valid bits in lookup table A to 1; the valid bits serve as the erase sector address index. Update the dynamic pointer P according to the sector address in the multi-sector erase command, so that the dynamic pointer P always points to the smallest sector address in the multi-sector erase command; the initial value of the dynamic pointer P is the invalid pointer 2048; The erasure process begins from the starting address of the dynamic pointer P, according to the number of erasures specified by the multi-sector erase command. When the erased sector address updated in lookup table A is less than the current value of dynamic pointer P, update the value of dynamic pointer P to the next valid erased sector address index in lookup table A. The sector erasure ends when the dynamic pointer P cannot find the next valid erase sector address index in the lookup table A.

3. A high-efficiency flash memory management device based on a lookup table algorithm, characterized in that, include: The command acquisition module is used to acquire write cache programming commands issued by the chip bus; The command mapping module is used to map the programming data to be written to flash memory to lookup table one according to the programming address of the write cache programming command; lookup table one is used to map the write cache programming command to the actual storage space of flash memory. The programming group mapping module is used to map the programming data that needs to be programmed into the actual storage body in lookup table 1 to the programming group in lookup table 2; lookup table 2 is used to map the data that needs to be programmed into the actual storage space to the programming group; The programming index mapping module is used to map the programming groups in lookup table 2 to the programming group indexes that need to be programmed in lookup table 3; lookup table 3 is used to index programming addresses and data during the programming process; The lookup index module is used to look up the third lookup table based on the number of programming commands written to the cache. After indexing the programming group in the second lookup table through the matching programming operation information, it indexes the programming address and programming data in the first lookup table based on the matched programming group. The write programming module is used to program the matched programming data into the corresponding physical memory in parallel based on the matched programming address.

4. The high-efficiency flash memory management device based on table lookup algorithm according to claim 3, characterized in that, The command acquisition module is also used to acquire multi-sector erase commands issued by the chip bus; High-efficiency flash memory management devices also include: The erase mapping module is used to set the valid bits in lookup table A to 1 according to the sector address in the multi-sector erase command; the valid bits serve as the erase sector address index. The pointer update module is used to update the dynamic pointer P according to the sector address in the multi-sector erase command, so that the dynamic pointer P always points to the smallest sector address in the multi-sector erase command; the initial value of the dynamic pointer P is the invalid pointer 2048; The sector erasure module is used to erase sectors starting from the starting address of the dynamic pointer P according to the number of erasures indicated by the multi-sector erasure command. When the erased sector address updated in lookup table A is less than the current value of the dynamic pointer P, the pointer update module updates the value of the dynamic pointer P to the next valid erased sector address index in lookup table A. When the dynamic pointer P cannot find the next valid erased sector address index in lookup table A, the sector erasure ends.

5. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the efficient flash memory management method based on the lookup table algorithm as described in claim 1 or 2.

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