Floating point multiplication method and floating point multiplication circuit

Abstract

The application provides a floating-point multiplication method and a floating-point multiplication circuit, and relates to the technical field of processors. The method comprises the following steps: obtaining a first exponent of a first floating-point number and a second exponent of a second floating-point number; obtaining a to-be-shifted value corresponding to a decimal part of a product of the first floating-point number and the second floating-point number according to the first exponent and the second exponent; the to-be-shifted value is used for representing a shift bit number of a shift operation on the decimal part of the product; and the shift operation is performed on the decimal part of the product according to the to-be-shifted value, so as to obtain a multiplication result of the first floating-point number and the second floating-point number. The method has the advantages of short processing time and short operation period.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of processors, and particularly relates to a floating-point multiplication method and a floating-point multiplication circuit. BACKGROUND

[0002] The floating-point multiplication is used to calculate the product of floating-point numbers, and the decimal part of the product of floating-point numbers needs to be shifted during the floating-point multiplication.

[0003] In the related art, the product of floating-point numbers is obtained first, then the to-be-shifted value is determined according to the product, and the mantissa of the product is shifted according to the to-be-shifted value.

[0004] However, this method has the problems of low processing efficiency, long operation time, and large number of operation cycles. SUMMARY

[0005] Embodiments of the present application provide a floating-point multiplication method and a floating-point multiplication circuit to solve the problem of long time and large number of operation cycles in the prior art.

[0006] In a first aspect, an embodiment of the present application provides a floating-point multiplication method, comprising: obtaining a first exponent of a first floating-point number and a second exponent of a second floating-point number; in the process of calculating the product of the first floating-point number and the second floating-point number, obtaining a to-be-shifted parameter for shifting operation on the decimal part of the product according to the first exponent and the second exponent; the to-be-shifted parameter comprises a shift bit number and a shift direction; and performing the shift operation on the decimal part of the product according to the shift bit number and the shift direction to obtain the multiplication result of the first floating-point number and the second floating-point number.

[0007] In a second aspect, an embodiment of the present application provides a floating-point multiplication circuit, comprising a shift parameter calculation unit, a first multiplexer, a second multiplexer, a product calculation unit, and a shift operation unit; the first multiplexer and the second multiplexer are connected to the shift parameter calculation unit, the shift parameter calculation unit and the product calculation unit, and the shift operation unit are connected; the first multiplexer is configured to obtain a first exponent of a first floating-point number; the second multiplexer is configured to obtain a second exponent of a second floating-point number; the shift parameter calculation unit is configured to obtain a to-be-shifted parameter for performing a shift operation on a decimal part of a product of the first floating-point number and the second floating-point number according to the first exponent and the second exponent in a process in which the product calculation unit calculates the product; the to-be-shifted parameter comprises a shift bit number and a shift direction; and the shift operation unit is configured to perform a shift operation on the decimal part of the product according to the shift bit number and the shift direction to obtain a multiplication result of the first floating-point number and the second floating-point number.

[0008] In a third aspect, an embodiment of the present application further provides a floating-point multiplication device, comprising: a first obtaining module configured to obtain a first exponent of a first floating-point number and a second exponent of a second floating-point number; a second obtaining module configured to obtain a to-be-shifted parameter for performing a shift operation on a decimal part of a product of the first floating-point number and the second floating-point number according to the first exponent and the second exponent in a process in which the product is calculated; the to-be-shifted parameter comprises a shift bit number and a shift direction; and a third obtaining module configured to perform a shift operation on the decimal part of the product according to the shift bit number and the shift direction to obtain a multiplication result of the first floating-point number and the second floating-point number.

[0009] In a fourth aspect, an embodiment of the present application further provides an electronic device, comprising a processor; a memory for storing instructions executable by the processor; wherein the processor is configured to execute the instructions to implement the method of the first aspect.

[0010] In a fifth aspect, an embodiment of the present application further provides a computer-readable storage medium, when instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the method of the first aspect.

[0011] In the embodiment of the present application, the first exponent of the first floating-point number and the second exponent of the second floating-point number are obtained, and in the process of calculating the product of the first floating-point number and the second floating-point number, the to-be-shifted parameter corresponding to the mantissa of the product of the first floating-point number and the second floating-point number is obtained according to the first exponent and the second exponent, and the mantissa of the product is subjected to a shift operation according to the to-be-shifted bit number and the shift direction, to obtain the multiplication result of the first floating-point number and the second floating-point number. In the embodiment, the to-be-shifted value is not obtained after the product of the first floating-point number and the second floating-point number is obtained, but the to-be-shifted value is obtained according to the product. Compared with the method of obtaining the product first and then obtaining the shift value according to the product in the related art, the embodiment reduces the time of floating-point multiplication and reduces the operation period of floating-point multiplication.

[0012] The above description is only a summary of the technical solutions of the present application. In order to more clearly understand the technical means of the present application, the content of the specification can be implemented, and in order to make the above and other purposes, characteristics and advantages of the present application more obvious and easy to understand, the following specific embodiments of the present application are described. BRIEF DESCRIPTION OF DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0014] Figure 1 is a floating-point multiplication method application scenario provided by an embodiment of the present application;

[0015] Figure 2 is a floating-point multiplication method step flowchart provided by an embodiment of the present application;

[0016] Figure 3 is another floating-point multiplication method step flowchart provided by an embodiment of the present application;

[0017] Figure 4 is a method for obtaining a shift bit number step flowchart provided by an embodiment of the present application;

[0018] Figure 5 is a floating-point multiplication method step flowchart provided by an embodiment of the present application;

[0019] Figure 6 is a floating-point multiplication method step flowchart provided by an embodiment of the present application;

[0020] Figure 7 is a floating-point multiplication method step flowchart provided by an embodiment of the present application;

[0021] Figure 8 is a schematic diagram of a floating point multiplication circuit provided by an embodiment of the present application;

[0022] Figure 9 is a schematic diagram of a product exponent acquisition circuit provided by an embodiment of the present application;

[0023] Figure 10 is a schematic diagram of a product to-be-shifted parameter acquisition circuit provided by an embodiment of the present application;

[0024] Figure 11 is a schematic diagram of a product sign acquisition circuit provided by an embodiment of the present application;

[0025] Figure 12 is a schematic diagram of a product non-carrying processing exponent acquisition circuit provided by an embodiment of the present application;

[0026] Figure 13 is a schematic diagram of a floating point multiplication circuit provided by an embodiment of the present application;

[0027] Figure 14 is a block diagram of a floating point multiplication device provided by an embodiment of the present application;

[0028] Figure 15 is a block diagram of an electronic device provided by an embodiment of the present application;

[0029] Figure 16 is a block diagram of another electronic device provided by another embodiment of the present application. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.

[0031] The terms "first", "second", etc. in this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally a class, not limited to the number of objects, for example, the first object can be one or more. In addition, the term "and / or" is used to describe the relationship between the associated objects, which means that there can be three relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects. The term "multiple" in the embodiments of the present application means two or more, and other quantifiers are similar.

[0032] Figure 1 is an application scenario diagram of a floating-point multiplication method provided by an embodiment of the present application, referring to Figure 1 The floating-point multiplication instruction is a commonly used instruction in a processor, which can be used to instruct the first floating-point number and the second floating-point number to perform multiplication, and then obtain the product between the first floating-point number and the second floating-point number.

[0033] In the multiplication process, the clock frequency is high, and correspondingly, the time of each operation period is very short, and the operation process of the floating-point multiplication is relatively complex, which leads to the fact that usually multiple periods are needed to complete the floating-point multiplication. For example, in the related art, in some processor architectures, the multiplication between half-precision floating-point numbers, the multiplication between single-precision floating-point numbers, and the multiplication between double-precision floating-point numbers all need three periods.

[0034] Further, the floating-point number usually includes a sign part, an exponent part and a mantissa part, and the floating-point multiplication can be represented by the following formula:

[0035]

[0036] wherein, is the first floating-point number, is the second floating-point number, is the product between the first floating-point number and the second floating-point number.

[0037] The floating-point multiplication operation is multiplying the values of the first floating-point number and the second floating-point number. Specifically, the sign values of the first floating-point number and the second floating-point number are multiplied, the exponent values of the first floating-point number and the second floating-point number are multiplied, and the decimal values of the first floating-point number and the second floating-point number are multiplied, thereby obtaining the product of the first floating-point number and the second floating-point number, and then the product is converted into a binary floating-point number representation. Further, the sign value multiplication is an exclusive OR operation on the binary sign parts of the first floating-point number and the second floating-point number; the exponent value multiplication is an addition operation on the binary exponent parts of the first floating-point number and the second floating-point number; and the decimal value multiplication is a multiplication operation on the binary decimal parts of the first floating-point number and the second floating-point number.

[0038] Based on the above multiplication operation processing process, the value range of the result obtained by multiplying the decimal parts of the two floating-point numbers should be [0, 4). If both of the two floating-point numbers are normalized numbers, the value range of the result of the decimal part multiplication should be [1, 4), and if the actual result obtained by multiplying the binary decimal parts of the two floating-point numbers is between [2, 4), the mantissa part of the product of the two floating-point numbers needs to be shifted to the right, and the exponent part of the product of the two floating-point numbers needs to be incremented by 1.

[0039] If both of the two floating-point numbers are non-normalized numbers, the actual result obtained by multiplying the binary decimal parts of the two floating-point numbers is between [0, 1).

[0040] Based on the above multiplication operation processing process, the value range of the exponent part of the multiplication result should be If the exponent part is greater than the upper limit value of the floating-point number exponent , it needs to be overflowed to infinity; if the exponent part is less than the lower limit value of the floating-point number exponent , the decimal part of the product needs to be shifted to the left, and the exponent part of the product needs to be decreased. That is, after obtaining the product of the two floating-point numbers, the decimal part of the product needs to be shifted according to the shift bit number and the shift direction.

[0041] If the value of the exponent part of the result obtained by multiplying the exponent parts of the two floating-point numbers is in , and the result of the multiplication of the decimal parts is in , the decimal part of the multiplication result needs to be shifted to the left, and the exponent value decreases after the left shift.

[0042] In the related art, the product of the two floating-point numbers is usually calculated first, and then the product is analyzed to obtain the shift bit number and the shift direction, and the decimal part of the product is shifted according to the shift bit number and the shift direction, but this method takes a long time to process, resulting in a large number of operation cycles of the floating-point multiplication operation.

[0043] To address the problems in related technologies, this application provides a floating-point multiplication method. The method includes: obtaining a first exponent of a first floating-point number and a second exponent of a second floating-point number; during the calculation of the product of the first and second floating-point numbers, obtaining a shift parameter to be shifted based on the first and second exponents; the shift parameter includes the number of shift positions and the shift direction; and performing a shift operation on the fractional part of the product based on the number of shift positions and the shift direction to obtain the multiplication result of the first and second floating-point numbers. This embodiment eliminates the need to obtain the shift parameter after obtaining the product of the first and second floating-point numbers. Compared to related technologies that first obtain the product and then obtain the shift parameter, this embodiment saves the time of floating-point multiplication operations and reduces the computation cycle of floating-point multiplication.

[0044] The floating-point multiplication method provided in this application will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0045] Figure 2 This is a flowchart illustrating the steps of a floating-point multiplication method provided in an embodiment of this application, as follows: Figure 2 As shown, the method may include:

[0046] Step 101: Obtain the first exponent of the first floating-point number and the second exponent of the second floating-point number.

[0047] The first and second floating-point numbers are the floating-point numbers to be multiplied. The binary representation of a floating-point number consists of three parts: the sign part (sign), the exponent part (exp), and the mantissa part (frac). The calculation methods and value ranges of each part of the floating-point number are illustrated below:

[0048] The exponent part exp of a floating-point number can be normalized according to the following formula to obtain the normalized result of the exponent part exp of the floating-point number. :

[0049]

[0050] According to this expression, if the exponent of a floating-point number is exp=0, then the normalized result of its exponent is... =1; If the exponent of the floating-point number exp≠0, then the result of its exponent normalization is 1. =exp.

[0051] In this step, obtaining the first exponent of the first floating-point number includes: obtaining the normalized result of the exponent exp of the first floating-point number. The result of normalizing the exponent of the first floating-point number. Determine a first exponent of the first floating-point number. Obtain a second exponent of the second floating-point number, including obtaining a normalized result of an exponent exp of the second floating-point number obtaining the normalized result of the exponent of the second floating-point number Determine a second exponent of the second floating-point number.

[0052] In step 102, in the process of calculating the product of the first floating-point number and the second floating-point number, according to the first exponent and the second exponent, obtain a to-be-shifted parameter for shifting the decimal part of the product.

[0053] The to-be-shifted parameter includes a shift bit number and a shift direction.

[0054] For example, the shift bit number can include a left shift bit number and / or a right shift bit number, and the shift direction includes left shift or right shift.

[0055] For example, the first leading zero number of the first floating-point number and the second leading zero number of the second floating-point number can be obtained, and the left shift bit number can be obtained according to the first exponent, the second exponent, the first leading zero number and the second leading zero number; and the right shift bit number can be obtained according to the first exponent and the second exponent.

[0056] In step 103, the decimal part of the product is shifted according to the shift bit number and the shift direction, to obtain the multiplication result of the first floating-point number and the second floating-point number.

[0057] For example, the left shift bit number and the right shift bit number can be obtained and stored in a register of a processor, so that in the subsequent process, the shift bit number corresponding to the shift direction can be obtained from the register according to the shift direction, and the decimal part of the product is shifted according to the shift direction and the obtained shift bit number.

[0058] For example, when the product of the first floating-point number and the second floating-point number is shifted, if the obtained shift direction is left shift, the left shift bit number is obtained from the register, and the decimal part of the product is shifted to the left according to the left shift bit number; if the obtained shift direction is right shift, the right shift bit number is obtained from the register, and the decimal part of the product is shifted to the right according to the right shift bit number.

[0059] For example, the left shift bit number and the right shift bit number can be obtained and stored in a register of a processor, so that in the subsequent process, the shift bit number corresponding to the shift direction can be obtained from the register according to the shift direction, and the decimal part of the product is shifted according to the shift direction and the obtained shift bit number.

[0060] For example, if the shift direction is left shift, the left shift number is stored in the register of the processor for subsequent left shift of the decimal part of the product according to the left shift number; if the shift direction is right shift, the right shift number is stored in the register of the processor for subsequent right shift of the decimal part of the product according to the right shift number.

[0061] In the embodiment, the first exponent of the first floating-point number and the second exponent of the second floating-point number are obtained, and in the process of calculating the product of the first floating-point number and the second floating-point number, the to-be-shifted parameter corresponding to the decimal part of the product of the first floating-point number and the second floating-point number is obtained according to the first exponent and the second exponent, and the shift operation is performed on the decimal part of the product according to the to-be-shifted bit number in the to-be-shifted parameter and the shift direction, to obtain the multiplication result of the first floating-point number and the second floating-point number. The embodiment does not need to obtain the to-be-shifted bit number and the shift direction according to the product after obtaining the product of the first floating-point number and the second floating-point number, and relative to the method in the related art that the shift bit number and the shift direction are obtained according to the product after the product is obtained, the embodiment can process the steps of obtaining the product and obtaining the to-be-shifted parameter in parallel, thereby reducing the time of floating-point number multiplication and reducing the operation period of floating-point number multiplication.

[0062] Figure 3 is a floating-point number multiplication method provided by the embodiment, as shown in Figure 3 The method can include the following steps:

[0063] In step 201, if the first floating-point number and the second floating-point number both belong to the first digital type, the first exponent of the first floating-point number and the second exponent of the second floating-point number are obtained.

[0064] The first digital type includes other digital types except the second digital type, and the second digital type includes zero, non-number, and infinite number.

[0065] The floating-point number of the second digital type belongs to special numbers. When the floating-point number is zero, it can be divided into positive zero and negative zero according to the sign bit, and the exponent exp and the tail number part frac are both equal to zero. When the floating-point number is non-number (Not a number, NaN), it can include two types, qnan with the highest bit of the tail number part frac being 1 and snan with the highest bit of the tail number part frac being 0. When the floating-point number is infinite, the value of each bit of the exponent exp is 1, and the value of each bit of the tail number part frac is 0, which represents infinity, and it is divided into positive infinity and negative infinity according to the sign bit.

[0066] The multiplication operation process of the floating point number belonging to the second digital type can not acquire the shift parameter and does not shift the product according to the shift parameter. Therefore, if the first floating point number and the second floating point number both belong to the first digital type, the steps of acquiring the first exponent of the first floating point number and acquiring the second exponent of the second floating point number are entered again to acquire the to-be-shifted parameter according to subsequent steps, and the decimal part of the product is shifted according to the to-be-shifted parameter. In this way, the step of analyzing the shift value of the floating point number of the second digital type when the first floating point number and the second floating point number belong to the second digital type can be saved, the processing efficiency is improved, and the number of periods required for the floating point multiplication operation is shortened.

[0067] For example, the step of acquiring the first exponent of the first floating point number in step 201 includes sub-steps A1 to A3:

[0068] Sub-step A1, acquiring the first initial exponent of the first floating point number.

[0069] For example, the binary representation of the first floating point number is acquired, and the binary representation is composed of a sign , an exponent , and a mantissa . The exponent in the binary representation of the first floating point number is the first initial exponent of the first floating point number.

[0070] For example, the first floating point number P_A is 0-10000-000000000, wherein the highest bit 0 is the sign , 10000 is the first initial exponent , and 000000000 is the mantissa .

[0071] Sub-step A2, if the first initial exponent is equal to zero, determining that the first exponent of the first floating point number is equal to 1.

[0072] For example, if the first floating point number P_A is 0-00000-000000000, the first initial exponent is 00000, and the first initial exponent is equal to zero, it is determined that the first exponent of the first floating point number P_A is equal to 1.

[0073] Sub-step A3, if the first initial exponent is not equal to zero, determining that the first exponent of the first floating point number is equal to the first initial exponent.

[0074] For example, if the first floating point number P_A is 0-10000-000000000, the first initial exponent is 10000, and the first initial exponent is not equal to zero, it is determined that the first exponent of the first floating point number P_A is equal to the first initial exponent. ​​The first initial exponent is 10000, and the first exponent is 16 after conversion to decimal.

[0075] In step 201, the second exponent of the second floating-point number is obtained, including sub-steps B1 to B3:

[0076] In sub-step B1, the second initial exponent of the second floating-point number is obtained.

[0077] For example, the binary representation of the second floating-point number is obtained, which is composed of a sign , an exponent and a mantissa . The exponent in the binary representation of the second floating-point number is obtained, and the exponent in the binary representation is the second initial exponent of the second floating-point number.

[0078] For example, the second floating-point number P_B is 0-10000-000000001, wherein the highest bit 0 is the sign , 10000 is the second initial exponent , and 000000001 is the mantissa .

[0079] In sub-step B2, if the second initial exponent is equal to zero, it is determined that the second exponent of the second floating-point number is equal to 1.

[0080] For example, if the second floating-point number P_B is 0-00000-000000001, the second initial exponent is 00000, and the second initial exponent is equal to zero, it is determined that the second exponent of the second floating-point number P_B is equal to 1.

[0081] In sub-step B3, if the second initial exponent is not equal to zero, it is determined that the second exponent of the second floating-point number is equal to the first initial exponent.

[0082] For example, if the first floating-point number P_B is 0-10000-000000001, the first initial exponent is 10000, and the first initial exponent is not equal to zero, it is determined that the first exponent of the first floating-point number P_B is equal to the first initial exponent 10000, which is equal to 16 in decimal representation.

[0083] ​​Based on the embodiment, if the first initial exponent is equal to zero, it is determined that the first exponent of the first floating-point number is equal to 1; if the first initial exponent is not equal to zero, it is determined that the first exponent of the first floating-point number is equal to the first initial exponent, if the second initial exponent is equal to zero, it is determined that the second exponent of the second floating-point number is equal to 1; if the second initial exponent is not equal to zero, it is determined that the second exponent of the second floating-point number is equal to the first initial exponent, based on the method of obtaining the exponent of the floating-point number, it can be ensured that the exponent of the floating-point number meets the requirement of floating-point number binary exponent normalization.

[0084] In step 202, the third exponent of the product is obtained according to the first exponent of the first floating-point number and the second exponent of the second floating-point number.

[0085] For example, the floating-point number types of the first floating-point number and the second floating-point number are the same, the sum of the first exponent and the second exponent is obtained, and a preset exponent bias value corresponding to the floating-point number type of the first floating-point number and the second floating-point number is obtained; the exponent difference between the sum of the exponents and the preset exponent bias value is obtained, and the third exponent is determined as the exponent difference.

[0086] For example, the third exponent can be obtained by the following method :

[0087]

[0088] wherein, is the first exponent, is the second exponent, is a preset exponent bias value corresponding to the floating-point number type of the first floating-point number and the second floating-point number.

[0089] For example, if the first floating-point number and the second floating-point number are half-precision floating-point numbers, the preset exponent bias value is 15; if the first floating-point number and the second floating-point number are single-precision floating-point numbers, the preset exponent bias value is 127; if the first floating-point number and the second floating-point number are double-precision floating-point numbers, the preset exponent bias value is 1023.

[0090] In step 203, the shift bit number corresponding to the decimal part of the product is obtained according to the third exponent.

[0091] For example, in the case that the shift bit number includes a left shift bit number, the first leading zero number of the first floating-point number decimal part and the second leading zero number of the second floating-point number decimal part are obtained, and the first leading zero number and the second leading zero number are operated to obtain a third leading zero number. The left shift bit number is obtained according to the comparison result of the third exponent and the third leading zero number.

[0092] For example, in the case that the shift bit number includes a right shift bit number, the right shift bit number is directly obtained according to the third exponent.

[0093] In this embodiment, the number of shift bits corresponding to the fractional part of the product of the first floating-point number and the second floating-point number can be obtained based on the third exponent obtained from the first exponent and the second exponent. Since it is not necessary to calculate the number of shift bits based on the product, the steps of calculating the product and obtaining the number of shift bits can be performed in parallel, thereby saving computation time and reducing the number of cycles required for computation.

[0094] For example, in the case where the number of shifts includes the left shift, refer to Figure 4 Step 203 may include the following sub-steps:

[0095] Sub-step C1: Obtain the first number of leading zeros in the fractional part of the first floating-point number and the second number of leading zeros in the fractional part of the second floating-point number;

[0096] Among them, the decimal part of the floating-point number It can be expressed as follows:

[0097]

[0098] Based on the last digit The descriptive formula, if the exponent of the floating-point number A value of 0 indicates that the floating-point number is denormalized, and its fractional part is decima= If the exponent of the floating-point number Not equal to 0 indicates that the floating-point number is a normalized number, and its fractional part is decima= .

[0099] The fractional part of a floating-point number The value range is [0,2). The fractional part includes the mantissa part frac and a 1-bit integer implicit bit, which is either 1 or 0.

[0100] For example, methods for obtaining the first number of leading zeros of a first floating-point number and the second number of leading zeros of a second floating-point number may include at least two of the following:

[0101] Method 1: The number of leading zeros in the fractional part of the first floating-point number can be obtained using the following method. :

[0102]

[0103] In this context, {} represents a concatenation operation, and .orR represents an OR / reduction operation. The mantissa of the first floating-point number. It is the first exponent of the first floating-point number.

[0104] For example, the number of leading zeros in the fractional part of a second floating-point number can be obtained using the following method. :

[0105]

[0106] wherein, b is a mantissa part of the second floating-point number, is a second exponent of the second floating-point number.

[0107] Method two, the number of leading zeros of the floating-point number can be obtained according to the method shown in the following formula:

[0108]

[0109] According to the formula, when the exponent exp of the floating-point number ≠ 0, it indicates that the floating-point number is a normalized number, and the number of leading zeros of the floating-point number is equal to 0; when the exponent exp of the floating-point number = 0, it indicates that the floating-point number is a non-normalized number, and the number of leading zeros of the floating-point number is .

[0110] The first number of leading zeros of the first floating-point number and the second number of leading zeros of the second floating-point number can be obtained by method one or method two.

[0111] In an example, the operation of method two can be implemented using a one-level MUX (such as a two-way multiplexer), which replaces the or reduction operation on the exponent exp in method one, thereby reducing the processing time and achieving timing optimization of the floating-point multiplication operation.

[0112] In an example, sub-step C1 can include sub-steps C11 to C14:

[0113] Sub-step C11, if the first exponent of the first floating-point number is equal to zero, a first splicing result obtained by splicing zero and the mantissa of the first floating-point number is obtained, and the number of leading zeros of the first splicing result is determined as the first number of leading zeros of the decimal part of the first floating-point number.

[0114] Wherein, the splicing operation of 0 and the mantissa of the first floating-point number is , and the splicing result obtained is .

[0115] Sub-step C12, if the first exponent of the first floating-point number is not equal to zero, the first number of leading zeros of the decimal part of the first floating-point number is determined as zero.

[0116] Sub-step C13, if the second exponent of the second floating-point number is equal to zero, a second splicing result obtained by splicing zero and the mantissa of the second floating-point number is obtained, and the number of leading zeros of the second splicing result is determined as the second number of leading zeros of the decimal part of the second floating-point number.

[0117] Wherein, the splicing operation of 0 and the mantissa of the second floating-point number The splicing operation is The resulting splicing result is .

[0118] Sub-step C14: If the second exponent of the second floating-point number is not equal to zero, then determine that the number of the second leading zeros in the fractional part of the second floating-point number is zero.

[0119] In this embodiment, if the exponent of the floating-point number is not equal to zero, it indicates that the floating-point number is a normalized number. In this case, the fractional part of the floating-point number is... The number of leading zeros is zero. Therefore, if the exponent of a floating-point number is not zero, its number of leading zeros can be directly set to zero. If the exponent of a floating-point number is zero, it indicates that the floating-point number is denormalized. In this case, the fractional part of the floating-point number is zero. Since the number of leading zeros is not equal to zero, when the floating-point exponent is not equal to zero, the concatenation result of 0 and the floating-point mantissa is then obtained. The number of leading zeros in the floating-point number is determined and used as the number of leading zeros in the floating-point number. Compared to methods that perform OR and reduction operations on the exponent of a floating-point number and obtain the number of leading zeros based on the operation result, this embodiment does not require complex OR operations and has a short processing cycle.

[0120] Sub-step C2 performs an OR operation on the first and second leading zero counts to obtain the third leading zero count.

[0121] In this embodiment, the first number of leading zeros and the second number of leading zeros can also be added together to obtain the third number of leading zeros. This method can be expressed by the following formula:

[0122]

[0123] in, The number of leading zeros for the third time. The number of the first leading zeros, The number of the second leading zeros.

[0124] This embodiment is used to determine the number of left shift bits. When it is necessary to perform a left shift operation on the mantissa of the product of a first floating-point number and a second floating-point number based on the number of left shift bits, the product to be shifted must satisfy the left shift operation condition. When the left shift operation condition is satisfied, at least one of the first floating-point number and the second floating-point number is a normalized number. Therefore, the third leading zero quantity can also be obtained through the method in this step. The method in this step can be expressed by the following formula:

[0125]

[0126] In the embodiment, the processing of obtaining the third number of leading zeros can be time-optimized by using or operation instead of addition operation between the first number of leading zeros and the second number of leading zeros, thereby saving the time of obtaining the third number of leading zeros and reducing the number of processing cycles.

[0127] In the substep C3, the left shift number corresponding to the decimal part of the product is obtained according to the third exponent and the third number of leading zeros.

[0128] In the embodiment, the first number of leading zeros of the decimal part of the first floating-point number and the second number of leading zeros of the decimal part of the second floating-point number are or operated to obtain the third number of leading zeros, which is different from the method of determining the sum of the first number of leading zeros and the second number of leading zeros as the third number of leading zeros, thereby realizing time optimization of the operation process and reducing the time length of obtaining the third number of leading zeros.

[0129] For example, the substep C3 can include a substep C31 and a substep C32.

[0130] In the substep C31, if the third number of leading zeros is less than the third exponent, the third number of leading zeros is determined as the left shift number.

[0131] The third number of leading zeros is used to represent the number of leading zeros of the decimal part of the product without shifting the decimal part of the product of the first floating-point number and the second floating-point number.

[0132] In order to ensure that the exponent of the product after the shifting operation is greater than 0, if the third number of leading zeros is less than the third exponent, the third number of leading zeros is determined as the left shift number.

[0133] In the substep C32, if the third number of leading zeros is greater than or equal to the third exponent, the difference between the third exponent and the first preset exponent is determined as the left shift number.

[0134] For example, the first preset exponent is 1, and the left shift number can be obtained by the following method :

[0135]

[0136] wherein, is the third number of leading zeros, is the third exponent.

[0137] When , the decimal part of the product is shifted left by 1 bit each time, and the third exponent of the product needs to be reduced by 1, and the minimum value of the floating-point exponent is 1, so , and .

[0138] The maximum value of the left shift number is equal to the maximum value of , is the width of the mantissa of a floating point number. When is equal to , one of the operands is 0, and special case handling is performed.

[0139] In this embodiment, if the third number of leading zeros is less than the third exponent, the third number of leading zeros is determined as the left shift number; if the third number of leading zeros is greater than or equal to the third exponent, the difference between the third exponent and the first preset exponent is determined as the left shift number. In this way, it can be ensured that when the decimal part of the product is shifted according to the left shift number, the decimal part after the shift will not exceed the floating point number decimal value range, and the exponent of the product will not exceed the floating point number exponent value range after the carry according to the shift result.

[0140] In the example, in the case where the shift number includes the right shift number, referring to Figure 4 , step 203 can include sub-step D1:

[0141] Sub-step D1: the difference between the second preset exponent and the third exponent is determined as the right shift number corresponding to the mantissa of the product of the first floating point number and the second floating point number.

[0142] In the shift operation process, if , the shift operation is right shift, and the exponent of the product needs to be incremented by 1 once for every right shift by one bit. The second preset exponent can be determined as 1, and the method of obtaining the right shift number may include:

[0143]

[0144] In this embodiment, the difference between the second preset exponent and the third exponent is determined as the right shift number corresponding to the decimal part of the product, which can ensure that when the decimal part of the product is shifted according to the right shift number, the decimal part after the shift will not exceed the floating point number decimal value range, and the exponent of the product will not exceed the floating point number exponent value range after the carry according to the shift result.

[0145] Step 204: if the third exponent is greater than zero, it is determined that the shift direction is left shift.

[0146] If the third exponent is greater than zero, it is determined that the to-be-shifted operation of the product satisfies the left shift operation condition, and it is determined that the shift direction is left shift.

[0147] In an example, the method further comprises: obtaining the third exponent of the product according to the first exponent of the first floating-point number and the second exponent of the second floating-point number; and in an example, the third exponent can be obtained according to the method shown in step 202.

[0148] In an example, the left shift corresponds to a left shift operation condition may be expressed as:

[0149]

[0150] wherein, is the third exponent. In other words, if the third exponent is greater than 0, it is determined that the decimal part meets the left shift condition, and the shift direction is left shift.

[0151] In step 205, if the third exponent is less than or equal to 0, it is determined that the shift direction is right shift.

[0152] If it is determined that the to-be-shifted operation of the product meets the right shift operation condition according to the third exponent, it is determined that the shift direction is right shift.

[0153] According to the third exponent, it is determined whether the to-be-shifted operation of the product meets the left shift operation condition or the right shift operation condition, and the shift direction is obtained according to the determination result. Therefore, it is not necessary to analyze the shift direction after obtaining the product, and the multiplication time and multiplication period are shortened.

[0154] In an example, the method further comprises: obtaining the third exponent of the product according to the first exponent of the first floating-point number and the second exponent of the second floating-point number; and in an example, the left shift corresponds to a left shift operation condition may be expressed as:

[0155]

[0156] In an example, if the first floating-point number and the second floating-point number are both non-normalized numbers, the third exponent obtained according to the first exponent of the first floating-point number and the second exponent of the second floating-point number is less than 0, and the shift operation does not meet the left shift operation condition. In other words, if the first floating-point number and the second floating-point number are both non-normalized numbers, the shift operation meets the right shift condition.

[0157] After the decimal part of the product is left shifted, the third exponent of the product needs to be reduced by a value equal to the number of left shifts; after the mantissa of the product is right shifted, the third exponent of the product needs to be increased by a value equal to the number of right shifts. In this embodiment, if the third exponent is greater than zero, it is determined that the to-be-shifted operation of the product satisfies the left shift condition; if the third exponent is less than or equal to zero, it is determined that the to-be-shifted operation of the product satisfies the right shift condition, so that it can be ensured that the exponent corresponding to the processed operation will not exceed the floating-point number exponent range after the decimal part of the product is shifted according to the determined shift condition.

[0158] In step 206, the decimal part of the product is shifted according to the shift number and the shift direction, to obtain the multiplication result of the first floating-point number and the second floating-point number.

[0159] For example, the decimal part of the product is shifted according to the shift direction, and the number of shifts is equal to the shift number corresponding to the shift direction.

[0160] For example, the width of the shift number can only be truncated The data after truncation of the left shift number and the right shift number are and , respectively.

[0161] Left shift and right shift are mutually exclusive. After the left shift number and the right shift number are calculated, the two shift numbers can be stored in a register, and the shift number corresponding to the shift direction can be extracted from the register after the shift direction is determined. Alternatively, only the shift number corresponding to the shift direction can be stored in the register:

[0162]

[0163]

[0164]

[0165] For example, the present application also provides a method for obtaining the sign of the product of the first floating-point number and the second floating-point number. The method for obtaining the sign is exemplarily described as follows:

[0166] The binary representation of the floating-point number can be described as follows:

[0167]

[0168] wherein, is the value of the sign part, is the value of the exponent part, ​The value of the complete mantissa part is the value of the complete mantissa part including the digit before the decimal point and the mantissa part frac after the decimal point.

[0169] The value of the sign part is The value of the sign part can be expressed as follows:

[0170]

[0171] In the expression, sign is the binary representation of the sign part of the floating-point number, The value of the sign part of the floating-point number is

[0172] In the binary representation of the floating-point number, if the sign number sign = 0, it indicates that the sign of the floating-point number is positive; if the sign number sign = 1, it indicates that the sign of the floating-point number is negative.

[0173] For example, the sign of the product is obtained according to the following formula :

[0174]

[0175] That is, the first sign of the first floating-point number and the second sign of the second floating-point number are subjected to an exclusive-OR operation, and the sign of the product is obtained.

[0176] For example, when the method according to the foregoing embodiment is used to obtain a shift operation on the product, the exponent of the product needs to be adjusted correspondingly. For example, when the mantissa of the product is subjected to a left shift operation, the exponent of the product needs to be reduced, and the reduced exponent is equal to the number of left shifts; when the mantissa of the product is subjected to a right shift operation, the exponent of the product needs to be increased, and the increased exponent is equal to the number of right shifts. The method for obtaining the exponent of the product is described exemplarily as follows:

[0177] The value of the exponent part of the floating-point number is The value of the exponent part of the floating-point number can be expressed as follows:

[0178]

[0179] wherein, is the exponent bias of the floating-point number, for example, if the floating-point number is a half-precision floating-point number, is equal to 15; if the floating-point number is a single-precision floating-point number, is equal to 127; if the floating-point number is a double-precision floating-point number, is equal to 1023.

[0180] The value of the exponent part is processed as follows: The signed exponent is obtained: ​

[0181]

[0182] is the exponent of the floating point number, is the number of leading zeros of the fractional part of the floating point number. is the result of the number of leading zeros of the fractional part acting on the exponent part when the floating point number is not normalized, is a signed number, which can be negative.

[0183]

[0184]

[0185] The value of the third exponent of the normalized product is given by the following equation where, and are the value of the first exponent of the first floating point number and the value of the second exponent of the second floating point number, respectively. and are the first exponent and the second exponent, respectively. Further, the third exponent of the product is:

[0186]

[0187] Further, the signed third exponent of the product is:

[0188]

[0189] where, and are the signed exponent of the first floating point number and the signed exponent of the second floating point number, respectively.

[0190] The bit width of the is 3 bits more than the bit width of the exponent The extra 3 bits include 1 bit for calculating and , 1 bit for calculating the sum of and , and 1 bit for calculating the subtraction .

[0191] where, in the case that is less than 0, the exponent is adjusted to 0; in the case that is greater than the exponent limit value , the exponent is adjusted to , to ensure that the signed exponent of the product is within the range of the exponent of the floating point number.

[0192] Furthermore, when no carry is applied to the exponent of the product of the first and second floating-point numbers, the initial exponent of the product is... for:

[0193]

[0194] According to this calculation formula, if Then determine the initial exponent. If it is 0; Then determine the initial exponent. for If neither of the following conditions are met Not satisfied Then determine the initial exponent. for .

[0195] Based on the values ​​of the aforementioned index section The descriptive formula for the floating-point number is: if the exponent exp equals 0, then the value of the exponent part is... = If the exponent of a floating-point number is not equal to 0, then the value of the exponent part... = .

[0196] If the floating-point number belongs to the first numeric type, the range of its exponent part exp is:

[0197]

[0198] The first number type is any number other than the second number type. The second number type includes: zero (0), not a number (NaN), and infinity (INF). and These are the lower and upper limits of the floating-point exponent part exp, respectively.

[0199] Among them, the values ​​of the exponent when exp=0 and exp=1 are... The values ​​are equal, and both are:

[0200] =

[0201] Correspondingly, if the floating-point number belongs to the first numeric type, then the value of its exponent part is... The range of values ​​for is:

[0202]

[0203] in, and The values ​​of the exponent are respectively The lower limit and upper limit.

[0204] Based on the above description of the values ​​of the exponent part of a floating-point number, the exponent exp of a floating-point number is equal to 0 or 1, and its exponent part value... All equal to .

[0205] Correspondingly, the value of the exponent part It can be expressed as follows:

[0206]

[0207] For example, the method in this embodiment may further include the following steps:

[0208] Step 207: If the first floating-point number and / or the second floating-point number belongs to the second number type, then according to the multiplication operation strategy corresponding to the second number type, obtain the multiplication result of the first floating-point number and the second floating-point number.

[0209] The second number type includes: zero, non-digits, and infinite numbers.

[0210] If the first floating-point number and / or the second floating-point number belong to the second number type, then the product of the first floating-point number and the second floating-point number is obtained according to the multiplication operation strategy corresponding to the second number type. In this way, the step of analyzing the number of shifts according to the method of steps 201 to 206 can be avoided when the first floating-point number and / or the second floating-point number belong to the second number type and their product does not need to be shifted. This shortens the processing time and the multiplication operation cycle.

[0211] For example, multiplication strategies include:

[0212] If the first floating-point number and / or the second floating-point number are not numbers, then the result of the multiplication of the first floating-point number and the second floating-point number is determined to be equal to the preset value.

[0213] The method for determining whether the first and second floating-point numbers are NOT numbers can be expressed by the following formula:

[0214]

[0215]

[0216] in, The result of determining if the first floating-point number and / or the second floating-point number is not a number. Represents the first floating-point number Yes or no numbers, Represents the second floating-point number Are or are not numbers; Represents the first floating-point number is 0, represents the second floating-point number is an infinite number; represents the second floating-point number is 0, represents the first floating-point number is an infinite number.

[0217] If the first floating-point number and the second floating-point number are both zero, or one of the first floating-point number and the second floating-point number is zero and the other is a number type other than the infinite number and the zero number, it is determined that the multiplication result of the first floating-point number and the second floating-point number is equal to zero.

[0218] The method for determining whether the first floating-point number and / or the second floating-point number is zero can be expressed as follows:

[0219]

[0220] is the determination result of whether the first floating-point number and / or the second floating-point number is zero, represents that the first floating-point number and the second floating-point number do not satisfy the condition that the first floating-point number and / or the second floating-point number is a non-number.

[0221] If the first floating-point number and the second floating-point number are both infinite numbers, or one of the first floating-point number and the second floating-point number is an infinite number and the other is a number type other than the infinite number and the zero number, it is determined that the multiplication result of the first floating-point number and the second floating-point number is equal to infinity.

[0222] The method for determining whether the first floating-point number and / or the second floating-point number is an infinite number can be expressed as follows:

[0223]

[0224] is the determination result of whether the first floating-point number and / or the second floating-point number is an infinite number.

[0225] In the present embodiment, if one of the first floating-point number and the second floating-point number is a non-number NaN or zero, and the other is multiplied by an infinite number, the multiplication result of the first floating-point number and the second floating-point number is a non-number; if one of the first floating-point number and the second floating-point number is zero, and both of the floating-point numbers are not non-numbers, the multiplication result is 0; if one of the first floating-point number and the second floating-point number is an infinite number, the multiplication result is an infinite number.

[0226] For example, if the first floating-point number and / or the second floating-point number is a non-number, different preset strategies can be used to obtain the sign of the product. Further, the corresponding product can be obtained based on the method in the RISC-V instruction set. :

[0227]

[0228] wherein, represents an exponent width corresponding to the floating-point number type of the first floating-point number and the second floating-point number; represents a mantissa width corresponding to the floating-point number type of the first floating-point number and the second floating-point number.

[0229] According to the expression of the product , if the first floating-point number, and / or the second floating-point number is a non-number, the product with the sign of 0, the sign bit followed by ones, and zeros after the ones can be obtained; in other words, the data of each bit of the cNaN sign bit is 0, the data of each bit of the exponent bit is 1, the highest bit of the mantissa is 1, and the data of the other bits is 0.

[0230] wherein, if the floating-point number type is a half-precision floating-point number, equals 5; if the floating-point number type is a single-precision floating-point number, equals 8; if the floating-point number type is a double-precision floating-point number, equals 11.

[0231] wherein, if the floating-point number type is a half-precision floating-point number, equals 11; if the floating-point number type is a single-precision floating-point number, equals 23; if the floating-point number type is a double-precision floating-point number, equals 52.

[0232] According to the sign of the floating-point number, if the first floating-point number, and / or the second floating-point number is zero, and the first floating-point number and the second floating-point number are both of other number types except for non-numbers and infinities, the product zero of the first floating-point number and the second floating-point number can be obtained as follows:

[0233] =

[0234] According to the expression of the product zero, if the first floating-point number, and / or the second floating-point number is zero, the sign of the zero is sign, and the data of the other bits is 0.

[0235] According to the sign of the floating-point number, if the first floating-point number, and / or the second floating-point number is an infinity, the product of the first floating-point number and the second floating-point number can be obtained as follows:

[0236]

[0237] According to the expression of the product inf, if the first floating-point number and / or the second floating-point number is an infinite number, the value of the sign bit of the floating-point multiplication result is equal to sign, the bit data of the exponent is all 1, and the bit data of the mantissa is all 0.

[0238] In an example, a one-hot selector or a multiplexer can be used to determine that the first floating-point number and / or the second floating-point number belongs to the second number type, and the multiplication result of the first floating-point number and the second floating-point number can be determined according to the following formula:

[0239]

[0240]

[0241] wherein, is the total width of the floating-point number, for example, the floating-point number is a half-precision floating-point number, is equal to 16; the floating-point number is a single-precision floating-point number, is 32; the floating-point number is a double-precision floating-point number, is 64,

[0242] According to the expression of the multiplication result , if the floating-point number is the second number type, the total width of the corresponding multiplication result is obtained according to the above formula.

[0243] In an example, the final multiplication result can be obtained according to the following formula:

[0244]

[0245] According to the above examples, the multiplication result of the first floating-point number and the second floating-point number can be represented as:

[0246]

[0247] wherein, represents the multiplication result when the first floating-point number and the second floating-point number are both the first number type.

[0248] ​The multiplication result of the first floating-point number and the second floating-point number in the first number type is obtained according to the method of steps 201 to 206, and the multiplication result of the first floating-point number and the second floating-point number in the second number type is obtained according to the method of steps 206 to 207. The two cases can be started in parallel, and the multiplication result is obtained according to the corresponding method according to the number type of the first floating-point number and the second floating-point number.

[0249] According to the method of the embodiment, the product of the first floating-point number and the second floating-point number can be accurately and quickly obtained, the operation time is short, and the number of operation cycles is less.

[0250] For example, with reference to Figure 5 The method of floating-point multiplication of the first floating-point number and the second floating-point number can also include the following steps:

[0251] Step S1, the first symbol of the first floating-point number and the second symbol of the second floating-point number are processed, and the symbol result of the multiplication result is obtained.

[0252] Step S2, the first exponent of the first floating-point number and the second exponent of the second floating-point number are processed, and the exponent of the product of the first floating-point number and the second floating-point number before the shift processing is obtained.

[0253] Step S3, the shift parameter of the decimal part of the product of the first floating-point number and the second floating-point number is calculated.

[0254] The method of steps S1 to S3 can be implemented by any of the foregoing embodiments, which will not be repeated here.

[0255] Step S4, the decimal multiplication result of the product of the first floating-point number and the second floating-point number is obtained.

[0256] Step S5, the special result of the multiplication of the special number when the first floating-point number and / or the second floating-point number is a special number.

[0257] The method of multiplying the special number is shown in the above embodiments, which will not be repeated here.

[0258] Steps S1 to S5 can be processed in parallel, thereby saving processing and reducing the processing period of the floating-point multiplication.

[0259] Step S6, according to the shift value and the decimal multiplication result, the carry detection is performed.

[0260] Step S7, according to the carry detection result and the exponent of the product before the shift processing, the first exponent carry processing is performed.

[0261] Step S8, according to the value to be shifted and the decimal multiplication result, decimal shifting is performed.

[0262] The steps S6 to S8 can be processed in parallel, thereby saving processing implementation and reducing processing period of floating point multiplication operation.

[0263] Optionally, the first exponent of the first floating point number and the second exponent of the second floating point number are obtained, and the value to be shifted parameter for the value to be shifted operation on the decimal part of the product of the first floating point number and the second floating point number is obtained according to the first exponent and the second exponent; the value to be shifted parameter includes a shifting direction and a shifting bit number; in the process of obtaining the shifting result of the product according to the value to be shifted parameter, the overflow information of the decimal part of the shifting result is obtained according to the value to be shifted parameter; the overflow information includes overflow or no overflow; and the exponent of the shifting result is adjusted according to the overflow information to obtain the multiplication result of the first floating point number and the second floating point number.

[0264] Optionally, in the case that the shifting direction is left shifting and the shifting bit number includes a left shifting number, the overflow information of the decimal part of the shifting result is obtained according to the value to be shifted parameter, including: obtaining an initial mask; the highest bit of the initial mask is 1, and the other bits are 0; the value of the highest bit of the initial mask is shifted right to obtain a shifting mask according to the left shifting number; the shifting mask and the product are ANDed to obtain an AND operation result; and the overflow information of the decimal part of the shifting result is obtained according to the AND operation result.

[0265] Optionally, the overflow information of the decimal part of the shifting result is obtained according to the AND operation result, including: the OR reduction operation is performed on the AND operation result to obtain an OR reduction operation result; and the overflow information of the decimal part of the shifting result is obtained according to the OR reduction operation result.

[0266] Optionally, the overflow information of the decimal part of the left shifting result is obtained according to the OR reduction operation result, including: the third exponent of the product is obtained according to the first exponent and the second exponent; the first overflow information of the shifting result is obtained according to the third exponent; if the OR reduction operation result is 1 and the first overflow information is overflow, it is determined that the overflow information of the decimal part of the shifting result is overflow; and if the OR reduction operation result is 0 or the first overflow information is no overflow, it is determined that the overflow information of the decimal part of the shifting result is no overflow.

[0267] Optionally, the first overflow information of the shifting result is obtained according to the third exponent, including: the first number of leading zeros of the first floating point number and the second number of leading zeros of the second floating point number are obtained; the third number of leading zeros of the product is obtained according to the first number of leading zeros and the second number of leading zeros; and the first overflow information of the shifting result is obtained according to the comparison result of the third exponent and the third number of leading zeros.

[0268] Optionally, the shift mask and the product are subjected to an AND operation to obtain an AND operation result, including:

[0269] The shift mask and the product are subjected to an AND operation to obtain an initial AND operation result; data from the highest bit to the first bit of the initial AND operation result is intercepted to obtain the AND operation result; wherein the total number of bits from the highest bit to the first bit of the initial AND operation result is equal to the width of the mantissa of the preset floating-point type.

[0270] Optionally, according to the left shift number, the value of the highest bit of the initial mask is right shifted to obtain the shift mask, including: according to the first exponent and the second exponent, a third exponent of the product is obtained; if the third exponent is equal to zero, the value of the highest bit of the initial mask is right shifted according to a first shift value to obtain the shift mask; the first shift value is equal to the sum of the left shift number and 1; if the third exponent is not equal to zero, the value of the highest bit of the initial mask is right shifted according to the left shift number to obtain the shift mask.

[0271] Optionally, in the case that the shift direction includes right shift and the shift bit number includes right shift number, according to the parameter to be shifted, the overflow information of the decimal part of the shift result is obtained, including: if the value of the highest bit of the decimal part of the product is equal to 1 and the right shift number is equal to 1, it is determined that the decimal part of the shift result overflows; if the value of the highest bit of the decimal part of the product is equal to 0 or the right shift number is not equal to 1, it is determined that the decimal part of the shift result does not overflow.

[0272] Optionally, according to the overflow information, the exponent of the shift result is adjusted to obtain the multiplication result of the first floating-point number and the second floating-point number, including: if the overflow information is no overflow, or the value of each bit of the third exponent of the product is 1, the exponent is kept unchanged; if the overflow information is overflow, and the value of at least one bit of the third exponent of the product is equal to 0, the exponent is subjected to a carry operation.

[0273] Optionally, the method further includes: obtaining a first mantissa of the first floating-point number and a second mantissa of the second floating-point number; obtaining a first partial product according to the first mantissa and the second mantissa; compressing the first partial product to obtain a first compression result, and obtaining a second partial product of the first implicit bit of the first floating-point number and the second implicit bit of the second floating-point number in the process of compressing the first partial product; obtaining the product of the first floating-point number and the second floating-point number according to the first compression result and the second partial product.

[0274] Optionally, the overflow information acquisition unit, the to-be-shifted parameter acquisition unit, and the index adjustment unit are included; the overflow information acquisition unit is connected to the to-be-shifted parameter acquisition unit and the index adjustment unit; the to-be-shifted parameter acquisition unit is configured to acquire a first index of the first floating-point number and a second index of the second floating-point number; the to-be-shifted parameter acquisition unit is further configured to acquire, according to the first index and the second index, a to-be-shifted parameter for performing a to-be-shifted operation on a decimal part of a product of the first floating-point number and the second floating-point number; the to-be-shifted parameter includes a shift direction and a shift bit number; the overflow information acquisition unit is configured to acquire, in a process of acquiring a shift result of the product according to the to-be-shifted parameter, overflow information of a decimal part of the shift result according to the to-be-shifted parameter; the overflow information includes overflow or no overflow; and the index adjustment unit is configured to adjust, according to the overflow information, an index of the shift result to obtain a multiplication result of the first floating-point number and the second floating-point number.

[0275] Optionally, in the case where the shift direction is left shift and the shift bit number includes a left shift number, the overflow information acquisition unit includes a shift mask acquisition subunit, a first AND operation subunit connected to the shift mask acquisition subunit, and a left shift operation overflow information acquisition subunit connected to the first AND operation subunit; the shift mask acquisition subunit is configured to acquire an initial mask and shift a value of a highest bit of the initial mask to the right to obtain a shift mask according to the left shift number; the value of the highest bit of the initial mask is 1 and values of other bits are 0; the first AND operation subunit is configured to perform AND operation on the shift mask and the product to obtain an AND operation result; and the left shift operation overflow information acquisition subunit is configured to acquire, according to the AND operation result, the overflow information of the decimal part of the shift result.

[0276] Step S9, after the decimal shift, the mantissa is rounded to obtain a mantissa of the product.

[0277] Step S10, according to the first index carry processing result and the mantissa rounding result, the second index carry processing is performed on the result after the mantissa rounding to obtain an index of the product after the shift operation.

[0278] Step S11, according to the sign, the index, and the mantissa of the product, the product of the first floating-point number and the second floating-point number is obtained, and the product is a normal result.

[0279] Step S12, according to the mantissa of the product, the mantissa rounding result, and whether the floating-point number is a special number, a special result is obtained.

[0280] Step S13, according to the normal result and the special result, the final multiplication result of the first floating-point number and the second floating-point number is obtained.

[0281] Optionally, a shift result of the product of the first floating-point number and the second floating-point number is obtained; the shift result is a result of a shift operation on a decimal part of the product; a mantissa rounding operation is performed on the shift result to obtain a mantissa rounding result of the shift result; a first judgment result of whether the mantissa of the shift result satisfies a first preset rounding condition is obtained in the process of performing the mantissa rounding operation; if the first judgment result is that the mantissa satisfies the first preset rounding condition, a target mantissa of a multiplication result of the first floating-point number and the second floating-point number is obtained according to the mantissa rounding result.

[0282] Optionally, obtaining the first judgment result of whether the mantissa satisfies the first preset rounding condition comprises: obtaining a first parameter of the shift result; the first parameter comprises at least one of a value of a first reserved bit of the shift result, a value of a first rounding bit, and a value of a first sticky bit; and the first judgment result of whether the mantissa satisfies the first preset rounding condition is obtained according to the first parameter.

[0283] Optionally, in a case where the shift operation comprises a right shift operation, the value of the first sticky bit is obtained by: obtaining a shift mask; data of the shift mask from a second position of the shift mask to a lowest bit of the shift mask is 1, and data of other bits of the shift mask is 0; a total number of bits from the second position to the lowest bit of the shift mask is equal to a right shift number of the right shift operation on the decimal part of the product; first data from a third position of the decimal part of the product to a lowest bit of the product is obtained; a total number of bits from the third position to the lowest bit of the product is equal to a difference between the total width corresponding to the preset floating-point number type and 1; a result of an AND operation on the shift mask and the first data is obtained; and a value of the first sticky bit corresponding to the right shift operation is obtained by performing an OR reduction operation on the result of the AND operation.

[0284] Optionally, the mantissa rounding operation is performed on the shift result to obtain the mantissa rounding result of the shift result, comprising: a preset mantissa of the shift result is subjected to the mantissa rounding operation to obtain the mantissa rounding result of the shift result; wherein, if the shift result satisfies a first condition, the preset mantissa comprises: data of the shift result from a fourth position to a lowest bit; a total number of bits from the fourth position to the lowest bit of the shift result is equal to a sum of a mantissa bit width corresponding to the preset floating-point number type and 1; the first condition comprises: the shift operation is a left shift operation, the decimal part of the product overflows, and the exponent of the product is not equal to 0; if the shift result does not satisfy the first condition, the preset mantissa comprises: a zero padding result of low-bit zero padding operation on data of the shift result from a fifth position to a lowest bit; a total number of bits from the fifth position to the lowest bit of the shift result is equal to the mantissa bit width corresponding to the preset floating-point number type.

[0285] Optionally, the mantissa rounding operation is performed on the shift result to obtain a mantissa rounding result of the shift result, including: performing a plus 1 operation on data from a highest bit to a sixth bit of the preset mantissa to obtain the mantissa rounding result of the shift result; wherein a total number of bits from the highest bit to the sixth bit of the preset mantissa is equal to a mantissa width of the preset floating-point number type.

[0286] Optionally, the method further includes: if the first judgment result is that the mantissa does not satisfy the first preset rounding condition, obtaining a target mantissa of the multiplication result of the first floating-point number and the second floating-point number according to the preset mantissa.

[0287] Optionally, the method further includes: obtaining overflow information of the exponent of the shift result; if the overflow information is no overflow and the first judgment result is that the mantissa does not satisfy the first preset rounding condition, the method further includes: determining data from a highest bit to a sixth bit of the preset mantissa as the target mantissa of the multiplication result; and a total number of bits from the highest bit to the sixth bit of the preset mantissa is equal to a mantissa width of the preset floating-point number type.

[0288] Optionally, the method further includes: obtaining overflow information of the exponent of the shift result; if the overflow information is no overflow and the first judgment result is that the mantissa satisfies the first preset rounding condition, obtaining the target mantissa of the multiplication result of the first floating-point number and the second floating-point number according to the mantissa rounding result, including: determining the mantissa rounding result as the target mantissa of the multiplication result.

[0289] Optionally, the method further includes: obtaining the overflow information of the exponent of the shift result; if the overflow information is overflow, determining the preset target mantissa as the target mantissa of the multiplication result; wherein if the preset rounding mode is a rounding mode other than a rounding mode to zero, a rounding mode of positive numbers down and a rounding mode of negative numbers up, a total number of bits of the preset target mantissa is equal to a mantissa bit width corresponding to the preset floating-point number type, and each bit value is 0; if the preset rounding mode is the rounding mode to zero, the rounding mode of positive numbers down or the rounding mode of negative numbers up, the total number of bits of the preset target mantissa is equal to the mantissa bit width corresponding to the preset floating-point number type, and each bit value is 1.

[0290] Optionally, the method further includes: obtaining the exponent of the shift result and performing an exponent carry operation on the exponent of the shift result to obtain an exponent carry result; in the process of performing the exponent carry operation, obtaining a second judgment result of whether the exponent of the shift result satisfies a first preset carry condition; if the second judgment result is that the exponent satisfies the first preset carry condition, obtaining the target exponent of the multiplication result of the first floating-point number and the second floating-point number according to the exponent carry result; if the second judgment result is that the exponent does not satisfy the first preset carry condition, obtaining the target exponent of the multiplication result of the first floating-point number and the second floating-point number according to the exponent.

[0291] Optionally, the second judging result of whether the exponent of the shift result satisfies the first preset carry condition comprises: if the mantissa of the shift result satisfies the first preset rounding condition, and the values of the preset mantissa from the highest bit to the sixth bit are all 1, it is determined that the second judging result is that the exponent of the shift result satisfies the first preset carry condition; the total number of bits from the highest bit to the sixth bit of the preset mantissa is equal to the mantissa width of the preset floating-point number type; if the mantissa of the shift result does not satisfy the first preset rounding condition, or the value of any bit of the preset mantissa from the highest bit to the sixth bit is 0, it is determined that the second judging result is that the exponent of the shift result does not satisfy the first preset carry condition.

[0292] Optionally, the method further comprises: obtaining overflow information of the exponent of the shift result; if the overflow information is overflow, the preset target exponent is determined as the target exponent of the multiplication result; wherein if the preset rounding mode is a rounding mode other than the rounding to zero mode, rounding down for positive numbers and rounding up for negative numbers, the preset target exponent is an exponent with a total bit number equal to the exponent bit width of the preset floating-point number and the values of all bits being equal to 1; if the preset rounding mode is the rounding to zero mode, the rounding down for positive numbers or the rounding up for negative numbers, the preset target exponent is an exponent with a total bit number equal to the exponent bit width of the preset floating-point number, the value of the lowest bit being 0 and the values of the other bits being all 1.

[0293] Optionally, the method further comprises: obtaining overflow information of the exponent of the shift result; if the overflow information is no overflow, and the second judging result is that the exponent satisfies the first preset carry condition, the multiplication result of the first floating-point number and the second floating-point number is obtained according to the carry result of the exponent, comprising: the carry result of the exponent is determined as the target exponent of the multiplication result; if the overflow information is no overflow, and the second judging result is that the exponent does not satisfy the first preset carry condition, the multiplication result of the first floating-point number and the second floating-point number is obtained according to the exponent, comprising: the exponent of the shift result is determined as the target exponent of the multiplication result.

[0294] Optionally, the method further comprises: obtaining overflow information of the exponent of the shift result; if the overflow information of the exponent is overflow, it is determined that the sign bit of the multiplication result is overflow; if the shift result satisfies any one of the second conditions, it is determined that the sign bit of the multiplication result is inaccuracy; the second conditions comprise: the overflow information is overflow, the values of the first rounding bit and the first sticky bit of the shift result are 1; if the exponent of the product is equal to 0, and the exponent of the shift result does not satisfy the preset second carry condition, and the shift result satisfies any one of the second conditions, it is determined that the sign bit of the multiplication result is underflow.

[0295] Optionally, the method further comprises: if the values of the exponent from the highest bit to the first bit are all 1, and the exponent satisfies a third condition, determining that the overflow information is an overflow; the third condition comprises that the value of the lowest bit of the exponent is 1, or the exponent satisfies a first preset carry condition; if the shift result does not satisfy the third condition, determining that the exponent of the shift result does not satisfy a second preset carry condition, and the third condition comprises that the values of the preset mantissa of the fractional part of the shift result from the highest bit to the sixth bit are all 1, the value of the second reserved bit of the shift result is 1, and the mantissa of the shift result satisfies a second preset rounding condition.

[0296] Optionally, the method further comprises: obtaining a second parameter of the shift result; the second parameter comprises at least one of the following: a value of a second reserved bit of the shift result, a value of a second rounding bit, and a value of a second sticky bit; and obtaining a third determination result of whether the mantissa satisfies the second preset rounding condition according to the second parameter; the value of the second reserved bit is a value of the preset mantissa at a seventh bit; a position interval between the seventh bit and the lowest bit of the mantissa is equal to a sum of a mantissa bit width of the preset floating-point number type and 1; the value of the second rounding bit is a value of the preset mantissa at an eighth bit; a total number of bits from the eighth bit to the lowest bit of the preset mantissa is equal to the mantissa bit width of the preset floating-point number type; in a case where the shift operation is a left shift, the value of the second sticky bit is an or reduction operation result of data of the preset mantissa from a ninth bit to the lowest bit; a total number of bits from the ninth bit to the lowest bit of the preset mantissa is equal to a difference between the mantissa bit width of the preset floating-point number type and 1; in a case where the shift operation is a right shift, the value of the second sticky bit is equal to the value of the first sticky bit corresponding to the right shift operation.

[0297] The method for obtaining the special result is as described in the foregoing embodiments, which will not be repeated here.

[0298] By the embodiment, the problem of long processing period caused by serial processing of each part of the floating-point number is avoided. In the related art, the multiplication of the half-precision floating-point number, the multiplication of the single-precision floating-point number, and the multiplication of the double-precision floating-point number all need three periods. Based on the embodiment, the processing time can be shortened, and the operation period of the multiplication of the half-precision floating-point number and the multiplication of the single-precision floating-point number can be shortened to two. For the multiplication of the double-precision floating-point number, the operation can be completed in a half period of the third period, that is, based on the embodiment, the number of periods of the floating-point multiplication operation can be shortened.

[0299] In one embodiment, refer to Figure 6For multiplication of double-precision floating-point numbers (f64), three periods can be used for processing, the first period is used for parallel execution of steps S1 to S5, and the processing result is stored in the corresponding register 1. The second period is used to obtain the data of steps S6 to S8, and the data is stored in the corresponding register 2. Steps S9 to S13 are executed in the third period. Based on the method of the embodiment, the third period is calculated in half a period, and the data can be bypassed to other functional units for fast wake-up.

[0300] With reference to the foregoing Figure 6 The multiplication of decimal numbers is implemented by using the fast Booth and setting compression method, the partial product is stored in the register 1, and the partial product is added to obtain the product, and then the decimal shift operation of step S8 is performed on the product. The setting compression method is the carry-saved adder (CSA) method.

[0301] In one embodiment, with reference to the foregoing Figure 7 For multiplication of half-precision floating-point numbers (f16) and single-precision floating-point numbers (f32), the operation period can be shortened to two periods. The first period is used for parallel execution of steps S1 to S5, and the processing result is stored in the corresponding register (Reg); the second period is used for execution of the method of steps S6 to S13. Based on the method of the embodiment, the second period is calculated in half a period, and the data can be bypassed to other functional units for fast wake-up.

[0302] In combination with Figure 6 and Figure 7 The difference between the two processing methods is that Figure 7 The embodiment can calculate the product of floating-point numbers by using the multiplication sign, Figure 6 The embodiment shown in the figure obtains the product of floating-point numbers by using the fast Booth and CSA compression method.

[0303] It should be noted that f64 can also be implemented by using the two-period processing method shown in the figure, and f32 and f16 can also be implemented by using the three-period processing method shown in the figure. Figure 7 Figure 6 It should be noted that f64 can also be implemented by using the two-period processing method shown in the figure, and f32 and f16 can also be implemented by using the three-period processing method shown in the figure.

[0304] The embodiment optimizes the timing of the floating-point multiplication calculation method, and designs a pipeline to reduce the floating-point multiplication calculation period of f32 and f16 in the processor to two periods and f64 to three periods, and all can support fast wake-up. The embodiment can shorten the calculation period of floating-point multiplication, improve the performance of the processor in executing floating-point multiplication instructions, and is not limited to the processor, but also can improve the calculation performance in other calculation fields that need to use floating-point multiplication.

[0305] ​For example, based on the method of the embodiment, in the application scenario of performing half-precision floating-point multiplication and single-precision floating-point multiplication based on a CPU processor, the number of periods of floating-point multiplication in the related art is reduced from 3 to 2, and the total number of periods is reduced by 33.3%.

[0306] The embodiment shows a floating-point multiplication circuit, as shown in the circuit can include: a shift parameter calculation unit 301, a first multiplexer (MUX) 302, a second multiplexer 303, a product calculation unit 304, and a shift operation unit 305; the first multiplexer 301 and the second multiplexer 303 are connected to the shift parameter calculation unit 301, and the shift parameter calculation unit 301 is connected to the product calculation unit 304 and the shift operation unit 305. Figure 8

[0307] The first multiplexer 302 is configured to obtain a first exponent of a first floating-point number, and the second multiplexer 303 is configured to obtain a second exponent of a second floating-point number; the shift parameter calculation unit 301 is configured to obtain a to-be-shifted parameter for performing a shift operation on a decimal part of a product of the first floating-point number and the second floating-point number according to the first exponent and the second exponent in a process in which the product calculation unit 304 calculates the product of the first floating-point number and the second floating-point number; the to-be-shifted parameter includes a shift bit number and a shift direction.

[0308] The shift operation unit 305 is configured to perform the shift operation on the decimal part of the product according to the shift bit number and the shift direction, to obtain a multiplication result of the first floating-point number and the second floating-point number.

[0309] Based on the floating-point multiplication circuit of the embodiment, the first exponent of the first floating-point number and the second exponent of the second floating-point number are obtained through the first multiplexer and the second multiplexer, in a process in which the product calculation unit calculates the product of the first floating-point number and the second floating-point number, the shift parameter calculation unit obtains a to-be-shifted parameter corresponding to a mantissa of the product of the first floating-point number and the second floating-point number according to the first exponent and the second exponent, and the shift operation unit performs the shift operation on the decimal part of the product according to the to-be-shifted bit number and the shift direction, to obtain the multiplication result of the first floating-point number and the second floating-point number. The embodiment does not need to obtain the to-be-shifted value according to the product after obtaining the product of the first floating-point number and the second floating-point number, and the method of obtaining the shift value according to the product in the related art is reduced. The time of floating-point multiplication is reduced, and the operation period of floating-point multiplication is reduced.

[0310] ​For example, the shift parameter calculation unit includes a product exponent acquisition subunit and a shift number acquisition subunit connected to the product exponent acquisition subunit; the product exponent acquisition subunit is used to acquire the third exponent of the product based on the first exponent of the first floating-point number and the second exponent of the second floating-point number; the shift number acquisition subunit is used to acquire the shift number corresponding to the fractional part of the product based on the third exponent.

[0311] Based on this embodiment, it is no longer necessary to obtain the product between floating-point numbers and then analyze the product to obtain the number of shifts. Instead, the number of shifts can be obtained during the calculation of the product, which shortens the calculation time and reduces the calculation cycle.

[0312] For example, in the case where the number of shifts includes a left shift, the number of shifts acquisition subunit includes: a third multiplexer, a fourth multiplexer, an OR gate circuit connected to the third multiplexer and the fourth multiplexer, and a fifth multiplexer connected to the OR gate circuit.

[0313] The third multiplexer is used to obtain the first number of leading zeros in the fractional part of the first floating-point number; the fourth multiplexer is used to obtain the second number of leading zeros in the fractional part of the second floating-point number; the OR gate circuit is used to perform an OR operation on the first number of leading zeros and the second number of leading zeros to obtain the third number of leading zeros; the fifth multiplexer is used to obtain the number of shift bits corresponding to the fractional part of the product based on the third exponent and the third number of leading zeros.

[0314] For example, refer to Figure 9 The third multiplexer is used to obtain the number of leading zeros of the first floating-point number. The fourth multiplexer is used to obtain the number of leading zeros of the second floating-point number. . Reference Figure 10 or gate circuit according to and The number of leading zeros of the third generation is obtained. .

[0315] In this embodiment, a third leading zero quantity is obtained by performing an OR operation on the first and second leading zero quantities using an OR gate circuit. Compared to the method of adding the first and second leading zero quantities to obtain the third leading zero quantity, the timing can be optimized and the computation time and number of cycles required can be reduced by using an OR gate circuit to point to the aforementioned processing method. Furthermore, due to the coordinated processing of the leading zero acquisition circuit, the OR gate circuit, and the left shift bit processing circuit, it is not necessary to obtain the left shift bit based on product analysis. Therefore, based on this circuit, the left shift bit and the product can be obtained in parallel, which also reduces the computation time and the number of cycles required.

[0316] The third multiplexer is configured to: if the first exponent of the first floating-point number is equal to zero, obtain a first splicing result by splicing zero and the mantissa of the first floating-point number, and determine the number of leading zeros of the first splicing result as the first number of leading zeros of the decimal part of the first floating-point number; and if the first exponent of the first floating-point number is not equal to zero, determine the first number of leading zeros of the decimal part of the first floating-point number as zero.

[0317] The fourth multiplexer is configured to: if the second exponent of the second floating-point number is equal to zero, obtain a second splicing result by splicing zero and the mantissa of the second floating-point number, and determine the number of leading zeros of the second splicing result as the second number of leading zeros of the decimal part of the second floating-point number; and if the second exponent of the second floating-point number is not equal to zero, determine the second number of leading zeros of the decimal part of the second floating-point number as zero.

[0318] The multiplexer is configured to: if the exponent of the floating-point number is equal to zero, obtain a splicing result by splicing zero and the mantissa of the floating-point number, and determine the number of leading zeros of the splicing result as the number of leading zeros of the floating-point number; and if the second exponent of the floating-point number is not equal to zero, determine the number of leading zeros of the floating-point number as zero. Compared with the method of obtaining the number of leading zeros according to the operation result of the or operation on the exponent exp of the floating-point number, the embodiment does not need to perform complex or operation, and has short processing time and short processing period.

[0319] Referring to Figure 10 , the fifth multiplexer obtains the third exponent and the third number of leading zeros to obtain the left shift number .

[0320] Further, the fifth multiplexer obtains the difference between the third exponent and a first preset exponent (for example, 1), the judgment result of whether the third number of leading zeros is less than the third exponent , and the third number of leading zeros to obtain the left shift number .

[0321] For example, the fifth multiplexer is configured to: if the third number of leading zeros is less than the third exponent, determine the third number of leading zeros as the left shift number; and the fifth multiplexer is further configured to: if the third number of leading zeros is greater than or equal to the third exponent, determine the difference between the third exponent and the first preset exponent as the left shift number.

[0322] By the fifth multiplexing circuit, the left shift number can be quickly obtained, and based on the specific processing logic of the first multiplexing circuit, the obtained left shift number can be avoided to be unreasonable, and after the shift operation is performed on the decimal part of the product according to the left shift number, the problem that the mantissa of the product exceeds the mantissa value range of the floating point number.

[0323] Further, referring to Figure 10 , the circuit further includes a sixth multiplexer. The sixth multiplexer obtains the right shift number ( ), and then performs the intercepting processing on the right shift number according to to obtain the final right shift number .

[0324] As shown in Figure 10 , the left shift value and the right shift number are obtained by the circuit for obtaining the right shift number and the circuit for obtaining the left shift number respectively, and then the left shift value , the right shift number , and the comparison result of whether the third number of leading zeros is greater than 0 are input into the sixth multiplexer to obtain the final shift value .

[0325] The processing logic for obtaining the left shift value leftshiftBits is as follows:

[0326]

[0327] The processing logic for obtaining the right shift number rightshiftBits is as follows:

[0328]

[0329] The processing logic for obtaining the final shift value is as follows:

[0330]

[0331] In an example, the floating point number multiplication circuit further includes a symbol processing circuit as shown in Figure 11 . The symbol processing circuit is configured to perform an exclusive or operation on the first symbol sign_a of the first floating point number and the second symbol sign_b of the second floating point number to obtain the symbol sign_c of the product.

[0332] With reference to Figure 9The floating-point multiplication circuit also includes a circuit section for calculating the value of the exponent portion of the product of the first floating-point number and the second floating-point number. Specifically, this section includes at least a second multiplexer, a third multiplexer, adder 1, adder 2, adder 3, and adder 4.

[0333] The number of leading zeros of the first floating-point number is obtained through the third multiplexer. The first exponent of the first floating-point number is obtained through the first multiplexer. The second exponent of the second floating-point number is obtained through the second multiplexer. The number of leading zeros of the second floating-point number is obtained through the fourth multiplexer. .

[0334] For example, the number of the first leading zeros can be calculated using a subtractor. Perform reverse processing, then input it into adder 1. Adder 1 calculates the result of the reverse processing and the first exponent. To obtain the signed exponent of the first floating-point number. The number of second leading zeros is calculated using a subtractor. Perform reverse processing, then input it into adder 3. Adder 3 then processes the result of the reverse processing and the second exponent. To obtain the signed exponent of the second floating-point number. .

[0335] Get the signed value of the first exponent of the first floating-point number. The method is as follows:

[0336]

[0337] Get the signed value of the second exponent of the second floating-point number The method is as follows:

[0338]

[0339] Furthermore, the signed exponent of the first floating-point number... The signed exponent of the second floating-point number The inverse value of the preset exponent bias (-exponentBias) is input into adder 4 to obtain the signed exponent of the product. .

[0340] That is, to obtain the signed exponent of the product. The processing logic is as follows:

[0341]

[0342] Furthermore, the floating-point arithmetic circuit also includesFigure 12 The circuit part shown includes a seventh multiplexer and an eighth multiplexer.

[0343] Referring to Figure 12 , the signed exponent of the product , the upper limit value of the floating-point exponent , and the signed exponent whether the signed exponent is greater than the upper limit value of the floating-point exponent , the exponent before the product is shifted is obtained by inputting the results of the judgment into the seventh multiplexer. The eighth multiplexer obtains the output result of the seventh multiplexer and the result of the judgment whether the signed exponent is less than 0, and obtains the exponent before the product is shifted

[0344] . The method for obtaining the exponent before the product is shifted

[0345]

[0346] That is, if , the exponent before the product is shifted is determined as 0; otherwise, it is determined whether is satisfied. If yes, the exponent before the product is shifted is determined as the upper limit value of the floating-point exponent ; if no, the exponent before the product is shifted is determined as .

[0347] The circuit of the embodiment further includes Figure 13 The circuit part shown, referring to Figure 13 , inputs the or gate circuit with , and obtains ; inputs the and gate circuit with and , and obtains ; inputs the and gate circuit with and , and obtains .

[0348] Inputs the or gate circuit with and and , and obtains .

[0349] Further, according to the or gate circuit, the result of the judgment whether the first floating-point number and the second floating-point number are non-numbers is:

[0350]

[0351]

[0352] input an OR gate circuit to obtain input an AND gate circuit to obtain input an OR gate circuit to obtain input an AND gate circuit to obtain a result of determining whether the first floating-point number and / or the second floating-point number is zero :

[0353] input an OR gate circuit to obtain

[0354] input an AND gate circuit to obtain input an OR gate circuit to obtain input an AND gate circuit to obtain a result of determining whether the first floating-point number and / or the second floating-point number is an infinite number :

[0355]

[0356] obtain a multiplication processing result resultNormal of the first floating-point number and the second floating-point number being of the first number type :

[0357]

[0358]

[0359] obtain a multiplication processing result resultNormal of the first floating-point number and the second floating-point number being of the first number type

[0360] input a ninth multiplexer to obtain an operation result of the multiplication operation of the first floating-point number and the second floating-point number :

[0361] reference

[0362] Figure 14 ​​​​The embodiment of the application provides a floating point multiplication device, and the floating point multiplication device 40 comprises: a first obtaining module 401, which is used to obtain a first exponent of a first floating point and a second exponent of a second floating point; a second obtaining module 402, which is used to obtain a to-be-shifted parameter for performing a shift operation on a decimal part of a product of the first floating point and the second floating point according to the first exponent and the second exponent in a process of calculating the product; the to-be-shifted parameter comprises a shift bit number and a shift direction; and a third obtaining module 403, which is used to perform the shift operation on the decimal part of the product according to the shift bit number and the shift direction, so as to obtain a multiplication result of the first floating point and the second floating point.

[0363] Optionally, the second obtaining module 402 is further used to: obtain a third exponent of the product according to the first exponent of the first floating point and the second exponent of the second floating point; and obtain the shift bit number corresponding to the decimal part of the product according to the third exponent.

[0364] Optionally, in the case that the shift bit number comprises a left shift bit number, the second obtaining module 402 is further used to: obtain a first leading zero number of a decimal part of the first floating point and a second leading zero number of a decimal part of the second floating point; perform an or operation on the first leading zero number and the second leading zero number to obtain a third leading zero number; and obtain the left shift bit number corresponding to the decimal part of the product according to the third exponent and the third leading zero number.

[0365] Optionally, the second obtaining module 402 is further used to: if the third leading zero number is less than the third exponent, determine the third leading zero number as the left shift bit number; and if the third leading zero number is greater than or equal to the third exponent, determine a difference value between the third exponent and a first preset exponent as the left shift bit number.

[0366] Optionally, the second obtaining module 402 is further used to: if the first exponent of the first floating point is equal to zero, obtain a first splicing result obtained by splicing zero and a mantissa of the first floating point, and determine a leading zero number of the first splicing result as the first leading zero number of the decimal part of the first floating point; if the first exponent of the first floating point is not equal to zero, determine the first leading zero number of the decimal part of the first floating point as zero; if the second exponent of the second floating point is equal to zero, obtain a second splicing result obtained by splicing zero and a mantissa of the second floating point, and determine a leading zero number of the second splicing result as the second leading zero number of the decimal part of the second floating point; and if the second exponent of the second floating point is not equal to zero, determine the second leading zero number of the decimal part of the second floating point as zero.

[0367] Optionally, in the case that the shift bit number comprises a right shift bit number, the second obtaining module 402 is further used to: determine a difference value between a second preset exponent and the third exponent as the right shift bit number corresponding to the decimal part of the product.

[0368] Optionally, the second obtaining module 402 is further configured to: obtain a third exponent of the product according to the first exponent of the first floating-point number and the second exponent of the second floating-point number; and determine that the shift direction is left shift if the third exponent is greater than zero, or determine that the shift direction is right shift if the third exponent is less than or equal to zero.

[0369] Optionally, the first obtaining module 401 is further configured to: obtain the first exponent of the first floating-point number and the second exponent of the second floating-point number if the first floating-point number and the second floating-point number both belong to a first digital type; and wherein the first digital type includes other digital types except for a second digital type, and the second digital type includes zero, non-number, and infinite number.

[0370] Optionally, the apparatus 400 further includes a fifth obtaining module configured to: obtain a multiplication result of the first floating-point number and the second floating-point number according to a multiplication operation strategy corresponding to a second digital type if the first floating-point number and / or the second floating-point number belongs to the second digital type; and wherein the second digital type includes zero, non-number, and infinite number; and wherein the multiplication operation strategy includes: determining that the multiplication result of the first floating-point number and the second floating-point number is equal to a preset value if the first floating-point number and / or the second floating-point number is non-number; determining that the multiplication result of the first floating-point number and the second floating-point number is equal to zero if the first floating-point number and the second floating-point number both are zero, or one of the first floating-point number and the second floating-point number is zero and the other is a digital type other than non-number and infinite number; and determining that the multiplication result of the first floating-point number and the second floating-point number is equal to infinite if the first floating-point number and the second floating-point number both are infinite, or one of the first floating-point number and the second floating-point number is infinite and the other is a digital type other than non-number and zero.

[0371] Optionally, the first obtaining module 401 is further configured to: obtain a first initial exponent of the first floating-point number; determine that the first exponent of the first floating-point number is equal to 1 if the first initial exponent is equal to zero; and determine that the first exponent of the first floating-point number is equal to the first initial exponent if the first initial exponent is not equal to zero; and obtain a second exponent of the second floating-point number, including: obtaining a second initial exponent of the second floating-point number; determining that the second exponent of the second floating-point number is equal to 1 if the second initial exponent is equal to zero; and determining that the second exponent of the second floating-point number is equal to the first initial exponent if the second initial exponent is not equal to zero.

[0372] In summary, in the process of calculating the product of the first floating-point number and the second floating-point number, the to-be-shifted parameter corresponding to the mantissa of the product of the first floating-point number and the second floating-point number is obtained according to the first exponent and the second exponent, and the mantissa of the product is shifted according to the to-be-shifted bit number and the shift direction, to obtain the multiplication result of the first floating-point number and the second floating-point number. In the embodiment, the to-be-shifted value is not obtained after the product of the first floating-point number and the second floating-point number is obtained, and the time of the floating-point number multiplication is reduced, and the operation period of the floating-point number multiplication is reduced, compared with the method of obtaining the product first and then obtaining the shift value according to the product in the related art.

[0373] Figure 15 is a block diagram of an electronic device 500 according to an example embodiment. Referring to Figure 15 , the electronic device 500 can include one or more components such as a processing component 502, a memory component 504, a power supply component 506, a multimedia component 508, an audio component 510, an input / output (I / O) interface 512, a sensor component 514, and a communication component 516.

[0374] The processing component 502 usually controls overall operations of the electronic device 500, such as operations associated with display, phone call, data communication, camera operation and recording operation. The processing component 502 can include one or more processors 520 to execute instructions to complete all or part of the steps of the methods described above. The memory 504 is used to store various types of data to support the operation of the electronic device 500. Examples of these data include instructions for operating any application or method on the electronic device 500. The memory 504 can be realized by any type of volatile or non-volatile storage device or a combination thereof.

[0375] The power supply component 506 provides power for various components of the electronic device 500. The multimedia component 508 includes a screen that provides an output interface between the electronic device 500 and the user. The audio component 510 is used to output and / or input audio signals. The audio signals can be further stored in the memory 504 or transmitted via the communication component 516. In some embodiments, the audio component 510 also includes a speaker for outputting audio signals. The I / O interface 512 provides an interface between the processing component 502 and the peripheral interface module. The sensor component 514 includes one or more sensors for providing state evaluation of various aspects of the electronic device 500. The communication component 516 is used to facilitate wired or wireless communication between the electronic device 500 and other devices. In an example embodiment, the electronic device 500 is used to implement a floating-point number multiplication method provided by the embodiments of the present application.

[0376] In an example embodiment, a non-transitory computer-readable storage medium including instructions, such as the memory 504 including instructions, is also provided, which can be executed by the processor 520 of the electronic device 500 to complete the above method. For example, the non-transitory storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, and an optical data storage device, etc.

[0377] Figure 16 is a block diagram of an electronic device 600 according to an example embodiment. For example, the electronic device 600 can be provided as a server. Referring to Figure 16 , the electronic device 600 includes a processing component 622, which further includes one or more processors, and a memory resource represented by a memory 632, for storing instructions executable by the processing component 622, such as an application program. The application program stored in the memory 632 can include one or more than one module each corresponding to a set of instructions. In addition, the processing component 622 is configured to execute the instructions to perform a floating-point multiplication method provided by the embodiments of the present application. The electronic device 600 can also include a power supply component 626 configured to perform power management of the electronic device 600, a wired or wireless network interface 650 configured to connect the electronic device 600 to a network, and an input / output (I / O) interface 658. The electronic device 600 can operate based on an operating system stored in the memory 632.

[0378] The embodiments of the present application also provide a computer program product, including a computer program, which when executed by a processor implements a floating-point multiplication method.

[0379] Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims. The specification and examples are to be considered exemplary only, with the true scope of the application being indicated by the following claims.

Claims

1. A floating-point multiplication circuit, characterized in that, The circuit comprises a shift parameter calculation unit, a first multiplexer, a second multiplexer, a product calculation unit and a shift operation unit; the first multiplexer and the second multiplexer are connected with the shift parameter calculation unit; the shift parameter calculation unit is connected with the product calculation unit and the shift operation unit; The first multiplexer is configured to obtain a first exponent of a first floating-point number; The second multiplexer is configured to obtain a second exponent of a second floating-point number; The shift parameter calculation unit is configured to obtain a to-be-shifted parameter for performing a shift operation on a decimal part of a product of the first floating-point number and the second floating-point number according to the first exponent and the second exponent during calculation of the product by the product calculation unit; the to-be-shifted parameter comprises a shift bit number and a shift direction; The shift operation unit is configured to perform a shift operation on the decimal part of the product according to the shift bit number and the shift direction, to obtain a multiplication result of the first floating-point number and the second floating-point number. The shift parameter calculation unit comprises a product exponent obtaining subunit and a shift bit number obtaining subunit connected with the product exponent obtaining subunit; the product exponent obtaining subunit is configured to obtain a third exponent of the product according to the first exponent of the first floating-point number and the second exponent of the second floating-point number; and the shift bit number obtaining subunit is configured to obtain a shift bit number corresponding to the decimal part of the product according to the third exponent. In a case where the shift bit number comprises a left shift bit number, the shift bit number obtaining subunit comprises a third multiplexer, a fourth multiplexer, an OR subcircuit connected with the third multiplexer and the fourth multiplexer, and a fifth multiplexer connected with the OR subcircuit; the third multiplexer is configured to obtain a first number of leading zeros of the decimal part of the first floating-point number; the fourth multiplexer is configured to obtain a second number of leading zeros of the decimal part of the second floating-point number; the OR subcircuit is configured to perform an OR operation on the first number of leading zeros and the second number of leading zeros to obtain a third number of leading zeros; and the fifth multiplexer is configured to obtain the shift bit number corresponding to the decimal part of the product according to the third exponent and the third number of leading zeros.

2. The circuit of claim 1, wherein the fifth multiplexer is configured to determine the third number of leading zeros as the left shift bit number if the third number of leading zeros is less than the third exponent; and the fifth multiplexer is further configured to determine a difference between the third exponent and a first preset exponent as the left shift bit number if the third number of leading zeros is greater than or equal to the third exponent.

3. The circuit of claim 1, wherein the third multiplexer is configured to obtain a first splicing result obtained by splicing zero and a mantissa of the first floating-point number if the first exponent of the first floating-point number is equal to zero, and determine a number of leading zeros of the first splicing result as the first number of leading zeros of the decimal part of the first floating-point number. If the first exponent of the first floating-point number is not equal to zero, the first floating-point number is determined to have a first number of leading zeros in the fractional part of the first floating-point number as zero; If the second exponent of the second floating-point number is equal to zero, the fourth multiplexer is configured to obtain a second splicing result obtained by splicing zero and the mantissa of the second floating-point number, and determine the number of leading zeros of the second splicing result as the second number of leading zeros in the fractional part of the second floating-point number. If the second exponent of the second floating-point number is not equal to zero, the second floating-point number is determined to have a second number of leading zeros in the fractional part of the second floating-point number as zero.

4. The circuit of claim 1, wherein, In a case where the shift bit number includes a right shift bit number, the shift bit number obtaining subunit is configured to determine a difference between the second preset exponent and the third exponent as the right shift bit number corresponding to the fractional part of the product.

5. The circuit of claim 1, wherein, The shift parameter calculation unit is configured to obtain a third exponent of the product according to the first exponent of the first floating-point number and the second exponent of the second floating-point number. If the third exponent is greater than zero, the shift direction is determined to be left shift. If the third exponent is less than or equal to zero, the shift direction is determined to be right shift.

6. The circuit of claim 1, wherein The first multiplexer is configured to obtain a first exponent of the first floating-point number if the first floating-point number and the second floating-point number both belong to a first digital type. The second multiplexer is configured to obtain a second exponent of the second floating-point number if the first floating-point number and the second floating-point number both belong to the first digital type. The first digital type includes other digital types except a second digital type, and the second digital type includes zero, non-number, and infinite number.

7. The circuit of claim 1, wherein, The floating-point multiplication circuit further includes a ninth multiplexer. The ninth multiplexer is configured to obtain a multiplication result of the first floating-point number and the second floating-point number according to a multiplication strategy corresponding to the second digital type if the first floating-point number and / or the second floating-point number belongs to the second digital type. The second digital type includes zero, non-number, and infinite number. The multiplication strategy includes: If the first floating-point number and / or the second floating-point number is non-number, the multiplication result of the first floating-point number and the second floating-point number is determined to be equal to a preset value. If the first floating-point number and the second floating-point number both are zero, or one of the first floating-point number and the second floating-point number is zero and the other is a digital type other than non-number and infinite, the multiplication result of the first floating-point number and the second floating-point number is determined to be equal to zero. If the first floating-point number and the second floating-point number both are infinite number, or one of the first floating-point number and the second floating-point number is infinite number and the other is a digital type other than non-number and zero, the multiplication result of the first floating-point number and the second floating-point number is determined to be equal to infinite.

8. The circuit of claim 1, wherein The first multiplexer is configured to obtain a first initial exponent of the first floating-point number. if the first initial exponent is equal to zero, then determining that a first exponent of the first floating-point number is equal to 1; if the first initial exponent is not equal to zero, then determining that the first exponent of the first floating-point number is equal to the first initial exponent; the second multiplexer, configured to obtain a second initial exponent of the second floating-point number; if the second initial exponent is equal to zero, then determining that a second exponent of the second floating-point number is equal to 1; if the second initial exponent is not equal to zero, then determining that the second exponent of the second floating-point number is equal to the first initial exponent.

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