Chaotic TRNG method for double-loop interference refreshing iteration based on FPGA

Abstract

The invention relates to the technical field of FPGA embedded development, in particular to a chaos TRNG method based on double-loop interference refresh iteration of an FPGA, which comprises a TRNG circuit deployed on a programmable logic device, the programmable logic device comprises at least one of an ARTIX-7 FPGA and a PYNQK2FPGA, and the TRNG circuit is configured to generate a true random number sequence meeting cryptographic security standards. According to the invention, the high-throughput true random number generator is realized by using the oscillation and jitter of the self-timing ring to disturb the work of the chaotic cell, the iterative algorithm is optimized, and the proposed structure has excellent performance and has the performance of resisting interference and converting the interference into a random source; the generated random sequence has successfully passed the test of NISTSP800-22, TESTU01, NISTSP800-90B and ASI-31 (American Standard Standard Specification); the throughput of 1040Mbps can be realized on a XilinxArtix-7and PYNQ-K2 series development board, and the circuit occupies less resources when being realized on an FPGA (Field Programmable Gate Array), is low in power consumption when a unit works, and has remarkable advantages in resource utilization and quality factor of comprehensive consideration of performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of FPGA embedded development, in particular to a chaotic TRNG method based on double-loop interference refresh iteration of FPGA. BACKGROUND

[0002] With the advent of the intelligent era, more and more Internet of Things (IoT) devices are deployed in various aspects of life and production. Ensuring the operation and communication security of Internet of Things devices has become a key issue. In order to enhance the overall security of Internet of Things devices, random numbers are used in Internet of Things devices for identity authentication, access control, data encryption, prevention of replay attacks, security protocols and key exchange. Random numbers play a crucial role in modern cryptography, information security, financial transactions, Internet of Things (IoT) and hardware security. According to the different ways of generating random numbers, random number generators are mainly divided into two categories: pseudo-random number generators and true random number generators (TRNG). Among them, the true random number generator generates real random numbers by using unpredictable phenomena in the physical world, and the core is non-deterministic, which is theoretically unpredictable and non-reproducible.

[0003] Generally, the general architecture of a true random number generator is as shown in Figure 1 , which includes four stages of entropy source acquisition, signal conditioning, sampling quantization and post-processing. There are various types of entropy sources in the physical world, and the commonly used types include electronic noise and chaotic systems. Different types of entropy sources have different characteristics and costs in the design process. Then the random signal is processed through amplification, filtering and other signal conditioning methods to facilitate subsequent sampling. Post-processing can improve statistical bias and improve randomness. Common post-processing techniques include using hash function algorithms (SHA-3) and Von Neumann correction. According to the specific design, post-processing and signal conditioning can not be used.

[0004] At present, the update of Internet of Things devices urgently needs a TRNG with higher performance, which requires it to have a more efficient and stable entropy source structure. However, the development of existing technologies also affects its security. For example, side channel attacks can use leakage signals during circuit operation to analyze, and some TRNGs using ring oscillation structures are also vulnerable to frequency injection attacks, which can cause the quality of the true random numbers generated to decline. In view of the above problems, a high-performance true random number generator not only needs to have a high throughput, but also needs to have certain anti-interference ability. SUMMARY

[0005] The purpose of the present application is to provide a chaotic TRNG method based on double-loop interference refresh iteration of FPGA to solve the problems raised in the background art.

[0006] To achieve the above purpose, the present application provides the following technical solutions:

[0007] An FPGA-based interference refreshing CA chaotic true random number generator, comprising a TRNG circuit deployed in a programmable logic device, the programmable logic device comprising at least one of an ARTIX-7 FPGA and a PYNQK2 FPGA, the TRNG circuit being configured to generate a true random number sequence meeting a cryptography security standard.

[0008] Specifically, the cryptography security standard passes the NIST SP800-22, NIST SP90B, AIS-31, and TESTU01 tests.

[0009] Preferably, the TRNG circuit comprises:

[0010] A self-timed oscillation module configured to generate an interference signal with stable frequency and controllable spectrum;

[0011] A CA chaotic iteration module comprising a plurality of CA units cascaded in a ring, each CA unit generating an iteration output based on its current state and the state of the neighborhood;

[0012] A post-processing module configured to eliminate transient noise in the signal switching process and generate a smooth random sequence with excellent statistical properties.

[0013] Preferably, the self-timed oscillation module comprises a plurality of cascaded Muller-C units, each Muller-C unit comprising:

[0014] An output port C connected to a feedforward input port of a secondary unit and a feedback input port of a previous unit;

[0015] A feedforward input port F connected to an output port C of a previous Muller-C unit;

[0016] A feedback input port R connected to an output port C of a secondary Muller-C unit;

[0017] The Muller-C unit is configured to keep the output C unchanged when the F and R signals are consistent, and update the output C to the current value of F when the F and R signals are inconsistent;

[0018] By configuring the uniform distribution density of Token and Bubble, the self-timed oscillation module works in a preset uniform oscillation mode.

[0019] Preferably, the CA chaotic iteration module comprises at least 8 CA units cascaded in a ring, each CA unit comprising:

[0020] A first input port connected to an output of a previous CA unit;

[0021] a second input port connected to an output of the secondary CA unit;

[0022] an output port providing a state output of the current CA unit;

[0023] each CA unit is configured to generate an iteration output through an XOR gate coupling circuit based on signals of its two input ports;

[0024] the iteration process of the CA unit has time memory and sensitive dependence on initial conditions, forming chaotic characteristics.

[0025] Preferably, the post-processing module comprises at least two cascaded D flip-flops configured to perform timing synchronization and secondary sampling on the original signal.

[0026] It comprises at least one XOR gate configured to perform logical XOR operation on the output of the D flip-flop to eliminate transient signals in the form of 010 or 101.

[0027] Preferably, the FPGA-based TRNG is characterized in that the ARTIX-7 FPGA uses an xc7a35tcgs324 chip and an xc7a100tcgs324 chip, and the PYNQK2 FPGA uses an XC7Z020 system-on-chip.

[0028] An operation method of a FPGA-based TRNG, comprising the following steps:

[0029] Initialize the self-timed oscillation module by a 2-bit configuration signal, and configure it to work in a preset uniform oscillation mode;

[0030] After initialization, set the configuration signal to an invalid state to make the TRNG circuit enter a normal working mode;

[0031] Inject the high-frequency signal generated by the self-timed oscillation module into the CA chaotic iteration module through the XOR gate to interfere with the iteration process of the CA unit;

[0032] Use the timing jitter in the self-timed oscillation module signal as a random source to affect the timing of the CA unit iteration refresh;

[0033] Process the output of the CA chaotic iteration module through the post-processing module to generate four independent random number sequences;

[0034] Use the on-chip integrated logic analyzer ILA to collect the random number sequences and store them as text files.

[0035] Preferably, the post-processing module is configured to work automatically under the system clock domain without external control signals.

[0036] Preferably, the ILA is configured as:

[0037] Working in a sampling clock domain independent of the design clock;

[0038] 4 probe channels are configured, respectively connected to the 4-way output of the post-processing module;

[0039] The sampling depth is 131072, and the frequency is the system clock.

[0040] Compared with the prior art, the present application has the beneficial effects that:

[0041] The present application aims to solve the problems of contradiction between throughput rate and resource consumption, insufficient stability of entropy source, and poor randomness quality in existing TRNG design, and provides a high-performance, low-resource-consuming double-ring structure TRNG, which has the following characteristics:

[0042] Balanced design of high throughput rate and low resource consumption, in the overall design, there are multiple true random number output channels, and random number sequences can be output at the same time, which maximizes the utilization of entropy source structure and reduces the problem of excessive resource consumption caused by area increase during performance improvement.

[0043] The TRNG entropy source structure of the present application belongs to a chaotic structure, and uses the STR and CA double-ring structure to realize stable high-entropy source, has the function of converting interference into random source, enhances randomness through disturbance refreshing mechanism, and resists environmental interference and side channel attacks.

[0044] When implemented on an FPGA, manual wiring is not required, and the implementation on different FPGA platforms maintains stable high-quality random number generation performance and has good portability.

[0045] The present application balances resources and performance, and when ensuring excellent throughput, the resources only occupy 36LUT and 8DFF on the FPGA;

[0046] The present application uses an iterative chaotic structure, and the generated random sequence has high entropy value, high efficiency and low power consumption.

[0047] The present application has an anti-interference function and can use interference as a source of randomness of entropy;

[0048] The present application optimizes the traditional CA iterative algorithm, and the deficiencies of the traditional algorithm require detection circuit and correction circuit, but the present application does not need to detect the system, greatly improving the portability of the structure. BRIEF DESCRIPTION OF DRAWINGS

[0049] Figure 1 The true random number general architecture mentioned in the background technology part of the present application;

[0050] Figure 2 CA unit structure designed for the present application;

[0051] Figure 3 Interference refresh double-ring TRNG structure designed for the present application. DETAILED DESCRIPTION

[0052] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0053] According to the FPGA-based TRNG, ARTIX-7 FPGA and PYNQ K2 FPGA adopt xc7a35tcgs324 chips, xc7a100tcgs324 chips and XC7Z020 system-on-chip, respectively.

[0054] As shown in Figure 3 A chaotic system TRNG based on FPGA, comprising:

[0055] ARTIX and PYNQ series FPGAs internally deploy a chaotic TRNG structure for realizing iterative refresh by utilizing interference;

[0056] As shown in Figure 2 The ROPUF circuit comprises:

[0057] A self-timed ring for generating a stable and analogizable interference signal;

[0058] A CA ring internally formed by cascading CA units into a ring, each unit generating a true random number sequence according to the unit state;

[0059] A post-processing circuit for processing glitches caused in the unit signal switching process, so that the output result is smoother;

[0060] According to the above-mentioned FPGA-based TRNG control method, characterized in that the method comprises the following sequential steps:

[0061] (1) In the initialization stage, the self-timed ring is set through a 2-bit configuration signal. The self-timed ring itself has two different oscillation modes. By configuring the uniform oscillation of the self-timed ring, a stable interference signal is generated;

[0062] (2) After initialization, the configuration signal is set to 00 to invalidate the configuration signal, and the circuit starts normal work. The entropy source is collected using a 260Mhz clock.

[0063] (3) The random number sequence of the TRNG is output from the post-processing circuit, and there are 8 random number sequence outputs, which are collected through the on-chip ILA, and the collected random sequence is written to a txt file;

[0064] According to step (1) in the above method, characterized in that:

[0065] The design of the self-timing ring needs to be paired with the CA ring, the high-speed iteration of the CA ring needs a matching interference signal, and the self-timing ring is required to output a high-speed signal, and the oscillation mode adopts uniform oscillation;

[0066] According to step (2) in the above method, characterized in that:

[0067] After the initial configuration, the circuit does not output a true random number sequence, and when the 2-bit configuration signal is set to 00, the circuit starts working after receiving the configuration completion signal;

[0068] The self-timing ring provides a stable interference signal to the CA ring, and the internal state of the CA ring is flipped by changing the input of the unit, and the internal characteristics of the unit are:

[0069] When the internal state of the CA unit changes, it will not affect the next iteration of the unit, and when any input of the CA unit, including the feedforward input and the feedback input, is reversed, the state value of the unit will be flipped in the next iteration. When the two inputs are reversed, the state of the unit remains stable and does not flip;

[0070] The internal states of multiple CA units are output simultaneously and are collected by flip-flops under the system clock;

[0071] According to step (3) in the above method, characterized in that:

[0072] The collected multi-channel signal is transmitted to the post-processing circuit after being processed by XOR, and the post-processing circuit is used to process the burr caused by signal collision in the random sequence, so that the output sequence waveform is smoother;

[0073] During the ILA collection of the random sequence, the number of probes is set to 4, and the collected waveform and data are displayed on the PC, and the sequence data is written to a txt file on the PC;

[0074] The present application solves the above technical problems by the following technical means:

[0075] The core structure is realized by using a chaotic unit named cellular automata (CA), the internal structure of which is realized according to a set truth table mapping, has a unique three-input logic function, and the unit output can be iterated according to the truth table;

[0076] During the iterative operation of the unit, the iteration period and randomness are limited by the structure, and when the circuit works, the output random number can be predicted by observing a large number of results;

[0077] Therefore, a high-frequency signal is introduced to interfere with the original iteration process, realize random jump of the unit state, and reduce the possibility of being predicted;

[0078] The high-frequency signal needs to match the high-speed working capability of the CA unit, and the signal interference speed is sufficient for the iteration of the internal state of the unit, and a configurable self-timing ring is used to meet the design requirements;

[0079] The entire circuit has 2-bit configuration signals, which affect the working mode of the self-timing ring and the initial value of the unit; after the configuration operation is completed, the 2-bit configuration signals are set to zero, and the working output true random number can be started;

[0080] During the operation, the double rings run independently, the iteration rule of the CA ring internal unit is not affected, the stability of the entropy source is ensured, and the iteration rule conforms to the truth table, and the iteration rule is as follows:

[0081] The CA ring has more performance resource arrangement unit number, and the units are cascaded with each other to form an iteration chain.

[0082] The CA unit structure of the application is shown in Figure 2 The CA unit has three I / O interfaces inside, which are the unit state as output, the unit feedforward output, and the unit feedback input.

[0083] The unit state values of different units are cascaded with each other, iterated according to the states of the three CA units in the neighborhood range of 1, and the three parameters in a unit determine the unit state of the next iteration.

[0084] In order to cope with the change of the iteration process affecting the stability, the stability of the state in the unit must be ensured, and when the unit state changes, the value of the next iteration will not be affected.

[0085] The self-timing ring ring will select the oscillation mode according to the specific configuration signal, play different roles, and the independent self-timing ring has multiple outputs, and the output signal is connected to the CA ring to affect the iteration process of the CA unit.

[0086] The specific double ring structure is shown in Figure 3When a single CA cell in the figure is affected, we classify this disturbed iteration model into three cases:

[0087] The first case is that the XOR gates on both sides of the single CA cell act as a buffer. The operation of this part is unchanged, and the three input values in the iteration process are not refreshed.

[0088] Further, the iteration state of the cell will not change, and the state transfer will continue according to the original process. A parameter of the secondary cell and the previous cell will remain stable in the next iteration.

[0089] The second case is that the XOR gates act as inverters, causing a parameter to flip and changing the state transfer process of the CA cell, resulting in the state of the cell flipping and completing the refresh process.

[0090] Further, the state of the cell input to the previous cell will cause a flip, and because there is an inverter in the connection with the secondary cell, the flipped state input to the secondary cell will be restored and will not affect the iteration process of the secondary cell in the next iteration.

[0091] The third case is that the two XOR gates do not act consistently. In this case, only one of the three adjacent cells will have its state changed in this iteration.

[0092] Further induction of the third case shows that if the state of the cell flips, the previous cell will be affected in the next iteration, and the secondary cell will not be affected. If the state of the cell does not flip, the previous cell will not be affected, and the secondary cell will be affected in the next iteration.

[0093] In the design of the cell, state jumping is considered to ensure randomness. The changes of the three parameters in the cell are strictly deduced.

[0094] When the signal between the cells flips, the state of the cell flips. When the internal state signal of the cell flips, it does not affect the result of the next iteration, ensuring the stability of the cell and preventing the output result from being unbalanced due to excessive sensitivity.

[0095] Because this optimized disturbance refresh algorithm improves the randomness of the original structure while maintaining the independence between cells, the unpredictable state of each cell serves as the output of a true random number. In this way, the number of true random number output ports has increased to multiple, and the parallel output mode greatly improves the throughput.

[0096] The specific circuit true random number generation process includes:

[0097] After the circuit is powered on, different initialization results will be presented due to the difference in load capacity and driving capacity of elements, and different initial states directly lead to different state jump paths, and the possibility of such paths increases exponentially according to the number of units, and the difference in physical reality is maximized;

[0098] After simple initial configuration, the initial state in the circuit can be conflicted, and the initial state is better randomized and refreshed, and the TRNG starts to work;

[0099] The self-timed ring provides a stable interference signal to the CA ring, and the iteration process is constantly refreshed, in which the environment or noise can also cause the signal of the multi-path internal to mutate;

[0100] For example, when the environmental noise forces the logic output of the element to mutate, such a random phenomenon directly reflects on the inter-unit loop, affecting the feedforward and feedback;

[0101] The feedback signal will affect the next iteration of the previous unit, and the feedforward signal will affect the next iteration of the subsequent unit, and the effect achieved also conforms to the above description, and the state flip of the adjacent unit changes the iteration history, and the state flip of the unit itself does not change the iteration history.

[0102] Each unit in the CA ring maintains an independent output state value, and uses a multi-path collection method to collect random numbers, because there are inevitable interference and conflicts in the iteration process, the mutated signal needs a post-processing circuit to eliminate burrs, so that the output result is smoother;

[0103] After the post-processing operation, the multi-path output true random number can be obtained.

[0104] In summary, the present application uses self-timed ring oscillation and jitter to disturb the chaotic cell operation to realize a high-throughput true random number generator, and the proposed structure has excellent performance and resistance to interference and random source performance. On the Xilinx Artix-7 series development board and PYNQ K2, the implementation process on the FPGA does not require manual wiring, and the present application has good portability on different devices. The random sequence generated by the designed TRNG can pass the NISTSP800-22 and TESTU01 randomness test with a good threshold value. And 1040Mbps throughput is obtained, at the same time, the TRNG of the application only needs 36 LUT and 8 DFF, realizes high resource utilization, thereby solving the problems of performance and area compromise of traditional TRNG and the entropy source being easily disturbed, and the application optimizes the CA iteration algorithm, so that the circuit does not need detection and calibration circuit in operation.

[0105] While embodiments of the application have been shown and described, it is to be understood that the embodiments described are merely exemplary of the principles and application of the present application. Numerous modifications and adaptions can be effected without departing from the spirit and scope of the present application, which is not limited to the exact construction and arrangement described. It is intended, therefore, to cover all modifications and adaptions that fall within the scope of the claims and their equivalents.

Claims

1. An interference-refreshed CA chaotic true random number generator based on FPGA, characterized by: It includes a TRNG circuit deployed in a programmable logic device, wherein the programmable logic device includes at least one of ARTIX-7 FPGA and PYNQK2 FPGA, and the TRNG circuit is configured to generate a true random number sequence that meets cryptographic security standards.

2. The FPGA-based TRNG according to claim 1, wherein: The TRNG circuit includes: a self-timed oscillator module configured to generate a frequency-stable and spectrum-controllable interference signal; The CA chaotic iteration module includes multiple CA units cascaded into a ring, each CA unit generates an iterative output based on its current state and the state of its neighborhood; The post-processing module is configured to eliminate transient noise during the signal switching process and generate a smooth random sequence with excellent statistical characteristics.

3. The self-timed oscillator module according to claim 2, wherein: Contains multiple cascaded Muller-C units, each Muller-C unit includes: An output port C connected to a feedforward input port of a secondary unit and a feedback input port of a preceding unit; The feedforward input port F is connected to the output port C of the secondary Muller-C unit; Feedback input port R is connected to the output port C of the preceding Muller-C unit; The Muller-C unit is configured to: when the F and R signals are consistent, keep the output C unchanged; when the F and R signals are inconsistent, update the output C to the current value of F; By configuring the uniform distribution density of tokens and bubbles, the self-timed oscillator module can operate in a preset uniform oscillation mode.

4. The CA chaotic iteration module according to claim 2, characterized in that: Contains at least 8 CA units cascaded into a ring, each CA unit includes: A first input port connected to the output of the previous CA unit; a second input port connected to the output of the secondary CA unit; Output port, providing the status output of the current CA unit; Each CA unit is configured to generate an iterative output based on the signals of its two input ports through an XOR gate coupling circuit; The iterative process of the CA unit has time memory and sensitive dependence on initial conditions, forming chaotic characteristics.

5. The post-processing module according to claim 2, characterized in that: comprising at least two stages of cascaded D flip-flops configured to perform timing synchronization and secondary sampling on an original signal; The device comprises at least one XOR gate configured to perform a logical XOR operation on the output of the D flip-flop to eliminate transient signals in the form of 010 or 101.

6. The FPGA-based TRNG according to claim 1, wherein: The ARTIX-7 FPGA uses the xc7a35tcgs324 chip and the xc7a100tcgs324 chip, the PYNQK2 FPGA uses the XC7Z020 system-on-chip chip, and the TRNG circuit realizes a physically isolated signal path through the internal wiring of the FPGA.

7. An operating method of a TRNG based on FPGA according to any one of claims 1 to 3, characterized in that: The following steps are involved: Initialize the self-timed oscillator module through a 2-bit configuration signal and configure it to work in a preset uniform oscillation mode; After initialization is completed, the configuration signal is set to an invalid state, so that the TRNG circuit enters the normal working mode; The high-frequency signal generated by the self-timed oscillation module is injected into the CA chaotic iteration module through an XOR gate to interfere with the iteration process of the CA unit; The timing jitter in the self-timed oscillation module signal is used as a random source to affect the timing of the iterative refresh of the CA unit; The output of the CA chaotic iteration module is processed by the post-processing module to generate four independent random number sequences; The random number sequence is collected using the on-chip integrated logic analyzer ILA and stored as a text file.

8. The method according to claim 7, wherein: The post-processing module is configured to automatically operate in the system clock domain without the need for external control signals.

9. The method according to claim 7, wherein: The ILA configuration is: Works in a sampling clock domain independent of the design clock; Configure 4 probe channels, which are connected to the 4 outputs of the post-processing module respectively; The sampling depth is 131072 and the frequency is the system clock.

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