High-speed multimode logic block with combined output for programmable logic devices

Abstract

The embodiment of the invention relates to a high-speed multimode logic block with a combined output for a programmable logic device. Embodiments of the present disclosure include improved logic blocks having combined outputs for programmable logic devices and methods of operating and programming these logic blocks. In an exemplary aspect, a programmable logic device (PLD) is described. In some embodiments, the PLD includes a logic block. The logic block may include a first lookup table (LUT) circuit configured to generate a first output; a second LUT circuit configured to generate a second output; a ripple logic circuit configured to receive the first output and the second output, and generate a third output; and a three-to-one multiplexer circuit configured to receive the first output, the second output, and the third output, and selectively generate an output of the logic block.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to programmable logic devices (PLDs), and more particularly to PLDs with improved logic block configurations. BACKGROUND

[0002] Programmable logic devices (PLDs) (e.g., field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), field programmable systems on a chip (FPSCs), or other types of programmable devices) can be configured with various user designs to implement desired functionality. Typically, the user designs are synthesized and mapped into configurable resources (e.g., programmable logic gates, look-up tables (LUTs), embedded hardware, or other types of resources) and interconnects available in a particular PLD. Physical placement and routing of the synthesized and mapped user designs can then be determined to generate configuration data for the particular PLD.

[0003] PLDs can include a plurality of programmable logic blocks (PLBs) and configurable routing resources, which can be used to interconnect the PLBs. Logic block design involves complex tradeoffs between various quantities such as area, speed, cost, and functionality. For example, PLBs that support different modes of combination can have multiple output ports and associated circuit paths and components dedicated to various modes, which have associated costs in terms of delay, area, and routing resources. There remains a need for PLBs that provide multiple modes while reducing delay and routing complexity. SUMMARY

[0004] Embodiments of the present disclosure include improved logic blocks with combined outputs for programmable logic devices and methods of operating and programming such logic blocks.

[0005] In an example aspect, a PLD is described. In certain embodiments, the PLD includes a logic block. The logic block can include: a first LUT circuit configured to generate a first output; a second LUT circuit configured to generate a second output; a ripple logic circuit configured to receive the first output and the second output and generate a third output; and a three-to-one multiplexer circuit configured to receive the first output, the second output, and the third output and selectively produce an output of the logic block.

[0006] In another example aspect, a method of operating a logic block within a PLD is described. In certain embodiments, the method can include: generating a first output by a first LUT circuit; generating a second output by a second LUT circuit; generating a third output from the first output and the second output by a ripple logic circuit; receiving the first output, the second output, and the third output; and generating an output of the logic block based on the first output, the second output, and the third output, wherein the receiving and the generating are performed by a three-to-one multiplexer circuit.

[0007] In another exemplary aspect, a method of programming a PLD is described. In certain embodiments, the PLD includes a plurality of programmable logic blocks (PLBs). Each PLB of the plurality of PLBs can include a first LUT circuit configured to generate a first output, a second LUT circuit configured to generate a second output, a ripple logic circuit configured to receive the first output and the second output and generate a third output, and a multiplexer circuit configured to selectively place the PLB in a LUT mode or a ripple mode by selecting one of the first output, the second output, and the third output as an output of the PLB. The method of programming can include generating configuration data to configure physical components of the PLD in accordance with a synthesized design that includes one of the LUT mode or the ripple mode for each PLB, and programming the PLD with the configuration data.

[0008] Additional aspects, features, and advantages of the disclosure will become apparent from the following detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0009] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate several aspects of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0010] Figure 1 A block diagram of a programmable logic device (PLD) in accordance with certain aspects of the present disclosure is shown.

[0011] Figure 2 A block diagram of a logic block 104 of a PLD 100 in accordance with certain aspects of the present disclosure is shown.

[0012] Figure 3 A design process for a PLD in accordance with certain aspects of the present disclosure is shown.

[0013] Figure 4 An example PLB in accordance with certain aspects of the present disclosure is shown.

[0014] Figure 5 An example combinatorial circuit of a PLB in accordance with certain aspects of the present disclosure is shown.

[0015] Figure 6 An example embodiment of a ripple circuit in accordance with certain aspects of the present disclosure is shown.

[0016] Figure 7 An example combinatorial circuit of a PLB in accordance with certain aspects of the present disclosure is shown.

[0017] Figure 8 An example slice for a PLD in accordance with certain aspects of the present disclosure is shown.

[0018] Figure 9 FIG. illustrates an example embodiment of another ripple circuit in accordance with certain aspects of the present disclosure.

[0019] Figure 10 FIG. illustrates another example slice for a PLD in accordance with certain aspects of the present disclosure.

[0020] Figure 11 is an example method of operating a logic block in accordance with certain aspects of the present disclosure. DETAILED DESCRIPTION

[0021] To facilitate an understanding of the principles of the present disclosure, reference is made to the embodiments illustrated in the drawings, and specific language will be used to describe these embodiments. However, no limitation of the scope of the present disclosure is intended by this use of specific language. Any alterations and further modifications in the described devices, systems, and methods, and any further applications of the principles of the present disclosure are fully contemplated and included within the scope of the present disclosure as though expressly set forth in the present disclosure. Specifically, it is contemplated that features, components, and / or steps described with respect to one embodiment can be combined with features, components, and / or steps described with respect to other embodiments of the present disclosure. However, for the sake of brevity, numerous iterations of these combinations will not be described separately.

[0022] A PLD can include various logic blocks, each of which supports multiple modes of combination. For example, a conventional logic block can support an n-input LUT (LUTn or nLUT) mode (F), a SUM mode (FS), and a mode that dynamically selects between two LUTns using an additional input M (extended logic or OFS mode). Additionally, the conventional logic block can include an additional output port (Q) as a registered (stored) version of the combination mode or as a standalone input (M). This example conventional logic block illustrates a need to minimize the number of output ports while providing high performance.

[0023] The present disclosure recognizes that various modes of combination in a logic block can be combined into a single output without impacting the performance of the LUTn mode. This can be achieved by combining the other modes in parallel with the last stage of the LUTn itself, thereby eliminating intermediate multiplexers and other intermediate logic, such as inverters, in the logic block. Various embodiments of these techniques are presented and further explained herein.

[0024] Figure 1A block diagram of a programmable logic device (PLD) 100 is shown in accordance with certain aspects of the present disclosure. The PLD 100 can be an FPGA, a CPLD, an FPSC, or other type of programmable device. The PLD 100 generally includes input / output (I / O) blocks 102 and logic blocks 104 (e.g., also referred to as programmable logic blocks (PLBs), programmable function units (PFUs), or programmable logic cells (PLCs)).

[0025] The I / O blocks 102 provide I / O functionality (e.g., for supporting one or more I / O and / or memory interface standards) for the PLD 100, while the logic blocks 104 provide logic functionality (e.g., LUT-based logic or logic gate array-based logic) for the PLD 100. Additional I / O functionality can be provided by a serial / deserializing (SERDES) block 150 and a physical coding sublayer (PCS) block 152. The PLD 100 can also include hard intellectual property (IP) blocks 160 to provide additional functionality (e.g., substantially predetermined functionality provided in hardware that can be configured with less programming than the logic blocks 104).

[0026] The PLD 100 can also include blocks of memory 106 (e.g., blocks of EEPROM, blocks of SRAM, and / or flash memory), clock-related circuitry 108 (e.g., clock sources, PLL circuitry, and / or DLL circuitry), and / or various routing resources (e.g., interconnects and appropriate switching logic for providing paths for routed signals throughout the PLD 100, such as for clock signals, data signals, or other signals), as the case can be. Generally, the various elements of the PLD 100 can be used to perform their intended functions for a desired application, as understood by one of skill in the art.

[0027] For example, certain I / O blocks 102 can be used to program the memory 106 or transfer information to / from the PLD 100 (e.g., various types of user data and / or control signals). Other I / O blocks 102 include a first programming port (which can represent a central processing unit (CPU) port, a peripheral data port, an SPI interface, and / or a sysCONFIG programming port) and / or a second programming port, such as a joint test action group (JTAG) port (e.g., by employing a standard such as the Institute of Electrical and Electronics Engineers (IEEE) 1149.1 standard or the IEEE 1532 standard). In various embodiments, I / O blocks 102 can be included to receive configuration data and commands (e.g., over one or more connections 140) to configure the PLD 100 for its intended use, and to support serial or parallel device configuration and information transfer with the SERDES block 150, the PCS block 152, the hard IP blocks 160, and / or the logic blocks 104, as the case can be.

[0028] It should be appreciated that the number and placement of various elements is not limited and can depend on the desired application. For example, various elements can not be needed for the desired application or design specifications (e.g., for the type of programmable device selected).

[0029] Further, it should be appreciated that the elements are illustrated in blocks for clarity and that various elements are typically distributed throughout the PLD 100, such as in and between the logic blocks 104, hard IP blocks 160, and routing resources, to perform their traditional functions (e.g., to store configuration data that configures the PLD 100 or to provide an interconnect structure within the PLD 100). It should also be appreciated that the various embodiments disclosed herein are not limited to programmable logic devices, such as the PLD 100, and can be applied to various other types of programmable devices, as understood by those skilled in the art.

[0030] The external system 130 can be used to create a desired user configuration or design for the PLD 100 and to generate corresponding configuration data to program (e.g., configure) the PLD 100. For example, the system 130 can provide such configuration data to one or more of the I / O blocks 102, SERDES blocks 150, and / or other portions of the PLD 100. Accordingly, the logic blocks 104, various routing resources, and any other appropriate components of the PLD 100 can be configured to operate in accordance with the user-specified application.

[0031] In the illustrated embodiment, the system 130 is implemented as a computer system. In this regard, the system includes, for example, one or more processors 132 that can be configured to execute instructions, such as software instructions, provided in one or more memories 134 and / or stored in a non-transitory form in one or more non-transitory machine-readable media 136 (e.g., which can be internal or external to the system 130). For example, in certain embodiments, the system 130 can run PLD configuration software, such as the Lattice Diamond system planning software provided by Lattice Semiconductor Corporation, to allow a user to create a desired configuration and to generate corresponding configuration data to program the PLD 100.

[0032] For example, the system 130 also includes a user interface 135 (e.g., a screen or display) to display information to a user and one or more user input devices 137 (e.g., a keyboard, mouse, trackball, touch screen, and / or other devices) to receive user commands or design inputs to prepare a desired configuration for the PLD 100.

[0033] Figure 2A block diagram of logic blocks 104 of PLD 100 is illustrated, in accordance with certain aspects of the present disclosure. As described above, PLD 100 includes a plurality of logic blocks 104, including various components for providing logic and arithmetic functions.

[0034] exist Figure 2 In the example embodiment shown, logic blocks 104 can be interconnected with other logic blocks using routing resources. Each logic block 104 includes combinatorial circuitry 240 and register circuitry 250. More specifically, each logic block 104 can include various components, such as one or more lookup tables (LUTs), mode logic circuitry, registers 206 (e.g., flip-flops or latches), and various programmable multiplexers (e.g., programmable multiplexers 212 and 214) for selecting desired signal paths for and / or between logic blocks 104. In this example, combinatorial circuitry 240 accepts four inputs 220A through 220D. Combinatorial circuitry 240 can implement or include a four-input LUT (which may be abbreviated as "4LUT" or "LUT4") and can be programmed using configuration data from PLD 100 to implement any suitable logic operation with four or fewer inputs. Combinatorial circuitry 240 can include various logic elements and / or additional inputs, such as input 220E, to support various modes of functionality, as described herein. The LUTs within the combinational circuit 240 may be of any other suitable size, with any other suitable number of inputs for a particular implementation of the PLD. In some embodiments, different sizes of LUTs may be provided for different logic blocks 104. Figure 4 Various more detailed embodiments of the combinational circuit 240 are initially presented.

[0035] In some embodiments, output signal 222 from combinatorial circuit 240 may be passed through register 206 to provide output signal 233 of logic block 104. In various embodiments, output signal 223 from combinatorial circuit 240 may be passed directly to output 223, as shown. Depending on the configuration of multiplexers 210 through 214 and / or mode logic within combinatorial circuit 240, output signal 222 may be temporarily stored (e.g., latched) in register 206 according to control signal 230. In some embodiments, configuration data for PLD 100 may configure outputs 223 and / or 233 of logic block 104 to be provided as one or more inputs to another logic block 104 (e.g., within another logic block or the same logic block) in a hierarchical or cascaded arrangement (e.g., including multiple levels) to configure logic operations that cannot be implemented in a single logic block 104 (e.g., logic operations with too many inputs to be implemented by a single LUT). Furthermore, logic block 104 may be implemented with multiple outputs and / or interconnects to facilitate selectable operating modes, as described herein.

[0036] The combinational circuit 240 can include mode logic circuitry that can be used for certain configurations of the PLD 100 to efficiently implement arithmetic operations, such as adders, subtracters, comparators, counters, or other operations to efficiently form some extended logic operations (e.g., higher order LUTs operating on multi-bit data) to efficiently implement relatively small RAM and / or to allow selection between logic, arithmetic, extended logic, and / or other selectable modes of operation. In this regard, logic circuits within the combinational circuit 240 can be linked together across multiple logic blocks 104 to pass carry-in input signals 205 and carry-out output signals 207 and / or other signals (e.g., output signals 222) between adjacent logic blocks 104, as described herein. In certain embodiments, logic circuits within the combinational circuit 240 can be linked across multiple logic blocks 104. Figures 9 to 11 More detailed embodiments are provided in

[0037] Figure 2 The logic blocks 104 shown in FIG. 1 are merely examples, and logic blocks 104 according to different embodiments can include different combinations and arrangements of PLD components. Each of the logic blocks 104 can be used to implement a portion of a user design implemented by the PLD 100. In this regard, the PLD 100 can include a number of logic blocks 104 that are used to collectively implement a user design.

[0038] Figure 3 A design process 300 for a PLD according to certain aspects of the present disclosure is illustrated. For example, Figure 3 The process of FIG. 1 can be performed by the system 130 running Lattice Diamond software to configure the PLD 100. In certain embodiments, for example, Figure 3 The various files and information referenced in FIG. 1 can be stored in one or more databases and / or other data structures in the memory 134, the machine-readable medium 136, and / or other means.

[0039] In operation 310, the system 130 receives a user design that specifies a desired functionality of the PLD 100. For example, a user can interact with the system 130 (e.g., through user input devices 137 and hardware description language (HDL) code representing the design) to identify various features of the user design (e.g., high-level logic operations, hardware configurations, and / or other features). In certain embodiments, the user design can be provided in a register transfer level (RTL) description (e.g., a gate-level description). The system 130 can perform one or more rule checks to confirm that the user design describes a valid configuration of the PLD 100. For example, the system 130 can reject invalid configurations and / or request that the user provide new design information, as appropriate.

[0040] In operation 320, the system 130 synthesizes the design to create a netlist (e.g., a synthesized RTL description) that identifies the user-designed abstract logic implementation as a plurality of logic components (e.g., also referred to as netlist components). In certain embodiments, the netlist can be stored in a native generic database (NGD) file in electronic design interchange format (EDIF).

[0041] In certain embodiments, synthesizing the design into a netlist in operation 320 can involve converting (e.g., translating) a high-level description of the logic operations, hardware configurations, and / or other features in the user design into a set of PLD components (e.g., logic blocks 104 and other components of the PLD 100 configured for logic, arithmetic, or other hardware functions to implement the user design) and their associated interconnections or signals. According to embodiments, the converted user design can be represented as a netlist.

[0042] In certain embodiments, synthesizing the design into a netlist in operation 320 can also involve performing an optimization process on the user design (e.g., the user design converted / translated into a set of components and their associated interconnections or signals) to reduce propagation delay, consumption of PLD resources and routing resources, and / or otherwise optimize performance of the PLD when configured to implement the user design. According to embodiments, the optimization process can be performed on the netlist representing the converted / translated user design. According to embodiments, the optimization process can represent the optimized user design in the netlist (e.g., produce an optimized netlist).

[0043] In certain embodiments, the optimization process can include optimizing logic function operations, ripple arithmetic operations, and / or certain instances of an extended logic function operation that would consume multiple configurable PLD components (e.g., logic blocks 104 and / or routing resources) when the PLD is configured to implement the user design. For example, the optimization process can include detecting multiple patterns or configurable logic blocks implementing logic function operations, ripple arithmetic operations, extended logic function operations, and / or corresponding routing resources in the user design, swapping the operational modes of the logic blocks implementing the various operations to reduce the number of PLD components and / or routing resources used to implement the operations and / or reduce the propagation delay associated with the operations, and / or reprogramming the corresponding LUTs and / or mode logic to interpret the swapped operational modes.

[0044] In another example, the optimization process can include detecting an extended logic function operation and / or corresponding routing resources in the user design, implementing the extended logic operation as a plurality of modes or a convertible logic block having a single physical logic block output, routing or coupling the logic block output of a first set of logic blocks to an input of a second set of logic blocks to reduce a number of PLD components used to implement the extended logic operation and / or routing resources and / or reduce a propagation delay associated with the extended logic operation, and / or programming the corresponding LUTs and / or mode logic to implement the extended logic function operation using at least the first set of logic blocks and the second set of logic blocks.

[0045] In another example, the optimization process can include detecting a plurality of modes or configurable logic blocks implementing logic function operations, ripple arithmetic operations, extended logic function operations and / or corresponding routing resources in the user design, swapping the operational modes of the logic blocks implementing the various operations to provide programmable registers along signal paths within the PLD to reduce a propagation delay associated with the signal paths, and reprogramming the corresponding LUTs, mode logic and / or other logic block control bits / registers to account for the swapped operational modes and / or to program the programmable registers to store or latch signals on the signal paths.

[0046] In operation 330, system 130 performs a mapping process that identifies components of PLD 100 that can be used to implement the user design. In this regard, system 130 can map the optimized netlist (e.g., stored as a result of the optimization process in operation 320) to various types of components provided by PLD 100 (e.g., logic blocks 104, embedded hardware and / or other portions of PLD 100) and their associated signals (e.g., in a logical manner, but not yet assigned placement or routing). In certain embodiments, the mapping can be performed on one or more previously stored NGD files, with the mapping results stored as a physical design file (e.g., also referred to as an NCD file). In certain embodiments, the mapping process can be performed as part of the synthesis process in operation 320 to produce a netlist mapped to PLD components.

[0047] In operation 340, system 130 performs a placement process to assign the mapped netlist components to specific physical components (e.g., to specific logic blocks 104, routing resources and / or other physical components of PLD 100) that reside at specific physical locations of PLD 100, thereby determining a layout of PLD 100. In certain embodiments, the placement can be performed on one or more previously stored NCD files, with the placement results stored as another physical design file.

[0048] In operation 350, the system 130 performs a routing process to route connections (e.g., using routing resources) among the components of the PLD 100 based on the placement layout determined in operation 340, thereby implementing physical interconnections among the placed components. In certain embodiments, the routing can be performed on one or more previously stored NCD files, with the routing results stored as another physical design file.

[0049] In various embodiments, routing the connections in operation 350 can also involve performing an optimization process on the user design to reduce propagation delay, consumption of PLD resources and / or routing resources, and / or to otherwise optimize the configuration for performance of the PLD when implementing the user design. In certain embodiments, the optimization process can be performed on the physical design file representing the translated user design, and the optimization process can represent the optimized user design in the physical design file (e.g., resulting in an optimized physical design file).

[0050] In certain embodiments, the optimization process can include optimizing logic function operations, ripple arithmetic operations, and / or certain instances of an extended logic function operation that would occupy multiple configurable PLD components (e.g., logic blocks 104 and / or routing resources) when the PLD is configured to implement the user design. For example, the optimization process can include detecting multiple instances of logic function operations, ripple arithmetic operations, extended logic function operations, and / or corresponding routing resources in the user design, swapping the operational modes of the logic blocks that would implement the various operations to reduce the number of PLD components and / or routing resources used to implement the operations and / or to reduce the propagation delay associated with the operations, and / or reprogramming the corresponding LUTs and / or mode logic to account for the swapped operational modes.

[0051] In another example, the optimization process can include detecting an extended logic function operation and / or corresponding routing resources in the user design, implementing the extended logic operation as multiple modes or transformable logic blocks having a single physical logic block output, routing or coupling the logic block outputs of a first set of logic blocks to the inputs of a second set of logic blocks to reduce the number of PLD components used to implement the extended logic operation and / or routing resources and / or to reduce the propagation delay associated with the extended logic operation, and / or programming the corresponding LUTs and / or mode logic to implement the extended logic function operation using at least the first set of logic blocks and the second set of logic blocks.

[0052] In another example, the optimization process can include detecting multiple patterns or configurable logic blocks in the user design that implement logic function operations, ripple arithmetic operations, extended logic function operations, and / or corresponding routing resources, swapping the operational modes of the logic blocks that implement the various operations to provide programmable registers along the signal paths within the PLD to reduce the propagation delay associated with the signal paths, and reprogramming the corresponding LUTs, mode logic, and / or other logic block control bits / registers to account for the swapped operational modes and / or to program the programmable registers to store or latch signals on the signal paths.

[0053] Changes in the routing can be propagated back to previous operations, such as synthesis, mapping, and / or placement, to further optimize various aspects of the user design.

[0054] Accordingly, after operation 350, one or more physical design files can be provided that specify the user design that was synthesized (e.g., transformed and optimized), mapped, placed, and routed (e.g., further optimized) for the PLD 100 (e.g., by combining the results of the corresponding previous operations). In operation 360, the system 130 generates configuration data for the synthesized, mapped, placed, and routed user design. In operation 370, the system 130 configures the PLD 100 with the configuration data, e.g., by loading the configuration data bitstream into the PLD 100 through the connection 140.

[0055] Figure 4 An example logic block 400, such as the logic block 104, is illustrated in accordance with certain aspects of the present disclosure. The logic block 400 includes a combinational portion or circuit 440 coupled to a register portion or circuit 450, as shown.

[0056] In this logic block 400, two combinational modes are combined into a single FS output. The logic block 400 supports two combinational modes: (1) FS in 4LUT mode (by selecting F) can support any 4-input combination function of A, B, C, D inputs; (2) FS in ripple mode can support various ripple functions (such as add, subtract, multiply, increment) of one output bit as well as progress to the next bit. The logic block 400 register circuit (output Q) 450 supports sequential functions. The logic block 400 illustrates a baseline logic block that serves as a comparison for the improvements in the logic blocks presented herein.

[0057] Next, assume that each logic block has a combinational portion and a register portion (as shown in Figure 2 and Figure 4 The focus of the remainder of the present disclosure is on the combinational portion, so the register circuit 450 is not shown in the remaining figures. It is also assumed that distributed RAM can also be supported, but this functionality is known and not explicitly shown in the figures.

[0058] Figure 5 An example combinational circuit 540 is illustrated that is representative of a logic block, such as logic block 104, in accordance with certain aspects of the present disclosure. Combinational circuit 540 includes 3LUTs 502, 504, a ripple circuit 510, and a three-to-one (sometimes abbreviated as 3:1 or 3-to-1) multiplexer (MUX) 512. As shown, each 3LUT 502, 504 is in series with a respective inverter, with the 3LUT in series with an inverter representing an example 3LUT circuit. The output signals 514, 516 of the 3LUTs 510, 512 (in this example, after inversion) are provided to the multiplexer 512 and the ripple circuit 510, respectively (inputs labeled PRP_N and GEN_N, respectively). The ripple circuit in turn can generate an output provided as an input to the multiplexer 512 (labeled “prop”) and a select signal (“sel”) used to select the multiplexer 512 output.

[0059] A truth table for the multiplexer 512 is illustrated, where in this example, if sel = 1, then the output of the multiplexer 512 is the output of the ripple circuit 510 (labeled “prop”), regardless of the value of the input D. If sel = 0, then the input D is used to select one of the LUT inputs as the output of the multiplexer 512. In other words, when in a logic or LUT mode, the prop input is ignored (sel = 0), and the multiplexer 512 behaves as a simple 2-to-1 multiplexer controlled by the D input to select one of the 3LUT outputs 514, 516, which provides a 4LUT function (and can also be referred to as a LUT mode or 4LUT mode). When ripple logic is enabled, sel will be responsive to cin, and the signal labeled “prop” is selected for the ripple function, as appropriate. Configuration bits that can be set in a design process, such as a design process in Figure 3 The “sel” bit can be determined by configuration bits that can be set in a design process, such as a design process in

[0060] A conventional combinational circuit includes two 3LUTs, such as 502 and 504, feeding into a 2-to-1 multiplexer. The output of the multiplexer is selectable by the input D to provide a 4LUT function. The conventional combinational circuit also includes a ripple circuit that can support various ripple functions for one output bit as well as an output carry signal cout. Combinational circuit 540 has the same or similar functionality as the conventional combinational circuit, but without the added delay of the additional multiplexer and buffer. Instead, the ripple mode is introduced in parallel with the final stage 2-to-1 multiplexer of the LUT4, making it a 3-to-1 multiplexer 512. Thus, the LUT circuit outputs 514, 516 and the ripple logic circuit output “prop” can be received by the multiplexer 512 simultaneously.

[0061] Figure 6 FIGURE illustrates an example embodiment of a rippler circuit 600, such as the rippler circuit 510 in Figure 5 Note that the nomenclature used for signals herein, a signal ending in "n" means that the signal is low. While Figure 6 The rippler circuit 600 here illustrates the use of configuration bits labeled mc1n_gen and mc1n_rip, although not shown in

[0062] Figure 7 FIGURE illustrates an example combinatorial circuit 740 of a logic block, such as the logic block 104, in accordance with certain aspects of the present disclosure. The combinatorial circuit 740 is similar to the combinatorial circuit 540 of Figure 5 but provides means to favor certain destinations for higher performance. The FS output is used for speed critical destinations. The FS' output is generated by buffering the FS output using a buffer 714 to handle higher fanout loads (e.g., connecting longer distances within a PLD). The FS output and the FS' output are functionally identical in all modes, so they can both be used in all modes. Then, routing only needs to support a single combined output consisting of the combined destinations of FS and FS'.

[0063] Figure 8 FIGURE illustrates an example sub-block or slice 800 for a PLD, such as the PLD 100, in accordance with certain aspects of the present disclosure. In certain embodiments, the slice 800 includes two combinatorial circuits 802a and 802b, outputting FS0 and FS1, respectively. The combinatorial circuits 802a, 802b are functionally separated by a line 810. The combinatorial circuits 802a, 802b can be used and configured separately to receive inputs AO-D0 and Al-Dl, respectively, or can be configured so as to use an additional input (Ml) to dynamically multiplex between their respective LUT outputs (shown as F and F0 at multiplexer 812) on the output FS1.

[0064] Figure 8 FIGURE illustrates the slice 800, providing the same functionality as a conventional slice, but without the drawbacks of additional delay of certain output multiplexers and buffers used. The output FS0 is used for the same purposes as the output FS0 in Figure 5The illustrated implementation is identical to the implementation of combinational circuit 802a (combinational circuit 802b is identical implementation to combinational circuit 540). The output FS1 provides the same functionality as the FS1 output in a conventional slice (LUT4 ripple and LUT5 support), but without the addition of multiplexers and buffers downstream of the LUT4 output. In a similar manner, the LUT5 support and ripple mode are introduced in parallel with the final stage multiplexer 812 of LUT4, increasing the multiplexer from a 2: 1 mux (in a conventional slice) to a 4: 1 mux. When FS1 is in LUT4 mode, selr and selm are both zero and the inputs, FS0 and prop1 are not selected, and the 4: 1 mux behaves as a simple 2: 1 mux controlled by D1 input. When the ripple logic is enabled, selm is zero and selr will select prop1 for ripple functionality in response to cin and as the case can be. When the LUT5 mode is enabled, selr is zero and selm will select FS0 for LUT5 operation in response to M1 and as the case can be. The configuration bits mc1_rip, mc1_gen, and mc1_lut5 are illustrated to select the mode of operation of combinational circuits 802a and 802b. For example, the configuration bits can set the inputs to multiplexer 812 for selr and selm so that combinational circuit 802b (and thus the corresponding logic block) is in LUT mode or ripple mode.

[0065] Combinational circuit 802b includes a ripple circuit 814 and a four-to-one multiplexer 812, as illustrated. The truth table illustrated in multiplexer 812 is expanded for illustration purposes. The LUT5 mode and the ripple mode are mutually exclusive so that configuration bits mc1_rip and mc1_lut5 are not programmed to a logic high level at the same time. Thus, there are two truth tables 820 and 822 for multiplexer 812, as illustrated. If configuration bit mc1_rip is a logic high level, then the lower truth table 822 is applied. If configuration bit mc1_lut5 is a logic high level, then the upper truth table 820 is applied.

[0066] Figure 9 FIG. illustrates an example embodiment of a ripple circuit 900, such as ripple circuit 814 in Figure 8 FIG. illustrates an example embodiment of a ripple circuit 900, such as ripple circuit 814 in

[0067] Figure 10 FIG. illustrates another example slice 1000 for a PLD, in accordance with certain aspects of the present disclosure. Figure 9 FIG. illustrates another example slice 1000 for a PLD, in accordance with certain aspects of the present disclosure. Figure 8The illustrated slice is similar to the example slice 1000, but provides hardware designers with a means to favor certain destinations for higher performance for certain purposes. The FS0, FS1 outputs are for speed critical destinations. The FS0', FS1' outputs handle higher fanout loads. The FS0 outputs and the FS0' outputs are functionally identical in all modes, so they can both be used in all modes. The FS1 outputs and the FS1' outputs are functionally identical in all modes, so they can both be used in all modes. Then, the routing only needs to support two combined outputs: FS0 plus FS0' and FS1 plus FS1'.

[0068] Figure 11 An example method of operating a logic block, such as logic block 104 or 400, in accordance with certain aspects of the present disclosure is illustrated. The logic block can include combinational circuitry, including a first LUT circuit, a second LUT circuit, a glitch logic circuit, and a three-to-one multiplexer circuit, for example, as illustrated in Figure 4 and Figure 5 In step 1102, a first output, such as output signal 514, is generated by a first LUT circuit, such as a LUT circuit including 3LUT 502 and connected inverters in Figure 5 In step 1104, a second output, such as output signal 516, is generated by a second LUT circuit, such as a LUT circuit including 3LUT 504 followed by an inverter in Figure 5 In step 1106, a third output is generated by a glitch logic circuit, such as glitch logic circuit 510 in Figure 5 In step 1108, the first output, the second output, and the third output are received, such as by three-to-one multiplexer 512 in Figure 5 In step 1110, an output of the logic block is generated based on the first output, the second output, and the third output. By selectively providing one of the first output, the second output, and the third output, the multiplexer, such as three-to-one multiplexer 512 in Figure 5 Figure 5 The first output, the second output, and the third output can be received by the multiplexer simultaneously, thereby eliminating intermediate components, such as intermediate multiplexers, used in conventional logic blocks, and providing related improvements in speed and routing cost.

[0069] Those skilled in the art will realize that the aforementioned apparatus, systems, and methods can be modified by varying the above-described specific examples. Accordingly, those skilled in the art will understand that the embodiments encompassed by the present disclosure are not limited to the particular exemplary embodiments described above. In this regard, although illustrative embodiments have been shown and described, a wide range of modifications, changes, and substitutes are contemplated in the aforementioned disclosure. It should be understood that such variations can be made to the foregoing without departing from the scope of the present disclosure. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the present disclosure.

Claims

1. A programmable logic device (PLD), comprising: Logic blocks, including: a first lookup table (LUT) circuit configured to generate a first output; a second LUT circuit configured to generate a second output; a ripple logic circuit configured to receive the first output and the second output and generate a third output; and A three-to-one multiplexer circuit is configured to receive the first output, the second output, and the third output and selectively generate an output of the logic block.

2. The PLD of claim 1 , wherein the first output, the second output, and the third output are received simultaneously by the three-to-one multiplexer circuit.

3. The PLD of claim 1 , wherein the first LUT circuit comprises a first three-input LUT (3LUT) connected in series with a first inverter, wherein the first output is an output of the first inverter, wherein the second LUT circuit comprises a second 3LUT connected in series with a second inverter, and wherein the second output is an output of the second inverter.

4. The PLD of claim 3, wherein the three-to-one multiplexer circuit selectively implements a four-input LUT (4LUT) mode from the first 3LUT and the second 3LUT by selecting one of the first output and the second output.

5. The PLD of claim 3, wherein the ripple logic circuit is further configured to receive a carry-in signal from one logic block and generate a carry-out signal for another logic block.

6. The PLD of claim 5, wherein the ripple logic circuit is further configured to generate a select signal for the three-to-one multiplexer circuit.

7. The PLD of claim 3 , further comprising: A buffer is configured to receive the output of the logic block and generate a fan-out output.

8. The PLD of claim 4 , wherein the ripple logic circuit is further configured to generate a select signal for the three-to-one multiplexer circuit, and wherein the select signal determines a mode of the logic block as either a LUT mode or a ripple mode.

9. A method of operating the PLD of claim 1, comprising: generating the first output by the first LUT circuit; generating the second output by the second LUT circuit; generating, by the ripple logic circuit, the third output from the first output and the second output; receiving, by the three-to-one multiplexer circuit, the first output, the second output, and the third output; as well as The output of the logic block is generated by the three-to-one multiplexer circuit based on the first output, the second output, and the third output.

10. A method of programming the PLD according to claim 1, the method comprising: generating configuration data to configure physical components of the PLD according to the synthesized design; as well as The PLD is programmed with the configuration data.

11. The PLD of claim 8, further comprising: The second logic block includes: a second multiplexer circuit configured to selectively implement a second 4LUT mode, a 5LUT mode, or a second ripple mode function.

12. A method of operating a logic block within a programmable logic device (PLD), the method comprising: generating, by a first lookup table (LUT) circuit, a first output; generating, by a second LUT circuit, a second output; generating, by a ripple logic circuit, a third output from the first output and the second output; receiving the first output, the second output, and the third output; and generating an output of the logic block based on the first output, the second output, and the third output, wherein the receiving and the generating are performed by a three-to-one multiplexer circuit.

13. The method of claim 12, wherein the first output, the second output, and the third output are simultaneously received by the three-to-one multiplexer circuit.

14. The method of claim 12, wherein the first LUT circuit comprises a first three-input LUT (3LUT) in series with a first inverter, wherein the first output is an output of the first inverter, wherein the second LUT circuit comprises a second 3LUT in series with a second inverter, and wherein the second output is an output of the second inverter.

15. The method of claim 14, further comprising: receiving, by the ripple logic circuit, a carry-in signal from one logic block; and generating, by the ripple logic circuit, a carry-out signal for another logic block.

16. The method of claim 15, further comprising: generating, by the ripple logic circuit, a select signal for the three-to-one multiplexer circuit, wherein the select signal determines a mode of the logic block as either a LUT mode or a ripple mode.

17. The method of claim 14, further comprising: generating, by a buffer, a fan-out output from the output of the logic block.

18. The method of claim 12, wherein a programmable logic device (PLD) comprises the logic block, and wherein the method further comprises: generating configuration data to configure physical components of the PLD according to a synthesized design, the physical components including the logic block; and programming the PLD with the configuration data.

19. A method of programming a programmable logic device (PLD), the PLD comprising: a plurality of programmable logic blocks (PLBs), wherein each PLB of the plurality of PLBs comprises: a first lookup table (LUT) circuit configured to generate a first output; a second LUT circuit configured to generate a second output; a ripple logic circuit configured to receive the first output and the second output and generate a third output; and a multiplexer circuit configured to selectively place the PLB in a LUT mode or a ripple mode by selecting one of the first output, the second output, and the third output as an output of the PLB, the method comprising: generating configuration data to configure physical components of the PLD according to a synthesized design, the synthesized design including one of the LUT mode or the ripple mode for each PLB; and programming the PLD with the configuration data. programming the PLD with the configuration data.

20. The method of claim 18, wherein each PLB includes a generation register and a ripple register coupled to the ripple logic circuit, and wherein a mode selected from among the LUT mode or the ripple mode is determined by a value of the ripple register and a value of the generation register established during the programming of the PLD.

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