Bus spacing determination method and device of bus network, equipment and medium

Abstract

The invention provides a bus spacing determination method and device for a bus network, equipment and a medium, and the method comprises the steps: configuring initial wiring parameters of signal lines in the bus network based on the bus width and a DRC rule, and determining an initial sampling point set; parallel simulation processing is carried out on the signal delay of each signal line of each group of candidate wiring parameter configuration in the initial sampling point set, and the maximum delay value of each group of candidate wiring parameter configuration is determined; and training the Gaussian process prior model based on each group of candidate wiring parameter configurations and the corresponding maximum delay value, determining the optimal wiring parameter configuration based on the acquisition function and the prediction delay distribution, and performing next round of training on the Gaussian process prior model based on the optimal wiring parameter configuration. And determining the optimal line width and line distance configuration. The bus spacing of the bus network is dynamically adjusted through the Gaussian process prior model, and the optimal line width and line spacing configuration efficiency and accuracy of the bus network are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic design automation (EDA), in particular to a bus pitch determination method, device and equipment of bus network and medium. BACKGROUND

[0002] In the electronic design automation (EDA) design, the width and pitch of the bus network directly affect the signal integrity (SI), power integrity (PI), electromagnetic compatibility (EMC) and manufacturing cost. The bus design mainly adopts the method of combining rule-driven and simulation optimization. Rule-driven design relies on IPC standards and design manuals, which is suitable for low-frequency and ordinary digital circuits. For high-speed signals (such as DDR, PCIe) and radio frequency circuits, designers will use simulation tools (such as HyperLynx, ADS, HFSS) to analyze signal integrity (SI) and power integrity (PI) to optimize the width and pitch of the wire.

[0003] In the prior art, the bus parameters are designed with the aid of a simple model of delay, and iteration is not stopped. For example, the delay of each line is inversely proportional to its line width, and the increase of the line spacing reduces the capacitance between the wires and reduces the delay. However, after considering more cases, the problem becomes very complex, such as the inductance between the wires, which is related to the current flow direction of the wire itself. For two wires in the opposite direction, the reduction of the spacing increases the capacitance and reduces the inductance. It is difficult to determine whether the actual delay is increased or decreased. In addition, the bus width is a fixed value, and the reduction of the delay of one wire may increase the delay of other wires. Therefore, how to provide the efficiency of the bus pitch determination of the bus network has become a technical problem that cannot be ignored. SUMMARY

[0004] Therefore, the purpose of the present application is to provide a bus pitch determination method, device and equipment of bus network and medium, which automatically optimizes the line width and line spacing of each signal line in the bus network through a Gaussian process prior model to achieve the goal of minimizing the maximum delay, and improves the efficiency and accuracy of the optimal line width and line spacing configuration of the bus network.

[0005] The bus pitch determination method of the bus network provided in the embodiments of the present application comprises: The initial routing parameters of each signal line in the bus network are configured based on the preset bus width and DRC rules, and an initial sample point set is determined; wherein the initial routing parameters include the line width of the signal line and the line spacing between the previous signal line; perform parallel simulation processing on signal delays of signal lines of each candidate routing parameter configuration in the initial sample point set to determine a maximum delay value of each candidate routing parameter configuration; train a Gaussian process prior model based on each candidate routing parameter configuration and the corresponding maximum delay value, determine an optimal routing parameter configuration based on an acquisition function and a predicted delay distribution output by the Gaussian process prior model, perform next round training on the Gaussian process prior model based on the optimal routing parameter configuration, and determine an optimal line width and line spacing configuration when training reaches a maximum iteration number.

[0006] In a possible implementation, the initial routing parameters of each signal line in the bus network are combined based on the preset bus width and the DRC rule to determine the initial sample point set, including: The initial routing parameters of each signal line are configured based on random sampling under the condition that the line width and line spacing of each signal line are within the preset parameter value range and the bus width constraint is met to generate a plurality of candidate routing parameter configurations. It is checked whether each candidate routing parameter configuration meets the DRC rule, and all candidate routing parameter configurations meeting the DRC rule are taken as the initial sample point set.

[0007] In a possible implementation, the Gaussian process prior model is trained based on each candidate routing parameter configuration and the corresponding maximum delay value, including: A square exponential kernel function is used as a covariance function, each candidate routing parameter configuration is taken as input information of the Gaussian process prior model, and the maximum delay value is taken as an output target of the Gaussian process prior model. The Gaussian process prior model is controlled to learn a distribution relationship between each candidate routing parameter configuration and the corresponding maximum delay value. Hyperparameters in the square exponential kernel function and noise variance are optimized based on maximum marginal likelihood to realize training of the Gaussian process prior model.

[0008] In a possible implementation, the predicted delay distribution is determined in the following manner: A first covariance matrix between a new routing parameter configuration and the existing candidate routing parameter configuration is determined. The first covariance matrix, a covariance matrix between the existing candidate routing parameter configurations, and the maximum delay value between the new routing parameter configurations are used to calculate a prediction mean and a variance to determine a prediction delay distribution of the new routing parameter configuration.

[0009] In a possible implementation, the optimal routing parameter configuration is determined based on the prediction delay distribution output by the acquisition function and the Gaussian process prior model, including: searching for a line width and line spacing configuration parameter with a maximum improvement expectation value in the entire line width and line spacing configuration space based on probability information of a maximum delay value provided on the prediction delay distribution by using the acquisition function; detecting whether the line width and line spacing configuration parameter meets the bus width and the DRC rule; if yes, taking the line width and line spacing configuration parameter as the optimal routing parameter configuration, and if no, continuing to search in the entire line width and line spacing configuration space.

[0010] In a possible implementation, the signal delay of each signal line of each candidate routing parameter configuration in the initial sampling point set is processed in parallel to determine a maximum delay value of each candidate routing parameter configuration, including: allocating each candidate routing parameter configuration to a corresponding processing process, and controlling the processing process to listen to a running state of each subtask in real time, where the subtask is a simulation task of determining the signal delay of the signal line; if it is detected that the subtask ends abnormally, controlling the processing process to automatically record abnormal information, and resubmitting the subtask for simulation processing to determine the maximum delay value according to a subtask identifier.

[0011] In a possible implementation, after the Gaussian process prior model is trained based on each candidate routing parameter configuration and the corresponding maximum delay value, the bus spacing determination method further includes: storing product information obtained in each training process of the Gaussian process prior model.

[0012] Embodiments of the present application further provide a bus spacing determination apparatus of a bus network, and the bus spacing determination apparatus includes: a parameter configuration module configured to configure an initial routing parameter of each signal line in a bus network based on a preset bus width and a DRC rule, and determine an initial sampling point set, where the initial routing parameter includes a line width of the signal line and a line spacing between the signal line and a previous signal line; a delay calculation module configured to process, in parallel, a signal delay of each signal line of each candidate routing parameter configuration in the initial sampling point set, and determine a maximum delay value of each candidate routing parameter configuration; The processing module is configured to train a Gaussian process prior model based on each candidate routing parameter configuration and the corresponding maximum delay value, determine an optimal routing parameter configuration based on a collection function and a predicted delay distribution output by the Gaussian process prior model, and perform next-round training on the Gaussian process prior model based on the optimal routing parameter configuration until a maximum iteration number is reached to determine an optimal line width and line spacing configuration.

[0013] The electronic device comprises a processor, a memory and a bus. The memory stores machine readable instructions executable by the processor. When the electronic device is running, the processor and the memory communicate through the bus. The machine readable instructions are executed by the processor to perform the steps of the bus network bus pitch determination method described above.

[0014] The electronic device comprises a processor, a memory and a bus. The memory stores machine readable instructions executable by the processor. When the electronic device is running, the processor and the memory communicate through the bus. The machine readable instructions are executed by the processor to perform the steps of the bus network bus pitch determination method described above.

[0015] The bus network bus pitch determination method, device, equipment and medium provided by the embodiment of the present application comprise: configuring initial routing parameters of each signal line in a bus network based on a preset bus width and a DRC rule to determine an initial sample point set; wherein the initial routing parameters comprise a line width of the signal line and a line spacing between the signal line and a previous signal line; performing parallel simulation processing on signal delays of each candidate routing parameter configuration of each group of candidate routing parameter configurations in the initial sample point set to determine a maximum delay value of each candidate routing parameter configuration; training a Gaussian process prior model based on each candidate routing parameter configuration and the corresponding maximum delay value, determining an optimal routing parameter configuration based on a collection function and a predicted delay distribution output by the Gaussian process prior model, and performing next-round training on the Gaussian process prior model based on the optimal routing parameter configuration until a maximum iteration number is reached to determine an optimal line width and line spacing configuration. The line width and line spacing of each signal line in the bus network are automatically optimized by the Gaussian process prior model to achieve the goal of minimizing the maximum delay, thereby improving the efficiency and accuracy of the optimal line width and line spacing configuration of the bus network.

[0016] To make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the following preferred embodiments are described in detail below, and the accompanying drawings are described as follows. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced as follows. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be regarded as a limitation on the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0018] Figure 1 A flow chart of a bus pitch determination method of a bus network provided by an embodiment of the present application; Figure 2 A structure schematic diagram of a bus pitch determination device of a bus network provided by an embodiment of the present application; Figure 3 A structure schematic diagram of a bus pitch determination device of a bus network provided by an embodiment of the present application; Figure 4 A structure schematic diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. The components of the embodiments of the present application described and shown in the drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, every other embodiment obtained by those skilled in the art without creative labor belongs to the scope of the present application.

[0020] Firstly, the application scenarios applicable to the present application are introduced. The present application can be applied to the field of electronic design automation (EDA).

[0021] It is found through research that in the prior art, bus parameters are designed according to a simple model of delay, and iteration is not stopped. For example, the delay of each line is inversely proportional to the line width of the line itself, and an increase in the line spacing reduces the capacitance between the lines and reduces the delay. However, after considering more cases, the problem becomes very complex, for example, there is an inductance effect between the lines, the inductance is related to the current flow direction of the line itself, and for two lines in the opposite direction, the reduction of the spacing increases the capacitance and reduces the inductance. It is difficult to determine whether the actual delay is increased or decreased. In addition, the bus width is a fixed value, and a reduction in the delay of one of the lines can cause an increase in the delay of the other lines. Therefore, how to provide the efficiency of the bus spacing determination of the bus network has become a technical problem that cannot be underestimated.

[0022] Based on this, the bus spacing determination method of the bus network provided by the embodiments of the present application dynamically adjusts the bus spacing of the bus network through the Gaussian process prior model, and improves the efficiency and accuracy of the optimal line width and line spacing configuration of the bus network.

[0023] Please refer to Figure 1 , Figure 1 The flowchart of the bus spacing determination method of the bus network provided by the embodiments of the present application is shown in FIG. 1. Figure 1 The bus spacing determination method provided by the embodiments of the present application includes the following steps. S101: Configure the initial routing parameters of each signal line in the bus network based on the preset bus width and DRC rules, and determine an initial sampling point set; wherein the initial routing parameters include the line width of the signal line and the line spacing between the signal line and the previous signal line.

[0024] In this step, the initial routing parameters of each signal line in the bus network are configured based on the preset bus width and DRC rules, and an initial sampling point set is determined.

[0025] The initial routing parameters include the line width of the signal line and the line spacing between the signal line and the previous signal line.

[0026] Here, if there are n signal lines, a set of initial points {w[1] s[1]w[2] s[2]... w[n]} that satisfy the constraint conditions are randomly sampled in the variable space (where w represents the line width and s represents the line spacing), the sampling points ensure that ∑(w[i]+s[i]) = bus width, and the sampling satisfies the DRC rule. A plurality of samples are obtained as the initial sampling point set.

[0027] In one possible implementation, the initial routing parameters of each signal line in the bus network are combined based on the preset bus width and DRC rules to determine the initial sampling point set, including: The initial routing parameters of each signal line are configured based on random sampling under the condition that the line width and the line spacing of each signal line are within the preset parameter value range and the bus width constraint is met, and a plurality of candidate routing parameter configurations are generated; whether each candidate routing parameter configuration meets the DRC rule is checked, and all candidate routing parameter configurations meeting the DRC rule are taken as the initial sampling point set.

[0028] It should be noted that the bus width constraint is that the sum of all line widths and line spacings is equal to the total bus width. The DRC (Design Rule Check) rule is that each line width must meet the minimum line width and maximum line width limit, and the line spacing meets the minimum line spacing limit.

[0029] In specific embodiments, the line width is randomly selected from the range of [w_min, w_max], the line spacing is randomly selected from the range of [s_min, s_max], and whether the total bus width of the candidate routing parameter configuration meets the condition w1 + w2 + w3 + w4 + s1 + s2 + s3 ≤ 30μm is checked. If all conditions are met, the candidate routing parameter configuration is retained. S102: Perform parallel simulation processing on the signal delay of each signal line of each candidate routing parameter configuration in the initial sampling point set, and determine the maximum delay value of each candidate routing parameter configuration.

[0030] In this step, the signal delay of each signal line of each candidate routing parameter configuration in the initial sampling point set is simulated in parallel to determine the maximum delay value of each candidate routing parameter configuration.

[0031] Here, the signal delay of each signal line of each candidate routing parameter configuration can be determined according to a timing simulation tool.

[0032] In a possible implementation, the parallel simulation processing on the signal delay of each signal line of each candidate routing parameter configuration in the initial sampling point set to determine the maximum delay value of each candidate routing parameter configuration includes: Each candidate routing parameter configuration is assigned to a corresponding processing process, and the processing process is controlled to listen to the running state of each subtask in real time; wherein the subtask is a simulation task for determining the signal delay of a signal line; if it is detected that the subtask ends abnormally, the processing process is controlled to automatically record abnormal information, and the subtask is resubmitted for simulation processing to determine the maximum delay value according to the subtask identifier.

[0033] Here, each set of candidate routing parameter configuration is assigned to the corresponding processing process, and the processing process is controlled to monitor the running state of each subtask in real time. If it is detected that the subtask ends abnormally, the processing process is controlled to automatically record abnormal information, and the subtask is resubmitted for simulation processing according to the subtask identifier, so as to improve the efficiency of the simulation task.

[0034] S103: Training the Gaussian process prior model based on each set of candidate routing parameter configuration and the corresponding maximum delay value, determining the optimal routing parameter configuration based on the acquisition function and the predicted delay distribution output by the Gaussian process prior model, and performing the next round of training on the Gaussian process prior model based on the optimal routing parameter configuration, until the optimal line width and line spacing configuration is determined when the training reaches the maximum number of iterations.

[0035] In this step, the Gaussian process prior model is trained based on each set of candidate routing parameter configuration and the corresponding maximum delay value, the optimal routing parameter configuration is determined based on the acquisition function and the predicted delay distribution output by the Gaussian process prior model, and the next round of training is performed on the Gaussian process prior model based on the optimal routing parameter configuration, until the optimal line width and line spacing configuration is determined when the training reaches the maximum number of iterations. It should be noted that the "optimal line width and line spacing configuration" refers to a set of parameter combinations of the width of the signal line and the spacing of the signal line that can best balance signal integrity (SI), power integrity (PI), electromagnetic compatibility (EMC), and manufacturing cost in bus network design through an optimization algorithm.

[0036] It should be noted that the user can set the maximum number of iterations of the tuning or the target value of the tuning, and the iteration is automatically stopped when the maximum number of iterations or the target value is reached.

[0037] Here, the next round of training is performed on the Gaussian process prior model based on the optimal routing parameter configuration, and the optimal line width and line spacing configuration is determined when the training reaches the maximum number of iterations, including: continuing to perform the next round of training on the Gaussian process prior model based on the optimal routing parameter configuration and the corresponding actual maximum delay value, repeating the above steps until the optimal line width and line spacing configuration is determined when the training reaches the maximum number of iterations.

[0038] In one possible implementation, the training of the Gaussian process prior model based on each set of candidate routing parameter configuration and the corresponding maximum delay value includes: (1) Using a square exponential kernel function as a covariance function, each set of candidate routing parameter configuration is used as input information of the Gaussian process prior model, and the maximum delay value is used as the output target of the Gaussian process prior model.

[0039] Here, each set of candidate routing parameter configuration is taken as an input vector X of the Gaussian process prior model, and the output target of the Gaussian process prior model is the maximum delay value y = max(delay(O[i])), delay(O[i]) is a delay value calculation formula, and O[i] represents the line width and line spacing configuration of the i-th signal line. Since the delay is usually related to the line width and line spacing, y can be considered as a function of x: is an observed noise. A Gaussian process prior is placed for the function f(x):

[0040] where m(x) is a prior mean function, gp is a Gaussian process prior function, the covariance function k(x, x') adopts a squared exponential kernel, and the squared exponential kernel is:

[0041] where x is a candidate routing parameter configuration, is another candidate routing parameter configuration, 2 n -1 is the dimension of the candidate routing parameter configuration, is the i-th parameter information in the candidate routing parameter configuration x, i is the i-th parameter information in , , i , , and are all hyperparameters.

[0042] (2) controlling the Gaussian process prior model to learn the distribution relationship between each set of candidate routing parameter configuration and the corresponding maximum delay value; and optimizing the hyperparameters in the squared exponential kernel function and the noise variance based on maximum marginal likelihood to realize training of the Gaussian process prior model.

[0043] where the process of optimizing the hyperparameters in the squared exponential kernel function and the noise variance based on maximum marginal likelihood is: where K is a covariance matrix calculated by the covariance function for all groups of inputs x, I is an identity matrix, n is the dimension, is the noise variance.

[0044] In one possible implementation, the predicted delay distribution is determined by: ​​​Determine a first covariance matrix between the new wiring parameter configuration and the existing candidate wiring parameter configurations; calculate a predicted mean and variance based on the first covariance matrix, the covariance matrix between the existing candidate wiring parameter configurations, and the maximum delay value between the new wiring parameter configurations to determine a predicted delay distribution of the new wiring parameter configuration.

[0045] Here, the predicted delay distribution is determined by the following formula:

[0046]

[0047] in, is the new wiring parameter configuration, y is the predicted maximum delay corresponding to the new wiring parameter configuration, X is a vector consisting of multiple candidate wiring parameter configurations, is the first covariance matrix, k ( ) is the covariance function, For The actual delay f ( ), For Dealing with real delay f ( ), N is a normal distribution.

[0048] In one possible implementation, determining the optimal routing parameter configuration based on the acquisition function and the predicted delay distribution output by the Gaussian process prior model includes: A: Based on the probability information of the maximum delay value provided by the predicted delay distribution, a line width and line spacing configuration parameter having the maximum expected value of improvement is searched for using an acquisition function in the entire line width and line spacing configuration space.

[0049] Here, according to the probability information of the maximum delay value provided by the predicted delay distribution, a configuration parameter of line width and line spacing with the maximum expected value of improvement is searched in the entire configuration space of line width and line spacing using an acquisition function.

[0050] The acquisition function is the EI acquisition function.

[0051] Here, the EI function is formally defined as: . is the currently known best observed value (smallest maximum delay among all sampled configurations). is the actual function value at some new bus configuration. Indicates at point the improvement. If the delay of the new point is less than the current best then the improvement is 0; otherwise, the improvement is Since is a random variable (following the distribution given by the GP), the improvement is also an average of random variables.

[0052] B: detecting whether the configuration parameters of the line width and line spacing meet the bus width and the DRC rule; if yes, the configuration parameters of the line width and line spacing are taken as the optimal routing parameter configuration; if not, the search is continued in the whole line width and line spacing configuration space.

[0053] Here, whether the configuration parameters of the line width and line spacing meet the bus width and the DRC rule is detected; if yes, the configuration parameters of the line width and line spacing are taken as the optimal routing parameter configuration; if not, the search is continued in the whole line width and line spacing configuration space.

[0054] In one possible implementation, after the Gaussian process prior model is trained based on each set of candidate routing parameter configuration and the corresponding maximum delay value, the bus pitch determination method further includes: data storage of the product information obtained in each training process of the Gaussian process prior model.

[0055] In a specific embodiment, step one initializes sampling: 10 sets of line width and line spacing combinations are randomly generated in the range meeting the constraint condition as initial sampling points; the group configuration is composed of the line width of 8 wires and 7 line spacings, constituting a 15-dimensional input vector. Step two simulates and calculates the delay: ​The input information is submitted to the simulation process (such as static timing analysis using `Primetime`), the delay value of each signal line is extracted for each configuration, the maximum wire delay under each configuration is calculated as the objective function value, and all input configurations and output values are collected as the initial training set. Step three: training the Gaussian process prior model: a Gaussian process prior model based on the square exponential kernel function is trained, the model input is a 15-dimensional configuration vector, and the output is the maximum wire delay; the hyperparameters (such as length scale, signal variance, and noise variance) of the model are optimized by maximizing the marginal likelihood function; a proxy model is obtained for predicting the maximum delay and its uncertainty under any configuration. Step four: according to the acquisition function and select a new sampling point: for each candidate configuration in the search space, calculate its EI value, select the configuration with the maximum EI value as the next sampling point, perform DRC check on the next sampling point to ensure that it meets the manufacturing process constraints, generate the corresponding simulation input file, and submit the simulation task. Step five: iterative optimization and model updating: add the simulation results of the new configuration to the training set, update the Gaussian process model, repeat steps four and five until any of the following termination conditions are met: output the optimal configuration, which corresponds to the line width and line spacing assignment; output the corresponding maximum wire delay value, output the complete simulation input file, log file, and visualization chart for user to view the optimization process and results.

[0056] In this application, the delay and configuration of the bus are regarded as a Gaussian process model, a probability distribution is calculated for each sample, and a new configuration is sampled based on this distribution to obtain a better bus delay. The new sample is used to update the model after the actual timing tool calculates the delay, and the posterior probability distribution is obtained to guide the next sampling to obtain more accurate and optimal line width and line spacing configuration.

[0057] The bus pitch determination method provided by the embodiment of the application comprises: configuring initial routing parameters of each signal line in a bus network based on a preset bus width and a DRC rule, and determining an initial sample point set; wherein the initial routing parameters comprise a line width of the signal line and a line spacing between the signal line and a previous signal line; performing parallel simulation processing on signal delays of each signal line configured by each set of candidate routing parameters in the initial sample point set, and determining a maximum delay value of each set of candidate routing parameters; training a Gaussian process prior model based on each set of candidate routing parameters and a corresponding maximum delay value, determining an optimal routing parameter configuration based on an acquisition function and a predicted delay distribution output by the Gaussian process prior model, and performing next-round training on the Gaussian process prior model based on the optimal routing parameter configuration, until an optimal line width and line spacing configuration is determined when training reaches a maximum iteration number. The line width and line spacing of each signal line in the bus network are automatically optimized by the Gaussian process prior model, so as to achieve the goal of minimizing the maximum delay, and the efficiency and accuracy of the optimal line width and line spacing configuration of the bus network are improved.

[0058] Please refer to Figure 2 、 Figure 3 , Figure 2 Figure 1 is a structural schematic diagram of a bus pitch determination device for a bus network provided by an embodiment of the application; Figure 3 Figure 2 is another structural schematic diagram of a bus pitch determination device for a bus network provided by an embodiment of the application. As shown in Figure 2, the bus pitch determination device 200 for the bus network comprises: Figure 2 a parameter configuration module 210, configured to configure initial routing parameters of each signal line in a bus network based on a preset bus width and a DRC rule, and determine an initial sample point set; wherein the initial routing parameters comprise a line width of the signal line and a line spacing between the signal line and a previous signal line; a delay calculation module 220, configured to perform parallel simulation processing on signal delays of each signal line configured by each set of candidate routing parameters in the initial sample point set, and determine a maximum delay value of each set of candidate routing parameters; a processing module 230, configured to train a Gaussian process prior model based on each set of candidate routing parameters and a corresponding maximum delay value, determine an optimal routing parameter configuration based on an acquisition function and a predicted delay distribution output by the Gaussian process prior model, and perform next-round training on the Gaussian process prior model based on the optimal routing parameter configuration, until an optimal line width and line spacing configuration is determined when training reaches a maximum iteration number.

[0059] ​Further, the parameter configuration module 210 is configured to combine the initial routing parameters of each signal line in the bus network based on the preset bus width and the DRC rules to determine an initial sample point set: In the guarantee of the line width and the line spacing of each signal line being within the preset parameter value range and the constraint of the bus width, the initial routing parameters of each signal line are configured based on random sampling to generate a plurality of candidate routing parameter configurations; It is checked whether each candidate routing parameter configuration meets the DRC rules, and all candidate routing parameter configurations meeting the DRC rules are taken as the initial sample point set.

[0060] Further, the processing module 230 is configured to train a Gaussian process prior model based on each group of candidate routing parameter configurations and the corresponding maximum delay value: An exponential square kernel function is taken as a covariance function, each group of candidate routing parameter configurations is taken as input information of the Gaussian process prior model, and the maximum delay value is taken as an output target of the Gaussian process prior model; The Gaussian process prior model is controlled to learn the distribution relationship between each group of candidate routing parameter configurations and the corresponding maximum delay value; The hyperparameters in the exponential square kernel function and the noise variance are optimized based on maximization of marginal likelihood to realize training of the Gaussian process prior model.

[0061] Further, the processing module 230 determines the predicted delay distribution in the following manner: A first covariance matrix between a new routing parameter configuration and the existing candidate routing parameter configurations is determined; The predicted mean and variance are calculated based on the first covariance matrix, the covariance matrix between the existing candidate routing parameter configurations, and the maximum delay value between the new routing parameter configurations to determine the predicted delay distribution of the new routing parameter configuration.

[0062] Further, the processing module 230 is configured to determine an optimal routing parameter configuration based on an acquisition function and the predicted delay distribution output by the Gaussian process prior model: The probability information of the maximum delay value provided on the predicted delay distribution is used to search for a line width and line spacing configuration parameter with a maximum improvement expectation value in the entire line width and line spacing configuration space based on the acquisition function; It is detected whether the line width and line spacing configuration parameter meets the bus width and the DRC rules; If yes, the line width and line spacing configuration parameter is taken as the optimal routing parameter configuration, and if no, the search is continued in the entire line width and line spacing configuration space.

[0063] Further, the delay calculation module 220 is configured to perform parallel simulation processing on the signal delay of each signal line in each candidate routing parameter configuration in the initial sampling point set, and determine a maximum delay value of each candidate routing parameter configuration. Each candidate routing parameter configuration is allocated to a corresponding processing process, and the processing process is controlled to monitor the running state of each subtask in real time, wherein the subtask is a simulation task for determining the signal delay of the signal line. If it is detected that the subtask ends abnormally, the processing process is controlled to automatically record abnormal information, and resubmit the subtask for simulation processing to determine the maximum delay value according to the subtask identifier.

[0064] Further, as shown in Figure 3 The bus network bus pitch determination apparatus 200 further includes a data storage module 240, and the data storage module 240 is configured to: Store the product information obtained in each training process of the Gaussian process prior model.

[0065] The bus network bus pitch determination apparatus provided by the embodiment of the present application includes: a parameter configuration module configured to configure initial routing parameters of each signal line in a bus network based on a preset bus width and a DRC rule, and determine an initial sampling point set; wherein the initial routing parameters include a line width of the signal line and a line spacing between the signal line and a previous signal line; a delay calculation module configured to perform parallel simulation processing on signal delays of each signal line in each candidate routing parameter configuration in the initial sampling point set, and determine a maximum delay value of each candidate routing parameter configuration; and a processing module configured to train a Gaussian process prior model based on each candidate routing parameter configuration and the corresponding maximum delay value, determine an optimal routing parameter configuration based on an acquisition function and a predicted delay distribution output by the Gaussian process prior model, perform next-round training on the Gaussian process prior model based on the optimal routing parameter configuration, and determine an optimal line width and line spacing configuration when the training reaches a maximum iteration number. The line width and line spacing of each signal line in the bus network are automatically optimized by the Gaussian process prior model to achieve the goal of minimizing the maximum delay, and the efficiency and accuracy of the optimal line width and line spacing configuration of the bus network are improved.

[0066] Please refer to Figure 4 , Figure 4 A structural schematic diagram of an electronic device provided by the embodiment of the present application. As shown in Figure 4 The electronic device 400 includes a processor 410, a memory 420 and a bus 430.

[0067] The memory 420 stores machine readable instructions executable by the processor 410, when the electronic device 400 is running, the processor 410 and the memory 420 communicate through the bus 430, the machine readable instructions are executed by the processor 410, can execute the above Figure 1 The steps of the bus pitch determination method of the bus network in the method embodiment are shown, and the specific implementation mode can be referred to the method embodiment, which will not be repeated here.

[0068] The embodiment of the application further provides a computer readable storage medium, the computer readable storage medium stores a computer program, the computer program is run by the processor, and the computer program can execute the above Figure 1 The steps of the bus pitch determination method of the bus network in the method embodiment are shown, and the specific implementation mode can be referred to the method embodiment, which will not be repeated here.

[0069] The skilled in the art can clearly understand that, for the convenience and brevity of the description, the specific working process of the above described system, device and unit can refer to the corresponding process in the foregoing method embodiment, which will not be repeated here.

[0070] In several embodiments provided in the application, it should be understood that the disclosed system, device and method can be implemented by other ways. The device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division mode, and for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some communication interface, device or unit, which can be electrical, mechanical or other forms.

[0071] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, they can be located in one place, or they can be distributed on a plurality of network units. According to actual needs, part or all of the units can be selected to achieve the purpose of the embodiment.

[0072] In addition, the functional units in each embodiment of the application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit.

[0073] If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a nonvolatile computer readable storage medium executable by a processor. Based on this understanding, the technical solutions of the present application essentially or the parts of the prior art that make contributions or parts of the technical solutions can be embodied in the form of software products. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0074] Finally, it should be noted that: the above-described embodiments are only specific embodiments of the present application, which are used to illustrate the technical solutions of the present application, but not to limit them. The protection scope of the present application is not limited thereto. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can make modifications or easily think of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed by the present application, or make equivalent replacements to some of the technical features. The modifications, changes or replacements do not make the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for determining bus spacing of a bus network, characterized in that: The bus spacing determination method comprises: Configuring initial routing parameters for each signal line in the bus network based on a preset bus width and DRC rules to determine an initial sampling point set; wherein the initial routing parameters include the line width of the signal line and the line spacing between the signal line and the previous signal line; Performing parallel simulation processing on the signal delay of each signal line of each set of candidate wiring parameter configurations in the initial sampling point set to determine the maximum delay value of each set of candidate wiring parameter configurations; The Gaussian process prior model is trained based on each set of candidate wiring parameter configurations and the corresponding maximum delay value. The optimal wiring parameter configuration is determined based on the acquisition function and the predicted delay distribution output by the Gaussian process prior model. The Gaussian process prior model is trained for the next round based on the optimal wiring parameter configuration until the training reaches the maximum number of iterations to determine the optimal line width and line spacing configuration.

2. The bus spacing determination method according to claim 1, wherein: The initial routing parameters of each signal line in the bus network are combined based on the preset bus width and DRC rules to determine the initial sampling point set, including: The initial routing parameters of each signal line are configured based on random sampling while ensuring that the line width and line spacing of each signal line are within the preset parameter value range and satisfying the bus width constraint, thereby generating multiple candidate routing parameter configurations. Check whether each of the candidate wiring parameter configurations complies with the DRC rule, and use all candidate wiring parameter configurations that comply with the DRC rule as the initial sampling point set.

3. The method for determining bus spacing according to claim 1, wherein: The training of the Gaussian process prior model based on each set of candidate wiring parameter configurations and the corresponding maximum delay value includes: Using a square exponential kernel function as a covariance function, taking each set of candidate wiring parameter configurations as input information of the Gaussian process prior model, and taking a maximum delay value as an output target of the Gaussian process prior model; Controlling the Gaussian process prior model to learn the distribution relationship between each set of candidate wiring parameter configurations and the corresponding maximum delay values; The hyperparameters and noise variance in the square exponential kernel function are optimized based on maximizing marginal likelihood to achieve training of the Gaussian process prior model.

4. The method for determining bus spacing according to claim 1, wherein: The predicted delay distribution is determined by: Determining a first covariance matrix between a new wiring parameter configuration and the existing candidate wiring parameter configuration; A predicted mean and variance are calculated based on the first covariance matrix, the covariance matrix between the existing candidate wiring parameter configurations, and the maximum delay value between the new wiring parameter configurations to determine a predicted delay distribution of the new wiring parameter configuration.

5. The method for determining bus spacing according to claim 1, wherein: The determining of the optimal routing parameter configuration based on the acquisition function and the predicted delay distribution output by the Gaussian process prior model includes: Based on the probability information of the maximum delay value provided in the predicted delay distribution, searching for a configuration parameter of line width and line spacing with a maximum expected value of improvement in the entire configuration space of line width and line spacing by using an acquisition function; Detecting whether the configuration parameters of the line width and line spacing meet the bus width and the DRC rule; If so, the configuration parameters of the line width and line spacing are used as the optimal wiring parameter configuration; if not, the search is continued in the entire configuration space of the line width and line spacing.

6. The method for determining bus spacing according to claim 1, wherein: The performing parallel simulation processing on the signal delay of each signal line of each set of candidate wiring parameter configurations in the initial sampling point set to determine the maximum delay value of each set of candidate wiring parameter configurations includes: Assigning each set of candidate wiring parameter configurations to a corresponding processing process, and controlling the processing process to monitor the running status of each subtask in real time; wherein the subtask is a simulation task for determining the signal delay of a signal line; If it is detected that the subtask ends abnormally, the processing process is controlled to automatically record the abnormal information, and the subtask is resubmitted according to the subtask identifier for simulation processing to determine the maximum delay value.

7. The method for determining bus spacing according to claim 1, wherein: After training the Gaussian process prior model based on each set of candidate wiring parameter configurations and the corresponding maximum delay value, the bus spacing determination method further includes: The product information obtained during each training process of the Gaussian process prior model is stored as data.

8. A bus network bus spacing determination device, characterized in that: The bus spacing determination device comprises: A parameter configuration module is used to configure the initial routing parameters of each signal line in the bus network based on the preset bus width and DRC rules, and determine the initial sampling point set; wherein the initial routing parameters include the line width of the signal line and the line spacing between the signal line and the previous signal line; a delay calculation module, configured to perform parallel simulation processing on the signal delays of the signal lines of each set of candidate wiring parameter configurations in the initial sampling point set, and determine the maximum delay value of each set of candidate wiring parameter configurations; A processing module is used to train a Gaussian process prior model based on each set of candidate wiring parameter configurations and the corresponding maximum delay value, determine the optimal wiring parameter configuration based on the acquisition function and the predicted delay distribution output by the Gaussian process prior model, and perform the next round of training on the Gaussian process prior model based on the optimal wiring parameter configuration until the training reaches the maximum number of iterations to determine the optimal line width and line spacing configuration.

9. An electronic device, characterized in that: include: A processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor and the memory communicate via the bus. When the processor runs the machine-readable instructions, the steps of the method for determining the bus spacing of a bus network as described in any one of claims 1 to 7 are executed.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method for determining the bus spacing of a bus network according to any one of claims 1 to 7 are executed.

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