A fast routing method with adaptive standard cell adjustment and via optimization

Abstract

The application discloses a kind of self-adapting standard frame adjustment and through-hole optimization fast wiring method, including the following steps: initialization division is carried out to chip area, and initialization region is obtained;Congestion assessment operation is carried out to initialization region;Whether congestion assessment result reaches the condition of re-division is judged, if the condition of secondary division is reached, then this division region is classified, and then the standard frame of region is dynamically adjusted and divided again;Wiring operation is carried out, and weighted through-hole influence evaluation model is used in wiring process, to guide wiring operation to preferentially select the wiring path of reducing through-hole.The mechanism of the application is based on real-time congestion data dynamically adjusting the size of standard frame, reduces DRC violation, significantly improves wiring efficiency;Through weighted through-hole influence evaluation model, by increasing the weight of through-hole use, more accurately measure the influence of through-hole on wiring quality, guide wiring algorithm to preferentially select the wiring path of reducing through-hole, so as to optimize DRC violation and the number of through-hole.

Description

Technical Field

[0001] This invention belongs to the field of circuit routing technology, and in particular relates to a rapid routing method with adaptive standard frame adjustment and via optimization. Background Technology

[0002] In the field of detailed routing for integrated circuits, routing framework design and pin order selection still lack sufficient attention, and fixed framework schemes are currently prevalent. Based on the track allocation results, multiple detailed routing iterations are performed. In each iteration, the design is divided into 7×7 non-overlapping, grid cell-aligned regions, and a detailed routing worker is created for each region. Each detailed routing worker first initializes its own data structure (worker database) from the global database, then performs routing and design rule checks without modifying the global database. Finally, each worker commits its changes by writing back to the global database. In alternating iterations, the partitioning of the 7×7 regions is adjusted using offsets of 0 and -4 to optimize routing at region boundaries.

[0003] When constructing a detailed routing work unit, each area has three bounding boxes: a standard bounding box, a Design Rule Check (DRC) bounding box, and an extended bounding box. In the detailed routing work unit's database, all objects within the extended bounding box are built locally. However, only objects located within or within the standard bounding box can be modified; other objects are fixed. Fixed objects are used for cost calculations and design rule checks.

[0004] Most existing routing frameworks allocate routing space based on a single, fixed-size standard frame. The fixed-frame scheme in traditional algorithms is suitable for routing environments with uniform density. However, the limitations of fixed frames in modern designs are becoming increasingly apparent, especially in high-density chip areas with significant local congestion, where they struggle to meet the requirements for fine-grained routing.

[0005] In fixed-frame routing, the frame size significantly impacts the search space of the A* algorithm. Larger frames provide a larger search space, facilitating complex path optimization, but also increase computational overhead and search time. In low-congestion areas, smaller frames effectively reduce search space and computational complexity, accelerating routing. However, current fixed-frame designs cannot adapt to the varying needs of local areas: large frames in high-density areas increase the search space, leading to excessive consumption of computational resources; while in low-density areas, excessively small frames may result in inflexible path selection, making it difficult to balance efficiency and quality.

[0006] Furthermore, pin selection strategies still primarily rely on traditional shortest path algorithms, typically optimized based on Manhattan distance. However, this singular consideration fails to adequately address the impact of via quantity on overall routing quality. In multilayer routing designs, the number of vias directly affects signal transmission delay and process complexity, especially as design nodes approach smaller process levels, via management becomes a crucial factor influencing routing performance. Although some research has attempted to introduce via penalties into path selection, the overall approach remains post-processing-oriented, failing to adequately consider this beforehand and increasing wasted routing resources. Summary of the Invention

[0007] To address the aforementioned issues, this invention proposes a fast routing method that integrates adaptive standard frame adjustment and via optimization. Based on a mechanism that dynamically adjusts the standard frame size using real-time congestion data, the method dynamically adjusts the standard frame size according to pin density, wire density, and metal shape density within the region, reducing DRC violations and significantly improving routing efficiency. Furthermore, a weighted via impact assessment model is used to more accurately measure the impact of vias on routing quality by increasing the weight of via usage, guiding the routing algorithm to prioritize routing paths that minimize vias, thereby optimizing DRC violations and the number of vias.

[0008] To achieve the above objectives, the technical solution adopted by this invention is: a rapid routing method with adaptive standard frame adjustment and via optimization, comprising the following steps:

[0009] S10, Initialize the chip area to obtain the initialization area;

[0010] S20, Initialize the regional congestion assessment operation;

[0011] S30, determine whether the congestion assessment result meets the conditions for re-division. If the conditions for re-division are met, classify the divided area and then dynamically adjust the standard frame of the area for division again.

[0012] Set the judgment condition for whether to perform secondary partitioning, and judge the number of rewiring operations in the area. If the number of rewiring operations reaches the preset value, secondary partitioning is not allowed.

[0013] S30, perform routing operations. During the routing process, a weighted via impact assessment model is used to guide the routing operation to prioritize routing paths that reduce vias.

[0014] Furthermore, the initial partitioning divides the chip area into standardized 8×8 grid cells, ensuring that each cell contains an appropriate number of pins and wires.

[0015] Furthermore, the congestion assessment operation includes:

[0016] After initializing the grid into 8×8 cells, congestion assessment is performed on each cell; the congestion value of each cell is calculated to determine whether further subdivision is needed.

[0017] Furthermore, the formula for calculating the congestion value is as follows:

[0018] Congestion=α×wlen+β×irs+γ×pins+δ×pins_area+ϵ×blks+ζ×blks_area+η×nets;

[0019] Where: wlen represents the global wiring length of the region; irs ​​represents the number of iroutes in the region; pins represents the number of pins in the region; pins_area represents the total area of ​​pins in the region; blks represents the number of blockages in the region; blks_area represents the total area of ​​blockages in the region; nets represents the number of different net segments in the region; α, β, γ, δ, ε, ζ and η are weight parameters that adjust the degree of influence of each factor.

[0020] Furthermore, after the congestion assessment, each region is divided into high-congestion, medium-congestion, and low-congestion regions, and a standard frame size is matched for each type of region.

[0021] Furthermore, the high-congestion area is maintained at 8×8, providing sufficient computing resources to optimize cabling;

[0022] The moderately congested area was reduced to 4×4 to balance cabling quality and efficiency.

[0023] The low-congestion area is further reduced to 2×2, which improves wiring speed and reduces computation time.

[0024] Furthermore, after regional classification, areas marked as low-congestion are further subdivided to refine cabling resource allocation.

[0025] Furthermore, in the secondary partitioning stage, the low-congestion area is further subdivided into smaller grids, and the number of rewiring operations is determined. If the number of rewiring operations in an area exceeds the preset limit, further partitioning is not allowed.

[0026] Furthermore, during the routing operation, the available pins are traversed, and the next connection point is dynamically selected based on the weighted via impact assessment model.

[0027] Furthermore, the weighted via impact assessment model adopts a weighted cost model to minimize the Manhattan distance while penalizing excessive via usage; by controlling the weights of each factor, it adaptively optimizes connectivity and resource allocation according to design requirements.

[0028] To evaluate each candidate pin, the cost of the potential path is calculated using the following cost function:

[0029] Cost pin=Δx+Δy+Δz+α*via_count;

[0030] Where Δx, Δy, and Δz represent the horizontal, vertical, and vertical distances between the current pin and the candidate pin, respectively, via_count is the estimated number of vias in global routing, and α is an adjustable parameter that assigns weight to via usage, prioritizing the reduction of the number of vias.

[0031] The beneficial effects of adopting this technical solution are:

[0032] This invention demonstrates significant advantages in routing speed and via count. Compared to traditional methods such as TritonRoute-WXL, it significantly improves routing efficiency and reduces the number of vias while ensuring the original quality solution.

[0033] This invention provides an adaptive cabling frame size adjustment based on layout connectivity and congestion prediction. By dynamically adjusting the cabling frame size and combining area division and congestion prediction, it ensures that sufficient cabling resources are allocated to high-congestion areas while avoiding resource waste in low-congestion areas, thereby optimizing overall cabling efficiency and resource utilization.

[0034] This invention utilizes pin sequence optimization to reduce wiring complexity and path length by analyzing the connection relationships between pins, thereby improving wiring efficiency.

[0035] This invention uses an adaptive pin sorting strategy, which sorts the pins according to their positions and connection requirements to minimize wiring crossovers and path overlaps. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of a rapid routing method for adaptive standard frame adjustment and via optimization according to the present invention.

[0037] Figure 2 This is a path diagram showing the different pin connection sequences in embodiments of the present invention. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described below with reference to the accompanying drawings.

[0039] In this embodiment, see Figure 1 As shown, this invention proposes a fast routing method with adaptive standard frame adjustment and via optimization, including the following steps:

[0040] S10, Initialize the chip area to obtain the initialization area;

[0041] S20, Initialize the regional congestion assessment operation;

[0042] S30, determine whether the congestion assessment result meets the conditions for re-division. If the conditions for re-division are met, classify the divided area and then dynamically adjust the standard frame of the area for division again.

[0043] The system sets conditions for determining whether to perform secondary partitioning, and judges the number of rerouting attempts for a region. If the number of rerouting attempts reaches a preset value, secondary partitioning is not allowed. This avoids some unsolvable design rule violations caused by the reduction of the routing area. This improves the efficiency of detailed routing while ensuring the final DCV (Distributed Value) count.

[0044] S30, Perform routing operations. During the routing process, a weighted via impact assessment model is used to guide the routing operations to prioritize routing paths that reduce vias.

[0045] Finally, output the routing results, such as a DEF file.

[0046] As an optimization of the above embodiment, the initial partitioning divides the chip area into standardized 8×8 grid cells, with each cell containing an appropriate number of pins and wires. This partitioning method can provide local information within the region at an early stage, facilitating subsequent congestion assessment and dynamic adjustment. Through this standardized initial partitioning, we can quickly determine the initial routing resource configuration while ensuring a balance between computational efficiency and fine-grained analysis.

[0047] As an optimization of the above embodiments, the congestion assessment operation includes:

[0048] After initializing the grid into 8×8 cells, congestion assessment is performed on each cell; the congestion value of each cell is calculated to determine whether further subdivision is needed.

[0049] Preferably, the formula for calculating the congestion value is:

[0050] Congestion=α×wlen+β×irs+γ×pins+δ×pins_area+ϵ×blks+ζ×blks_area+η×nets;

[0051] Where: wlen represents the global wiring length of the region; irs ​​represents the number of iroutes in the region; pins represents the number of pins in the region; pins_area represents the total area of ​​pins in the region; blks represents the number of blockages in the region; blks_area represents the total area of ​​blockages in the region; nets represents the number of different net segments in the region; α, β, γ, δ, ε, ζ and η are weight parameters that adjust the degree of influence of each factor.

[0052] As an optimization of the above embodiments, after congestion assessment, each region is divided into high-congestion, medium-congestion, and low-congestion regions, and a standard frame size is matched for each type of region.

[0053] The high-congestion area is maintained at 8×8 to provide sufficient computing resources to optimize cabling;

[0054] The moderately congested area was reduced to 4×4 to balance cabling quality and efficiency.

[0055] The low-congestion area is further reduced to 2×2, increasing routing speed and reducing computation time. Through this classification adjustment, the algorithm significantly improves overall computational efficiency while ensuring routing accuracy.

[0056] As an optimization of the above embodiments, after the region classification, the regions marked as low congestion are further divided to further refine the allocation of cabling resources.

[0057] In the secondary partitioning stage, low-congestion areas are further subdivided into smaller grids to more precisely control routing paths and reduce the impact of localized congestion. The secondary partitioning criteria are based not only on congestion values ​​but also on the number of rerouting attempts. If the number of rerouting attempts for an area exceeds a preset limit, further partitioning is not allowed to avoid unrecoverable design rule violations caused by excessive subdivision. In this way, secondary partitioning effectively improves the overall computational efficiency of the algorithm while ensuring routing quality.

[0058] As an optimization of the above embodiments, in order to reduce the impact of standard frame reduction on the routing results, we adopted a step of reducing vias and adopted a new method for selecting the next connection pin before the routing operation performs path search.

[0059] During routing operations, the available pins are traversed, and the next connection point is dynamically selected based on a weighted via impact assessment model.

[0060] The weighted via impact assessment model adopts a weighted cost model to minimize the Manhattan distance while penalizing excessive via usage, as vias significantly increase signal delay and wiring complexity in multi-layer designs; by controlling the weights of each factor, it adaptively optimizes connectivity and resource allocation according to design requirements.

[0061] To evaluate each candidate pin, the cost of the potential path is calculated using the following cost function:

[0062] Cost pin=Δx+Δy+Δz+α*via_count;

[0063] Where Δx, Δy, and Δz represent the horizontal, vertical, and vertical distances between the current pin and the candidate pin, respectively, via_count is the estimated number of vias in global routing, and α is an adjustable parameter that assigns weight to via usage, prioritizing the reduction of the number of vias.

[0064] like Figure 2 As shown, due to the addition of via weights, after the pin connection order was adjusted from 1-2-3-4 to 1-4-2-3, the wiring result also changed accordingly, with a significant reduction in the number of vias.

[0065] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. A rapid routing method with adaptive standard frame adjustment and via optimization, characterized in that, Including the following steps: S10, Initialize the chip area to obtain the initial area; Initialization divides the chip area into standardized 8×8 grid cells, so that each cell contains an appropriate number of pins and wires; S20, Perform congestion assessment on the initialization area; the congestion assessment includes: after initializing the area into 8×8 grid cells, performing congestion assessment on each cell; calculating the congestion value of each cell to determine whether further subdivision is needed; S30, determine whether the congestion assessment result meets the conditions for re-division. If the conditions for re-division are met, classify the divided area and then dynamically adjust the standard frame of the area for division again. Set the judgment condition for whether to perform secondary partitioning, and judge the number of rewiring operations in the area. If the number of rewiring operations reaches the preset value, secondary partitioning is not allowed. S30, Perform routing operations. During the routing process, a weighted via impact assessment model is used to guide the routing operations to prioritize routing paths that reduce vias. During routing operations, the available pins are traversed, and the next connection point is dynamically selected based on the weighted via impact assessment model. The weighted via impact assessment model adopts a weighted cost model to minimize the Manhattan distance while penalizing excessive via usage; by controlling the weights of each factor, it adaptively optimizes connectivity and resource allocation according to design requirements. To evaluate each candidate pin, the cost of the potential path is calculated using the following cost function: Cost pin=Δx+Δy+Δz+α*via_count; Where Δx, Δy, and Δz represent the horizontal, vertical, and vertical distances between the current pin and the candidate pin, respectively, via_count is the estimated number of vias in global routing, and α is an adjustable parameter that assigns weight to via usage, prioritizing the reduction of the number of vias.

2. The rapid routing method for adaptive standard frame adjustment and via optimization according to claim 1, characterized in that, The formula for calculating the congestion value is as follows: Congestion=α×wlen+β×irs+γ×pins+δ×pins_area+ε×blks+ζ×blks_area+η×nets; Where: wlen represents the global wiring length of the region; irs ​​represents the number of iroutes in the region; pins represents the number of pins in the region; pins_area represents the total area of ​​pins in the region; blks represents the number of blockages in the region; blks_area represents the total area of ​​blockages in the region; nets represents the number of different net segments in the region; α, β, γ, δ, ε, ζ and η are weight parameters that adjust the degree of influence of each factor.

3. The rapid routing method for adaptive standard frame adjustment and via optimization according to claim 1, characterized in that, After congestion assessment, each region is divided into high-congestion, medium-congestion, and low-congestion regions, and a standard frame size is matched for each type of region.

4. The rapid routing method for adaptive standard frame adjustment and via optimization according to claim 3, characterized in that, The high-congestion area is maintained at 8×8 to provide sufficient computing resources to optimize cabling; The moderately congested area was reduced to 4×4 to balance cabling quality and efficiency. The low-congestion area is further reduced to 2×2, which improves wiring speed and reduces computation time.

5. The rapid routing method for adaptive standard frame adjustment and via optimization according to claim 4, characterized in that, After regional classification, regions marked as low-congestion are further subdivided to refine cabling resource allocation.

6. The rapid routing method for adaptive standard frame adjustment and via optimization according to claim 4, characterized in that, In the secondary partitioning stage, the low-congestion area is further subdivided into smaller grids, and the number of rewiring operations is determined. If the number of rewiring operations in an area exceeds the preset limit, further partitioning is not allowed.

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