Clock tree clustering method, system, device, medium, and product

Abstract

The present application relates to the field of EDA algorithm design, and particularly relates to a clock tree clustering method, system, device, medium and product. The clock tree clustering method comprises the following steps: inputting an initial clock tree, extracting the position and capacitance parameter of a to-be-driven element, constructing a minimum spanning tree based on the element position, deleting edges in the tree with a length greater than a clustering cost f, and obtaining a spanning tree set. The spanning tree is converted into a binary tree, it is verified whether the sub-tree satisfies a design constraint, and a child sub-tree with the largest total cost is separated. The remaining sub-trees are continuously verified until all the sub-trees meet the standard. Each sub-tree is taken as a cluster, a driver is added to the top end to generate a clustering cluster. The clustering cluster is taken as a new clock tree, and iteration is repeated until the number of clusters is unchanged or exceeds an upper limit of iteration. Finally, a clock source is added to the top layer, and a clock tree is output. The system, computer device, computer readable storage medium and computer program product of the present application have the same beneficial effects as the clock tree clustering method.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of EDA algorithm design, and particularly relates to a clock tree clustering method, system, device, medium and product. BACKGROUND

[0002] In the electronic design automation (EDA) process, with the increase of chip integration, clock signal synchronization is increasingly critical. Clock tree synthesis technology emerges as the times require, and is used for constructing an efficient clock distribution network to guarantee the timing performance of a chip.

[0003] In the clock tree synthesis stage, the primary problem is how to properly cluster and divide clock elements to obtain an initial clock tree structure. Subsequent adjustment and balancing of the clock tree are based on the initial clock tree, and the initial clock tree will greatly affect the quality of the final clock tree.

[0004] The prior art adopts general clustering methods such as multiple rounds of K-means and hierarchical clustering to process the clock tree clustering problem. For example, the K-means algorithm is used to divide the elements to be divided into several large clusters, a driver is inserted for each large cluster, and the large clusters are recursively divided until the generated clusters meet the design constraints. The main disadvantage of this kind of general algorithm is that it cannot directly guide clustering according to various constraints and optimization objectives in clock tree synthesis, the target is not clear when clustering, and problems such as waste of driving ability and design rule violation are prone to occur. SUMMARY

[0005] To solve the technical problems that the existing clock tree clustering method cannot directly guide clustering according to various constraints and optimization objectives in clock tree synthesis, the target is not clear when clustering, and problems such as waste of driving ability and design rule violation are prone to occur, the present application provides a clock tree clustering method, system, device, medium and product.

[0006] The technical problem of the present application is solved by providing a clock tree clustering method, comprising the following steps: inputting an initial clock tree, extracting the positions and capacitance parameters of the to-be-driven elements therein, constructing a minimum spanning tree based on the positions of the to-be-driven elements, deleting all edges in the minimum spanning tree with a length greater than a clustering cost f to obtain a spanning tree set, converting all spanning trees into binary trees, verifying whether the sub-trees of each binary tree satisfy a design constraint, if the child sub-trees of a sub-tree of a binary tree all satisfy the design constraint but the sub-tree itself does not satisfy the design constraint, separating the child sub-trees as independent clusters and continuing to verify the remaining sub-trees of the binary tree, repeating the verification process until all sub-trees of the binary tree satisfy the design constraint, regarding each sub-tree as a cluster, adding a driver at the top of the cluster to generate a clustered cluster, regarding the clustered cluster as a new to-be-driven element of the clock tree, repeating the above steps until the number of clustered clusters is unchanged or the iteration number reaches a preset upper limit, obtaining a final clustered cluster, adding a clock source at the top layer of the final clustered cluster, and outputting a clock tree.

[0007] Preferably, verifying whether the sub-trees of each binary tree satisfy the design constraint comprises the following steps:

[0008] Traversing the binary tree from bottom to top to find the root node of the sub-tree that violates the design constraint, wherein the child sub-trees of the sub-tree all satisfy the design constraint;

[0009] Deleting the edge between the root node of the sub-tree and the child sub-tree with the maximum total cost, so that the child sub-tree is separated from the whole binary tree, and the separated child sub-tree is processed as an independent cluster;

[0010] Continuing to traverse the remaining sub-trees of the binary tree from bottom to top and separate the child sub-trees of the sub-trees that violate the design constraint until all sub-trees satisfy the design constraint;

[0011] The total cost formula of the sub-tree is:

[0012]

[0013] Wherein, n represents the number of nodes in the sub-tree T, C(v i ) represents the capacitance value of the node vi, Q(e) represents the length of the edge e of the sub-tree T, and E T represents the set of edges in the sub-tree T.

[0014] Preferably, the clustering cost is equal to the driver capacitance; or,

[0015] The clustering cost is calculated by the following formula:

[0016]

[0017] Wherein, f represents the clustering cost, P driver represents the driver power consumption, and ω represents a compromise coefficient, and ω∈[0.2, 1].

[0018] Preferably, the formula of the edge between two points in the minimum spanning tree is:

[0019]

[0020] Wherein, Q(e) represents the length of the edge e, d1(u,v) represents the 1-norm distance of the points u and v constituting the edge e, and C0 represents the network capacitance of the unit length conductor.

[0021] Preferably, the design constraints include a maximum fan-out and / or a maximum drive capacitance.

[0022] When the number of elements contained in the subtree exceeds the maximum fan-out, and / or the total capacitance of the subtree exceeds the maximum drive capacitance, the subtree violates the design constraints.

[0023] Preferably, the design constraints include a maximum fan-out and / or a maximum drive capacitance.

[0024] When the number of elements contained in the subtree exceeds the maximum fan-out, and / or the total capacitance of the subtree exceeds the maximum drive capacitance, the subtree violates the design constraints.

[0025] Preferably, the clustering process aims to optimize the minimization of the following global objective function:

[0026]

[0027]

[0028] Wherein, min Cost is the optimization objective function for balancing the total capacitance and the number of drivers; k represents the total number of clustering clusters, represents the i-th clustering cluster, and respectively represent the total capacitance of the element pins and the total capacitance of the interconnection network of the i-th clustering cluster, represents the number of elements contained in the i-th clustering cluster, f represents the clustering cost determined by the parameters of the driver, max_fanout represents the maximum fan-out in the design constraints, and max_cap represents the maximum drive capacitance in the design constraints.

[0029] Preferably, the conversion of the spanning tree into a binary tree includes: optionally rooting and orienting the edges, and virtually splitting the nodes with an out-degree greater than 2 into multiple nodes with an out-degree equal to 2.

[0030] The application also provides a clock tree clustering system, which comprises a user terminal and a micro-service terminal in communication connection; the micro-service terminal receives a to-be-processed command input by the user terminal and executes the steps of the above-mentioned clock tree clustering method according to the to-be-processed command.

[0031] The application further provides a computer device comprising a storage, a processor and a computer program stored on the storage, wherein the processor executes the computer program to implement the steps of the clock tree clustering method.

[0032] The application further provides a computer readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the clock tree clustering method.

[0033] The application further provides a computer program product comprising a computer program, wherein the computer program, when executed by a processor, implements the steps of the clock tree clustering method.

[0034] Compared with the prior art, the clock tree clustering method, system, device, medium and product provided by the application have the following advantages:

[0035] 1. The clock tree clustering method provided by the embodiment of the application overcomes the technical problem that the existing clock tree clustering method cannot guide clustering according to various constraints and optimization targets in clock tree synthesis, and the driving capacity is easily wasted and the design rules are easily violated. Specifically, the clock tree clustering method maximizes the utilization of drivers under the premise of ensuring design constraints through a bottom-up iterative minimum spanning tree partition mechanism; the cutting boundary of the sub-tree is accurately controlled by the clustering cost, which maximizes the driving capacity of the drivers to the greatest extent, and the binary tree verification process takes the maximum fan-out and maximum capacitance as hard partition conditions, thereby avoiding design constraint violations from the root cause.

[0036] Further, by verifying whether the sub-tree of the binary tree satisfies the design constraints and finding the deepest sub-tree, i.e., the sub-tree with the maximum hierarchical depth, that violates the design constraints to split the child sub-tree, the driving capacity of the drivers can be maximized under the premise that each independent cluster satisfies the design constraints, thereby avoiding excessive insertion of the drivers.

[0037] It should be noted that the method also has the advantages of strong scalability and fast running speed. The scalability mainly reflects in two aspects. First, the scheme is not coupled with specific design constraints, i.e., the restrictions on the clustering cluster, such as the maximum input waveform conversion time and other common constraints in the industry, can be freely added without changing the algorithm flow. In addition, the single-layer algorithm and the overall structure of the algorithm are separated, based on which the overall logic or the single-layer algorithm can be modified separately to meet actual needs without the need for full modification.

[0038] 2. The clock tree clustering method provided by the embodiment of the present application verifies whether the sub-tree of each binary tree satisfies the design constraint, cuts the sub-tree with the largest total cost preferentially through bottom-up traversal of the binary tree and separation strategy based on the total cost of the sub-tree, can guarantee that the child sub-tree satisfies the design constraint while avoiding the generation of low-load clusters, and realizes deterministic convergence.

[0039] 3. The clock tree clustering method provided by the embodiment of the present application, wherein the design constraint comprises maximum fan-out and / or maximum drive capacitance; when the number of elements contained in the sub-tree exceeds the maximum fan-out, and / or the total capacitance of the sub-tree exceeds the maximum drive capacitance, the sub-tree violates the design constraint.

[0040] Understandably, by limiting the design constraint to the maximum fan-out and / or the maximum drive capacitance, the maximum fan-out constraint prevents signal quality deterioration, and the maximum capacitance constraint prevents driver overload, and the two complement each other to form an integrity protection closed loop.

[0041] 4. The clock tree clustering method provided by the embodiment of the present application, wherein the clustering cost is equal to the drive capacitance; or,

[0042] The clustering cost is calculated by the following formula:

[0043]

[0044] Wherein, f represents the clustering cost, P represents the drive capacitance, and ω represents the compromise coefficient, and ω∈[0.2, 1]. driver The drive power consumption is represented by ω, and ω represents the compromise coefficient, and ω∈[0.2, 1].

[0045] Understandably, by adjusting the clustering cost to be equal to the drive capacitance, the high-capacitance long side is preferentially cut when pruning the initial minimum spanning tree, the total capacitance is directly reduced, and the total capacitance of the clock tree is minimized; when the clustering cost is adjusted to be the product of the drive power consumption and the compromise coefficient, the capacitance and the power consumption are automatically balanced, and by selecting a suitable compromise coefficient, the capacitance and the power consumption of the clock tree are relatively balanced.

[0046] 5. The clock tree clustering method provided by the embodiment of the present application, wherein the length formula of the edge between two points in the minimum spanning tree is:

[0047]

[0048] Wherein, Q(e) represents the length of the edge e, d1(u,v) represents the 1-norm distance of the point u and the point v constituting the edge e, and C0 represents the network capacitance of the unit length conductor.

[0049] It can be understood that the length formula of two points is defined by the 1-norm distance, that is, the Manhattan distance, and the network capacitance of the unit length conductor, which can make the length value more consistent with the physical implementation rules of the chip and directly reflect the interconnection line capacitance, a key electrical indicator.

[0050] It should be noted that the Manhattan distance is the sum of the distances between two points in the plane along the coordinate axis direction, that is, the horizontal or vertical direction, and the calculation formula is the sum of the absolute values of the coordinate difference between the two points. In the clock tree clustering, the Manhattan distance is an important indicator for measuring the layout correlation between different clock nodes. Since the transmission path of the clock signal in the chip layout is limited by the wiring channel and can only extend along the horizontal or vertical direction, which is highly consistent with the calculation logic of the Manhattan distance. In the clustering process, the spatial aggregation degree of the nodes can be quickly judged by calculating the Manhattan distance between the clock nodes: the smaller the distance, the closer the nodes are in the layout, and grouping them into the same cluster can effectively shorten the wiring length of the clock tree branch, reduce signal transmission delay and power consumption.

[0051] Further, by limiting the length formula, the capacitance of the to-be-driven element and the network capacitance are defined as specific weights of points and edges, so that the clock tree clustering method can directly perceive the design constraints and avoid the blind division caused by the lack of physical parameter perception in traditional general clustering algorithms, such as the K-means clustering algorithm.

[0052] 6、The clock tree clustering method provided by the embodiment of the present application minimizes the global objective function as the optimization objective in the clustering process, the optimization objective function includes two parts of element capacitance and network capacitance, and the fan-out of the clustering cluster is limited to be less than the limited maximum fan-out, and the sum of the element capacitance and the network capacitance of the clustering cluster is limited to be less than the limited maximum capacitance, so as to ensure that the clustering cluster does not violate the design constraints. Further, by the constraint term of kf, that is, the product of the total number of clustering clusters and the clustering cost, the number of clustering clusters is as small as possible, so as to ensure that the driving capability of the driver is maximally exerted.

[0053] 7、The clock tree clustering method provided by the embodiment of the present application comprises: optionally selecting a root node and orienting an edge, and virtually splitting a node with an out-degree greater than 2 into a plurality of nodes with an out-degree equal to 2.

[0054] It can be understood that by virtually splitting the node with an out-degree greater than 2 into a plurality of two-degree nodes, the arbitrary tree structure is forcibly converted into a standard binary tree. This conversion eliminates the interference of irregular topologies such as star connection on the traversal algorithm. The virtual node does not introduce physical load and maintains the accuracy of capacitance calculation; the electrical characteristics of the original tree structure are completely retained in the binary tree model, ensuring the reliability of the verification result.

[0055] 8. This embodiment of the invention also provides a clock tree clustering system, the system including a user terminal and a microservice terminal with communication connection; the microservice terminal receives a command to be processed input by the user terminal, and executes the steps of the above clock tree clustering method according to the command to be processed.

[0056] It should be noted that the clock tree clustering system provided by this invention has the same beneficial effects as the clock tree clustering method described above, and will not be elaborated here.

[0057] 9. The present invention also provides a computer device, including a storage device, a processor, and a computer program stored on the storage device, wherein the processor executes the computer program to implement the steps of the above-described clock tree clustering method.

[0058] It should be noted that the computer device provided by this invention has the same beneficial effects as the clock tree clustering method described above, and will not be elaborated here.

[0059] 10. Embodiments of the present invention also provide a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the above-described clock tree clustering method.

[0060] It should be noted that the computer-readable storage medium provided by the present invention has the same beneficial effects as the clock tree clustering method described above, and will not be elaborated here.

[0061] 11. This embodiment of the invention also provides a computer program product, including a computer program, which, when executed by a processor, implements the steps of the above-described clock tree clustering method.

[0062] It should be noted that the computer program product provided by this invention has the same beneficial effects as the clock tree clustering method described above, and will not be elaborated here. Attached Figure Description

[0063] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0064] Figure 1 This is a flowchart illustrating steps S1 to S6 in a clock tree clustering method provided in an embodiment of the present invention.

[0065] Figure 2 This is a flowchart illustrating steps S31 to S33 of a clock tree clustering method provided in an embodiment of the present invention.

[0066] Figure 3is a framework schematic diagram of a clock tree clustering system provided by an embodiment of the present application.

[0067] Figure 4 is a framework schematic diagram of a computer device provided by an embodiment of the present application.

[0068] Figure 5 is a framework schematic diagram of a computer readable storage medium provided by an embodiment of the present application.

[0069] Figure 6 is a framework schematic diagram of a computer program product provided by an embodiment of the present application.

[0070] Explanation of the drawings:

[0071] 1. a clock tree clustering system; 11. a user end; 12. a micro-service end;

[0072] 2. a computer device; 21. a storage; 22. a processor;

[0073] 3. a computer readable storage medium;

[0074] 4. a computer program product;

[0075] 100. a computer program. DETAILED DESCRIPTION

[0076] In order to make the objectives, technical solutions and advantages of the present application clearer, further detailed description will be made to the present application in combination with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0077] In the embodiments provided by the present application, it should be understood that "B corresponding to A" means that B is associated with A, and B can be determined according to A. However, it should also be understood that the determination of B according to A does not mean that B is determined only according to A, but B can also be determined according to A and / or other information.

[0078] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. Those skilled in the art should also know that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily required by the present application.

[0079] In various embodiments of the present application, it should be understood that the size of the sequence number of the above processes does not mean the inevitable sequence of execution, and the execution sequence of the processes should be determined according to their functions and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0080] The flow diagrams and the block diagrams in the drawings are illustrations of the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present application. In this regard, each block in the flow diagrams or block diagrams can represent a module, a segment, or a portion of code, which comprises one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently or in the reverse order, depending on the functionality involved. It is also noted that each block of the block diagrams and / or flow diagrams, and combinations of blocks in the block diagrams and / or flow diagrams, can be implemented by dedicated hardware-based systems that perform the specified functions or operations, or combinations of hardware and software.

[0081] In the clock tree clustering stage, the prior art usually uses general clustering methods such as multiple rounds of K-means, hierarchical clustering, etc. to process the clock tree clustering problem. The main disadvantage of such general algorithms is that they cannot directly guide clustering according to various constraints and optimization objectives in clock tree synthesis, and the target is not clear when clustering, which is prone to problems such as wasting driving capability and violating design rules.

[0082] To solve the technical problems that the existing clock tree clustering method cannot directly guide clustering according to various constraints and optimization objectives in clock tree synthesis, the target is not clear when clustering, and it is prone to problems such as wasting driving capability and violating design rules, the present application provides a clock tree clustering method, system, device, medium and product.

[0083] First, please refer to Figure 1 The embodiment of the present application provides a clock tree clustering method, comprising the following steps:

[0084] S1: input an initial clock tree, extract the positions and capacitance parameters of the to-be-driven elements therein, and construct a minimum spanning tree based on the positions of the to-be-driven elements;

[0085] S2: delete all edges in the minimum spanning tree with a length greater than the clustering cost to obtain a spanning tree set;

[0086] S3: converting all the spanning trees into binary trees, verifying whether the sub-tree of each binary tree satisfies the design constraint, if the child sub-trees of a binary tree all satisfy the design constraint, but the sub-tree itself does not satisfy the design constraint, separating the child sub-trees as independent clusters;

[0087] S4: continuing to verify the remaining sub-trees of the binary tree; repeating step S3 until all the sub-trees of the binary tree satisfy the design constraint;

[0088] S5: regarding each sub-tree as a cluster, adding a driver at the top of the cluster to generate a clustered cluster;

[0089] S6: regarding the clustered cluster as a new clock tree, repeating the iteration of steps S1-S5 until the number of clustered clusters is unchanged or the iteration number reaches a preset upper limit, obtaining a final clustered cluster, adding a clock source at the top layer of the final clustered cluster, and outputting the clock tree.

[0090] It can be understood that the clock tree clustering method provided by the embodiment of the application overcomes the problem that the existing clock tree clustering method cannot guide clustering according to various constraints and optimization targets in clock tree synthesis, and is prone to waste of driver capability and design rule violation. Specifically, the clock tree clustering method maximizes the utilization rate of the driver under the premise of ensuring the design constraint through the minimum spanning tree division mechanism of the bottom-up iteration; the cutting boundary of the sub-tree is accurately controlled by the clustering cost, elements that are too far apart are not forced to be connected in the same cluster, and the additional wiring capacitance and resistance introduced by long-distance interconnection are avoided, thereby maximizing the driving capability of the driver to the greatest extent, and the binary tree verification process takes the maximum fan-out and maximum capacitance as the hard division condition, thereby avoiding design constraint violations from the root.

[0091] Further, by verifying whether the sub-tree of the binary tree satisfies the design constraint, and finding the deepest sub-tree that violates the design constraint in the binary tree, i.e., the sub-tree with the largest hierarchical depth, the child sub-tree is divided, which can maximize the driving capability of the driver under the premise that each independent cluster satisfies the design constraint, thereby avoiding too many drivers from being inserted.

[0092] It should be noted that the method also has the advantages of strong scalability and fast running speed. The scalability mainly reflects in two aspects. First, the scheme is not coupled with specific design constraints, i.e., other constraints such as the maximum input waveform conversion time can be freely added to the clustered cluster without changing the algorithm process. In addition, the single-layer algorithm and the overall structure of the algorithm are separated, based on which the overall logic or single-layer algorithm can be modified separately to meet actual needs without full modification.

[0093] The specific steps S1 to S6 of the clock tree clustering method will be described below.

[0094] Firstly, in step S1, the positions and capacitance parameters of the elements to be driven in the initial clock tree are input, and the network capacitance per unit length and the clustering cost are obtained.

[0095] A minimum spanning tree MST is constructed according to the positions of the elements to be driven, all the elements to be driven are connected as nodes through edges, and the total length of the edges connecting all the nodes is the shortest. Thus, under the premise of fixing the network capacitance per unit length, the total capacitance required for wiring all the elements to be driven is minimized.

[0096] The length of the edge is defined as the 1-norm distance, that is, the Manhattan distance. The Manhattan distance is the sum of the distances between two points in a plane along the coordinate axis direction, and the calculation formula is the sum of the absolute values of the coordinate differences of the two points. In clock tree clustering, the Manhattan distance is an important indicator for measuring the layout correlation between different clock nodes. Since the transmission path of the clock signal in the chip layout is limited by the wiring channel and can only extend along the horizontal or vertical direction, which is highly consistent with the calculation logic of the Manhattan distance.

[0097] Secondly, in step S2, all the edges in the minimum spanning tree MST whose distances are greater than the clustering cost are deleted to obtain a set of spanning trees {T1, T2, T3, …}.

[0098] The calculation formula of the length of the edge in the minimum spanning tree MST is:

[0099]

[0100] Wherein, Q(e) represents the length of the edge e, d1(u, v) represents the 1-norm distance between the points u and v constituting the edge e, and C0 represents the network capacitance per unit length of the conductor.

[0101] Further, the clustering cost is a constant representing the clustering cost, which is determined by the parameters of the driver and the optimization target of the overall clock tree.

[0102] When the total capacitance of the clock tree is expected to be the smallest, the value of the clustering cost is equal to the driver capacitance value, and the unit of the driver capacitance is defined as pF. At this time, when the edges with lengths greater than the clustering cost are deleted in step S2 for clustering, the influence of the two operations of increasing the network capacitance and increasing the driver capacitance on the total capacitance can be accurately balanced, thereby guiding the selection of the clustering scheme with smaller total capacitance in the pruning process, and inhibiting the growth of the total capacitance and power consumption from the source.

[0103] When the capacitance and power consumption of the clock tree are expected to be balanced, the clustering cost is calculated by the following formula:

[0104]

[0105] Wherein, f represents the clustering cost; Pdriver represents the driver power consumption, the unit of the driver power consumption is pW; ω represents a compromise coefficient, and ω ∈ [0.2, 1], the unit of the compromise coefficient is pF / pW.

[0106] It should be noted that when the clustering cost f is calculated based on the power consumption, the unit of the power consumption needs to be converted into an electrical unit consistent with the capacitance through a conversion coefficient. The conversion coefficient is determined through the power consumption-capacitance mapping relationship of the driver in the chip process library, or is calculated and inversely deduced based on the clock frequency, that is, the power consumption = capacitance × frequency × voltage 2 formula, or is obtained by using the commonly used process parameter fitting formula, and details are not described here.

[0107] At this time, when the edges with a length greater than the clustering cost are deleted in the clustering in step S2, the actual comparison is between the additional interconnection power consumption expected to be brought by retaining the long edge and the equivalent power consumption of the newly added driver. When the length of the edge is greater than the clustering cost, the disconnected edge is considered to be more beneficial to the overall power consumption optimization and balance under the power consumption model.

[0108] As for the selection of the compromise coefficient, specifically, 0.2, 0.5, 0.8, etc. can be selected according to different design target emphases and constraint strictness. The smaller the ω value, such as ω = 0.2, the smaller the value of the clustering cost, which means that the tolerance to long-distance interconnection lines is lower in the clustering process, and it tends to disconnect the long edge and insert the driver earlier and more frequently, which is usually used in the scene where the number of drivers is relatively loose, but the local interconnection length needs to be strictly controlled to meet the timing. The larger the ω value, such as ω = 0.8, the larger the value of the clustering cost, which means that the tolerance to long-distance interconnection lines is higher in the clustering process, and it tends to retain the long edge and reduce the driver insertion, which is usually used in the critical path design that needs to minimize the number of drivers to save area and cost.

[0109] Through the above length formula and the definition of the clustering cost f, the capacitance of the to-be-driven element and the network capacitance are defined as specific weights of points and edges, so that the clock tree clustering method can directly perceive the design constraints and avoid the blind division caused by the lack of physical parameter perception in traditional general clustering algorithms such as the K-means clustering algorithm.

[0110] In step S3, all the spanning trees are converted into binary trees. When the spanning tree is converted into a binary tree, the nodes with an out-degree greater than 2 are virtually split into multiple nodes with an out-degree equal to 2 by selecting a root node and orienting the edges. That is, a point is randomly selected as a root node, and then the direction of each edge is marked as from the point close to the root to the point away from the root. For the nodes with an out-degree greater than 2 in the tree, they are regarded as a plurality of coincident points, and the out-degree of each point is 2.

[0111] By virtually splitting a node with out-degree greater than 2 into multiple two-degree nodes, the arbitrary tree structure is forced to transform into a standard binary tree. This conversion eliminates the interference of irregular topologies, such as star connection, on the traversal algorithm. The virtual nodes do not introduce physical load, as their capacitance value is 0 and they do not participate in the calculation of tree cost, maintaining the accuracy of capacitance calculation. The electrical characteristics of the original tree structure are completely preserved in the binary tree model, ensuring the reliability of the verification results.

[0112] Further, it is verified whether each binary tree satisfies the design constraints. If the child sub-trees of a binary tree all satisfy the design constraints, but the sub-tree itself does not satisfy the design constraints, the child sub-trees are separated as independent clusters. At this time, the child sub-trees have been separated from the original binary tree, and as independent clusters they necessarily satisfy the design constraints.

[0113] When a sub-tree violates the design rules but its child sub-trees all satisfy the design rules, it can be known that the root cause of the violation of the design rules is not the overload of the internal load of the child sub-trees, but the driving ability of the root node of the sub-tree is insufficient to cover the cumulative load of all the sub-trees under it, or the interconnection line capacitance between the sub-tree and the child sub-trees causes a cascade load exceeding the standard.

[0114] Based on the above, separating the child sub-trees that satisfy the constraints into independent clusters is the optimal solution. This operation directly cuts off the edges of the child sub-trees that are connected to the root node and have the largest total cost, eliminating the violation of the current level sub-tree while maintaining the original load balancing state of the child sub-trees. This avoids redundant splitting of the internal part of the child sub-trees that satisfy the design rules, and ensures that each new independent cluster satisfies the design constraints, achieving the minimum structural adjustment.

[0115] The design constraints include the maximum fan-out and / or the maximum drive capacitance. In this embodiment, when the number of elements included in a sub-tree exceeds the maximum fan-out, or the total capacitance of the sub-tree exceeds the maximum drive capacitance, the sub-tree violates the design constraints. In some embodiments, only when the number of elements included in a sub-tree exceeds the maximum fan-out, and the total capacitance of the sub-tree exceeds the maximum drive capacitance, is the sub-tree determined to violate the design constraints.

[0116] It can be understood that by limiting the design constraints to the maximum fan-out and / or the maximum drive capacitance, the maximum fan-out constraint prevents signal quality degradation, and the maximum capacitance constraint prevents driver overload, and the two complement each other to form a complete protection closed loop.

[0117] In step S4, the remaining sub-trees after the binary tree separates the child sub-trees are verified, and the above step S3 is repeated until all the sub-trees satisfy the design constraints. The operations of steps S3 and S4 are performed for each binary tree to ensure that the sub-trees of each binary tree and the separated child sub-trees thereof all satisfy the design constraints.

[0118] In step S5, each sub-tree obtained after step S4 is taken as a cluster, and the top of the cluster and the top of the independent cluster separated from the child sub-tree are added to the driver to generate a clustered cluster.

[0119] In step S6, the clustered cluster obtained after step S5 is taken as a new clock tree to-be-driven element, and the steps S1-S5 are repeated until the number of clustered clusters is unchanged or the iteration number reaches a preset upper limit, and a final clustered cluster is obtained. A clock source is added to the top layer of the final clustered cluster, and a clock tree is output.

[0120] Understandably, after each execution of steps S1-S5, a driver is inserted for each clustered cluster, so that the clock tree has one more level, and the newly added driver replaces the to-be-driven element to become a new top layer element. The top layer element gradually decreases with the iteration number, and when the number of clustered clusters is unchanged or the iteration number reaches the preset upper limit, each clustered cluster in the current level has reached or approached the upper limit of the design constraint, and cannot further reduce the number of top layer elements through further clustering, forming an efficient multi-level driving architecture. Under the premise that each clustered cluster meets the design constraint, the driving capability of the driver is maximized, and the number of inserted drivers is avoided to be too large.

[0121] Finally, after the iteration ends, a final clustered cluster is obtained, a clock source is added to the top layer of the final clustered cluster, and a final clock tree is output.

[0122] It should be noted that in other embodiments, only the number of clustered clusters and / or the corresponding clock tree clustering scheme can be output based on the above steps S1-S6.

[0123] When the above steps S1-S6 are executed, it is necessary to ensure that the number of clustered clusters obtained is as small as possible without violating the design constraint, that is, the newly added driver is as small as possible. Therefore, in this embodiment, the following optimization function is proposed, and the clustering process takes minimizing the following global objective function as the optimization target:

[0124]

[0125]

[0126] Wherein, min Cost is the optimization target function, which is used to balance the total capacitance and the number of drivers; k represents the total number of clustered clusters, represents the i-th clustered cluster, and respectively represent the total capacitance of the element pin and the total capacitance of the interconnection network of the i-th clustered cluster, represents the number of elements contained in the i-th cluster, f represents the clustering cost determined by the parameters of the driver, max_fanout represents the maximum fanout in the design constraint, and max_cap represents the maximum drive capacitance in the design constraint.

[0127] It can be understood that the optimization objective function includes both the element capacitance and the network capacitance, and limits the fanout of the cluster to be less than the limited maximum fanout and limits the sum of the element capacitance and the network capacitance of the cluster to be less than the limited maximum capacitance, so as to ensure that the cluster does not violate the design constraint. Further, through the constraint term kf, that is, the product of the total number of clusters and the clustering cost, the number of clusters is as small as possible, so as to ensure that the driving capability of the driver is maximally exerted.

[0128] The steps of the clock tree clustering method provided in the embodiments of the present application solve the technical problems in the prior art that the existing clock tree clustering method cannot directly guide clustering according to various constraints and optimization objectives in clock tree synthesis, the target is not clear when clustering, and the driving capability is easily wasted and the design rules are easily violated.

[0129] Referring to Figure 2 , it is verified whether the sub-tree of each binary tree satisfies the design constraint, including the following steps:

[0130] S31: The binary tree is traversed from bottom to top to find the root node of the sub-tree that violates the design constraint, wherein the child sub-trees of the sub-tree all satisfy the design constraint;

[0131] S32: The edge between the root node of the sub-tree and the child sub-tree with the maximum total cost is deleted, so that the child sub-tree is separated from the whole binary tree, and the separated child sub-tree is processed as an independent cluster;

[0132] S33: The remaining sub-trees of the binary tree are continuously traversed from bottom to top, and the child sub-trees of the sub-trees that violate the design constraint are separated, until all the sub-trees satisfy the design constraint;

[0133] It can be understood that, by traversing the binary tree from bottom to top and based on the separation strategy of the total cost of the sub-tree, the sub-tree with the maximum total cost is preferentially cut, so as to ensure that the child sub-trees satisfy the design constraint while avoiding the generation of low-load clusters, and to realize deterministic convergence.

[0134] The specific steps S31 to S33 of the clock tree clustering method will be described below.

[0135] Firstly, in step S31, each binary tree is traversed from bottom to top to find the root node corresponding to the deepest sub-tree, that is, the sub-tree with the maximum hierarchical depth, that violates the design constraint, and the left and right child sub-trees of the sub-tree must satisfy the design constraint.

[0136] By traversing the binary tree from bottom to top, it can be ensured that when processing any subtree, its descendant subtree, i.e. the subtree at a lower level, has been checked and processed in advance, the most local design constraint violation subtree at the deepest level is solved first, each operation accurately eliminates a minimum violation unit, maximizes the utilization efficiency of driving capability, and minimizes unnecessary cluster splitting.

[0137] Secondly, in step S32, after traversing to the deepest subtree violating the design constraint, instead of directly separating the left and right child subtrees of the subtree, an edge between the root node of the subtree and the child subtree with the maximum total cost is deleted, so that the child subtree on one side is separated from the whole binary tree, and the separated child subtree is taken as an independent cluster.

[0138] It should be noted that the total cost formula of the subtree is:

[0139]

[0140] Wherein, n represents the number of nodes in the subtree T, C(v i ) represents the capacitance value of the node vi, Q(e) represents the length of the edge e of the subtree T, and E T represents the set of edges in the subtree T.

[0141] That is, the total cost of the subtree is the sum of the capacitance values of all points in the subtree plus the sum of the lengths of all edges in the minimum spanning tree.

[0142] By deleting the edge between the root node of the subtree and the child subtree with the maximum total cost, the load module that contributes most to the current design constraint violation can be removed. Separating the high-cost subtree can significantly reduce the load pressure of the remaining part, making it easier to meet the design constraint. At the same time, the separated high-cost subtree itself already meets the constraint and can be directly used as an independent cluster for efficient driving, avoiding the waste of driver capability, thereby optimizing the overall driving efficiency and cluster load balancing while solving the violation.

[0143] Finally, in step S33, the remaining subtree of the binary tree is continuously traversed from bottom to top, and the child subtree of the design constraint violation subtree is separated, that is, the operations of S31 and S32 are continuously performed on the remaining subtree until all subtrees meet the design constraint.

[0144] By the above clock tree clustering method, the to-be-driven elements of the initial clock tree are subjected to minimum spanning tree generation, pruning, and generation tree set obtaining; further, the binary tree conversion and bottom-up traversal of the binary tree are performed on the generation tree set to separate the clock tree into clustered clusters and insert the driver, and finally the clock tree is output.

[0145] In the clustering process of the clock tree clustering method, the design constraint is always taken as the bottom line to ensure that the clustered clock tree meets the design constraint. By traversing each binary tree from bottom to top, the sub-tree with the largest load but meeting the design constraint is found for cluster separation, effectively avoiding redundant partitioning of the sub-tree and redundant insertion of the driver, and efficiently utilizing the driving capability of each driver.

[0146] Referring to Figure 3 The embodiment of the present application also provides a clock tree clustering system 1, which comprises a user terminal 11 and a micro-service terminal 12 connected in communication; the micro-service terminal 12 receives a to-be-processed command input by the user terminal 11 and executes the steps of the clock tree clustering method according to the to-be-processed command.

[0147] It should be noted that the clock tree clustering method provided in the foregoing embodiments is implemented by using the micro-service-based clock tree clustering system 1. The micro-service is to separate a single-module unit from an original, comprehensive monomer application, so that the original software architecture is clearer and simpler, and the function of the single-module unit can be updated, maintained and further improved.

[0148] Specifically, the clock tree clustering system 1 of the embodiment of the present application separates the clock tree clustering function in the EDA software to form the micro-service terminal 12. Through this design, a person skilled in the art or a user skilled in EDA software only needs to deploy a set of micro-service of the clock tree clustering in advance, and can request the micro-service on different versions of EDA software in the local area network, so as to realize the clock tree clustering through the micro-service terminal 12 and reduce the occupation of the memory resource.

[0149] Referring to Figure 4 The embodiment of the present application also provides a computer device 2, which comprises a storage 21, a processor 22 and a computer program 100 stored in the storage 21. The processor 22 executes the computer program 100 to realize the steps of the clock tree clustering method.

[0150] It can be understood that the computer device 2 provided in the embodiment of the present application can realize the clock tree clustering method described in the foregoing embodiments when the processor 22 executes the computer program 100. The computer device 2 provided in the embodiment of the present application has the same beneficial effects as the clock tree clustering method provided in the foregoing embodiments.

[0151] In some embodiments, the computer device 2 is a computer device applied to the technical field of EDA software application, including but not limited to obtaining initial clock tree elements to be driven and capacitance values, generating an initial minimum spanning tree, traversing a binary tree and verifying whether a design constraint is met, and the like, which will not be described herein. In theory, the method steps involved in the technical solutions of the present application can be realized by participating in control of the computer device 2, and the related parameters involved can be adjusted by the computer device 2, including but not limited to preset command sets and preset option sets and the like.

[0152] In some embodiments, the processor 22 provided by the embodiments of the present application is a general-purpose processor, which is a microprocessor or any conventional processor, such as a central processing unit (CPU), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, which can implement or execute the methods, steps and logic block diagrams disclosed in the embodiments of the present application.

[0153] In some embodiments, the method steps disclosed in the embodiments of the present application can be embodied by a hardware processor for execution or by a combination of hardware and software modules in the processor 22 for execution.

[0154] Please refer to Figure 5 The embodiments of the present application also provide a computer readable storage medium 3 having a computer program 100 stored thereon, which realizes the steps of the clock tree clustering method described above when executed by a processor.

[0155] It can be understood that the computer readable storage medium 3 provided by the embodiments of the present application stores the computer program 100, and the computer program 100 can be called by the processor to execute the clock tree clustering method described in the above embodiments.

[0156] It should be noted that the computer readable storage medium 3 provided by the embodiments of the present application has the same beneficial effects as the clock tree clustering method provided by the above embodiments, which will not be described herein.

[0157] Specifically, the computer readable storage medium 3 can include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic memory, magnetic disk, optical disk, and the like.

[0158] In some embodiments, the computer readable storage medium 3 comprises a non-volatile computer readable storage medium, which can be used to store non-volatile software programs, non-volatile computer executable programs and modules.

[0159] In particular, the computer readable storage medium 3 has storage space for computer programs 100 that perform any of the method steps of the clock tree clustering methods described above, which can be read from or written to one or more computer program products.

[0160] In some embodiments, the computer programs 100 can be compressed in an appropriate form.

[0161] Referring to Figure 6 The embodiments of the present application also provide a computer program product 4 comprising the computer programs 100, which, when executed by a processor, implement the steps of the clock tree clustering described above.

[0162] It can be understood that the computer program product 4 provided by the embodiments of the present application comprises the computer programs 100, and the computer programs 100 can be called by a processor to execute the clock tree clustering methods described in the above embodiments, which will not be described here.

[0163] The clock tree clustering methods, clock tree clustering systems, devices, media and products disclosed by the embodiments of the present application are described in detail above, and the principles and implementation manners of the present application are described by applying specific examples in this paper. The above description of the embodiments is only used to help understand the method of the present application and its core idea.

[0164] At the same time, for those skilled in the art, according to the idea of the present application, there will be changes in specific implementation manners and application ranges, and the above description should not be understood as a limitation of the present application. Any modification, equivalent replacement and improvement within the principles of the present application should be included in the protection scope of the present application.

Claims

1. A clock tree clustering method, characterized in that, Includes the following steps: Given an initial clock tree, extract the position and capacitance parameters of the components to be driven, and construct a minimum spanning tree based on the positions of the components to be driven: Remove all edges in the minimum spanning tree whose length is greater than the clustering cost to obtain the set of spanning trees; Convert all spanning trees into binary trees and verify whether the subtrees of each binary tree satisfy the design constraints. If the child subtrees of a subtree of a binary tree all satisfy the design constraints, but the subtree itself does not satisfy the design constraints, then separate the child subtrees as independent clusters and continue to verify the remaining subtrees of the binary tree. Repeat the verification process until all subtrees of the binary tree satisfy the design constraints. Treat each subtree as a cluster, and add a driver at the top of the cluster to generate a cluster; Treat the clusters as new clock tree elements to be driven, and repeat the above steps until the number of clusters remains unchanged or the number of iterations reaches the preset upper limit to obtain the final clusters. Add a clock source to the top layer of the final clusters and output the clock tree.

2. The clock tree clustering method as described in claim 1, characterized in that: Verifying whether each subtree of a binary tree satisfies the design constraints includes the following steps: Traverse the binary tree from bottom to top to find the root node of the subtree that violates the design constraints, where all child subtrees of the subtree satisfy the design constraints. Delete the edge between the root node of the subtree and the child subtree with the largest total cost, so that the child subtree is separated from the binary tree as a whole, and the separated child subtree is treated as an independent cluster; Continue traversing the remaining subtrees of the binary tree from bottom to top, and separate the child subtrees of the subtrees that violate the design constraints, until all subtrees satisfy the design constraints; The total cost formula for the subtree is: Where n represents the number of nodes in subtree T, C(v i ) represents node v i The capacitance value, Q(e), represents the length of edge e in subtree T, E T Let T represent the set of edges in subtree T.

3. The clock tree clustering method as described in claim 1, characterized in that: The design constraints include maximum fan-out and / or maximum drive capacitance; A subtree violates design constraints when the number of components it contains exceeds the maximum fan-out, and / or the total capacitance of the subtree exceeds the maximum drive capacitance.

4. The clock tree clustering method as described in claim 1, characterized in that: Clustering cost equals driver capacitance; Alternatively, the clustering cost can be calculated using the following formula: Where f represents the clustering cost, P driver ω represents the power consumption of the driver, and ω represents the trade-off factor, where ω∈[0.2,1].

5. The clock tree clustering method as described in claim 1, characterized in that: The formula for the length of the edge between two points in a minimum spanning tree is: Where Q(e) represents the length of edge e, d1(u,v) represents the 1-norm distance between point u and point v that constitute edge e, and C0 represents the network capacitance per unit length of wire.

6. The clock tree clustering method as described in claim 4, characterized in that: The clustering process aims to minimize the following global objective function: Where, min Cost is the optimization objective function, used to balance the total capacitance and the number of drivers; k represents the total number of clusters. This represents the i-th cluster. and These represent the total capacitance of the component pins and the total capacitance of the interconnect network in the i-th cluster, respectively. The i-th cluster contains the number of elements, f represents the clustering cost, which is determined by the driver parameters, max_fanout represents the maximum fanout in the design constraints, and max_cap represents the maximum driving capacitance in the design constraints.

7. The clock tree clustering method as described in claim 1, characterized in that, The process of converting a spanning tree into a binary tree includes: Choose any root node and orient the edges, and virtually split any node with an out-degree greater than 2 into multiple nodes with an out-degree of 2.

8. A clock tree clustering system, characterized in that: The clock tree clustering system includes a user terminal and a microservice terminal with communication connections; The microservice receives the pending command input from the user and executes the steps of the clock tree clustering method according to any one of claims 1-7.

9. A computer device comprising a storage unit, a processor, and a computer program stored on the storage unit, characterized in that, The processor executes the computer program to implement the steps of the clock tree clustering method according to any one of claims 1-7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the clock tree clustering method according to any one of claims 1-7.

11. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the clock tree clustering method according to any one of claims 1-7.

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