Micro-channel thermal management structure for power management chip and low-temperature bonding process of micro-channel thermal management structure

Abstract

The invention relates to a micro-channel thermal management structure for a power management chip and a low-temperature bonding process of the micro-channel thermal management structure, and belongs to the field of semiconductor packaging, the micro-channel thermal management structure comprises a DC-DC converter wafer, a digital control wafer, a TSV silicon through hole array and a snakelike micro-channel, and the micro-channel thermal management structure is characterized in that the TSV silicon through hole array is arranged between the DC-DC converter wafer and the digital control wafer; the TSV array and the snakelike micro-channel are arranged in a staggered manner at an included angle of 30 + / -5 degrees, and the width tolerance of the channel is less than or equal to + / -1.5 [mu] m; the micro-channel is filled with ammonia water-based nanofluid, the volume concentration is 5%-8%, and the micro-channel heat management structure comprises a gradient porosity copper / graphene composite layer. The problems that although an existing chip structure is provided with a micro-channel heat dissipation structure, the heat dissipation effect is limited due to the fact that the micro-channel heat dissipation structure and TSV through holes are not designed cooperatively, the graphene heat dissipation film interface contact resistance is high, and the actual heat dissipation performance is poor are solved.

Description

TECHNICAL FIELD

[0001] The present application relates to a micro-channel heat management structure for power management chips and its low-temperature bonding process, belonging to the field of semiconductor packaging. BACKGROUND

[0002] With the development of electronic devices towards high performance, miniaturization and high power density, the heat dissipation problem of power management chips is increasingly prominent. The existing technology has the following defects: 1. High thermal resistance: the thermal resistance of traditional packaging is generally greater than 10℃ / W (as shown in US20220109345A1), which is difficult to meet the needs of 200W / cm² power density scenarios.

[0003] 2. Limitation of heat dissipation material: the thermal conductivity of pure copper heat dissipation layer is only 385W / mK, and the thermal expansion coefficient (17ppm / K) is seriously mismatched with the silicon substrate (2.6ppm / K), resulting in thermal stress problems.

[0004] 3. Bonding process bottleneck: conventional hot pressing bonding requires high temperature above 300℃, which is easy to cause thermal stress damage to TSV copper pillars, with a crack rate exceeding 15%.

[0005] For example, the invention patent with publication number CN114639647A discloses a micro-channel heat dissipation structure and a microelectronic chip structure, although there is a micro-channel heat dissipation structure, but it is not designed in cooperation with the TSV through hole, and the heat dissipation effect is limited.

[0006] The invention patent with publication number CN113226001A discloses a heat dissipation device based on a graphene heating chip, the thermal conductivity of the graphene heat dissipation film is only 500W / mK, and the interface contact resistance is high, the actual heat dissipation performance is not good.

[0007] Therefore, we improve it and propose a micro-channel heat management structure for power management chips and its low-temperature bonding process. SUMMARY

[0008] (1) The technical problem to be solved by the present application is that the existing chip structure has a micro-channel heat dissipation structure, but it is not designed in cooperation with the TSV through hole, the heat dissipation effect is limited, the interface contact resistance of the graphene heat dissipation film is high, and the actual heat dissipation performance is not good.

[0009] (2) Technical solution In order to achieve the above-mentioned purposes, the application provides a micro-channel thermal management structure for a power management chip, comprising a DC-DC converter wafer, a digital control wafer, a TSV through silicon via array and a serpentine micro-channel, wherein the TSV through silicon via array is arranged between the DC-DC converter wafer and the digital control wafer; the TSV through silicon via array and the serpentine micro-channel are staggered at an angle of 30°±5°, and the flow channel width tolerance is ≤±1.5μm; the micro-channel is filled with ammonia-based nanofluid with a volume concentration of 5%-8%.

[0010] The micro-channel thermal management structure comprises a gradient porosity copper / graphene composite layer, the composite layer comprises a Level 1 layer and an interlayer interface, the Level 1 layer is a copper powder sintered body and single-layer graphene film composite structure, and the interlayer interface is treated by plasma to form-COOH functional groups, and the contact resistance is less than 0.5Ω·cm².

[0011] The porosity of the copper powder sintered body is 10%, and the single-layer graphene film is prepared by a CVD growth method.

[0012] The gradient porosity copper / graphene composite layer further comprises: a Level 2 layer: a copper powder sintered body with a porosity of 20% and a 20-layer graphene film composite; a Level 3 layer: a copper powder sintered body with a porosity of 30% and a 30-layer graphene film composite.

[0013] The TSV through silicon via has a diameter of 5μm and a depth of 300μm, and the serpentine micro-channel has a wide slot structure with a depth of 200μm.

[0014] A low-temperature bonding process for a micro-channel thermal management structure for a power management chip, comprising the following steps: S1: silicon wafer preparation; S2: TSV via etching; S3: copper column electroplating; S4: plasma activation, using O2 / H2 mixed gas, radio frequency power 200W; S5: copper-copper bonding; S6: graphene film transfer; S7: gradient sintering, using metal injection molding technology, sintering temperature 1080℃, holding time 2h; forming a gradient porosity by electrochemical corrosion, electrolyte is 10% NaOH solution, current density 2A / cm²; S8: micro-channel laser processing, using laser micro-nano processing to form a micro-groove structure with a depth of 5μm and a pitch of 20μm.

[0015] The step S3 removes the oxide layer by chemical etching, and the roughness Ra is less than 0.1 nm.

[0016] The step S4 removes the fluorine component in the plasma activated gas.

[0017] The copper-copper bonding in the step S5 does not use ultrasonic auxiliary vibration, the bonding temperature is 180 DEG C, the pressure is 200 kPa, and the time is 30 min.

[0018] The graphene film in the step S6 is attached under the conditions of a temperature of 80 DEG C, a pressure of 10 kPa, and a time of 120 min.

[0019] (Three) beneficial effects The micro-channel heat management structure for the power management chip and the low-temperature bonding process provided by the application have the beneficial effects that: 1. Structural innovation: TSV and micro-channel cooperate to dissipate heat, the heat flux density is increased by 3 times compared with the traditional scheme, efficient heat dissipation is realized, the TSV array and the serpentine micro-channel are staggered at 30 DEG ± 5 DEG, the thermal resistance is reduced to 5.8 DEG C / W@200W, and the thermal resistance is reduced by 42% compared with the traditional package.

[0020] 2. Material breakthrough: the copper / graphene gradient composite layer effectively solves the interface thermal resistance problem, improves the overall thermal performance, effectively solves the interface thermal resistance problem, and the thermal conductivity reaches 612 W / mK.

[0021] 3. Process compatibility: the low-temperature bonding process is suitable for vehicle-grade chips, the bonding strength is 38.6 MPa, and no cracks are observed by SEM, which meets the AEC-Q101 certification requirements, and completely avoids the 15% crack rate risk of the traditional 300 DEG C process. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiment or prior art description. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0023] Figure 1 It is a whole structure schematic diagram of the micro-channel heat management structure for the power management chip. Figure 2 It is a three-dimensional packaging structure schematic diagram of the power management chip. Figure 3 It is a manufacturing process flow chart. Figure 4 It is a gradient porosity copper structure schematic diagram. Figure 5 It isFigure 4 Enlarged schematic view of the structure at A; Figure 6 SEM cross-sectional view of the gradient porosity copper layer of the present application; Figure 7 Enlarged schematic view of the structure at B; Figure 6 Enlarged schematic view of the structure at B; Figure 8 Temperature curve of the low-temperature bonding process of the present application; Figure 9 Schematic view of the photolithography mask for laser processing of the microfluidic channel of the present application; Figure 10 Schematic view of the top structure of the microfluidic channel of the present application. DETAILED DESCRIPTION

[0024] The specific embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings and examples. The following examples are only used to illustrate the present application, but cannot be used to limit the scope of the present application.

[0025] Example 1: As shown in Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 and Figure 10 , the present embodiment proposes a microfluidic heat management structure for a power management chip, which includes a DC-DC converter wafer, a digital control wafer, a TSV through-silicon via array and a serpentine microfluidic channel, the TSV through-silicon via array is arranged between the DC-DC converter wafer and the digital control wafer; the TSV through-silicon via array and the serpentine microfluidic channel are staggered at an angle of 30°, the TSV through-silicon via has a diameter of 5 μm and a depth of 300 μm, the serpentine microfluidic channel has a wide slot structure, a depth of 200 μm and a channel width tolerance of ≤±1.5 μm; the microfluidic channel is filled with ammonia-based nanofluid with a volume concentration of 5%-8%.

[0026] A low-temperature bonding process for a microfluidic heat management structure for a power management chip, comprising the following steps: S1: silicon wafer preparation; S2: TSV via etching; S3: copper column electroplating, using chemical etching (HNO3:H2O=1:3) to remove the oxide layer, roughness Ra<0.1 nm; S4: plasma activation, using O2 / H2 mixed gas (flow ratio 4:1), radio frequency power 200 W, and removing fluorine components from the plasma activated gas; S5: Copper-copper bonding, copper-copper bonding does not use ultrasonic auxiliary vibration, bonding temperature 180℃, pressure 200kPa, time 30min; S6: Graphene film transfer, graphene film bonding conditions: temperature 80℃, pressure 10kPa, time 120min; S7: Gradient sintering, using metal injection molding (MIM) technology, sintering temperature 1080℃, holding time 2h; form gradient porosity by electrochemical corrosion, electrolyte is 10% NaOH solution, current density 2A / cm²; S8: Micro-channel laser processing, laser micro-nano processing is used to form a micro-groove structure with a depth of 5μm and a pitch of 20μm.

[0027] Example 2: The scheme in Example 1 is further introduced in combination with a specific working mode, and details are described below: As shown in Figure 1 , Figure 2 , Figure 3 , Figure 7 , Figure 8 , Figure 9 , Figure 10 As a preferred embodiment, on the basis of the above mode, further, the micro-channel thermal management structure contains a gradient porosity copper / graphene composite layer, which includes a Level 1 layer and an interlayer interface, the Level 1 layer is a copper powder sintered body and a single-layer graphene film composite structure, and the interlayer interface adopts plasma treatment to form-COOH functional groups, the contact resistance is less than 0.5Ω·cm², the graphene surface is modified by carboxylation, and the contact angle is less than 15°, which effectively reduces the interface contact resistance. The porosity of the copper powder sintered body is 10%, and the single-layer graphene film is prepared by CVD growth method. Gradient porosity copper / graphene composite layer: Low-temperature bonding process: Experimental verification: Example 3: The schemes in Example 1 and Example 2 are further introduced in combination with a specific working mode, and details are described below: Specifically, the micro-channel thermal management structure for power management chip in use: As shown in Figure 1 , Figure 2 and Figure 3As shown, the TSV array (diameter 5 pm) vertically penetrates through three layers to realize electrical / thermal / signal interconnection, the wavy micro-channel (width 50 ± 2 pm) surrounds the TSV at an angle of 30°, the cooling liquid flows in from the left inlet and flows out from the right outlet after surrounding the TSV and hotspot area (power device / NPU); the gradient porosity copper / graphene composite layer, Level 1 to Level 3 porosity 10%→30% (combined Figure 4 、 Figure 5 、 Figure 6 and Figure 7 ), reduces the contact resistance through the carboxylated interface (contact angle < 15°), and the bottom FeRAM is directly connected to the middle NPU through the TSV to support radiation-resistant operation.

[0028] As shown in Figure 3 、 Figure 8 、 Figure 9 and Figure 10 , the low-temperature bonding process is as follows: first, silicon wafers are prepared to provide DC-DC converter wafers and digital control wafers. Then, TSV through holes are etched on the wafers, with a diameter of 5 pm and a depth of 300 pm. Then, copper pillars are electroplated in the TSV through holes. The copper pillar surface is pretreated by chemical etching (HNO3:H2O = 1:3) to remove the oxide layer, so that the surface roughness Ra is less than 0.1 nm. Then, plasma activation treatment is performed using O2 / H2 mixed gas (flow ratio 4:1), radio frequency power 200 W, temperature 30°C, pressure 50 kPa, and duration 60 min. Then, copper-copper bonding is performed at a temperature of 180°C, a pressure of 200 kPa, and a duration of 30 min without ultrasonic auxiliary vibration. Then, the graphene film is transferred to the composite layer interface, and a porous copper layer is prepared by gradient sintering. Metal injection molding (MIM) technology is used, with a sintering temperature of 1080°C and a holding time of 2 h. Gradient porosity (Level 1: 10%, Level 2: 20%, Level 3: 30%) is formed by electrochemical etching, with an electrolyte of 10% NaOH solution and a current density of 2 A / cm². Finally, micro-channel laser processing is performed, and 10-15 layers of graphene film are grown by surface chemical vapor deposition (CVD). The serpentine micro-channel (width 50 ± 2 pm, depth 200 pm) is laser processed, and a micro-groove structure with a depth of 5 pm and a pitch of 20 pm is formed.

[0029] The above embodiments are only used to illustrate the present application, but not to limit the present application. Although the present application is explained in detail with reference to the embodiments, those skilled in the art should understand that various combinations, modifications or equivalent replacements of the technical solutions of the present application do not deviate from the spirit and scope of the present application, and should be covered in the scope of the claims of the present application.

Claims

1. A microchannel thermal management structure for a power management chip, comprising a DC-DC converter wafer, a digital control wafer, a TSV through silicon via array, and a serpentine microchannel, characterized in that: The TSV through-silicon via array is arranged between the DC-DC converter wafer and the digital control wafer; the TSV through-silicon via array and the serpentine microchannel are staggered at an angle of 30°±5°, and the channel width tolerance is ≤±1.5μm; the microchannel is filled with ammonia-based nanofluid with a volume concentration of 5%-8%.

2. The microchannel thermal management structure for a power management chip according to claim 1, characterized in that: The microchannel thermal management structure includes a gradient porosity copper / graphene composite layer, which includes a Level 1 layer and an interlayer interface. The Level 1 layer is a composite structure of a copper powder sintered body and a single-layer graphene film. The interlayer interface is plasma-treated to form -COOH functional groups, and the contact resistance is less than 0.5Ω·cm².

3. The microchannel thermal management structure for a power management chip according to claim 2, characterized in that: The porosity of the copper powder sintered body is 10%, and the single-layer graphene film is prepared by a CVD growth method.

4. The microchannel thermal management structure for a power management chip according to claim 2, characterized in that: The gradient porosity copper / graphene composite layer further comprises: Level 2: A sintered copper powder with a porosity of 20% and 20 layers of graphene film. Level 3: A sintered copper powder with a porosity of 30% is composited with 30 layers of graphene film.

5. The microchannel thermal management structure for a power management chip according to claim 1, characterized in that: The TSV through silicon via has a diameter of 5 μm and a depth of 300 μm. The cross section of the serpentine microchannel is a wide groove structure with a depth of 200 μm.

6. A low-temperature bonding process for a microchannel thermal management structure for a power management chip according to claims 1-5, characterized in that: The following steps are involved: S1: Silicon wafer preparation; S2: TSV through-hole etching; S3: copper pillar electroplating; S4: plasma activation, using O2 / H2 mixed gas, RF power 200W; S5: copper-copper bonding; S6: graphene film transfer; S7: Gradient sintering, using metal injection molding technology, sintering temperature 1080℃, holding time 2h; gradient pores are formed by electrochemical corrosion, the electrolyte is 10% NaOH solution, the current density is 2A / cm²; S8: Microchannel laser processing, using laser micro-nano processing to form a micro-groove structure with a depth of 5μm and a spacing of 20μm.

7. The low temperature bonding process according to claim 6, characterized in that: In step S3, chemical etching is used to remove the oxide layer, with a roughness Ra of less than 0.1 nm.

8. The low temperature bonding process according to claim 6, characterized in that: In step S4, the plasma activated gas removes fluorine-containing components.

9. The low temperature bonding process according to claim 6, characterized in that: In step S5, the copper-copper bonding is performed without ultrasonic-assisted vibration, with a bonding temperature of 180° C., a pressure of 200 kPa, and a bonding time of 30 min.

10. The low temperature bonding process according to claim 6, characterized in that: The graphene film lamination conditions in step S6 are: temperature 80° C., pressure 10 kPa, and time 120 min.

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