Multi-mode wired transmitter based on CML driver and impedance calibration loop

Abstract

The invention discloses a multi-mode wired transmitter based on a CML driver and an impedance calibration loop, and the transmitter comprises a controller, the impedance calibration loop, N + 1 analog-to-digital converters DAC, and N-mode tailless CML drivers of which the output ends are connected with a numerical control load, the controller is connected with the impedance calibration loop and the control ends of the N + 1 analog-to-digital converters DAC, and the controller is connected with the impedance calibration loop and the control ends of the N + 1 analog-to-digital converters DAC. The impedance calibration loop is connected with an adjustment control end of a numerical control load of the tailless CML driver, and the N + 1 analog-to-digital converters DAC are respectively connected with the tailless CML driver in each mode so as to adjust the swing amplitude and balance intensity of signals. The invention aims to solve the problem of impedance mismatch caused by a tailless structure of a tailless CML driver, realizes high output swing while keeping low power consumption, realizes continuous adjustment of FFE strength in a wide range under the condition of not segmenting the driver, and supports three modulation modes to adapt to different transmission rates and channel loss.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, in particular to a multi-mode wired transmitter based on a CML driver and an impedance calibration loop. BACKGROUND

[0002] With the rapid development of artificial intelligence, cloud computing and big data, the demand for data exchange between local chips is rapidly growing. Therefore, it is essential to achieve high data rate, low bit error rate (BER) and low power consumption for wired link design. Current mode logic (CML) driver is widely used in high-speed differential wired transmission due to its high swing and high bandwidth characteristics. In previous work, various CML driver structures have been proposed. For example, inductance and feedback are introduced to improve bandwidth or CML-SST hybrid mode driver is used to achieve high swing. In some recent work, researchers have adopted tailless CML driver to reduce power consumption. However, this will cause impedance mismatch when the output swing is high, resulting in greater reflection, which in turn affects signal integrity. SUMMARY

[0003] The technical problem solved by the present application: In view of the above problems of the prior art, a multi-mode wired transmitter based on a CML driver and an impedance calibration loop is provided. The present application aims to solve the problem of impedance mismatch caused by the tailless structure of the tailless CML driver, achieve high output swing while maintaining low power consumption, achieve continuous adjustment of FFE strength in a wide range without driver segmentation, support three modulation modes to adapt to different transmission rates and channel losses.

[0004] To solve the above technical problems, the technical scheme adopted by the present application is: A multi-mode wired transmitter based on a CML driver and an impedance calibration loop, comprising a controller, an impedance calibration loop, N+1 analog-to-digital converters DAC and N mode tailless CML drivers connected with digital controlled loads at the output end, the controller is connected with the control end of the impedance calibration loop and the N+1 analog-to-digital converters DAC respectively, the impedance calibration loop is connected with the adjustment control end of the digital controlled load of the tailless CML driver, the N+1 analog-to-digital converters DAC are connected with the tailless CML driver in each mode respectively to adjust the swing and equalization strength of the signal in each mode of the tailless CML driver, wherein N is the number of modes.

[0005] Optionally, the impedance calibration loop comprises a replica resistor, an off-chip reference resistor, a comparator and a calibration logic, the replica resistor is an adjustable resistor and has one end connected to a power supply and the other end connected to the ground through the off-chip reference resistor, the middle connection point of the replica resistor and the off-chip reference resistor is connected to the positive input terminal of the comparator, the negative terminal of the comparator is connected to a reference voltage, the output terminal of the comparator is connected to the input terminal of the calibration logic, and the output terminal of the calibration logic is connected to the adjustment control terminal of the replica resistor and the adjustment control terminal of the digital controlled load.

[0006] Optionally, the output terminal of the tailless CML driver is connected to the output terminal of the multi-mode wired transmitter through a common connection point, the common connection point is connected to the power supply through an inductor and a digital controlled load, and is grounded through an electrostatic protection circuit (ESD).

[0007] Optionally, a T-type coil is connected in series between the output terminal of the tailless CML driver and the common connection point to improve the bandwidth.

[0008] Optionally, the input terminal of the tailless CML driver is connected to a mode selection module, a multiplexer and a data generator in sequence, the multiplexer is used to multiplex the data output by the data generator to generate a differential signal composed of high bit data (MSB) and low bit data (LSB), and the mode selection module is used to send the differential signal to the tailless CML driver of the corresponding mode according to the set communication mode.

[0009] Optionally, the multiplexer is a 32:8 multiplexer, which is used to multiplex the 32-bit data output by the data generator to generate an 8-bit differential signal composed of 4-bit high bit data (MSB) and 4-bit low bit data (LSB).

[0010] Optionally, each mode of the tailless CML driver comprises a main tap driver and a back tap driver, N of the N+1 analog-to-digital converters (DACs) are respectively connected to the gate of the bias tube of the main tap driver of one tailless CML driver, and the remaining 1 analog-to-digital converter (DAC) is connected to the gate of the bias tube of the back tap driver of all tailless CML drivers.

[0011] Optionally, further comprising a clock circuit, the clock circuit comprising a on-chip buffer, a first clock divider, a duty cycle correction circuit (DCC), a second clock divider and a third clock divider connected in sequence, a differential clock signal input from outside is connected to the input terminal of the on-chip buffer, the duty cycle correction circuit (DCC) comprises a quadrature four-phase clock output terminal for outputting a quadrature four-phase clock signal and a differential clock output terminal for outputting a differential clock signal, the quadrature four-phase clock output terminal is connected to the clock input terminal of the tailless CML driver, the differential clock output terminal is connected to the second clock divider and the third clock divider in sequence, the output terminal of the second clock divider is connected to the clock input terminal of the multiplexer, and the output terminal of the third clock divider is connected to the clock input terminal of the data generator.

[0012] Optionally, the quadrature four-phase clock signal comprises clock signals with phases of 0°, 90°, 180° and 270°, respectively.

[0013] Optionally, the N mode tailless CML drivers are three-mode tailless CML drivers, respectively used for transmitting PAM4 encoded data, NRZ encoded data and duobinary encoded data.

[0014] Compared with the prior art, the application mainly has the following beneficial effects: the multi-mode wired transmitter based on the CML driver and the impedance calibration loop comprises a controller, an impedance calibration loop, N+1 analog-to-digital converters (DACs) and N mode tailless CML drivers connected with digital controlled loads at the output terminals, the controller is connected with the control terminals of the impedance calibration loop and the N+1 analog-to-digital converters (DACs) respectively, the impedance calibration loop is connected with the adjustment control terminals of the digital controlled loads of the tailless CML drivers, and the N+1 analog-to-digital converters (DACs) are connected with the tailless CML drivers in each mode respectively to adjust the swing and equalization strength of the signals. The controller of the application is connected with the control terminals of the impedance calibration loop and the N+1 analog-to-digital converters (DACs) respectively, which can solve the impedance mismatching problem caused by the tailless structure of the tailless CML driver, realize high output swing while keeping low power consumption, realize continuous adjustment of the feedforward equalization (FFE) strength in a wide range without segmenting the driver, support three modulation modes to adapt to different transmission rates and channel losses. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 It is a transmitter structure diagram in the embodiment of the application.

[0016] Figure 2 It is a driver circuit principle diagram of the tailless CML driver in the embodiment of the application.

[0017] Figure 3Figure 1 is a schematic diagram of test results of the tailless CML driver in the embodiment of the present application, wherein A is a differential signal eye diagram when the output amplitude is maximum, B is a differential signal eye diagram when the output amplitude is minimum, C is the output pulse rising edge of the pulse generating unit when VSSH is 0 and 300 mV respectively, D is a curve of the node A / bias tube gate-source voltage / output swing and bias voltage, E is a curve of the DAC control code and output voltage, and F is a layout schematic diagram of the T-shaped coil.

[0018] Figure 4 Figure 4 is the optimal load resistance value after adjustment in the embodiment of the present application.

[0019] Figure 5 Figure 5 is the output signal (swing has been normalized) with channel reflection before and after impedance calibration in the embodiment of the present application.

[0020] Figure 6 Figure 6 is a work flow diagram of the impedance calibration loop in the embodiment of the present application.

[0021] Figure 7 Figure 7 is an output waveform diagram of the impedance calibration loop in the embodiment of the present application.

[0022] Figure 8 Figure 8 is a power consumption distribution diagram in the embodiment of the present application.

[0023] Figure 9 Figure 9 is a channel insertion loss and return loss curve for testing in the embodiment of the present application.

[0024] Figure 10 Figure 10 is a measured eye diagram in the embodiment of the present application, wherein (a) is an output 6 Gb / s Duobinary signal, an output signal eye diagram without FFE, (b) is an output 28 Gb / s NRZ signal, an output signal eye diagram with FFE, (c) is an output 56 Gb / s PAM4 signal, an output signal eye diagram with FFE, and (d) is an output 56 Gb / s PAM4 signal, an output signal eye diagram without FFE. DETAILED DESCRIPTION

[0025] In order to enable those skilled in the art to better understand the technical solutions of the present application, the technical solutions of the present application will be further described in detail below with reference to the accompanying drawings in the embodiments of the present application.

[0026] As Figure 1As shown, this embodiment of a multi-mode wired transmitter based on a CML driver and an impedance calibration loop includes a controller, an impedance calibration loop, N+1 analog-to-digital converters (DACs), and N-mode tailless CML drivers with digitally controlled loads connected to their outputs. The controller is connected to the control terminals of the impedance calibration loop and the N+1 DACs, respectively. The impedance calibration loop is connected to the adjustment control terminal of the digitally controlled load of the tailless CML driver. The N+1 DACs are connected to the tailless CML driver in each mode to adjust the signal swing and equalization strength of the tailless CML driver in each mode, where N is the number of modes. As an optional implementation, the multi-mode wired transmitter of this embodiment is a tri-mode (PAM4, NRZ, duobinary) transmitter. Its three 6-bit DACs are used to independently control the swing of signals A, B, and C in the three modes, and another DAC is used to control the post-tap driver to achieve high-resolution equalization coefficient adjustment. The digitally controlled load of the tailless CML driver is a digitally controlled 4-bit adjustable resistor, and the optimal control position is obtained through an impedance calibration loop.

[0027] like Figure 1 As shown, the impedance calibration loop of this embodiment includes a replica resistor, an off-chip reference resistor, a comparator, and calibration logic. The replica resistor is an adjustable resistor with one end connected to the power supply and the other end connected to the ground through the off-chip reference resistor. The intermediate connection point between the replica resistor and the off-chip reference resistor is connected to the positive input terminal of the comparator, and the negative terminal of the comparator is connected to the reference voltage. The output terminal of the comparator is connected to the input terminal of the calibration logic, and the output terminal of the calibration logic is connected to the adjustment control terminal of the replica resistor and the adjustment control terminal of the digital control load.

[0028] like Figure 1 As shown, the output end of the tailless CML driver of this embodiment is connected to the output end of the multi-mode wired transmitter through a common connection point, and the common connection point is connected to the power supply through an inductor and a digitally controlled load, and is grounded through an electrostatic protection circuit ESD.

[0029] like Figure 1 As shown, a T-type coil is connected in series between the output terminal and the common connection point of the tailless CML driver of this embodiment to improve the bandwidth.

[0030] like Figure 1 As shown, the input end of the tailless CML driver of this embodiment is connected to a mode selection module, a multiplexer and a data generator in sequence. The multiplexer is used to multiplex the data output by the data generator to generate a differential signal consisting of the upper data MSB and the lower data LSB. The mode selection module is used to send the differential signal to the tailless CML driver of the corresponding mode according to the set communication mode.

[0031] As shown in the figure, the multiplexer of the embodiment is a 32:8 multiplexer for multiplexing the 32-bit data outputted by the data generator to generate an 8-bit differential signal composed of 4-bit high data MSB and 4-bit low data LSB. Figure 1

[0032] In the embodiment, each mode of the tailless CML driver includes a main-tap driver and a back-tap driver, N of the N+1 analog-to-digital converters DAC are respectively connected to the bias tube gate of the main-tap driver of one tailless CML driver, and the remaining 1 analog-to-digital converter DAC is connected to the bias tube gate of the back-tap driver of all tailless CML drivers.

[0033] As the output stage of the transmitter, the tailless CML driver plays a decisive role in signal quality. Figure 2 The circuit principle diagram of the driver (main-tap driver and back-tap driver) of the tailless CML driver in the embodiment, the driver of the tailless CML driver is composed of a plurality of pulse generation units PGC sharing the same pair of loads, the pulse generation unit PGC is the basic unit of the driver, and the 4:1 multiplexing and the generation of the multi-level signal are realized by current modulation. Figure 2 In the embodiment, the node A on one side of which the drain of the bias tube M3 and the bias tube M4 are common is a positive branch, and the other side is a negative branch, the positive branch is sequentially connected by the adjustable resistor, the inductor L1, the transistor M1, and the bias tube M3 in series between the power supply VDDH and the ground GND, the middle node of the adjustable resistor and the inductor L1 is connected to the positive output end OUTP through an inductor L2, the gate of the bias tube M3 is connected with the bias voltage V BIAS The transistor M1 is controlled by the 0° clock signal CK0 and the 90° clock signal CK90, and the control circuit thereof includes three transistors connected in series between the power supply VDD and the lifted ground voltage VSSH, one gate of which is connected with the negative control signal DN, the gates of the other two transistors are connected with the 0° clock signal CK0, and the middle nodes of the above two transistors are connected to the gate of the transistor M1 through a transistor with the gate connected with the 90° clock signal CK90, and two transistors are connected in parallel between the gate of the transistor M1 and VSSH, one gate of which is connected with the 0° clock signal CK0 and the other gate of which is connected with the 90° clock signal CK90. The negative branch is sequentially connected by the adjustable resistor, the inductor, the transistor M2, and the bias tube M3 in series between the power supply VDDH and the ground GND, the middle node of the adjustable resistor and the inductor is connected to the positive output end OUTN through an inductor, and the gate of the bias tube M4 is connected with the bias voltage V BIAS ​Connected to the output of the analog-to-digital converter (DAC), transistor M2 is controlled by the 0° clock signal CK0 and the 90° clock signal CK90. Its control circuit is identical to the positive branch and will not be further described here. DP is the positive control signal. To mitigate driver current variations caused by channel length modulation, the tailless CML driver's bias voltage is asymmetrically designed to compensate for the linear distortion of the PAM4 signal.

[0034] Figure 3 Figure 1 is a diagram showing the test results of the tailless CML driver in this embodiment. A is the differential signal eye diagram when the output amplitude is maximum, B is the differential signal eye diagram when the output amplitude is minimum, C is the output pulse rising edge of the pulse generating unit when VSSH is 0 and 300mV, D is the relationship curve between node A / bias transistor gate-source voltage / output swing and bias voltage Vbias, E is the relationship curve between DAC control code and output voltage, and F is a schematic diagram of the T-coil layout. When the 6-bit analog-to-digital converter DAC output is in the range of 350mV to 850mV, the tailless CML driver can operate and achieve continuous adjustment of the differential output swing within the range of 70mV to 600mV. For example, when the 6-bit analog-to-digital converter DAC output is in the range of 350mV and 850mV, as shown in FIG. Figure 3 As shown in A and B. Figure 3 As shown in Figure C, the source voltage of all NMOS transistors is raised from ground (GND) to 300mV (VSSH), the pulse height is reduced, which helps M1 and M2 turn on faster (time reduced by 2.7ps), thereby reducing the output signal jitter. It is worth noting that when the bias voltage Vbias exceeds 720mV, as shown in Figure C, the source voltage of all NMOS transistors is raised from ground (GND) to 300mV (VSSH), the pulse height is reduced, which helps M1 and M2 turn on faster (time reduced by 2.7ps), thereby reducing the output signal jitter. Figure 3 As shown in D and E in the figure, the bottom transistors M3 and M4 enter the linear region. When the output swing increases to 600mV, the output PAM4 signal maintains a linearity (RLM) of 0.987, where VTH is the threshold voltage of the bias tube and the vertical axis is the voltage amplitude. The pulse generation unit PGC adopts a two-stage NAND-NOR structure to generate positive pulses at the gates of the driver transistors M1 and M2. In addition, in order to compensate for the influence of the parasitic capacitance at the output end on the bandwidth, a T-coil with a total inductance of 500pH (L1=350pH, L2=150pH) is deployed at the signal output end to achieve higher bandwidth. Figure 3 As shown in Figure F, the three ends of the T-coil are connected to the output end of the tailless CML driver, the load resistor, and the output PAD (pad) respectively.

[0035] like Figure 1As shown, the embodiment also includes a clock circuit, which includes an on-chip buffer, a first clock divider (‘ / 2’ represents), a duty cycle correction circuit DCC, a second clock divider (‘ / 2’ represents) and a third clock divider (‘ / 2’ represents) connected in sequence, the differential clock signal input from outside the chip is connected to the input end of the on-chip buffer, the duty cycle correction circuit DCC includes a quadrature four-phase clock output end for outputting a quadrature four-phase clock signal and a differential clock output end for outputting a differential clock signal, the quadrature four-phase clock output end is connected to the clock input end of the tailless CML driver, the differential clock output end is connected to the second clock divider and the third clock divider in sequence, the output end of the second clock divider is connected to the clock input end of the multiplexer, and the output end of the third clock divider is connected to the clock input end of the data generator.

[0036] As shown in Figure 1 The quadrature four-phase clock signal of the embodiment includes clock signals with phases of 0°, 90°, 180° and 270°, respectively.

[0037] As shown in Figure 1 The N-mode tailless CML driver of the embodiment is a three-mode tailless CML driver, which is respectively used for transmitting PAM4 encoded data, NRZ encoded data and dual binary encoded data.

[0038] The matching of the output resistance and the channel characteristic impedance directly affects the reflection of the terminal. In order to reduce the reflection, an impedance calibration loop is introduced in the embodiment to adapt to the change of the on-resistance of the driving transistor caused by the change of the output voltage and the fluctuation of the load resistance value caused by the process, voltage and temperature (PVT) variation. The impedance calibration loop is usually used in source series termination (SST) driver to adjust the impedance of the pull-up and pull-down branches respectively to ensure the matching. For CML driver, when the output is high, the output impedance of the driver is only composed of the load resistance; however, when the output is low, it is composed of the load resistance and the stacked resistance in parallel with the ground. As the gate voltage of M3 increases, its on-resistance gradually decreases. When the bias voltage Vbias=850mV, the on-resistance of M3 is about 390 ohms, which will significantly reduce the output impedance. This is also the inevitable price to achieve a wide range of adjustable output swing. In order to make up for this defect, the input control bit of the DAC is included in the loop in the embodiment. For different output voltages of the DAC, the load resistance control bit will adjust an offset appropriately to ensure that the output impedance is close to 50 ohms whether the output voltage is high or low.

[0039] Figure 4 For the optimal load resistance value adjusted in the embodiment, Figure 5 For the output signal (swing has been normalized) with channel reflection before and after impedance calibration in the embodiment.Figure 4 The middle black curve reflects the relationship between the bias tube drain-source resistance and the bias voltage. As the bias voltage is provided, the bias tube gradually enters the linear region, and the on-resistance gradually decreases. The red curve reflects the relationship between the total pull-down impedance, that is, the common-source common-gate structure resistance composed of the driving tube and the bias tube, and the bias voltage, which also decreases with the increase of the bias voltage. The blue curve reflects the relationship between the theoretical value of the load impedance and the bias voltage. When the load impedance is the theoretical value, the output impedance of the driver is closest to 50 ohms.

[0040] Figure 6 The figure is a working flowchart of the impedance calibration loop in the embodiment. Figure 7 The figure is an output waveform diagram of the impedance calibration loop in the embodiment. The detailed process of the impedance calibration loop includes: step 1: adjusting the load resistance to 50 ohms according to the comparator output; step 2: obtaining the offset according to the DAC control bit, and adjusting the load resistance to 50 ohms plus the offset. First, assign an initial value to the load resistance control bit, and then determine whether to increase or decrease the load resistance according to the comparator output. When the comparator continuously outputs the sequence 01010101, the first stage calibration is completed. In the second calibration stage, the load resistance is appropriately increased according to the control code of the analog-to-digital converter DAC to compensate for the change of the pull-down network impedance.

[0041] The transmitter proposed in the embodiment is taped out and tested using a 28nm CMOS process. The total chip area is 0.536 square millimeters, and the core circuit area (32:8 multiplexer and tailless CML driver) is 0.0144 square millimeters. The power consumption is 0.9pJ / bit in the PAM4 mode at 56Gb / s, the differential swing is 600mV, and the vertical eye diagram opening amplitude is 83mV. Figure 8 The figure is a power consumption distribution diagram in the embodiment. The clock is the power consumption of the clock circuit part, the driver represents the power consumption of the tailless CML driver, and the combiner represents the power consumption of the 32:8 multiplexer.

[0042] In order to verify the transmitter of the embodiment, a signal generator is used to generate a differential sinusoidal clock as the input of the chip through a pair of cables in the embodiment. Through the PCB channel board with an insertion loss of-6dB@14GHz and the SMA connector on the test board, an oscilloscope with a sampling rate of 160GS / s is used to observe the output waveform of the transmitter. A personal computer (PC) and a field programmable gate array (FPGA) board are used to control the registers on the chip. Figure 9 The figure is a channel insertion loss and return loss curve used for testing in the embodiment. Figure 10The eye diagrams measured in the embodiments of the present application, wherein (a) is the output 6 Gb / s Duobinary signal, the output signal eye diagram of the output 6 Gb / s Duobinary signal without FFE (the tap coefficients of the main tap driver and the post tap driver are fixed), (b) is the output 28 Gb / s NRZ signal, the output signal eye diagram of the output 28 Gb / s NRZ signal with FFE (the tap coefficients of the main tap driver and the post tap driver are automatically adjusted), (c) is the output 56 Gb / s PAM4 signal, the output signal eye diagram of the output 56 Gb / s PAM4 signal with FFE, and (d) is the output 56 Gb / s PAM4 signal, the output signal eye diagram of the output 56 Gb / s PAM4 signal without FFE. See Figure 10 It can be seen that when running at 28 Gbps in the NRZ mode, the vertical eye opening amplitude is 310 mV for the -6 dB insertion loss PCB channel with a feed-forward equalizer (FFE). When running at 56 Gbps in the PAM4 mode under the same channel, the eye height is 83 mV and has the function of an adjustable feed-forward equalizer FFE.

[0043] In summary, the three-mode (PAM4, NRZ, Duobinary) wired transmitter based on the CML driver and the impedance calibration loop in the embodiments solves the impedance mismatch problem caused by the tailless structure of the tailless CML driver by using the tailless CML driver and the CML impedance calibration scheme, and realizes high output swing while maintaining low power consumption. In addition, the adjustable feed-forward equalizer (FFE) is usually used to make the transmitter have appropriate equalization capability for channels with different losses, but implementing a wide-range and high-resolution adjustable FFE requires the designer to divide the driver into multiple parts, which will increase the power and area overhead of the re-timing and pre-driver, and the parasitic capacitance introduced by the additional wiring of the output node. In the embodiments, a 6-bit digital-to-analog converter DAC is designed to control the output amplitude of the differential tailless CML driver, so as to realize continuous adjustment of the strength of the adjustable feed-forward equalizer FFE composed of the main tap driver and the post tap driver in a wide range without driver segmentation. The transmitter proposed in the embodiments supports three modulation modes to adapt to different transmission rates and channel losses, and can also adjust the supported modulation modes as needed. The three-mode wired transmitter in the embodiments. The measured PAM4 data rate is as high as 56 Gb / s, the output swing is adjustable in the range of 70 mV to 600 mV, and fine adjustment of the FFE strength can be realized without additional driver segmentation. In order to solve the impedance mismatch problem of the tailless CML logic, a CML impedance calibration scheme is designed. The power efficiency of 0.9 pJ / bit is realized at the PAM4 rate of 56 Gb / s. The work of the embodiments verifies the feasibility of the impedance calibration design in high-speed differential transmitters and CML driver design, thereby realizing high speed and relatively high swing at the same time.

[0044] The above merely describes the preferred embodiments of the present application, and the protection scope of the present application is not limited to the above-described embodiments. Any technical solution falling within the concept of the present application shall fall within the protection scope of the present application. It should be noted that, for ordinary skilled persons in the art, some improvements and refinements without departing from the principles of the present application shall also be considered as falling within the protection scope of the present application.

Claims

1. A multi-mode wired transmitter based on a CML driver and an impedance calibration loop, characterized in that: The invention comprises a controller, an impedance calibration loop, N+1 analog-to-digital converters (DACs), and N modes of tailless CML drivers with output ends connected to digitally controlled loads. The controller is respectively connected to the control ends of the impedance calibration loop and the N+1 analog-to-digital converters (DACs). The impedance calibration loop is connected to the adjustment control end of the digitally controlled load of the tailless CML driver. The N+1 analog-to-digital converters (DACs) are respectively connected to the tailless CML driver in each mode to adjust the swing amplitude and equalization strength of the signal in each mode of the tailless CML driver. N is the number of modes.

2. The multi-mode wired transmitter based on a CML driver and an impedance calibration loop according to claim 1, wherein: The impedance calibration loop includes a replica resistor, an off-chip reference resistor, a comparator, and calibration logic. The replica resistor is an adjustable resistor with one end connected to the power supply and the other end connected to the ground through the off-chip reference resistor. The intermediate connection point between the replica resistor and the off-chip reference resistor is connected to the positive input terminal of the comparator, and the negative terminal of the comparator is connected to the reference voltage. The output terminal of the comparator is connected to the input terminal of the calibration logic, and the output terminal of the calibration logic is connected to the adjustment control terminal of the replica resistor and the adjustment control terminal of the digital control load.

3. The multi-mode wired transmitter based on a CML driver and an impedance calibration loop according to claim 2, wherein: The output end of the tailless CML driver is connected to the output end of the multi-mode wired transmitter via a common connection point. The common connection point is connected to a power supply via an inductor and a digitally controlled load and is grounded via an electrostatic protection circuit (ESD).

4. The multi-mode wired transmitter based on a CML driver and an impedance calibration loop according to claim 3, wherein: A T-type coil is connected in series between the output terminal and the common connection point of the tailless CML driver to increase bandwidth.

5. The multi-mode wired transmitter based on a CML driver and an impedance calibration loop according to claim 1, wherein: The input end of the tailless CML driver is connected to a mode selection module, a multiplexer, and a data generator in sequence. The multiplexer is used to multiplex the data output by the data generator to generate a differential signal consisting of the upper data MSB and the lower data LSB. The mode selection module is used to send the differential signal to the tailless CML driver of the corresponding mode according to the set communication mode.

6. The multi-mode wired transmitter based on a CML driver and an impedance calibration loop according to claim 5, wherein: The multiplexer is a 32:8 multiplexer, which is used to multiplex the 32-bit data output by the data generator to generate an 8-bit differential signal consisting of 4-bit high-order data MSB and 4-bit low-order data LSB.

7. The multi-mode wired transmitter based on a CML driver and an impedance calibration loop according to claim 1, wherein: Each mode of the tailless CML driver includes a main tap driver and a rear tap driver. N of the N+1 analog-to-digital converters DACs are respectively connected to the bias transistor gates of the main tap driver of one tailless CML driver, and the remaining analog-to-digital converter DAC is connected to the bias transistor gates of the rear tap drivers of all the tailless CML drivers.

8. The multi-mode wired transmitter based on a CML driver and an impedance calibration loop according to claim 5, wherein: The system further includes a clock circuit, which includes an on-chip buffer, a first clock divider, a duty cycle correction circuit DCC, a second clock divider, and a third clock divider connected in sequence. A differential clock signal input from outside the chip is connected to the input end of the on-chip buffer. The duty cycle correction circuit DCC includes an orthogonal four-phase clock output end for outputting an orthogonal four-phase clock signal and a differential clock output end for outputting a differential clock signal. The orthogonal four-phase clock output end is connected to the clock input end of the tailless CML driver. The differential clock output end is connected to the second clock divider and the third clock divider in sequence. The output end of the second clock divider is connected to the clock input end of the multiplexer, and the output end of the third clock divider is connected to the clock input end of the data generator.

9. The multi-mode wired transmitter based on a CML driver and an impedance calibration loop according to claim 8, wherein: The orthogonal four-phase clock signal includes clock signals with phases of 0°, 90°, 180° and 270° respectively.

10. The multi-mode wired transmitter based on a CML driver and an impedance calibration loop according to claim 1, wherein: The N modes of tailless CML drivers are three-mode tailless CML drivers, which are used to transmit PAM4 encoded data, NRZ encoded data and duobinary encoded data respectively.

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