Method and device for realizing synchronous cascading of Ethernet testers

Abstract

The invention provides a method and a device for realizing synchronous cascading of Ethernet testers, relates to the field of data transmission, and solves the technical problem of relatively low efficiency of synchronous cascading when a network environment changes in the prior art. The method comprises the following steps: receiving a cascade signal sent by superior equipment, and obtaining synchronous cascade information of the superior equipment; the synchronous cascading information comprises a cascading level, an upper-level total time delay compensation value and a lower-level time delay compensation value; according to the synchronization cascading information of the superior equipment, determining the synchronization cascading information of the current equipment; the cascading level of the current equipment is the next level of the cascading level of the upper-level equipment; the superior total time delay compensation value of the current equipment is the sum of the superior total time delay compensation value of the superior equipment and the subordinate time delay compensation value; and performing time delay compensation according to the synchronization cascade information of the current equipment. The method and the device are used in the synchronous cascading process of the Ethernet tester.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of data transmission, and in particular to a method and device for implementing synchronization cascading of Ethernet testers. BACKGROUND

[0002] In the synchronization cascading of Ethernet testers, accurate synchronization between master and slave testers is the key to ensuring the accuracy and reliability of test results. The traditional implementation method is to synchronize and delay compensate the Ethernet testers at each level according to the priority information and time delay compensation parameters of the Ethernet testers at each level set by humans in advance.

[0003] However, when the network environment changes, for example, the internet protocol (IP) address is re-allocated, or the physical location of the tester is changed, it is necessary to re-allocate the priority of each Ethernet tester and re-set the time delay compensation parameters. In large-scale networking, a large number of Ethernet testers are involved. Such operations are not only tedious, time-consuming and laborious, but also prone to errors in manual operation, which seriously affects the stability and operation efficiency of the entire test system, and greatly limits the flexible application and rapid deployment of large-scale networking of Ethernet testers. SUMMARY

[0004] The present application provides a method and device for implementing synchronization cascading of Ethernet testers, which solves the technical problem of low efficiency of synchronization cascading when the network environment changes in the prior art.

[0005] To achieve the above-mentioned purpose, the present application adopts the following technical solutions:

[0006] In a first aspect, a method for implementing synchronization cascading of Ethernet testers is provided, comprising: receiving a cascading signal sent by a superior device, and obtaining synchronization cascading information of the superior device; the synchronization cascading information comprising: a cascading level, a superior total time delay compensation value, and a subordinate time delay compensation value; according to the synchronization cascading information of the superior device, confirming synchronization cascading information of the current device; the cascading level of the current device being the next level of the cascading level of the superior device; the superior total time delay compensation value of the current device being the sum of the superior total time delay compensation value and the subordinate time delay compensation value of the superior device; and performing time delay compensation according to the synchronization cascading information of the current device.

[0007] Based on the technical solution, in the implementation method of Ethernet tester synchronization cascade provided in the application, the cascade level information of the upper device can be automatically obtained through the synchronization cascade information transmitted by the transmission path of the device, so as to update the cascade topology structure for accurate time delay compensation. The priority division and parameter configuration are not manually and tediously performed, the operation workload is greatly reduced, the probability of human operation failure is significantly reduced, and the flexibility, stability and operation efficiency of large-scale networking of the Ethernet tester are greatly improved.

[0008] In combination with the first aspect, in a possible implementation manner, the method further includes: according to the synchronization cascade information of the current device, sending a cascade signal to the lower-level device, so that the lower-level device obtains the synchronization cascade information of the current device.

[0009] In combination with the first aspect, in a possible implementation manner, the cascade signal is a pulse width modulation (PWM) signal; and the method of sending the cascade signal to the lower-level device according to the synchronization cascade information of the current device specifically includes: converting the synchronization cascade information of the current device into a corresponding PWM signal; the parameters of the PWM signal include a duty cycle; and generating and sending the PWM signal to the lower-level device.

[0010] In combination with the first aspect, in a possible implementation manner, the method of receiving the cascade signal sent by the upper device and obtaining the synchronization cascade information of the upper device specifically includes: receiving and decoding the PWM signal sent by the upper device, and restoring the synchronization cascade information of the upper device by detecting the duty cycle.

[0011] In combination with the first aspect, in a possible implementation manner, in the PWM signal, a preset target duty cycle represents a target signal value, and other duty cycles except the target duty cycle are null values.

[0012] In combination with the first aspect, in a possible implementation manner, before sending the cascade signal to the lower-level device, the method further includes: sending a first differential signal to the lower-level device; receiving a second differential signal returned by the lower-level device; and determining a lower-level time delay compensation value of the current device according to the first differential signal and the second differential signal.

[0013] In combination with the first aspect, in a possible implementation manner, the method of determining the lower-level time delay compensation value of the current device according to the first differential signal and the second differential signal specifically includes: calculating a two-way time delay according to the sending time stamp and the receiving time stamp of the first differential signal and the sending time stamp and the receiving time stamp of the second differential signal, and eliminating the clock deviation through a formula to obtain the lower-level time delay compensation value of the current device.

[0014] In combination with the first aspect, in a possible implementation manner, a calculation formula of the subordinate time delay compensation value of the current device is:

[0015]

[0016] T 1-recv is a receiving timestamp of the first differential signal; T 1-send is a sending timestamp of the first differential signal; T 2-recv is a receiving timestamp of the second differential signal; T 2-send is a sending timestamp of the second differential signal.

[0017] In a second aspect, an Ethernet tester is provided, including: a cascade information receiving module and a cascade information sending module; the cascade information receiving module is configured to receive a cascade signal sent by a superior device, and acquire synchronization cascade information of the superior device; the synchronization cascade information includes: a cascade level, a superior total time delay compensation value, and a subordinate time delay compensation value; the cascade information receiving module is further configured to confirm synchronization cascade information of a current device according to the synchronization cascade information of the superior device; the cascade level of the current device is a next level of the cascade level of the superior device; the superior total time delay compensation value of the current device is a sum of the superior total time delay compensation value and the subordinate time delay compensation value of the superior device; the cascade information receiving module is further configured to perform time delay compensation according to the synchronization cascade information of the current device; and the cascade information sending module is configured to send a cascade signal to a subordinate device according to the synchronization cascade information of the current device, so that the subordinate device acquires the synchronization cascade information of the current device.

[0018] In a third aspect, an implementation device of Ethernet tester synchronization cascade is provided, including: a communication unit and a processing unit; the communication unit is configured to receive a cascade signal sent by a superior device, and acquire synchronization cascade information of the superior device; the synchronization cascade information includes: a cascade level, a superior total time delay compensation value, and a subordinate time delay compensation value; the processing unit is configured to confirm synchronization cascade information of a current device according to the synchronization cascade information of the superior device; the cascade level of the current device is a next level of the cascade level of the superior device; the superior total time delay compensation value of the current device is a sum of the superior total time delay compensation value and the subordinate time delay compensation value of the superior device; and the processing unit is further configured to perform time delay compensation according to the synchronization cascade information of the current device.

[0019] In a fourth aspect, an implementation device of Ethernet tester synchronization cascade is provided, including: a processor and a storage medium; the storage medium includes instructions, and the processor is configured to run the instructions to implement the method described in the first aspect and any possible implementation manner of the first aspect. The implementation device of Ethernet tester synchronization cascade can be an electronic device, or a chip in an electronic device.

[0020] In a fifth aspect, the present application provides a system for implementing synchronization cascading of an Ethernet tester, comprising: a communication module and a processing module; the communication module is configured to receive a cascading signal sent by a superior device, and obtain synchronization cascading information of the superior device; the synchronization cascading information comprises: a cascading level, a superior total time delay compensation value, and a subordinate time delay compensation value; the processing module is configured to confirm synchronization cascading information of a current device according to the synchronization cascading information of the superior device; the cascading level of the current device is a next level of the cascading level of the superior device; the superior total time delay compensation value of the current device is a sum of the superior total time delay compensation value of the superior device and the subordinate time delay compensation value; and the processing module is further configured to perform time delay compensation according to the synchronization cascading information of the current device.

[0021] In a sixth aspect, the present application provides a computer readable storage medium, which stores instructions, and when the instructions are run on the device for implementing synchronization cascading of an Ethernet tester, the device for implementing synchronization cascading of an Ethernet tester performs the method described in the first aspect and any possible implementation manner of the first aspect.

[0022] In a seventh aspect, the present application provides a computer program product comprising instructions, and when the computer program product is run on the device for implementing synchronization cascading of an Ethernet tester, the device for implementing synchronization cascading of an Ethernet tester performs the method described in the first aspect and any possible implementation manner of the first aspect.

[0023] The present application provides a method and device for implementing synchronization cascading of an Ethernet tester, which can automatically obtain the cascading level information of a superior device through the synchronization cascading information transmitted by the transmission path of the device, so as to update the cascading topology structure and perform accurate time delay compensation. The priority division and parameter configuration are not manually and tediously performed, which greatly reduces the operation and maintenance workload, significantly reduces the probability of human operation errors, and greatly improves the flexibility, stability and operation and maintenance efficiency of large-scale networking of the Ethernet tester.

[0024] It should be understood that the description of technical features, technical solutions, advantages or similar language in this application does not imply that all features and advantages can be realized in any single embodiment. On the contrary, it can be understood that the description of a feature or advantage means that the specific technical feature, technical solution or advantage is included in at least one embodiment. Therefore, the description of technical features, technical solutions or advantages in this specification does not necessarily refer to the same embodiment. Further, the technical features, technical solutions and advantages described in this embodiment can be combined in any appropriate manner. Those skilled in the art will understand that the embodiments can be implemented without one or more specific technical features, technical solutions or advantages of the specific embodiments. In other embodiments, additional technical features and advantages can be identified in specific embodiments that do not embody all embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 A system architecture diagram of an Ethernet test system provided by an embodiment of the application;

[0026] Figure 2 A networking schematic diagram of synchronization cascade of an Ethernet tester provided by an embodiment of the application;

[0027] Figure 3 A flowchart schematic diagram of an implementation method of synchronization cascade of an Ethernet tester provided by an embodiment of the application;

[0028] Figure 4 A flowchart schematic diagram of an implementation method of synchronization cascade of an Ethernet tester provided by an embodiment of the application;

[0029] Figure 5 A flowchart schematic diagram of an implementation method of synchronization cascade of an Ethernet tester provided by an embodiment of the application;

[0030] Figure 6 An example diagram of a PWM encoding format principle provided by an embodiment of the application;

[0031] Figure 7 An example diagram of PWM encoding information transmission provided by an embodiment of the application;

[0032] Figure 8 A flowchart schematic diagram of an implementation method of synchronization cascade of an Ethernet tester provided by an embodiment of the application;

[0033] Figure 9 A flowchart schematic diagram of an implementation method of synchronization cascade of an Ethernet tester provided by an embodiment of the application;

[0034] Figure 10A schematic diagram of the cascade delay measurement principle of an Ethernet tester provided in an embodiment of the present application;

[0035] Figure 11 A flowchart of another method for implementing synchronous cascading of Ethernet testers provided in an embodiment of the present application;

[0036] Figure 12 A schematic structural diagram of a synchronous cascade device provided in an embodiment of the present application;

[0037] Figure 13 A schematic diagram of the hardware structure of a synchronous cascade device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] In the description of this application, unless otherwise specified, " / " means "or", for example, A / B can mean A or B. "And / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, "at least one" means one or more, and "a plurality" means two or more. Words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not limit them to be necessarily different.

[0039] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0040] The implementation method of Ethernet tester synchronous cascade provided in the embodiment of the present application can be applied to the Ethernet test system 100, such as Figure 1 As shown, the Ethernet test system 100 includes: a multi-stage Ethernet tester ( Figure 1 (Take device 101, device 102 and device 103 as an example).

[0041] The Ethernet testers are equipped with a cascade information sending module 104 , a cascade information receiving module 105 , a chip 106 and a central processing unit (CPU) 107 .

[0042] The cascade information sending module 104 in the Ethernet tester may be driven by the chip 106 via a serial / deserialization (serdes) driver.

[0043] Optionally, the chip 106 can be a complex programmable logic device (CPLD) or a field programmable gate array (FPGA) or other application specific integrated circuit (ASIC) chip.

[0044] The cascade information sending module 104 of the upper device can send a differential signal to the cascade information receiving module 105 of the lower device, and record the sending data and the receiving data. The cascade information receiving module 105 of the lower device can return a differential signal to the cascade information sending module 104 of the upper device, and record the sending data and the receiving data.

[0045] It is easy to understand that, for example, Figure 1 For example, the upper device 101 only uses the cascade information sending module 104, the lower device 103 only uses the cascade information receiving module 105, and the intermediate device 102 uses both. Among them, the upper device 101 can be a master tester, and the intermediate device 102 and the lower device 103 are both slave testers.

[0046] As described in the background, Figure 2 The networking schematic diagram of the conventional implementation method of the Ethernet tester synchronization cascade includes a master device A, an intermediate slave device B and a terminal slave device C. The conventional implementation method is to use a management personal computer (PC) to centrally manage the entire cascade network, bind the priority of each level of Ethernet tester with the IP address thereof, and perform synchronization delay compensation on each level of Ethernet tester according to the priority information and the time delay compensation parameters of each level of Ethernet tester artificially preset.

[0047] Compared with the conventional implementation method, the Ethernet test system 100 provided by the embodiment of the application can reduce the deployment of relay devices (switches or routers, etc.) and management PCs, and effectively reduce the networking cost.

[0048] To solve the technical problem of low efficiency of synchronization cascade in the prior art when the network environment changes, the embodiment of the application provides an implementation method of synchronization cascade of an Ethernet tester, which comprises the following steps: receiving a cascade signal sent by a superior device, and obtaining synchronization cascade information of the superior device; the synchronization cascade information comprises a cascade level, a superior total time delay compensation value and a subordinate time delay compensation value; according to the synchronization cascade information of the superior device, the synchronization cascade information of the current device is confirmed; the cascade level of the current device is the next level of the cascade level of the superior device; the superior total time delay compensation value of the current device is the sum of the superior total time delay compensation value and the subordinate time delay compensation value of the superior device; and according to the synchronization cascade information of the current device, time delay compensation is performed. Based on this, the cascade level information of the superior device can be automatically obtained through the synchronization cascade information transmitted by the transmission path of the device, so that the cascade topology structure is updated to perform accurate time delay compensation. Without manually and tediously performing priority division and parameter configuration, the operation and maintenance workload is greatly reduced, the probability of human operation errors is significantly reduced, and the flexibility, stability and operation and maintenance efficiency of large-scale networking of the Ethernet tester are greatly improved.

[0049] As shown in Figure 3 The implementation method of synchronization cascade of the Ethernet tester provided by the embodiment of the application comprises the following steps:

[0050] S301, receiving a cascade signal sent by a superior device, and obtaining synchronization cascade information of the superior device.

[0051] The synchronization cascade information comprises a cascade level, a superior total time delay compensation value and a subordinate time delay compensation value.

[0052] In some implementation modes, the synchronization cascade information can further comprise a device identifier of the superior device. The device identifier can be an IP address or other information that can uniquely identify the device.

[0053] For example, as shown in Table 1, taking a main device A, an intermediate level device B, an intermediate level device C and a terminal device D as an example. The format definition of cascade information transmission is that the data start flag is 0x5A5A5A5A, the data end flag is 0xEDEDEDED, each device sends the local IP address, the IP address of the previous device, the time delay value and the corresponding port of the next device, the cascade level of the device, the total time delay compensation information of the superior device to the next device, and the above information is filled with 0 if there is no such information.

[0054] Table 1: Format of cascade information transmission

[0055]

[0056]

[0057] In some implementation modes, the cascade signal can be a PWM signal.

[0058] S302, confirming the synchronization cascade information of the current device according to the synchronization cascade information of the upper-level device.

[0059] Wherein, the cascade level of the current device is the next level of the cascade level of the upper-level device, and the upper-level total time delay compensation value of the current device is the sum of the upper-level total time delay compensation value of the upper-level device and the lower-level time delay compensation value.

[0060] In some implementations, the cascade information is sequentially transmitted to the next level Ethernet tester in the cascade order, and the cascade information receiving module analyzes the preprocessed PWM signal. By accurately identifying the PWM encoding format in the signal, the cascade level information of the current tester is obtained.

[0061] In combination with the above example, the intermediate device B can obtain the IP address of the upper-level device as 192.168.0.A / 24 and the upper-level device as 0 level through the information sent by A, so that the current level is 1 by adding 1, the upper-level total time delay compensation is 10 ns, the lower-level time delay compensation is 20 ns, and the corresponding port y, and then the information is sent to the lower-level device C with the local IP address. The processing of device C is similar to that of device B, and finally the information is transmitted to the terminal device D. According to the information sent by C, it can be determined that the level of the local device is 3, and the accumulated time delay error is 60 ns, and the upper-level IP and port can also be determined. Therefore, the entire cascade topology is determined.

[0062] S303, performing time delay compensation according to the synchronization cascade information of the current device.

[0063] It should be noted that once the cascade topology of the network changes, such as adding a tester or removing part of the tester, the changed cascade information will be quickly transmitted to each tester. Each tester then repeats the above steps to automatically update its cascade level information, rebuild the cascade topology, and adjust the time delay compensation again to adapt to the dynamic changes of the network structure.

[0064] Based on the above technical solution, the Ethernet tester synchronization cascade implementation method provided by the present application can automatically obtain the cascade level information of the upper-level device through the synchronization cascade information transmitted by the transmission path of the device, thereby updating the cascade topology for accurate time delay compensation. Without manual and tedious priority division and parameter configuration, the operation and maintenance workload is greatly reduced, the probability of human operation errors is significantly reduced, and the flexibility, stability and operation and maintenance efficiency of large-scale networking of Ethernet testers are greatly improved.

[0065] In a possible implementation, in combination with Figure 3 For example, Figure 4As shown, the method further includes S401 implementation, which is specifically described as follows:

[0066] S401, according to the synchronization cascade information of the current device, a cascade signal is sent to the subordinate device to make the subordinate device obtain the synchronization cascade information of the current device.

[0067] Based on the above technical solution, the superior and subordinate devices in the cascade topology can automatically obtain the synchronization cascade information through the cascade signal, without manually and tediously dividing the priority and configuring the parameters, and the related parameters can be automatically updated and adjusted, which significantly improves the applicability of the system in various complex and dynamic application scenarios.

[0068] In a possible implementation manner, in combination with Figure 4 As shown, Figure 5 As shown, S401 can be implemented through S501 to S502, which are specifically described as follows:

[0069] S501, the synchronization cascade information of the current device is converted into a corresponding PWM signal.

[0070] The parameters of the PWM signal include the duty cycle.

[0071] In some implementation manners, in the PWM signal, the preset target duty cycle represents the target signal value, and the duty cycles other than the target duty cycle are null values.

[0072] S502, the PWM signal is generated and sent to the subordinate device.

[0073] It should be noted that when the Ethernet tester is used for large-scale networking cascade, the master tester first sends the PWM form cascade information containing the initial cascade information. Since the PWM signal is used for synchronization clock transmission and time delay measurement, the frequency, that is, the period, cannot be changed, and therefore the cascade information is encoded by changing the duty cycle of the PWM pulse without changing the frequency.

[0074] For example, Figure 6 As shown, the PWM signal with a duty cycle of 25% can represent 0, the PWM signal with a duty cycle of 75% can represent 1, and the PWM signals with other duty cycles are meaningless. Correspondingly, as shown, Figure 7 As shown, the duty cycle PWM signal can encode and transmit information.

[0075] Based on the above technical solution, the PWM signal can be in digital form from the processor to the controlled system signal, without the need for digital-to-analog conversion, because keeping the signal in digital form can minimize the noise impact and ensure the accuracy of information transmission.

[0076] In a possible implementation manner of the embodiments of the present application, in combination withFigure 5 As shown in Figure 8 S301 can be implemented by the following S801, which will be described in detail below.

[0077] S801, receive the PWM signal sent by the upper device and decode, and restore the synchronization cascade information of the upper device by detecting the duty cycle.

[0078] Based on the above technical solution, the PWM signal can be decoded to restore the synchronization cascade information of the upper device, without digital-to-analog conversion, which can reduce noise and ensure the accuracy of information transmission.

[0079] In a possible implementation of the embodiment of the present application, in combination with Figure 4 As shown in Figure 9 Before S401, the above method further includes S901 to S903, which will be described in detail below.

[0080] S901, send a first differential signal to a lower device.

[0081] S902, receive a second differential signal returned by the lower device.

[0082] S903, determine a lower time delay compensation value of the current device according to the first differential signal and the second differential signal.

[0083] In some implementations, as shown in Figure 10 The cascade information sending module is driven by a serdes driver after a CPLD or FPGA or other dedicated ASIC chip, and is transmitted to a lower tester through a TX differential signal, realizing clock synchronization between the testers. The transmitted signal is a differential 1 megahertz (MHz) PWM synchronization clock signal. At the same time, the lower device returns to the upper device through a RX differential signal, which is used for the sending module to measure the phase difference between the upper sending tester and the lower receiving tester, thereby realizing time delay measurement.

[0084] Based on the above technical solution, since the differential signal is obtained by comparing two signal values, common mode noise can be effectively eliminated, and the differential signal has strong resistance to external interference during transmission. Furthermore, the original signal can be restored more accurately through the differential signal, reducing signal distortion and error, and the accuracy of time delay measurement can be effectively increased.

[0085] In a possible implementation of the embodiment of the present application, in combination with Figure 9 As shown in Figure 11 S903 can be implemented by the following S1101, which will be described in detail below.

[0086] S1101, calculate the bidirectional time delay according to the sending timestamp and the receiving timestamp of the first differential signal and the sending timestamp and the receiving timestamp of the second differential signal, and eliminate the clock deviation through a formula to obtain the subordinate time delay compensation value of the current device.

[0087] In some implementations, the calculation formula of the subordinate time delay compensation value of the current device is:

[0088]

[0089] T 1-recv is the receiving timestamp of the first differential signal; T 1-send is the sending timestamp of the first differential signal; T 2-recv is the receiving timestamp of the second differential signal; T 2-send is the sending timestamp of the second differential signal.

[0090] Based on the above technical solution, the difference between the bidirectional timestamps in the formula offsets the clock asynchronization error between the first device and the second device, solves the two core problems of clock deviation elimination and internal time delay deduction in bidirectional time delay measurement, has the advantages of high precision and low implementation complexity, and is especially suitable for communication systems with strict requirements on real-time performance and resource efficiency.

[0091] In summary, due to the wireless communication being extremely susceptible to environmental factors such as signal shielding and electromagnetic interference, the signal stability is poor, which may cause inaccurate cascade information acquisition. Moreover, the power consumption of wireless communication is relatively high, which is not suitable for some Ethernet testers that need to work continuously for a long time and have strict power consumption restrictions. In addition, wireless communication requires additional wireless communication modules and complex protocol stack support, which undoubtedly increases the cost of the device and the overall complexity of the system. Compared with the above, the scheme of the present application utilizes the cascade information of the device to transmit the cascade information in the form of PWM, which has the advantages of high stability, low cost, low power consumption, and no need for additional complex communication modules, and is more suitable for the actual application requirements of large-scale networking of Ethernet testers.

[0092] The above describes the scheme of the embodiments of the present application mainly from the perspective of device implementation. It can be understood that, in order to implement the above functions, each device, for example, the implementation apparatus of the Ethernet tester synchronous cascade, comprises at least one of the corresponding hardware structure and software module for executing each function. Those skilled in the art should easily realize that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a certain function is implemented in the form of hardware or computer software driving hardware depends on the specific application of the technical scheme and the design constraint conditions. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0093] The embodiments of the present application can divide the functional units of the implementation apparatus of the Ethernet tester synchronous cascade according to the above method examples. For example, each functional unit can be divided according to each function, or two or more functions can be integrated in one processing unit. The above integrated unit can be implemented in the form of hardware or software functional unit. It should be noted that the division of units in the embodiments of the present application is illustrative, and is only a logical function division. In actual implementation, there can be another division method.

[0094] In the case of using integrated units, Figure 12 A possible structure schematic diagram of the implementation apparatus of the Ethernet tester synchronous cascade (denoted as synchronous cascade apparatus 1200) involved in the above embodiments is shown, which comprises a processing unit 1201 and a communication unit 1202, and can further comprise a storage unit 1203. Figure 12 The shown structure schematic diagram can be used to illustrate the structure of the implementation apparatus of the Ethernet tester synchronous cascade involved in the above embodiments.

[0095] When Figure 12 When the shown structure schematic diagram is used to illustrate the structure of the implementation apparatus of the Ethernet tester synchronous cascade involved in the above embodiments, the processing unit 1201 is used to control and manage the actions of the implementation apparatus of the Ethernet tester synchronous cascade, the communication unit 1202 is used for the communication between the implementation apparatus of the Ethernet tester synchronous cascade and other devices, and the storage unit 1203 is used to store the program code and data of the implementation apparatus of the Ethernet tester synchronous cascade.

[0096] For example, the communication unit 1202, the processing unit 1201 and the storage unit 1203;

[0097] The communication unit 1202 is configured to receive a cascade signal sent by the upper-level device, and acquire synchronization cascade information of the upper-level device; the synchronization cascade information comprises a cascade level, an upper-level total time delay compensation value, and a lower-level time delay compensation value.

[0098] The processing unit 1201 is configured to confirm synchronization cascade information of the current device according to the synchronization cascade information of the upper-level device; the cascade level of the current device is a next level of the cascade level of the upper-level device; and the upper-level total time delay compensation value of the current device is a sum of the upper-level total time delay compensation value of the upper-level device and the lower-level time delay compensation value.

[0099] The processing unit 1201 is further configured to perform time delay compensation according to the synchronization cascade information of the current device.

[0100] In a possible implementation, the communication unit 1202 is further configured to send, to the lower-level device, a cascade signal according to the synchronization cascade information of the current device, so that the lower-level device acquires the synchronization cascade information of the current device.

[0101] In a possible implementation, the cascade signal is a PWM signal; the communication unit 1202 is specifically configured to convert the synchronization cascade information of the current device into a corresponding PWM signal; a parameter of the PWM signal comprises a duty cycle; and the PWM signal is generated and sent to the lower-level device.

[0102] In a possible implementation, the communication unit 1202 is specifically configured to receive and decode a PWM signal sent by the upper-level device, and restore the synchronization cascade information of the upper-level device by detecting the duty cycle.

[0103] In a possible implementation, before sending the cascade signal to the lower-level device, the communication unit 1202 is further configured to send a first differential signal to the lower-level device; the communication unit 1202 is further configured to receive a second differential signal returned by the lower-level device; and the processing unit 1201 is further configured to determine the lower-level time delay compensation value of the current device according to the first differential signal and the second differential signal.

[0104] In a possible implementation, the processing unit 1201 is specifically configured to calculate a two-way time delay according to a sending time stamp and a receiving time stamp of the first differential signal and a sending time stamp and a receiving time stamp of the second differential signal, and eliminate clock bias through a formula to obtain the lower-level time delay compensation value of the current device.

[0105] In a possible implementation, the control information field in the standard format comprises a type identifier field; when the first format is the standard format and the second format is a custom frame format, the storage unit 1203 is specifically configured to store data in a data packet after receiving the data packet containing the type identifier field used to identify the start of data, until receiving a data packet containing a type identifier field used to identify the end of data.

[0106] In a possible implementation, the processing unit 1201 is specifically configured to encapsulate the data in at least one data packet received between the data packet containing the type identification field for identifying the start of data and the data packet containing the type identification field for identifying the end of data to obtain a data packet in a self-defined frame format; and the frame length indication field of the data packet is the sum of the lengths of the data in the data packet containing the type identification field for identifying the start of data and the data packet containing the type identification field for identifying the end of data.

[0107] In a possible implementation, the storage unit 1203 is specifically configured to monitor the capacity of the buffer area in real time; when the capacity of the buffer area is greater than the length of the data in the data packet, the data in the data packet is stored at the tail of the queue of the buffer area; and when the capacity of the buffer area is less than the length of the data in the data packet, the receiving of the data packet is suspended until the capacity of the buffer area is greater than the length of the data in the data packet, and then the storage of the data in the data packet is continued.

[0108] In a possible implementation, the buffer area includes two physically isolated main buffer areas and slave buffer areas; and the storage unit 1203 is further configured to receive data through the main buffer areas and read the stored data through the slave buffer areas; and when the main buffer areas are full or the slave buffer areas are empty, the roles of the two buffer areas are exchanged.

[0109] The processing unit 1201 can be a processor or a controller, and the communication unit 1202 can be a communication interface, a transceiver, a transceiver, a transceiver circuit, a transceiver device, or the like. The communication interface is a general term and can include one or more interfaces. The storage unit 1203 can be a memory. When the synchronous cascading device 1200 is a chip, the processing unit 1201 can be a processor or a controller, and the communication unit 1202 can be an input interface and / or an output interface, a pin or a circuit, or the like. The storage unit 1203 can be a storage unit (for example, a register, a cache, or the like) in the chip, or can be a storage unit (for example, a read-only memory (ROM), a random access memory (RAM), or the like) located outside the chip.

[0110] The communication unit can also be referred to as a transceiver unit. The antenna and the control circuit with the transceiver function in the synchronization cascading device 1200 can be regarded as a communication unit 1202 of the synchronization cascading device 1200, and the processor with the processing function can be regarded as a processing unit 1201 of the synchronization cascading device 1200. Optionally, the device for realizing the receiving function in the communication unit 1202 can be regarded as a communication unit, the communication unit is configured to perform the receiving steps in the embodiments of the present application, and the communication unit can be a receiver, a receiver, a receiving circuit, etc. The device for realizing the sending function in the communication unit 1202 can be regarded as a sending unit, the sending unit is configured to perform the sending steps in the embodiments of the present application, and the sending unit can be a transmitter, a sender, a sending circuit, etc.

[0111] Figure 12 The integrated units in the above embodiments can be stored in a computer readable storage medium if the integrated units are realized in the form of software function modules and sold or used as independent products. Based on such understanding, the technical solutions of the embodiments of the present application or the part of the technical solutions that make essential contributions to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the methods described in the embodiments of the present application. The storage medium for storing the computer software product includes a U disk, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk or an optical disk, and various media that can store program codes.

[0112] Figure 12 The units in the above embodiments can also be referred to as modules, for example, the processing unit can be referred to as a processing module.

[0113] The embodiments of the present application also provide a hardware structure schematic diagram of an implementation device (referred to as a synchronization cascading device 1300) of an Ethernet tester synchronization cascade, which is shown in Figure 13 The synchronization cascading device 1300 includes a processor 1301, and optionally further includes a memory 1302 connected with the processor 1301.

[0114] In the first possible implementation manner, referring to Figure 13The synchronization cascading apparatus 1300 further includes a transceiver 1303. The processor 1301, the memory 1302 and the transceiver 1303 are connected through a bus. The transceiver 1303 is configured to communicate with other devices or communication networks. Optionally, the transceiver 1303 can include a transmitter and a receiver. The device in the transceiver 1303 for realizing the receiving function can be regarded as a receiver, and the receiver is configured to perform the steps of receiving in the embodiments of the present application. The device in the transceiver 1303 for realizing the transmitting function can be regarded as a transmitter, and the transmitter is configured to perform the steps of transmitting in the embodiments of the present application.

[0115] Based on the first possible implementation manner, Figure 13 The structural schematic diagram shown can be used to show the structure of the implementation apparatus of the Ethernet tester synchronization cascading.

[0116] In the implementation process, Figure 13 The system chip in the implementation apparatus of the Ethernet tester synchronization cascading can also be shown. In this case, the actions performed by the implementation apparatus of the Ethernet tester synchronization cascading can be realized by the system chip, and the specific actions can be referred to the above and will not be described here.

[0117] In the implementation process, each step in the method provided by the embodiments can be completed by the integrated logic circuit of the hardware in the processor or the instructions in the software form. The steps of the method disclosed by the embodiments of the present application can be directly embodied as the execution completed by the hardware processor, or the execution completed by the combination of the hardware and the software modules in the processor.

[0118] The processor in the present application can include, but is not limited to, at least one of the following: a central processing unit (CPU), a microprocessor, a digital signal processor (DSP), a micro controller unit (MCU), or an artificial intelligence processor, and the like various computing devices running software, each of which can include one or more cores for executing software instructions to perform operations or processing. The processor can be a separate semiconductor chip, or can be integrated with other circuits as a semiconductor chip, for example, can be integrated with other circuits (such as coding and decoding circuits, hardware acceleration circuits, or various bus and interface circuits) to form a SoC (system on chip), or can be integrated as a built-in processor in an ASIC. The ASIC integrated with the processor can be packaged separately or packaged together with other circuits. In addition to including cores for executing software instructions to perform operations or processing, the processor can further include necessary hardware accelerators, such as field programmable gate arrays (FPGAs), PLDs (programmable logic devices), or logic circuits implementing special logic operations.

[0119] The memory in the embodiments of the present application can include at least one of the following types: read-only memory (ROM) or other types of static storage devices that can store static information and instructions, random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, and can also be electrically erasable programmable read-only memory (EEPROM). In some scenarios, the memory can also be a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage medium or other magnetic storage device, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and capable of being accessed by a computer, but not limited thereto.

[0120] The embodiments of the present application also provide a computer readable storage medium including instructions, which, when executed on a computer, cause the computer to perform any of the above methods.

[0121] The embodiments of the present application also provide a computer program product including instructions, which, when executed on a computer, cause the computer to perform any of the above methods.

[0122] The embodiment of the present application further provides a chip, which comprises a processor and an interface circuit, the interface circuit is coupled with the processor, the processor is used for running computer programs or instructions to realize the method described above, and the interface circuit is used for communicating with other modules outside the chip.

[0123] In the above embodiments, the implementation can be achieved by software, hardware, firmware or any combination thereof, entirely or partially. When implemented by software, the implementation can be achieved in the form of a computer program product, entirely or partially. The computer program product comprises one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the flow or function described in the embodiments of the present application is generated, entirely or partially. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable devices. The computer instructions can be stored in a computer readable storage medium or transferred from one computer readable storage medium to another, for example, the computer instructions can be transferred from one website, computer, server or data center to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode. The computer readable storage medium can be any available medium that can be accessed by a computer or data storage device including one or more servers, data centers, etc. integrated with the medium. The available medium can be magnetic medium (such as floppy disk, hard disk, magnetic tape), optical medium (such as DVD), or semiconductor medium (such as solid state disk (SSD)) and the like.

[0124] Although the present application is described herein in conjunction with various embodiments, other variations of the disclosed embodiments can be understood and implemented by those skilled in the art with reference to the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "one" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. Some measures described in mutually different dependent claims can be combined and produce a good result.

[0125] Although the present application has been described in connection with certain specific features and embodiments thereof, it is to be understood that it is intended to cover all modifications and variations of this application which are within the scope of the appended claims and their equivalents. Accordingly, the description and drawings are to be regarded as illustrative in nature and not as restrictive. It is intended that all such modifications and variations are included within the scope of the present application as defined by the following claims and their equivalents.

Claims

1. A method for realizing synchronous cascading of Ethernet testers, characterized in that: include: Receive a cascade signal sent by an upper-level device and obtain synchronous cascade information of the upper-level device; The synchronous cascade information includes: cascade level, upper level total delay compensation value, and lower level delay compensation value; Confirming the synchronization cascade information of the current device according to the synchronization cascade information of the upper device; the cascade level of the current device is the next lower cascade level of the upper device; the upper total delay compensation value of the current device is the sum of the upper total delay compensation value of the upper device and the lower delay compensation value; Delay compensation is performed according to the synchronization cascade information of the current device.

2. The method according to claim 1, characterized in that Also includes: According to the synchronous cascade information of the current device, a cascade signal is sent to a subordinate device, so that the subordinate device obtains the synchronous cascade information of the current device.

3. The method according to claim 2, characterized in that The cascade signal is a pulse width modulation (PWM) signal; and sending the cascade signal to the downstream device according to the synchronous cascade information of the current device includes: Converting the synchronous cascade information of the current device into a corresponding PWM signal; the parameters of the PWM signal include a duty cycle; Generate and send the PWM signal to the downstream device.

4. The method according to claim 3, characterized in that The receiving a cascade signal sent by an upper-level device and obtaining synchronous cascade information of the upper-level device includes: The PWM signal sent by the upper-level device is received and decoded, and the synchronous cascade information of the upper-level device is restored by detecting the duty cycle.

5. The method according to claim 4, characterized in that In the PWM signal, a preset target duty cycle represents a target signal value, and other duty cycles except the target duty cycle are null values.

6. The method according to claim 2, characterized in that Before sending the cascade signal to the lower-level device, the method further includes: Sending a first differential signal to the lower-level device; receiving a second differential signal returned by the lower-level device; Determine a lower-level delay compensation value of the current device according to the first differential signal and the second differential signal.

7. The method according to claim 6, characterized in that The determining, according to the first differential signal and the second differential signal, a lower-level delay compensation value of the current device includes: The two-way delay is calculated based on the sending timestamp and receiving timestamp of the first differential signal and the sending timestamp and receiving timestamp of the second differential signal, and the clock deviation is eliminated through a formula to obtain the lower-level delay compensation value of the current device.

8. The method according to claim 7, characterized in that The calculation formula for the lower-level delay compensation value of the current device is: T 1-recv is the receiving timestamp of the first differential signal; T 1-send is the sending timestamp of the first differential signal; T 2-recv is the receiving timestamp of the second differential signal; T 2-send is the sending timestamp of the second differential signal.

9. An Ethernet tester, characterized in that: include: Cascade information receiving module and cascade information sending module; The cascade information receiving module is used to receive the cascade signal sent by the upper-level device and obtain the synchronous cascade information of the upper-level device; The synchronous cascade information includes: cascade level, upper level total delay compensation value, and lower level delay compensation value; The cascade information receiving module is further configured to confirm the synchronous cascade information of the current device based on the synchronous cascade information of the upper device; the cascade level of the current device is one level lower than the cascade level of the upper device; and the upper total delay compensation value of the current device is the sum of the upper total delay compensation value of the upper device and the lower delay compensation value; The cascade information receiving module is further configured to perform delay compensation according to the synchronous cascade information of the current device; The cascade information sending module is configured to send a cascade signal to a lower-level device according to the synchronous cascade information of the current device, so that the lower-level device acquires the synchronous cascade information of the current device.

10. A device for realizing synchronous cascade of Ethernet testers, characterized in that: The device includes: a communication unit and a processing unit; The communication unit is configured to receive a cascade signal sent by an upper-level device and obtain synchronous cascade information of the upper-level device; the synchronous cascade information includes: a cascade level, an upper-level total delay compensation value, and a lower-level delay compensation value; The processing unit is configured to confirm the synchronization cascade information of the current device based on the synchronization cascade information of the upper-level device; the cascade level of the current device is one level lower than the cascade level of the upper-level device; and the upper-level total delay compensation value of the current device is the sum of the upper-level total delay compensation value and the lower-level delay compensation value of the upper-level device; The processing unit is further configured to perform delay compensation according to the synchronization cascade information of the current device.

Images