Adaptable memory system with multiple chiplets

Abstract

The invention relates to an adaptable memory system with a plurality of chiplets. An apparatus is provided that includes a silicon wafer and a plurality of memory dies. The silicon wafer includes a plurality of control dies, each control die having a first bond pad on a first surface. The plurality of memory dies each have a second bond pad on a second surface facing the first surface of the control die. The second bond pad of each memory die is bonded to a corresponding first bond pad on the first surface of the memory control circuit.

Description

BACKGROUND

[0001] Semiconductor memory is widely used in various electronic devices such as cellular phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid state drives, non-mobile computing devices, and other devices. Semiconductor memory can include non-volatile memory or volatile memory. Non-volatile memory allows storage and retention of information even when not connected to a power source (e.g., a battery).

[0002] One type of non-volatile memory has strings of non-volatile memory cells with select transistors at each end of the string. Generally, such strings are referred to as NAND strings, and a non-volatile memory chip or die in which such NAND strings are formed can be referred to as a NAND chip or die.

[0003] In some examples, a silicon wafer including a plurality of non-volatile memory dies (e.g., NAND dies) can be bonded to another silicon wafer including an equal number of dies that include logic circuitry (e.g., control dies, logic dies, or application specific integrated circuits (ASICs)). The bonded wafers are then scribed (singulated) into individual assemblies (integrated memory assemblies), each assembly including a memory die and a control die. Because a defect in either the memory die or the control die in such an arrangement can result in a failed integrated memory assembly, the failure rate can be undesirably high. BRIEF DESCRIPTION OF DRAWINGS

[0004] Like-numbered elements refer to common parts throughout the several views.

[0005] FIG. 1 is a functional block diagram of a memory device.

[0006] FIGS. 2A-2B is a block diagram depicting an embodiment of a memory system.

[0007] FIG. 3 is a perspective view of a portion of one embodiment of a monolithic three-dimensional memory structure.

[0008] FIGS. 4A-4C An example of a non-volatile memory structure is shown.

[0009] FIG. 5 An example of wafer-to-wafer bonding is shown.

[0010] FIGS. 6A-6B An example of a die-to-wafer bonding to form an integrated memory assembly is illustrated.

[0011] FIGS. 7A-7B Another example of a die-to-wafer bonding to form an integrated memory assembly is illustrated.

[0012] FIGS. 8A-8B Another example of die-to-wafer bonding to form an integrated memory assembly is illustrated.

[0013] FIGS. 9A-9B Another example of die-to-wafer bonding to form an integrated memory assembly is illustrated.

[0014] FIGS. 10A-10B Another example of die-to-wafer bonding to form an integrated memory assembly is illustrated.

[0015] FIGS. 11A-11B Examples of control die bond pads and corresponding bond pads on memory die are illustrated.

[0016] FIG. 12 An example of an integrated memory assembly is illustrated.

[0017] FIG. 13 An example of a probe pad formed in a scribe region between memory dies in a silicon wafer is illustrated.

[0018] FIGS. 14A-14D An example of scribing a silicon wafer to separate individual memory dies is illustrated.

[0019] FIG. 15 An example of fabricating an integrated memory assembly using die-to-wafer bonding is illustrated.

[0020] FIG. 16 An example of a method including bonding memory dies to control dies located in a silicon wafer is illustrated.

[0021] FIG. 17 An example of a method including determining whether a control die is defective / non-defective is illustrated. DETAILED DESCRIPTION

[0022] Techniques are provided for fabricating integrated memory assemblies in a manner that produces relatively few defective assemblies and with a high degree of configurability (e.g., integrated memory assemblies can be readily configured with different capacities and / or characteristics). Examples of the present techniques include individually bonding memory dies or dies to a memory control circuit wafer in a manner that can be referred to as die-to-wafer bonding. Die-to-wafer bonding allows for selection of the number of memory dies and the characteristics of individual memory dies (e.g., only defect-free memory dies with appropriate capacities) as compared to wafer-to-wafer bonding in which the relative dies of an entire wafer are aligned and bonded. The control die can have a plurality of slots, each configured to interface with a memory die. Some or all of the slots can be occupied by memory dies, which can be identical or can have different characteristics to give a high degree of configurability.

[0023] Testing the memory dies prior to die-to-wafer bonding can ensure that only non-defective memory dies are used, so that no good control dies are wasted due to bonding with defective memory dies. The testing of the memory dies can include probing using probe pads provided on the surface of the memory wafer. For example, such probe pads can be located in the scribe region of the memory wafer, so that the probe pads can be provided without adding to the memory die area (e.g., the probe pads only occupy space in the scribe region that is removed during scribing prior to die-to-wafer bonding).

[0024] FIG. 1 is a functional block diagram of an example memory system 100. FIG. 1 The components depicted in are electronic circuits. The memory system 100 includes one or more memory dies 108. The one or more memory dies 108 can be full memory dies or partial memory dies. In one embodiment, each memory die 108 includes a memory structure 126, a control circuit 110, and a read / write circuit 128. The memory structure 126 is addressable by word lines via a row decoder 124 and by bit lines via a column decoder 132. The read / write / erase circuit 128 includes a plurality of sense blocks 150 including SB1, SB2,..., SBp (sense circuitry) and allows a page of memory cells to be read or programmed in parallel. In addition, many strings of memory cells can be erased in parallel.

[0025] In some systems, the controller 122 is included in the same package as the one or more memory dies 108 (e.g., a removable memory card). However, in other systems, the controller can be separate from the memory dies 108. In some embodiments, the controller will be located on a different die than the memory dies 108. In some embodiments, one controller 122 will communicate with multiple memory dies 108. In other embodiments, each memory die 108 has its own controller. Commands and data are transferred between the host 140 and the controller 122 via a data bus 120, and between the controller 122 and the one or more memory dies 108 via lines 118. In one embodiment, the memory dies 108 include a set of input and / or output (I / O) pins connected to the lines 118.

[0026] The control circuit 110 cooperates with the read / write circuits 128 to perform memory operations (e.g., write, read, erase, etc.) on the memory structure 126, and includes a state machine 112, an on-chip address decoder 114, and a power control circuit 116. In one embodiment, the control circuit 110 includes a buffer such as a register, a ROM fuses, and other storage devices for storing default values such as base voltages and other parameters.

[0027] On-chip address decoders 114 provide an address interface between the addresses used by the host 140 or controller 122 to the hardware addresses used by decoders 124 and decoders 132. Power control circuitry 116 controls the power and voltages provided to the word lines, bit lines, and select lines during memory operations. In one embodiment, the power control circuitry 116 includes voltage circuitry. The power control circuitry 116 includes charge pumps 117 for generating voltages. The sense blocks include bit line drivers. In one embodiment, the power control circuitry 116 is executed under the control of the state machine 112.

[0028] The state machine 112 and / or controller 122 (or equivalent functional circuitry) in combination with all or a subset of the other circuitry depicted in FIG. 1 The control circuitry can include hardware only or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is one example of control circuitry. The control circuitry can include a processor, a PGA (programmable gate array), an FPGA (field programmable gate array), an ASIC (application specific integrated circuit), an integrated circuit, or other type of circuitry.

[0029] The (on-chip or off-chip) controller 122 (in one embodiment a circuit) can include one or more processors 122c, ROM 122a, RAM 122b, a memory interface (MI) 122d, and a host interface (HI) 122e, all interconnected. The storage (ROM 122a, RAM 122b) stores code (software) such as a set of instructions (including firmware) and the one or more processors 122c are operable to execute the set of instructions to provide the functions described herein. Alternatively or additionally, the one or more processors 122c can access code from storage in the memory structure, such as a reserved area of memory cells connected to one or more word lines. The RAM 122b can be used to store data for the controller 122, including cached program data (discussed below). The memory interface 122d in communication with the ROM 122a, RAM 122b, and processors 122c is circuitry that provides an electrical interface between the controller 122 and the one or more memory dies 108. For example, the memory interface 122d can change the format or timing of signals, provide a buffer, isolate from surges, latch I / O, etc. The one or more processors 122c can issue commands to the control circuitry 110 (or another component of the memory die 108) through the memory interface 122d. The host interface 122e provides an electrical interface to the host 140 data bus 120 to receive commands, addresses, and / or data from the host 140 to provide data and / or status to the host 140.

[0030] In one embodiment, the memory structure 126 includes a three-dimensional memory array of non-volatile memory cells, with multiple levels of memory formed over a single substrate such as a wafer. The memory structure can include any type of non-volatile memory monolithically formed in one or more physical layers of an array of memory cells, with active regions disposed over a silicon (or other type) substrate. In one example, the non-volatile memory cells include vertical NAND strings with charge-trapping material.

[0031] In another embodiment, the memory structure 126 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells with floating gates. Other types of memory cells (e.g., NOR type flash memory) can also be used. The exact type of memory array architecture or memory cell included in the memory structure 126 is not limited to the examples described above.

[0032] FIG. 2A is a block diagram of an example memory system 100, depicting more details of one embodiment of the controller 122. FIG. 2A The controller in is a flash memory controller, but it should be noted that the non-volatile memory die 108 is not limited to flash. Thus, the controller 122 is not limited to the example of a flash memory controller. As used herein, a flash memory controller is a device that manages data stored on flash memory and communicates with a host such as a computer or electronic device. In addition to the specific functions described herein, a flash memory controller can have various functions. For example, a flash memory controller can format the flash memory to ensure proper operation of the memory, map out bad flash memory cells, and allocate spare memory cells to replace future failed cells. Some of the spare cells can be used to hold firmware to operate the flash memory controller and implement other features. In operation, when a host needs to read data from or write data to the flash memory, it will communicate with the flash memory controller. If the host provides a logical address to read / write data, the flash memory controller can convert the logical address received from the host to a physical address in the flash memory. (Alternatively, the host can provide a physical address). The flash memory controller can also perform various memory management functions such as, but not limited to, wear leveling (allocating writes to avoid wearing out particular memory blocks that would otherwise be repeatedly written to) and garbage collection (after a block is full, only valid data pages are moved to a new block so the full block can be erased and reused).

[0033] The interface between the controller 122 and the non-volatile memory die 108 can be any suitable flash memory interface, such as switch mode 200, 400, or 800. In one embodiment, the memory system 100 can be a card-based system, such as a secure digital (SD) or micro secure digital (micro-SD) card. In alternative embodiments, the memory system 100 can be part of an embedded memory system. For example, the flash memory can be embedded in the host. In other examples, the memory system 100 can be in the form of a solid-state drive (SSD).

[0034] In some embodiments, the memory system 100 includes a single channel between the controller 122 and the non-volatile memory die 108. The subject matter described herein is not limited to having a single memory channel. For example, in some memory system architectures, there are 2, 4, 8, or more channels between the controller and the memory die, depending on the capabilities of the controller. In any of the embodiments described herein, even if a single channel is shown in the figures, there can be more than a single channel between the controller and the memory die.

[0035] like FIG. 2A As depicted in FIG, the controller 122 includes a front-end module 208 that interacts with a host, a back-end module 210 that interacts with one or more non-volatile memory dies 108, and various other modules that perform functions that will now be described in detail.

[0036] FIG. 2A The components of the controller 122 depicted in the drawings may take the form of, for example, packaged functional hardware units (e.g., circuits) designed for use with other components, portions of program code (e.g., software or firmware) that can be executed by a specific function (micro)processor or processing circuit that generally performs the related functions, or independent hardware or software components that interact with a larger system. For example, each module may include an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a circuit, a digital logic circuit, an analog circuit, a combination of discrete circuits, gates, or any other type of hardware, or a combination thereof. Alternatively or in addition, each module may include software stored in a processor-readable device (e.g., a memory) to program the processor to cause the controller 122 to perform the functions described herein. FIG. 2A The architecture depicted in this example may (or may not) use FIG. 1 One exemplary implementation of the components of controller 122 (ie, RAM, ROM, processor, interfaces) is depicted in FIG.

[0037] Referring again to the modules of the controller 122, the buffer manager / bus controller 214 manages buffers in random access memory (RAM) 216 and controls internal bus arbitration of the controller 122. Read only memory (ROM) 218 stores system boot code. While FIG. 2A Illustrated as located separately from the controller 122, in other embodiments, one or both of the RAM 216 and the ROM 218 can be located within the controller. In yet other embodiments, portions of the RAM and the ROM can be located both within the controller 122 and external to the controller. Further, in some implementations, the controller 122, the RAM 216, and the ROM 218 can be located on separate semiconductor dies.

[0038] The front end module 208 includes a host interface 220 and a physical layer interface (PHY) 222 that provides an electrical interface to a host or next level storage controller. The type of host interface 220 can be selected depending on the type of memory used. Examples of host interfaces 220 include, but are not limited to, SATA, SATA Express, SAS, Fibre Channel, USB, PCIe, and NVMe. The host interface 220 generally facilitates the transfer of data, control signals, and timing signals.

[0039] The back end module 210 includes an error correction code (ECC) engine 224 that encodes data bytes received from a host and decodes and error corrects data bytes read from the non-volatile memory. A command sequencer 226 generates command sequences, such as program command sequences and erase command sequences, for transmission to the non-volatile memory dies 108. A RAID (Redundant Array of Independent Dies) module 228 manages the generation of RAID parity and the recovery of failed data. The RAID parity can be used as an additional level of integrity protection for data written into the memory device 100. In some cases, the RAID module 228 can be part of the ECC engine 224. It should be noted that the RAID parity can be added as an extra die or dies as the common name implies, but can also be added within the existing dies, for example, as an extra plane, or extra blocks, or extra WLs within the blocks. A memory interface 230 provides command sequences to the non-volatile memory dies 108 and receives status information from the non-volatile memory dies 108. In one embodiment, the memory interface 230 can be a double data rate (DDR) interface, such as a Toggle Mode 200, 400, or 800 interface. A flash control layer 232 controls the overall operation of the back end module 210.

[0040] FIG. 2AAdditional components of the illustrated memory system 100 include a media management layer 238 that performs wear leveling of memory cells of the non-volatile memory dies 108. The memory system 100 also includes other discrete components 240 such as external electrical interfaces, external RAM, resistors, capacitors, or other components that can interact with the controller 122. In alternative embodiments, one or more of the physical layer interface 222, the RAID module 228, the media management layer 238, and the buffer management / bus controller 214 are optional components that are not needed in the controller 122.

[0041] A flash translation layer (FTL) or media management layer (MML) 238 can be integrated as part of flash management that can handle flash errors and interface with the host. In particular, the MML can be a module in flash management and can be responsible for the internals of NAND management. In particular, the MML 238 can include an algorithm in the memory device firmware that translates writes from the host to writes to the memory structure 126 of the memory dies 108. The MML 238 can be needed because: 1) the memory can have limited endurance; 2) the memory structure 126 can only be written to in multiples of pages; and / or 3) the memory can not be written to unless the memory structure 126 is erased as a block (or as a tier within a block in some embodiments). The MML 238 understands these potential limitations of the memory structure 126 that can not be visible to the host. Thus, the MML 238 attempts to translate writes from the host to writes into the memory structure 126.

[0042] The controller 122 can interface with one or more memory dies 108. In one embodiment, the controller 122 and the plurality of memory dies (together comprising the memory system 100) implement a solid state drive (SSD) that can emulate, replace, or supplement the use of hard disk drives within a host such as a NAS device, in a notebook computer, in a tablet computer, in a server, etc. Additionally, the SSD need not function as a hard disk drive.

[0043] Some embodiments of a non-volatile storage system will include one memory die 108 connected to one controller 122. However, other embodiments can include multiple memory dies 108 in communication with one or more controllers 122. In one example, multiple memory dies can be grouped as a set of memory packages. Each memory package includes one or more memory dies in communication with a controller 122. In one embodiment, a memory package includes a printed circuit board (or similar structure) on which one or more memory dies are mounted. In some embodiments, a memory package can include a molding material to encapsulate the memory dies of the memory package. In some embodiments, the controller 122 is physically separate from any memory package.

[0044] In one embodiment, control circuitry (e.g., control circuitry 110) is formed on a first die, referred to as a control die, and a memory array (e.g., memory structure 126) is formed on a second die, referred to as a memory die. For example, some or all of the control circuitry associated with the memory (e.g., control circuitry 110, row decoders 124, column decoders 132, and read / write circuits 128) can be formed on the same control die. The control die can be bonded to one or more corresponding memory dies to form an integrated memory component. The control die and the memory die can have bond pads arranged for electrical connection to each other. The bond pads of the control die and the memory die can be aligned and bonded together by any of a variety of bonding techniques, depending in part on the bond pad size and the bond pad spacing (i.e., the bond pad pitch). In some embodiments, the bond pads are bonded directly to each other without solder or other additional material in a so-called Cu-Cu bonding process. In some examples, the dies are bonded in a one-to-one arrangement (e.g., one control die to one memory die). In some examples, there can be more than one control die and / or more than one memory die in an integrated memory component. In some embodiments, an integrated memory component includes a stack of multiple control dies and / or multiple memory dies. In some embodiments, the control die is connected to or otherwise in communication with a memory controller. For example, the memory controller can receive data to be programmed into the memory array. The memory controller forwards the data to the control die so that the control die can program the data into the memory array on the memory die.

[0045] FIG. 2B Alternative arrangements of the arrangement of FIG. 2A may be implemented using wafer-to-wafer bonding to provide a bonded die pair. FIG. 2BA functional block diagram depicting one embodiment of an integrated memory component 307 is shown. One or more integrated memory components 307 can be used in a memory package in a memory system 100. The integrated memory component 307 includes two types of semiconductor dies (or more simply, “dies”). The memory dies 301 include the memory structure 126.

[0046] The control die 311 includes column control circuitry 364, row control circuitry 320, and system control logic 360 (including state machine 312, power control module 316 (including charge pump 117), storage 366, and memory interface 368). In some embodiments, the control die 311 is configured to connect to the memory array 126 in the memory die 301. FIG. 2B An example of peripheral circuitry is shown, including control circuitry formed in the peripheral circuitry or control die 311 that is coupled to the memory array 126 formed in the memory die 301. The system control logic 360, row control circuitry 320, and column control circuitry 364 are located in the control die 311. In some embodiments, all or a portion of the column control circuitry 364 and all or a portion of the row control circuitry 320 are located on the memory die 301. In some embodiments, some of the circuitry in the system control logic 360 is located on the memory die 301.

[0047] The system control logic 360, row control circuitry 320, and column control circuitry 364 can be formed from conventional processes (e.g., CMOS processes) such that the addition of elements and functions more commonly found on the memory controller 102, such as ECC, can require few or no additional process steps (i.e., the same process steps used to manufacture the memory controller 102 can also be used to manufacture the system control logic 360, row control circuitry 320, and column control circuitry 364). Thus, while removing such circuitry from a die (such as the memory die 301) can reduce the number of steps required to manufacture such a die, adding such circuitry to a die (such as the control die 311) can not require many additional process steps.

[0048] FIG. 2BColumn control circuitry 364 including sense blocks 350 on control die 311 is shown coupled through electrical paths 370 to memory array 126 on memory die 301. For example, electrical paths 370 can provide electrical connections between column decoders 332, drive circuitry 372 (bit line drive circuitry), block selectors 373, and bit lines of memory array (or memory structure) 126. Electrical paths can extend from column control circuitry 364 in control die 311 through pads on control die 311 that are bonded to corresponding pads of memory die 301 that are connected to bit lines of memory structure 126. Each bit line of memory structure 126 can have a corresponding electrical path in electrical paths 370 connected to column control circuitry 364, including a pair of bonding pads. Similarly, row control circuitry 320 (including row decoders 324, array drivers 374 (word line drive circuitry), and block selectors 376) is coupled through electrical paths 308 to memory array 126. Each electrical path in electrical paths 308 can correspond to a word line, dummy word line, or select gate line. Additional electrical paths can also be provided between control die 311 and memory die 301.

[0049] In some embodiments, there is more than one control die 311 and / or more than one memory die 301 in integrated memory component 307. In some embodiments, integrated memory component 307 includes a stack of multiple control dies 311 and multiple memory dies 301. In some embodiments, each control die 311 is attached (e.g., bonded) to at least one of memory dies 301.

[0050] FIG. 3 is a perspective view of part of one example embodiment of a monolithic three-dimensional memory array including a memory structure 126 that includes a plurality of non-volatile memory cells. For example, FIG. 3 A portion of one memory block is shown. The depicted structure includes a set of bit lines BL that are located over a stack of alternating layers of dielectric material and conductive material on a substrate. For example, one of the dielectric layers is labeled D and one of the conductive layers (also referred to as a word line layer) is labeled W. The number of alternating dielectric and conductive layers can vary based on particular implementation requirements. One set of embodiments includes between 108 and 300 alternating dielectric and conductive layers. One example embodiment includes 96 data word line layers, 8 select layers, 6 dummy word line layers, and 110 dielectric layers. More or fewer than 108 and 300 layers can also be used. The data word line layers have data memory cells. The dummy word line layers have dummy memory cells. As will be explained below, the alternating dielectric and conductive layers are divided into “fingers” in regions that are separated by local interconnects LI. FIG. 3Two regions each having respective NAND strings and two local interconnects LI are illustrated. Source line layers SL are located under alternating dielectric layers and word line layers. Memory holes are formed in the stack of alternating dielectric layers and conductive layers. For example, memory holes are labeled MH. Note that in FIG. 3 the dielectric layers are depicted as perspective views so that the reader can see the memory holes located in the stack of alternating dielectric layers and conductive layers. In one embodiment, the NAND strings are formed by filling the memory holes with material that includes charge-trapping material to form a vertical column of memory cells. Each memory cell can store one or more bits of data.

[0051] FIG. 4A is a block diagram illustrating one exemplary organization of the memory structure 126, which is divided into two planes 302 and 304. Each plane is then divided into M blocks. In one example, each plane has about 2000 blocks. However, different numbers of blocks and planes can also be used. In one embodiment, for two-plane memory, the block IDs are generally such that even blocks belong to one plane and odd blocks belong to the other plane; thus, plane 302 includes blocks 0, 2, 4, 6,..., while plane 304 includes blocks 1, 3, 5, 7,.... In one embodiment, a block of memory cells is an erase unit. That is, all memory cells of one block are erased together. In other embodiments, memory cells can be grouped into blocks for other reasons, such as to organize the memory structure 126 to enable signaling and selection circuitry.

[0052] FIGS. 4B-4C An exemplary 3D NAND structure is depicted. FIG. 4B is a block diagram depicting a top view of a portion of one block from the memory structure 126. FIG. 4B The portion of the block depicted in FIG. 4A corresponds to portion 306 in block 2 of FIG. 4B As can be seen from FIG. 4B the block depicted in extends in the direction of 332. In one embodiment, the memory array will have 60 layers. Other embodiments have fewer or more than 60 layers (e.g., 32, 64, 128, 256, etc.). However, FIG. 4B only the top layer is shown.

[0053] FIG. 4B A plurality of circles representing vertical columns are depicted. Each column in the vertical column includes a plurality of select transistors and a plurality of memory cells. In one embodiment, each vertical column implements one NAND string. For example, FIG. 4BVertical columns 422, 432, 442, and 452 are depicted. Vertical columns 422 implement NAND strings 482. Vertical columns 432 implement NAND strings 484. Vertical columns 442 implement NAND strings 486. Vertical columns 452 implement NAND strings 488. More details of these vertical columns are provided below. A block can include more vertical columns than FIG. 4B more vertical columns depicted in

[0054] FIG. 4B A set of bit lines 425 is also depicted, including bit lines 411, 412, 413, 414,..., 419. FIG. 4B Twenty-four bit lines are shown because only a portion of the block is shown. It is contemplated that more than twenty-four bit lines are connected to the vertical columns of the block. Each circle representing a vertical column has an "x" to indicate that it is connected to one bit line. For example, bit line 414 is connected to vertical columns 422, 432, 442, and 452.

[0055] FIG. 4B The block depicted in includes a set of local interconnects 402, 404, 406, 408, and 410 that connect the various layers to the source lines below the vertical columns. Local interconnects 402, 404, 406, 408, and 410 also serve to divide each layer of the block into four regions; for example, FIG. 4B The top layer depicted in is divided into regions 420, 430, 440, and 450, which are referred to as fingers. In a layer of a block that implements memory cells, the four regions are referred to as word line fingers, which are separated by local interconnects. In one embodiment, the word line fingers on a common level of a block are connected together at the ends of the block to form a single word line. In another embodiment, the word line fingers on the same level are not connected together. In one example implementation, a bit line is connected to only one vertical column in each of regions 420, 430, 440, and 450. In that implementation, each block has sixteen rows of active columns, and each bit line is connected to four rows in each block. In one embodiment, all four rows connected to a common bit line are connected to the same word line (via different word line fingers on the same level that are connected together); thus, the system uses source side select lines and drain side select lines to select one of the four (or another subset) to perform a memory operation (program, verify, read, and / or erase).

[0056] Although FIG. 4B While each region is shown to have four rows of vertical columns and there are sixteen rows of vertical columns for the four regions in one block, these exact numbers are example implementations. Other embodiments can include more or fewer regions per block, more or fewer rows of vertical columns per region, and more or fewer rows of vertical columns per block.

[0057] FIG. 4C Also shown is that the vertical columns are staggered. In other embodiments, different staggering patterns can be used. In some embodiments, the vertical columns are not staggered.

[0058] FIG. 4B A portion of an embodiment of a three-dimensional memory structure 126 is depicted showing the FIG. 4B This cross-sectional view cuts through vertical columns 432 and 434 and region 430 (see FIG. 4C ). FIG. 4B The structure includes four drain-side select layers SGD0, SGD1, SGD2, and SGD3; four source-side select layers SGS0, SGS1, SGS2, and SGS3; four dummy word line layers DD0, DD1, DS0, and DS1; and forty-eight data word line layers WLL0-WLL47 for connecting to data memory cells. Other embodiments may implement more or less than four drain-side select layers, more or less than four source-side select layers, more or less than four dummy word line layers, and more or less than forty-eight word line layers (e.g., 96 word line layers or more than 100 word line layers). Vertical columns 432 and 434 are depicted as protruding through the drain-side select layers, source-side select layers, dummy word line layers, and word line layers. In one embodiment, each vertical column includes a NAND string. For example, vertical column 432 includes NAND string 484. Below the vertical column and the layers listed below are the substrate 101, the insulating film 454 on the substrate, and the source line SL. The NAND strings of the vertical column 432 have source terminals at the bottom of the stack and drain terminals at the top of the stack. FIG. 4C Consistent, FIG. 4C Vertical columns 432 are shown connected to bit lines 414 via connectors 415. Local interconnects 404 and 406 are also depicted.

[0059] Bit lines 414 are connected to pads 416 through vias 417. Additional bit lines coupled to additional vertical columns are similarly connected. Multiple bit lines may extend above such a memory structure and may be connected to multiple blocks through block select circuitry. Such bit lines are connected to pads that may be exposed along the top surface (major surface) of the workpiece so that they can be used to make electrical connections. Similarly, word lines (e.g., WLL0 to WLL47), dummy word lines (e.g., DD0-1, DS0-1), and select lines (e.g., SGD0 to SGD3) may be connected to pads through vias ( FIG. 5 The word line layers (not shown) are coupled to pads on the major surface of the workpiece (e.g., pads coplanar with pad 416). For example, the word line layers can be arranged in a stepped "staircase" arrangement in the outer region (outside the region where the memory cells are formed) so that each word line layer is exposed and can be contacted by a via.

[0060] Non-volatile memory cells are formed along vertical columns that extend through alternating conductive and dielectric layers in a stack. In one embodiment, the memory cells are arranged in NAND strings. Word line layers WLL0 through WLL47 are connected to memory cells, also referred to as data memory cells. Dummy word line layers DD0, DD1, DS0, and DS1 are connected to dummy memory cells. The dummy memory cells do not store user data, while the data memory cells are eligible to store user data. Drain side select layers SGD0, SGD1, SGD2, and SGD3 are used to electrically connect and disconnect the NAND strings with bit lines. Source side select layers SGS0, SGS1, SGS2, and SGS3 are used to electrically connect and disconnect the NAND strings with source lines SL.

[0061] The exact type of memory array architecture or memory cell included in the memory structure 126 is not limited to the examples described above. Many different types of memory array architecture or memory cell technology can be used to form the memory structure 126. The implementation of the claimed new embodiments presented herein does not require a particular non-volatile memory technology. Other examples of technologies suitable for the memory cells of the memory structure 126 include ReRAM memory, magnetoresistive memory (e.g., MRAM, spin-transfer torque MRAM, spin-orbit torque MRAM), phase change memory (e.g., PCM), etc. Examples of suitable technologies for the architecture of the memory structure 126 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, etc. One of ordinary skill in the art will recognize that the technology described herein is not limited to a single particular memory structure, but encompasses many related memory structures within the spirit and scope of the technology described herein and as understood by one of ordinary skill in the art.

[0062] One example of ReRAM memory includes a reversible resistance switching element arranged in a cross-point array accessed by X and Y lines (e.g., word lines and bit lines). In another embodiment, the memory cells can include a conductive bridge memory element. The conductive bridge memory element can also be referred to as a programmable metallization cell. The conductive bridge memory element can function as a state change element based on physical repositioning of ions within a solid electrolyte. In some cases, the conductive bridge memory element can include two solid metal electrodes, one of which is relatively inert (e.g., tungsten) and the other of which is electrochemically active (e.g., silver or copper), with a thin film of solid electrolyte between the two electrodes. As temperature increases, the mobility of the ions also increases, which results in a lower programming threshold for the conductive bridge memory cell. Thus, the conductive bridge memory element can have a wide range of programming thresholds across a range of temperatures.

[0063] Magnetoresistive memory (MRAM) stores data by magnetic storage elements. The elements are formed from two ferromagnetic plates, each of which can hold a magnetization, separated by a thin insulating layer. One of the two plates is a permanent magnet set to a particular polarity; the magnetization of the other plate can be changed to match the magnetization of an external magnetic field to store memory. This configuration is called a spin valve, and is the simplest structure for an MRAM bit. Memory devices are constructed from a grid of such memory cells. In one embodiment for programming a non-volatile storage system, each memory cell is located between a pair of write lines, which are arranged at right angles to each other, parallel to the cell, one above the cell and one below the cell. When current is passed through them, an induced magnetic field is created.

[0064] Phase change memory (PCRAM) takes advantage of the unique properties of chalcogenide glasses. One embodiment uses a GeTe-Sb2Te3superlattice to achieve non-thermal phase change by changing the coordination state of germanium atoms with just a laser pulse (or light pulse from another source). Thus, the dose of programming is the laser pulse. A memory cell can be inhibited by preventing it from receiving light. It should be noted that the use of "pulse" in this document does not require a square pulse, but includes a (continuous or non-continuous) vibration or burst of sound, current, voltage light or other wave.

[0065] FIG. 3 The process of wafer-to-wafer bonding of wafer 500 and wafer 600 is illustrated. Substrate 501 is processed to fabricate a memory die including a non-volatile memory array (e.g., memory structure 126), interconnect structures, and pads for bonding, as discussed above with reference to FIGS. 4A-4C and FIG. 2B to form wafer 500. Substrate 601 is processed to fabricate a control die including memory control circuitry (e.g., logic circuitry formed as CMOS circuitry), interconnect structures, and pads for bonding, as discussed above with reference to FIG. 5The wafer 500 is then flipped (either wafer can be flipped in this example), so that the major surface 506 of the wafer 500 is opposite the major surface 606 of the wafer 600. The wafers 500 and 600 are aligned so that corresponding dies are aligned in pairs (in a one-to-one arrangement of memory dies and control dies), and pads on such pairs of dies are aligned for bonding. Subsequently, with the wafers 500, 600 aligned, pressure and / or heat or other conditions are applied to the wafers 500, 600 to bond the respective pads together, forming electrical connections between the memory arrays of the wafer 500 and the control circuitry of the wafer 600 (i.e., bonding along the interface between the major surfaces 506, 606). The bonded wafers 500 and 600 form a combined wafer 700 that includes pairs of dies, with each pair including a memory die and a control die that form a memory system. The combined wafer 700 can be scribed (cut) into pairs of dies 702 for packaging. The combined wafer 700 or a portion of such a wafer can be referred to as a CMOS bonded array (CbA), and an individual pair of dies 702 (a memory die and a control die) can be referred to as an integrated memory component.

[0066] One feature of wafer-to-wafer bonding as described with respect to FIG. 5 One feature of wafer-to-wafer bonding as described with respect to

[0067] FIG. 5Another feature of the one-to-one relationship between memory dies and control dies is that the failure rate of the integrated memory components can be relatively high and can waste several "good" dies (memory dies and control dies that meet specifications and are free of defects). Good memory dies can be bonded to bad control dies, and good control dies can be bonded to bad memory dies, resulting in bad integrated memory components. For example, where 5% of the memory dies are bad (defective) and 5% of the control dies are bad (defective), the resulting yield loss can be about 10% (e.g., about 10% of the resulting integrated memory components are defective because of a defective memory die or a defective control die). Even if the bad dies are identified prior to bonding, wafer-to-wafer bonding can not allow for any rearrangement of the die pairings (e.g., a given die is paired with a counterpart die based on its physical location in the wafer, which can not be changed prior to wafer-to-wafer bonding).

[0068] According to aspects of the present technology, the integrated memory components can not be limited to FIGS. 6A-6Bone-to-one arrangement, free from die size matching constraints and can allow for integration of high-density memory structures in an efficient manner (e.g., less defective integrated memory assemblies for a given die failure rate) with lower failure rates than wafer-to-wafer bonding. According to examples presented below, two or more memory small dies or chips (e.g., memory chips with memory array structures 126, such as memory chip 301, that can form one or more planes or sub-planes and are not limited by die size matching) can be combined with (e.g., directly bonded to) a control die that has slots to accommodate multiple memory small dies (e.g., bond pad arrangements connected to corresponding control circuitry). Each memory small chip can be composed of an appropriate unit of memory structure (e.g., one, two, or more planes or sub-planes of NAND memory). The memory small chips in such an arrangement can be the same or different. For example, the small chips can have different capacities (e.g., number of planes or blocks), different structures (e.g., different number of layers), different configurations (e.g., configured to store different number of bits per cell), and / or otherwise not be the same. Such an arrangement can be adaptable to different needs (e.g., capacity is configurable by using small chips of different capacities and / or different number of small chips), and can combine high performance and low cost (e.g., some high performance small chips for high demand applications and some low cost small chips for low demand applications). Testing the small chips and / or the control dies before assembly can reduce the number of defective integrated memory assemblies (e.g., compared to wafer-to-wafer bonding). For example, defective control dies in a wafer can be identified, marked as defective, and can not be bonded to any small chips, while defective small chips can be identified and discarded without being bonded to any control dies. Such die screening before bonding can have significant benefits. For example, with 5% of the memory small chips and 5% of the control dies defective, the defective memory small chips are discarded, and the remaining good memory small chips (95%) are bonded to good control dies (without being bonded to the 5% defective control dies), such that the yield loss is limited to 5% (e.g., about half of the yield loss of a similar die wafer-to-wafer bonding).

[0069] FIG. 6A An example of die-to-wafer bonding is shown, in which four memory small chips (memory dies) 610a-d are bonded to a control die 612 in a silicon wafer 600. For example, the silicon wafer 600 can include a large number of control dies, including FIG. 6A The control dies 612 and 614 are shown. In some cases, the control dies can be tested before assembly of the integrated memory assemblies (e.g., as described above with respect to FIG. 1). For example, the control dies can be tested before assembly of the integrated memory assemblies, and the defective control dies can be marked as defective and not bonded to any small chips. In some cases, the control dies can be tested after assembly of the integrated memory assemblies, and the defective control dies can be marked as defective and not bonded to any small chips. In some cases, the control dies can be tested after assembly of the integrated memory assemblies, and the defective control dies can be marked as defective and not bonded to any small chips. In some cases, the control dies can be tested after assembly of the integrated memory assemblies, and the defective control dies can be marked as defective and not bonded to any small chips. FIG. 5One or more defective control dies are detected before bonding the memory chiplets to the control die as shown. In the example shown, the control die 614 is detected as a defective control die, and therefore no memory chiplets are bonded to the control die 614. FIG. 6B Unlike the wafer-to-wafer bonding example of , bonding can be selective on a die-by-die basis, such that defective dies can be omitted from bonding, thereby saving resources.

[0070] FIGS. 7A-7B A top view of the control die 612 is shown, showing an upper (first) surface 616 including four slots 616a-d corresponding to the four memory chiplets 610a-d. Each slot 616a-d can include a bonding pad for bonding to a corresponding bonding pad of the memory chiplet 610a-d, and each slot can be sized to accommodate a memory chiplet (e.g., a size equal to or larger than the size of the memory chiplet or the opposing (second) surface of the die).

[0071] FIG. 7A Another example of die-to-wafer bonding is shown, where eight memory chiplets (memory dies) 620a-h are bonded to a control die 622 in a silicon wafer 600. For example, a silicon wafer 600 may include a large number of control dies, including FIG. 7A The control die 622 and 624 are shown. FIG. 7B In the example shown, the control die 624 is detected as a defective control die, and therefore no memory chiplets are bonded to the control die 624.

[0072] FIGS. 6A-7B A top view of a controller die 622 is shown, showing an upper (first) surface 626 including eight slots 626a-h corresponding to eight memory dies 620a-h. Each slot 626a-h can include a bonding pad for bonding to a corresponding bonding pad of a memory die 620a-h, and each slot can be sized to accommodate a memory die (e.g., a size equal to or larger than the size of the opposing (second) surface of the memory chiplet or die).

[0073] Although FIGS. 8A-8BThe examples of FIGS. 6A and 6B show four and eight slots, respectively, but the number of slots and the arrangement of slots is not limited to any particular number or arrangement. The examples described herein are for illustrative purposes and are not intended to provide an exhaustive list of all possible implementations. Further, control dies in a given silicon wafer can not be identical. For example, a single silicon wafer can include control dies with four slots (e.g., control die 612) and control dies with eight slots (e.g., control die 622) or dies that differ in other ways.

[0074] In addition to providing flexibility regarding whether to bond a die (e.g., to bond only good dies), aspects of the present technology can provide flexibility regarding how many memory dies and what types of memory dies to bond to a given control die. It is not generally required that every slot on a control die be occupied by a memory die in order to form a functionally integrated memory assembly.

[0075] For example, FIGS. 9A-9B An example is shown in which control die 612 has two used (occupied) slots 616a and 616c and two unused (empty) slots 616b and 616d. Memory dies 610a and 610c are bonded in corresponding slots 616a and 616c, while no memory dies are bonded in slots 616b and 616d, which remain empty. The assembly consisting of control die 612 and memory dies 610a and 610c can be considered a complete integrated memory assembly.

[0076] FIGS. 10A-10B Another example is shown in which control die 622 has eight slots 626a-h, of which six slots 626a and 626c-g are used and two slots 626b and 626h are unused. Memory dies 620a and 620c-g are bonded in corresponding slots 626a and 626c-g, while no memory dies are bonded in slots 626b and 626h, which remain empty. The assembly consisting of control die 622 and memory dies 620a and 620c-g can be considered a complete integrated memory assembly.

[0077] According to aspects of the present technology, different memory dies (e.g., memory dies having different structures, capacities, configurations, and / or otherwise different memory dies) can be used to form an integrated memory assembly.

[0078] FIGS. 10A-10BAn example is shown in which different memory dies are bonded to a control die 622 to form an integrated memory component. Memory dies 630a and 630c-g are not identical. For example, memory die 630a is physically larger than memory dies 630c-g and occupies two slots 626a and 626e. Memory die 630a can be designed to interface with the bonding pads of two slots, such that it can be bonded as shown (e.g., the slots can define a minimum memory die footprint and bonding pad arrangement, without limiting the die size to a single slot). Memory die 630c is smaller than memory die 630a (e.g., about half the size) and can accordingly have a smaller capacity (e.g., half the capacity, assuming similar structure and configuration). Memory die 630d has a greater number of layers than memory die 630c (e.g., more word line layers and more memory cells, which provides more data storage capacity). Memory die 630f has a different configuration than memory die 630c (e.g., while memory die 630c can be configured to store four bits per cell (QLC), memory die 630f can be configured to store three bits per cell (TLC) or one bit per cell (SLC)). Memory die 630g can have a different structure than memory die 630c. For example, while memory die 630c can have a 3D NAND flash memory structure, memory die 630g can have a different structure (e.g., ReRAM, MRAM, PCM, or other structure). While FIG. 10B The different memory dies shown in FIG. 6 are provided as examples, but the range of memory dies that can be bonded to a single control die is not limited to the examples described.

[0079] Forming integrated memory components from memory dies with different characteristics allows for customization of integrated memory components for particular uses in a cost-effective manner (e.g., combining high-performance memory dies with cheaper, lower-performance memory dies). Memory dies manufactured using older technology can be integrated with memory dies using newer technology to obtain the benefits of the newer technology at a lower overall cost. The data storage capacity of such integrated memory components can be configured by selecting the number and capacity of the memory dies used. A common control die can be used to provide integrated memory components with a range of different capacities. Integrated memory components with different capacities (and / or other different characteristics) can be formed in the same manufacturing facility, and can be formed from the same silicon wafer (e.g., silicon wafer 600 can include a control die bonded to a different set of memory dies than those bonded to control die 622).

[0080] slots (e.g., FIG. 11AThe bond pads of the slot 626c shown can correspond to the bond pads of the slot 626c of the memory chip 630c. FIG. 11B An example of the bond pads of the slot 626c is shown, including a bit line bond pad 1150 in the middle of the slot 626c and word line bond pads 1152a, 1152b on either side of the bit line bond pad 1150. The bit line bond pad 1150 can be connected to bit line drive circuitry (e.g., the drive circuitry 372 of the column control circuitry 364) in the control die 622. The word line bond pads 1152a-b can be connected to word line drive circuitry (e.g., the array drivers 374 of the row control circuitry 320) in the control die 622. Additional bond pads 1154 are provided in the slot 626c, and can include pads providing one or more voltages, such as ground or 0 volts; a power supply voltage such as 3 volts, 5 volts, or other non-zero voltage, one or more clock signals, and / or voltages or signals that can be used by the memory chip.

[0081] FIG. 10B A corresponding bond pad of the bond pads of the slot 626c shown is shown on the surface 632c (second surface) of the memory chip 630c. FIG. 11A bonded to in FIG. 11B the slot 626c. FIG. 4C A bit line bond pad 1160 in the middle of the surface 632c and word line bond pads 1162a, 1156b on either side of the bit line bond pad 1160 are shown. The bit line bond pad 1160 can be connected to bit lines (e.g., the bit lines 414) in the memory chip 630c. FIG. 4C The word line bond pads 1162a-b can be connected to word lines (e.g., the word lines WLL0 through WLL47) in the memory chip 630c. Additional bond pads 1164 are provided on the surface 632c, and can correspond to the additional bond pads 1154 (e.g., pads for one or more voltages, clock signals, and / or other signals). FIG. 12

[0082] ​During fabrication of the integrated memory component, the memory dielets can be aligned such that the bond pads of the memory dielets are aligned with corresponding bond pads of the slots on the surface of the control die. For example, the memory dielet 630c is aligned with the slot 626c such that the first bit line bond pad 1150 of the slot 626c is aligned with the second bit line bond pad 1160 on the surface 632c, the first word line bond pads 1152a-b are aligned with the second word line bond pads 1162a-b, and the first additional bond pad 1154 is aligned with the second additional bond pad 1164. Bonding of the bond pads can then be performed such that the first bit line bond pad 1150 is bonded to the second bit line bond pad 1160, the first word line bond pads 1152a-b are bonded to the second word line bond pads 1162a-b, and the first additional bond pad 1154 is bonded to the second additional bond pad 1164, which results in the connection of the control circuitry in the control die 622 with corresponding components of the memory dielet 630c (e.g., bit line drivers connected to bit lines and word line drivers connected to word lines).

[0083] FIG. 2B An example of an integrated memory component 1270 formed by bonding two memory dielets 1272a and 1272c to the control die 622 is illustrated. Certain components of the control die 622 have been previously described with respect to the control die 311 of the integrated memory component 307 FIG. 13 ) and are not further described here.

[0084] In contrast to the integrated memory component 307, the integrated memory component 1270 includes two memory die 1272a and 1272c connected to corresponding slots 616a and 616c of the control die 622. The memory die 1272a and 1272c each include word lines 1274 and bit lines 1276 and are aligned and bonded such that the pads of the memory die 1272a and 1272c are bonded to corresponding pads of the slots 616a and 616c to connect the WL 1274 to the row control circuit 320 and the BL 1276 to the column control circuit 364. The slots 616b and 616d are not used in the integrated memory component 1270. The system control logic 360 can include circuitry to detect the presence / absence of a memory die at each of the slots 616a-d and configure operations accordingly. For example, the memory interface circuit 1278 can be configured to detect the presence / absence of a memory die at each slot 616a-d (and can perform additional detection of, e.g., the capacity and / or configuration of each memory die). The physical configuration (number and type of memory die) can be used to determine the space available for data storage (e.g., to initiate a logical to physical mapping). Memory access operations (e.g., write, read, and erase operations) can be directed according to the configuration detected by the memory interface circuit 1278 (e.g., by accessing the memory die 1272a and 1272c through the corresponding slots 616a and 616c, without attempting to access through slots 616b and 616d).

[0085] In examples of the present technology, silicon wafers including control dies (e.g., silicon wafer 600) and / or silicon wafers including memory die (e.g., silicon wafers containing any of memory die 610a-d, 620a-h, 630a-g) can be evaluated prior to performing die-to-wafer bonding to determine whether they meet desired specifications. In some examples, metrology can be used to visually detect defects, and if such defects are observed, the dies or die can be marked as defective. In some examples, metrology data regarding film thickness, film quality, etch depth, pattern alignment, or other metrology can be used to detect defective dies and / or die. Further, in some cases, electrical testing can be performed to evaluate the dies and / or die. For example, probe pads can be located on the surface of a die or die to enable test equipment to electrically connect to components of the die or die. The surface area of a memory die can be limited, making it challenging to increase such probe pads without increasing area, which is costly. Aspects of the present technology provide technical solutions to the technical problem of obtaining test data from memory dies or die in an area-efficient manner (e.g., to enable pre-bonding screening of defective dies).

[0086] FIG. 13An example of a silicon wafer 1380 including memory dies (e.g., any of memory dies 630a-d, 610a-h, 620a-g) is shown. While FIG. 13 The silicon wafer 1380 is shown as a single physical body, but can be separated into individual dies or dies by scribing the silicon wafer along scribe lines (as shown by the dashed lines in FIG. 13 FIG. 13 An example of a scribe line 1382 is shown in FIG. 13B, and a portion of the scribe line 1382 is shown in close-up including probe pads 1384a-g. The probe pads 1384a-g (and additional probe pads not visible in this view) can be electrically connected to components of the memory dies of the silicon wafer 1380 (e.g., to word lines and / or bit lines), which can allow the components to be probed prior to scribing the silicon wafer 1380 (e.g., probes connected to test equipment can be brought into physical and electrical contact with the probe pads 1384a-g). For example, probe pads connected to word lines and bit lines can be probed to identify word line to word line shorts, bit line to bit line shorts, word line to bit line shorts, bit line open defects, bit line leakage, and / or other defects.

[0087] The area occupied by the scribe line (the scribe lane or scribe region) can be removed during the scribing process. For example, a portion of the wafer material (e.g., silicon and any structures formed on or in the silicon) between the dies can be removed using a saw or laser to separate the dies from each other and from the silicon wafer. In the example of FIG. 13B, the probe pads 1384a-g formed in the scribe region of the scribe line 1382 are removed during scribing, so that these components are no longer present during bonding. Positioning such components in the scribe region not only ensures that the die size is not affected by the addition of such structures, but also ensures that they are removed prior to bonding, which can be beneficial because the presence of such probe pads after probing is complete can contribute to non-uniformity of the die surface, which can affect bonding of the die to a control die (e.g., probe marks resulting from the probing process can contribute to surface non-uniformity and probing can leave contamination). FIGS. 14A-14D

[0088] FIG. 14A Removal of the scribe region in an example of a scribe process to separate individual memory dies is shown. FIG. 14A A portion of a silicon wafer including memory dies is shown in cross-section prior to scribing, the memory dies including memory dies 1490a-d. The memory dies 1490a-d are separated by scribe regions 1492a-c. Bond pads 1494a-d are shown in the upper surface of the respective memory dies 1490a-d (a single bond pad is shown in each memory die for simplicity of illustration). FIG. 14B ​​Scribe pads 1496a-c are also shown formed in scribe regions 1492a-c, respectively.

[0089] FIG. 14A Portions of the memory die 1490a-d are shown after deposition of a protective layer 1498 (e.g., a layer of organic material that can be spin-coated, deposited, or otherwise applied). The protective layer 1498 covers the upper surfaces of the memory dies 1490a-d during scribing to avoid damage and contamination (e.g., damage caused by debris resulting from scribing) that can result from scribing. FIG. 14C

[0090] FIG. 14D The memory dies 1490a-d are shown after scribing, in which all material in the scribe regions 1492a-c is removed, leaving the memory dies 1492a-d as physically separate bodies.

[0091] FIG. 15 The memory dies 1490a-d are shown after removal of portions of the protective layer 1498, leaving the bond pads 1494 exposed and ready for bonding (e.g., to corresponding bond pads of a control die).

[0092] FIG. 15 An example of a method of manufacturing an integrated memory assembly according to an example of the present technology is shown. A first silicon wafer 1500 (control wafer) is used for control die fabrication 1502 to form control dies in the first silicon wafer 1500. Bad die detection 1504 is used to identify bad control dies in the first silicon wafer 1500 (e.g., using metrology during or after fabrication and / or testing using external test equipment connected by probes and / or on-die testing using built-in self-test circuitry).

[0093] FIG. 16 ​A second silicon wafer 1510 (memory wafer) is also shown, which is used for memory die fabrication 1506 to form memory dies or chips in the second silicon wafer 1510. Bad die detection 1508 is used to identify bad memory dies in the second silicon wafer 1510. The bad die detection 1508 can include testing using metrology and / or using external test equipment connected by probes during or after fabrication and / or on-die testing using built-in self-test circuitry. For example, the bad die detection 1508 can include detecting defects (e.g., shorts) using probe pads located in a scribe region of the second silicon wafer 1510. Subsequently, a scribe 1512 separates the second silicon wafer 1510 into individual memory dies or chips 1514. Classification 1516 then separates good memory dies 1514a and bad memory dies 1514b. The bad memory dies 1514b can be discarded. The memory dies 1514 can additionally be classified according to various metrics based on testing (e.g., testing is not limited to making a good / bad determination). The good memory dies 1514a are bonded to good control dies of the first silicon wafer 1500 in die-to-wafer bonding 1518. Note that not all memory dies bonded to the first silicon wafer 1500 must come from the second silicon wafer 1510 (e.g., memory dies bonded to a single control wafer or a single control die can come from multiple memory wafers). After the die-to-wafer bonding 1518, the first silicon wafer 1500 can be scribed to separate individual integrated memory assemblies.

[0094] FIG. 17 An example of a method according to examples of the present technology is shown. The method includes bonding a first memory die to a first surface of a control die located in a silicon wafer 1620, subsequently bonding a second memory die to the first surface of the control die 1622, and subsequently separating the control die from the silicon wafer by removing a scribe region of the silicon wafer 1624.

[0095] FIGS. 14A-14C An example of a method according to examples of the present technology is illustrated. The method includes determining that a first subset of a plurality of control dies is defective and a second subset of the plurality of control dies is not defective prior to bonding a first memory die and a second memory die to a first surface 1730, determining that the first memory die and the second memory die are not defective prior to bonding the first memory die and the second memory die to the first surface includes probing test pads located in a scribe region of a second silicon wafer including the first memory die and the second memory die 1732, subsequently separating the first memory die and the second memory die by removing the scribe region of the second silicon wafer 1734 (e.g., as shown in FIG. 17B), and subsequently bonding the memory dies to only control dies of the second subset of the plurality of control dies 1736. ​

[0096] ​An example of an apparatus includes a silicon wafer and a plurality of memory dies. The silicon wafer includes a plurality of control dies, each control die having first bond pads on a first surface of the control die. The plurality of memory dies each have second bond pads on a second surface facing the first surface of the control dies. The second bond pads of each memory die are bonded to corresponding first bond pads on a first surface of a memory control circuit.

[0097] The first surface of the control dies can include a plurality of slots, each slot including a plurality of the first bond pads connected, each slot occupying an area on the first surface equal to or greater than an area of the second surface of the memory dies. Each slot can include first bond pads connected to word line drive circuitry and bit line drive circuitry of the control die. One or more of the plurality of slots can be unoccupied by a memory die. The plurality of memory dies can include first memory dies of a first type and second memory dies of a second type different from the first type. The first memory dies can have a first number of word line layers, and the second memory dies can have a second number of word line layers greater than the first number. The first memory dies can have non-volatile memory cells configured to store a first number of bits per cell, the second memory dies can have non-volatile memory cells configured to store a second number of bits per cell, and the second number is greater than the first number. The plurality of memory dies can be formed in a second silicon wafer including scribe line regions separating the plurality of memory dies; and a probe pad in the scribe line regions, the probe pad electrically connected to a component of a memory array formed in the plurality of memory dies. Each of the plurality of memory dies can include a 3D NAND memory array including a plurality of word line layers.

[0098] An example of a method includes bonding a first memory die to a first surface of a control die located in a silicon wafer; subsequently bonding a second memory die to the first surface of the control die; and subsequently singulating the silicon wafer to separate the control die from the silicon wafer.

[0099] The control die can include a plurality of slots, bonding the first memory die to the first surface of the memory control circuit can include aligning the first memory die with a first slot, and bonding the second memory die to the first surface of the memory control circuit can include aligning the second memory die with a second slot. In one example, each slot includes a plurality of first bond pads, aligning the first memory die with the first slot includes aligning corresponding second bond pads of the first memory die with the first bond pads of the first slot, and aligning the second memory die with the second slot includes aligning corresponding second bond pads of the second memory die with the first bond pads of the second slot. In one example, the first memory die is different from the second memory die. In one example, the first memory die and the second memory die have at least one of a different number of word line levels and / or a different number of bits per cell. In one example, the method further includes, prior to bonding the first memory die and the second memory die to the first surface, determining that the control die is free of defects. In one example, the method further includes, prior to bonding the first memory die and the second memory die to the first surface, determining that a first subset of the plurality of control dies is defective and a second subset of the plurality of control dies is free of defects; and subsequently bonding the memory die to only control dies of the second subset of the plurality of control dies. In one example, the method further includes, prior to bonding the first memory die and the second memory die to the first surface, determining that the first memory die and the second memory die are free of defects. In one example, determining that the first memory die and the second memory die are free of defects includes probing a probe pad located in a scribe region of a second silicon wafer that includes the first memory die and the second memory die, and subsequently separating the first memory die and the second memory die by removing the scribe region of the second silicon wafer.

[0100] An example of a memory system includes a control die including word line drivers connected to word line bond pads and bit line drivers connected to bit line bond pads on a first surface of the control die, the word line bond pads and the bit line bond pads arranged in a plurality of slots, each slot sized to accommodate a corresponding memory die and each slot having word line bond pads and bit line bond pads; a plurality of memory dies bonded to the control die, the plurality of memory dies including at least a first memory die at a first slot and a second memory die at a second slot, word lines of the first memory die and the second memory die connected to the word line bond pads of the respective first and second slots and bit lines of the first memory die and the second memory die connected to the bit line bond pads of the respective first and second slots; and at least one empty slot having un-bonded word line bond pads and bit line bond pads.

[0101] In one example, the first memory die and the second memory die differ in at least one of: a respective number of word line layers, a respective number of bits per cell, and / or a respective data capacity.

[0102] For the purposes of this document, references to “an embodiment”, “one embodiment”, “some embodiments” or “another embodiment” can be used to describe different embodiments or the same embodiment.

[0103] For the purposes of this document, a connection can be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element can be directly connected to the other element or be indirectly connected to the other element via an intervening element. When an element is referred to as being directly connected to another element, then there are no intervening elements between the element and the other element. Two devices are “in communication” if they are directly or indirectly connected such that they are capable of

[0104] For the purposes of this document, the term “based on” can be understood as “based at least in part on”.

[0105] For the purposes of this document, the use of numerical terms such as “first”, “second” and “third” objects can not imply an ordering of the objects, but can be used for identification purposes to identify different objects, in the absence of additional context.

[0106] For the purposes of this document, the term “group” of objects can refer to a “group” of one or more objects.

[0107] The detailed description above has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best illustrate the principles of the technology and its practical application to thereby enable others skilled in the art to best utilize it in various embodiments and with various modifications as are suited to the particular use contemplated. The scope of the disclosure is intended to be defined by the claims appended hereto.

Claims

1. A device comprising: a silicon wafer comprising a plurality of control dies, each control die having a first bonding pad on a first surface of the control die; and a plurality of memory dies, each memory die having a second bonding pad on a second surface of the memory die, the second surface of each memory die facing the first surface of the control die, and the second bonding pad of each memory die bonded to a corresponding first bonding pad on the first surface of the memory control circuit.

2. The apparatus of claim 1 , wherein the first surface of the control die comprises a plurality of trenches, each trench comprising a plurality of connected first bonding pads, and each trench occupies an area on the first surface that is equal to or greater than an area of ​​the second surface of the memory die. 3 . The apparatus of claim 2 , wherein each trench comprises a first bonding pad connected to a word line driver circuit and a bit line driver circuit of the control die.

4. The device of claim 2, wherein one or more of the plurality of slots are not occupied by a memory die. 5 . The apparatus of claim 1 , wherein the plurality of memory dies comprises a first memory die of a first type and a second memory die of a second type different from the first type. 6 . The apparatus of claim 5 , wherein the first memory die has a first number of word line layers, and the second memory die has a second number of word line layers greater than the first number.

7. The apparatus of claim 5, wherein the first memory die has nonvolatile memory cells configured to store a first number of bits per cell, the second memory die has nonvolatile memory cells configured to store a second number of bits per cell, and the second number is greater than the first number.

8. The apparatus of claim 1 , wherein the plurality of memory dies are formed in a second silicon wafer, the second silicon wafer comprising: a scribe line region separating the plurality of memory dies; and Probing pads are located in the scribe line regions, the probing pads being electrically connected to components of a memory array formed in the plurality of memory dies.

9. The device of claim 1, wherein each of the plurality of memory dies comprises a 3D NAND memory array comprising multiple word line layers.

10. A method comprising: bonding a first memory die to a first surface of a controller die located in a silicon wafer; subsequently bonding a second memory die to the first surface of the controller die; as well as The silicon wafer is then singulated to separate the control dies from the silicon wafer.

11. The method of claim 10 , wherein the control die comprises a plurality of slots, bonding the first memory die to the first surface of the memory control circuitry comprises aligning the first memory die with the first slots, and bonding the second memory die to the first surface of the memory control circuitry comprises aligning the second memory die with the second slots.

12. The method of claim 11 , wherein each slot comprises a plurality of first bonding pads, aligning the first memory die with the first slot comprises aligning corresponding second bonding pads of the first memory die with first bonding pads of the first slot, and aligning the second memory die with the second slot comprises aligning corresponding second bonding pads of the second memory die with first bonding pads of the second slot.

13. The method of claim 10, wherein the first memory die is different from the second memory die.

14. The method of claim 13, wherein the first memory die and the second memory die have at least one of: a different number of word line levels and / or a different number of bits per cell.

15. The method according to claim 10, further comprising: Prior to bonding the first and second memory dies to the first surface, the control die is determined to be free of defects.

16. The method of claim 15, wherein the silicon wafer comprises a plurality of control dies, the method further comprising: prior to bonding the first memory die and the second memory die to the first surface, determining that a first subset of the plurality of control dies are defective and a second subset of the plurality of control dies are non-defective; as well as Memory dies are then bonded to only the control dies in the second subset of the plurality of control dies.

17. The method according to claim 10, further comprising: Prior to bonding the first memory die and the second memory die to the first surface, it is determined that the first memory die and the second memory die are free of defects.

18. The method of claim 17 , wherein determining that the first memory die and the second memory die are free of defects comprises probing probe pads located in a scribe line region of a second silicon wafer comprising the first memory die and the second memory die, and subsequently separating the first memory die and the second memory die by removing the scribe line region of the second silicon wafer.

19. A memory system, comprising: a control die comprising a wordline driver connected to wordline bond pads and a bitline driver connected to bitline bond pads on a first surface of the control die, the wordline bond pads and the bitline bond pads being arranged in a plurality of slots, each slot being sized to accommodate a corresponding memory die and each slot having a wordline bond pad and a bitline bond pad; a plurality of memory dies bonded to the control die, the plurality of memory dies comprising at least a first memory die located at a first slot and a second memory die located at a second slot, word lines of the first memory die and the second memory die connected to word line bond pads of the respective first and second slots and bit lines of the first memory die and the second memory die connected to bit line bond pads of the respective first and second slots; and At least one empty trench has an unbonded wordline bonding pad and a bitline bonding pad.

20. The memory system of claim 19, wherein: The first memory die and the second memory die differ in at least one of: a respective number of wordline layers, a respective number of bits per cell, and / or a respective data capacity.

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