Fine control manufacturing method of carrier storage layer
By forming a floating ring-shaped doped region in a high aspect ratio trench structure and laterally connecting it to the carrier storage layer, the problem of fine control of the doped region of the carrier storage layer is solved, and the performance of the power semiconductor device is improved.
Patent Information
- Application Number
- CN202510780312.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-11
- Publication Date
- 2025-10-17
AI Technical Summary
Existing power semiconductor devices have difficulty in precisely controlling the doping region of the carrier storage layer in a high aspect ratio trench structure, especially the connection relationship with other regions, which limits further improvement of device performance.
A floating ring doped region is formed by forming a first trench on a semiconductor substrate and performing ion implantation, then deeply etching a second trench and filling it with photoresist, performing exposure and development, and then performing selective ion implantation to form the floating ring doped region, and achieving lateral connection with the carrier storage layer through heat treatment.
It achieves fine control of the doping area in the high aspect ratio trench structure, optimizes the carrier storage structure, significantly reduces the on-state voltage drop, reduces the conduction loss, improves the current density and energy efficiency, and is compatible with existing semiconductor manufacturing processes.
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Figure CN120812965A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor manufacturing, and particularly relates to a manufacturing process of a carrier storage layer in a power semiconductor device. BACKGROUND
[0002] In the design and manufacturing of power semiconductor devices, such as Insulated Gate Bipolar Transistor (IGBT) and the like, continuously reducing the cell size to improve the integration, current density, reduce the production cost and improve the device performance (such as reducing the on-state voltage drop Vce(sat)) is an important development direction of the technical iteration in this field. In order to pursue more excellent device performance, the structure of the power device has experienced the evolution from Punch-Through (PT) to Non-Punch-Through (NPT), and then to Field Stop (FS) and the like in different technical nodes, which aims to obtain smaller chip size, greater current density and lower on-state energy loss.
[0003] However, as the cell size is continuously reduced and gradually approaches its physical and process limit, the space for improving the device performance by simply reducing the size is more and more limited. In order to further improve the device performance, especially to reduce the on-state voltage drop, the industry has developed the Injection Enhanced (IE) technology. For example, in the IE-IGBT (Injection Enhanced IGBT), by introducing an injection enhanced layer (for example, an n-type injection layer, n-injector) in the device structure, the injection of the majority carriers (for example, electrons) can be effectively enhanced, and the minority carriers (for example, holes for N-channel IGBT) can be effectively prevented from being extracted and collected too quickly by the emitter. In this way, the carrier concentration in the drift region of the device in the on-state can be significantly improved, the conductance modulation effect is formed, and the drift region has higher conductivity, thereby effectively reducing the on-state voltage drop of the device.
[0004] Although the prior art, such as the injection of enhanced layer, can improve the performance of power devices to some extent, in advanced power devices with high aspect ratio (High Aspect Ratio) trench (Trench) structure, how to more finely and accurately control the doping distribution of the region near the trench structure to form a more optimized and more excellent performance carrier storage structure still faces challenges. Especially after the formation of deep and narrow trenches, how to use the limited heat budget to selectively dope the specific region of the trench sidewall or bottom, and accurately control the size and position of the doped region, as well as its interconnection relationship with other doped regions (such as carrier storage layer), there is a certain difficulty in process implementation. This precise doping structure is crucial for further optimizing the carrier distribution inside the device, improving the carrier storage effect, reducing the on-state loss and improving the switching characteristics.
[0005] Therefore, it is urgent to develop a new process method to realize fine control of the carrier storage related doped region in the high aspect ratio trench structure to meet the needs of the next generation of high-performance power semiconductor devices. SUMMARY
[0006] The technical problem to be solved by the present application is that in the process of pursuing small size and high performance of existing power semiconductor devices (such as IGBT), although deep trench structure and injection enhancement technology are adopted, it is difficult to finely and accurately control the doping region near the trench, especially the structure for enhancing the carrier storage effect, in devices with high aspect ratio trenches. For example, after forming a deep trench, it is difficult to accurately form a selective doping region in a specific region inside the trench and control its connection relationship with other parts of the device, which limits the further reduction of the on-state voltage drop of the device and the improvement of the overall performance.
[0007] In order to solve the above technical problems, the present application provides a fine control manufacturing method of carrier storage layer, which aims to realize accurate control of the carrier storage related doped region in the high aspect ratio trench structure through unique process step combination.
[0008] The fine control manufacturing method of carrier storage layer provided by the present application comprises the following steps:
[0009] Step one, first trench etching is performed on the semiconductor substrate to form a first trench; and after the formation of the first trench, first ion implantation is performed to form a carrier storage layer;
[0010] Step two, second trench etching is performed on the first trench to form a deeper second trench at the bottom of the first trench; then the photoresist layer is filled in the second trench, and the photoresist layer is subjected to exposure and development treatment to remove the photoresist layer in the predetermined region;
[0011] Step three, performing a second ion implantation in the predetermined region where the photoresist layer is removed to form a floating ring-shaped doping region;
[0012] Step four, performing a heat treatment to connect the floating ring-shaped doping region and the carrier storage layer in a lateral direction.
[0013] Preferably, the semiconductor substrate is a silicon substrate.
[0014] Preferably, before the first trench etching in step one, the method further comprises: forming a hard mask layer on the semiconductor substrate for defining the first trench pattern.
[0015] Preferably, in step one, the first ion implantation is a low-energy ion implantation.
[0016] Preferably, step one further comprises: forming a first protective layer on the surface of the first trench after the first trench etching and before the first ion implantation.
[0017] Preferably, in step two, the second trench is a high aspect ratio trench.
[0018] Preferably, in step two, the photoresist layer is a non-photosensitive photoresist.
[0019] Preferably, after removing the photoresist layer in step two and before performing the second ion implantation in step three, a second protective layer is formed.
[0020] Preferably, the first protective layer and / or the second protective layer is a sacrificial oxide layer.
[0021] Preferably, in step three, the second ion implantation is a boron ion implantation and the floating ring-shaped doping region is a floating P-type ring-shaped doping region.
[0022] Preferably, in step three, the boron ion implantation is completed by multiple implantations.
[0023] Preferably, in step four, the temperature and time of the heat treatment are controlled to achieve an accurate lateral connection of the floating ring-shaped doping region and the carrier storage layer.
[0024] Preferably, before performing the heat treatment in step four, the method further comprises a step of removing the remaining photoresist layer and the hard mask layer.
[0025] Preferably, the method is used for manufacturing a power semiconductor device with a trench structure.
[0026] Preferably, the power semiconductor device is an insulated gate bipolar transistor.
[0027] As described above, the fine control manufacturing method of the carrier storage layer of the present application has the following beneficial effects:
[0028] 1. Fine control of the doped region in high aspect ratio trench structure is achieved: By using the technology of shallow etching and ion implantation of carrier storage layer first, then deep etching to form high aspect ratio trench, and then filling with photoresist layer and selective exposure and development, the position of subsequent ion implantation can be accurately defined in the specific area (such as the bottom) of the deep trench, solving the problem of accurate selective doping in high aspect ratio morphology.
[0029] 2. Forming an optimized carrier storage structure: The floating ring-shaped doped region is formed by the second ion implantation, and the floating ring-shaped doped region is connected laterally with the previously formed carrier storage layer by accurately controlling the heat treatment, forming a new type of synergistic carrier storage structure.
[0030] 3. Improving the performance of power devices: This fine controlled carrier storage structure can store fewer carriers more effectively, enhancing the internal conductance modulation effect of the device, as shown in the simulation results, which can increase the carrier concentration (such as hole concentration) of the device drift region, thereby significantly reducing the on-state voltage drop (Vce(sat)) of the device, reducing the on-state loss, and expected to improve the current density and energy efficiency of the device.
[0031] 4. Good process compatibility: The method steps proposed in the present application have good compatibility with existing semiconductor manufacturing processes (especially power device process flow), and are easy to integrate into existing production lines. BRIEF DESCRIPTION OF DRAWINGS
[0032] Figure 1 shows the process flow diagram of the present application;
[0033] Figure 2 shows the formation of the first trench of the present application;
[0034] Figure 3 shows the formation of the first protective layer on the surface of the first trench of the present application;
[0035] Figure 4 shows the formation of the carrier storage layer of the present application;
[0036] Figure 5 shows the formation of the second protective layer of the present application;
[0037] Figure 6 shows the formation of the floating ring-shaped doped region of the present application;
[0038] Figure 7A schematic diagram showing the device simulation result of the present application.
[0039] Figure 8 A schematic diagram showing the device simulation result of the present application. DETAILED DESCRIPTION
[0040] Other advantages and effects of the present application can be easily understood by those skilled in the art from the above description. The present application can also be implemented or applied by other different specific embodiments, and the details in the description can be modified or changed based on different views and applications without departing from the spirit of the present application.
[0041] The present application provides a fine control manufacturing method of a carrier storage layer.
[0042] A fine control manufacturing method of a carrier storage layer, comprising the following steps:
[0043] Step one, performing first trench etching on the semiconductor substrate 101 to form a first trench, forming a structure as shown in Figure 2 After the first trench is formed, performing first ion implantation to form a carrier storage layer 104, forming a structure as shown in Figure 4
[0044] In some embodiments, the semiconductor substrate 101 can be a silicon substrate, which is a commonly used substrate material in power semiconductor device manufacturing.
[0045] In some embodiments, before performing the first trench etching in step one, the method further comprises forming a hard mask layer 102 on the semiconductor substrate 101. The hard mask layer 102 can be formed by, for example, depositing a layer of hard mask material (such as silicon nitride SiN or silicon oxide SiO2, etc.) and patterning by photolithography and etching process. The hard mask layer 102 is used to accurately define the position and pattern of the subsequent first trench etching, and is the basis for realizing the precise trench structure.
[0046] In some embodiments, step one can further comprise forming a first protective layer 103 on the surface of the first trench after performing the first trench etching and before performing the first ion implantation, forming a structure as shown in Figure 3 For example, a thin sacrificial oxide layer can be deposited. The first protective layer 103 can be a sacrificial oxide (SACOX). The first protective layer 103 can act as a buffer or scatterer during ion implantation, which helps to control the implantation depth and reduce the damage to the trench surface, and also protects the trench surface in subsequent processes.
[0047] In some embodiments, in step one, the first ion implantation is a low energy ion implantation, which helps to precisely control the implanted impurities in a shallow region near the trench, and lays a foundation for the formation of the carrier storage layer 104, such as the formation of an initial CS (Carrier Storage) layer. Through this step one, the carrier storage layer 104 can be preliminarily formed in the region near the first trench.
[0048] Step two, a second trench etching is performed on the first trench to form a deeper second trench at the bottom of the first trench; then the photoresist layer 106 is filled in the second trench, and the photoresist layer 106 is subjected to exposure and development processing to remove the photoresist layer 106 in a predetermined area;
[0049] In some embodiments, in step two, the second trench is a high aspect ratio trench.
[0050] In some embodiments, in step two, the photoresist layer 106 can be a non-photosensitive photoresist. After filling the high aspect ratio trench with the photoresist layer 106, exposure and development are performed using a separate mask, which can accurately remove the resist in a specific area inside the trench (such as a part of the bottom of the trench or a specific sidewall area), exposing the underlying semiconductor surface. This approach can overcome the precision problem of traditional lithography in high aspect ratio topography, achieve precise definition of the subsequent ion implantation area, and achieve good area selectivity even in complex trench structures, making it possible to precisely form the floating ring-shaped doped region 107.
[0051] Before performing the second ion implantation, in some embodiments, after removing the photoresist layer 106 in step two (such as after stripping and removing the hard mask HM), a second protective layer 105 is formed, forming a structure as shown in Figure 5 Similarly, the second protective layer 105 can also be a sacrificial oxide layer (SACOX). This second protective layer 105, such as the deposited SACOX, can serve as an implantation mask layer or screen oxide layer for the second ion implantation (such as multiple B ion implantations), to precisely control the energy and range of the implanted ions, reduce damage at the bottom of the trench, and ensure that the floating ring-shaped doped region 107 has the desired depth and concentration distribution.
[0052] Step three, performing a second ion implantation in the predetermined area where the photoresist layer 106 is removed, to form a floating ring-shaped doped region 107, forming a structure as shown in Figure 6
[0053] In some embodiments, in step three, the second ion implantation is boron ion implantation, and the floating ring-shaped doped region 107 is a floating P ring. The P-type doping is selected to form a local P-type region in the N-type drift region of an N-channel IGBT, which can effectively influence the carrier distribution of the surrounding region, especially for the minority carriers (holes) when the device is on.
[0054] In some embodiments, in step three, the boron ion implantation can be performed by multiple implantations, for example, using different combinations of energy and dose, which allows more flexibility to adjust the energy and dose of the implantation, and thus more precisely control the peak position, concentration gradient, and depth distribution of the doping concentration of the floating P ring-shaped doped region, to meet the specific requirements of the device design for the electrical characteristics of this region. For example, a buried floating P ring can be achieved.
[0055] In some embodiments, before the heat treatment in step four, a step of removing the remaining photoresist layer 106 and hard mask layer 102 is included. The photoresist layer 106 can be removed by a method of ashing and wet cleaning, and the hard mask layer 102 can be removed by a method of wet etching.
[0056] Step four, heat treatment is performed to connect the floating ring-shaped doped region 107 and the carrier storage layer 104 in the lateral direction, forming a structure as shown in Figure 7 .
[0057] In some embodiments, in step four, the temperature and time of the heat treatment are precisely controlled. The heat treatment is usually an activation annealing step after ion implantation, but can also include other heat process steps in the device manufacturing process. By reasonably designing and controlling the heat budget (combination of temperature and time), the activation and diffusion behavior of the impurities implanted in step one (forming the carrier storage layer 104) and the impurities implanted in step three (forming the floating ring-shaped doped region 107), especially the lateral diffusion (pushing the well), can be precisely controlled. The ultimate goal is to extend the doped region of the floating ring-shaped doped region 107 (e.g., the floating P ring) in the lateral direction until it is connected with the doped region of the carrier storage layer 104 (CS layer) formed in step one, respectively, and the two are also connected or very close in the longitudinal direction, forming a synergistic carrier storage structure. This lateral connection structure is crucial for forming an effective carrier storage function, which can more effectively store minority carriers during device operation, for example, increasing the hole concentration in the drift region.
[0058] The method provided by the embodiment of the present application successfully manufactures a new structure with a specific floating ring-shaped doping region 107 and a lateral connection with the carrier storage layer 104 in a complex trench structure by using selective filling and patterning of the photoresist layer 106 after etching of the high aspect ratio trench, and combining subsequent selective ion implantation and precise heat treatment. The method is particularly suitable for scenarios where precise selective doping is required in specific areas (for example, the bottom or sidewall) of the trench after the deep trench has been formed, and overcomes the difficulty of selective doping in high aspect ratio structures in the traditional process.
[0059] The fine control of the carrier storage structure, as shown in the simulation results of Figure 8 compared with a device without a floating ring structure, can effectively increase the concentration of minority carriers (for example, holes) in the drift region of the device in the on state, that is, enhance the carrier storage effect. The enhanced carrier storage effect can significantly improve the conductance modulation effect of the device, thereby facilitating the reduction of the on-state voltage drop (Vce(sat)) of the device, the reduction of the on-state loss, and the improvement of the current density and overall energy efficiency of the device. At the same time, precise control of the floating ring and the carrier storage layer 104 can also help to optimize the switching characteristics and other performance parameters of the device.
[0060] In some embodiments, the method can be used to manufacture various power semiconductor devices with trench structures. The technical idea of the method is not limited to a specific device type, and any semiconductor device that needs to utilize a trench structure and control precise doping to optimize carrier distribution and storage effect, especially those with high aspect ratio trench structures, can benefit from the technical solutions of the embodiments of the present application.
[0061] In some specific embodiments, the power semiconductor device is an insulated gate bipolar transistor (IGBT), for example, for manufacturing an injection enhanced IGBT (IE-IGBT) or other advanced structure IGBT. The method forms a fine control of the carrier storage structure (lateral connection of the CS layer and the floating P ring), which provides an effective process solution for further improving the performance of the IGBT device, especially in reducing the on-state voltage drop and improving the power density.
[0062] Although the present application is described in conjunction with an IGBT, those skilled in the art will understand that the method and structure proposed by the present application can also be applied to other types of power semiconductor devices, such as power MOSFETs, super-junction devices, or any other device containing high aspect ratio trenches and requiring fine doping control.
[0063] It should be noted that the terms used in the embodiments of the present application, such as "first", "second", etc., are only used for differentiation and description, and do not represent a specific order or importance. Specific process parameters, such as etching depth, ion implantation energy and dose, material type of non-photosensitive glue, exposure and development conditions, heat treatment temperature and time, etc., can be selected and optimized according to specific device design requirements and available process conditions, and should not be regarded as a limitation on the present application.
[0064] It should be noted that the diagrams provided in the embodiments only illustrate the basic concept of the present application in a schematic manner, and only show the components related to the present application in the diagrams, not the number, shape and size of the components when actually implemented. The actual implementation of each component may be arbitrarily changed in shape, number and proportion, and the layout pattern of the components may be more complex.
[0065] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical idea disclosed by the present application should be covered by the claims of the present application.
Claims
1. A method for finely controlling the manufacturing of a carrier storage layer, characterized in that: At least: Step 1: performing a first trench etching on the semiconductor substrate to form a first trench; and after the first trench is formed, performing a first ion implantation to form a carrier storage layer; Step 2: performing a second trench etching on the first trench to form a deeper second trench at the bottom of the first trench; then filling the second trench with a photoresist layer, and performing exposure and development processing on the photoresist layer to remove the photoresist layer in a predetermined area; Step 3: performing a second ion implantation in the predetermined area where the photoresist layer is removed to form a floating ring-shaped doped region; Step 4: performing heat treatment to connect the floating ring-shaped doped region to the carrier storage layer in a lateral direction.
2. The method for finely controlling the manufacturing of a carrier storage layer according to claim 1, characterized in that: The semiconductor substrate is a silicon substrate.
3. The method for finely controlling the manufacturing of a carrier storage layer according to claim 1, wherein: Before performing the first trench etching in step 1, the method further includes: forming a hard mask layer on the semiconductor substrate for defining the first trench pattern.
4. The method for finely controlling the manufacturing of a carrier storage layer according to claim 1, wherein: In step 1, the implantation energy of the first ion implantation enables the implanted impurities to be precisely controlled in a shallow region close to the trench.
5. The method for finely controlling the manufacturing of a carrier storage layer according to claim 1, wherein: Step one also includes: forming a first protection layer on the surface of the first trench after performing the first trench etching and before performing the first ion implantation.
6. The method for finely controlling the manufacturing of a carrier storage layer according to claim 1, wherein: In step 2, the second trench is a high aspect ratio trench.
7. The finely controlled manufacturing method for a carrier storage layer according to claim 1, characterized in that: In step 2, the photoresist layer is a non-photosensitive photoresist.
8. The method for finely controlling the manufacturing of a carrier storage layer according to claim 5, characterized in that: Also includes: After removing the photoresist layer in step 2 and before performing the second ion implantation in step 3, a second protective layer is formed.
9. The finely controlled manufacturing method for a carrier storage layer according to claim 5 or 8, characterized in that: The first protective layer and / or the second protective layer is a sacrificial oxide layer.
10. The method for finely controlling the manufacturing of a carrier storage layer according to claim 1, characterized in that: In step three, the second ion implantation is boron ion implantation, and the floating annular doped region is a floating P-type annular doped region.
11. The method for finely controlling the manufacturing of a carrier storage layer according to claim 10, characterized in that: In step three, the boron ion implantation is completed through multiple implantations.
12. The method for finely controlling the manufacturing of a carrier storage layer according to claim 1, wherein: In step four, the temperature and time of the heat treatment are controlled to achieve precise lateral connection between the floating ring doped region and the carrier storage layer.
13. The method for finely controlling the manufacturing of a carrier storage layer according to claim 3, characterized in that: Before performing the heat treatment in step 4, the method further includes removing the remaining photoresist layer and the hard mask layer.
14. The finely controlled manufacturing method for a carrier storage layer according to any one of claims 1 to 13, characterized in that: The method is used for manufacturing a power semiconductor device with a trench structure.
15. The method for finely controlling the manufacturing of a carrier storage layer according to claim 14, characterized in that: The power semiconductor device is an insulated gate bipolar transistor.