Solar cell and photovoltaic module

Abstract

The application provides a solar cell and a photovoltaic module, and belongs to the technical field of semiconductors. The solar cell comprises a silicon substrate, wherein the surface of the silicon substrate comprises: a plurality of first recessed regions, each extending into a strip shape along a first direction and being spaced apart along a second direction intersecting the first direction; and a plurality of first protruding regions, the first protruding regions being adjacent to the first recessed regions. The first recessed regions and the first protruding regions of the surface of the silicon substrate form a first texture structure, while ensuring light trapping effect, due to the lack of corner structures of a traditional tower base structure, the film layer is more uniformly deposited on the silicon substrate, and the quality of the deposited film layer is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a solar cell and a photovoltaic module. Background Technology

[0002] In the production of solar cells, silicon substrates typically undergo alkaline polishing to obtain a polished surface with angular, traditional tower-like structures. The morphology of this polished surface affects both the quality of the deposited film, thus influencing passivation, and the light-trapping effect, thereby impacting the light utilization efficiency of the solar cell. Therefore, the polishing of the silicon substrate has a significant impact on the efficiency of solar cells. Summary of the Invention

[0003] In view of the above, in order to at least partially solve at least one of the aforementioned technical problems, this application provides a solar cell and a photovoltaic module.

[0004] To achieve the above objectives, the technical solution of this application is as follows:

[0005] According to one embodiment of this application, a solar cell is provided, comprising: a silicon substrate, wherein the silicon substrate includes two opposing surfaces, at least one surface having a first texture structure, the first texture structure including: a plurality of first recessed regions; and a plurality of first raised regions, the first raised regions being adjacent to the first recessed regions.

[0006] According to an embodiment of this application, each of the first recessed regions extends into a strip shape along a first direction, and a plurality of first recessed regions are distributed at intervals along a second direction intersecting the first direction.

[0007] According to an embodiment of this application, the first recessed region has a protrusion extending in a second direction, and the first recessed region is divided into a multi-segment structure by the protrusion.

[0008] According to embodiments of this application, the multi-segment structure is at least one of bamboo joint shape or candied hawthorn shape; and / or, the projection of the protrusion on the first recessed area is at least one of cross shape, straight shape, or curved shape.

[0009] According to an embodiment of this application, the height of the protrusion is lower than the height of the first protrusion area adjacent to the protrusion.

[0010] According to embodiments of this application, at least a portion of the first recessed area has first pits distributed in a dotted pattern along a first direction; and / or, at least a portion of the plurality of first recessed areas has at least one second pit, the second pit having a shape of one or more combinations of cross-shaped, linear, and groove-shaped features; and / or, the cross-sectional shape of the first recessed area is a combination of one or more combinations of V-shaped, arc-shaped, rectangular, and trapezoidal features; and / or, at the location where the first recessed area and the first raised area are connected, there are third pits discontinuously distributed along the first direction, and there are protrusions between adjacent third pits.

[0011] According to an embodiment of this application, the number of first pits located in a first recessed area is 1 to 30; and / or, the number of second pits is less than the number of first pits.

[0012] According to an embodiment of this application, the spacing between adjacent first protrusions in the second direction is 1~10μm, and the depth of the first depression is 0.2~2μm; and / or, the spacing between two adjacent first depressions is 2~10μm; and / or, the number of first depressions is 3~20 within a width range of 100μm along the second direction.

[0013] According to an embodiment of this application, the surface of the silicon substrate further includes at least one crack, randomly distributed on the surface of the silicon substrate.

[0014] According to an embodiment of this application, the projection of the first protrusion region onto the surface of the silicon substrate in the direction of extension is at least one of a straight line, a broken line, a curve, a candied hawthorn shape, or a dot shape.

[0015] According to an embodiment of this application, the surface of the silicon substrate further includes a second texture structure, the second texture structure including a second recessed region, the second recessed region including a plurality of sub-recessed structures distributed in a non-linear manner; wherein, the depth of the second recessed region is less than the depth of the first recessed region.

[0016] According to an embodiment of this application, the first textured structure further includes a first sidewall located between the first recessed area and the first raised area; the first sidewall has a folded portion.

[0017] According to an embodiment of this application, the wrinkled portion includes a plurality of layered structures protruding from the first sidewall, the plurality of layered structures being stacked along the thickness direction of the silicon substrate to form a linear transverse texture; and / or, the wrinkled portion includes a plurality of dot-like protrusions stacked on the first sidewall to form a scale-like protrusion structure; and / or, the first sidewall further includes a plurality of steps stacked along the thickness direction of the silicon substrate to form a stepped structure.

[0018] According to embodiments of this application, the extension length of the layered structure along the surface of the silicon substrate is greater than the thickness of the layered structure; and / or, the height of the scale-like protrusions protruding in the direction away from the first sidewall is 0.1~1μm.

[0019] According to an embodiment of this application, the first texture structure further includes: a gentle slope adjacent to the first sidewall, the surface of the gentle slope having gentle hill stripes, the gentle hill stripes intersecting or being opposite to the linear transverse texture.

[0020] According to an embodiment of this application, the slope angle of the first sidewall is greater than the slope angle of the surface of the gentle slope; and / or, the slope angle of the first sidewall is greater than or equal to 25° and less than or equal to 75°, and the slope angle of the surface of the gentle slope is less than 25° and greater than 2°.

[0021] According to an embodiment of this application, the first recessed area or the first raised area is island-shaped, and the first sidewall extends into a ring or C-shape.

[0022] According to an embodiment of this application, the first sidewall is further provided with: a first sidewall bifurcation structure, including a first sub-sidewall extending toward the first recessed area; and / or, the first sidewall is further provided with: a second sidewall bifurcation structure, including a second sub-sidewall extending toward the first protruding area.

[0023] According to embodiments of this application, the first sub-sidewall and / or the second sub-sidewall each have a plurality of dot-like protrusions, a plurality of layered structures, and / or a plurality of steps.

[0024] According to an embodiment of this application, one side of the first recessed area is adjacent to a first sidewall, and the other side may be adjacent to another first sidewall or a gentle slope.

[0025] According to an embodiment of this application, the surface of the silicon substrate further includes a second textured structure; the flatness of the second textured structure is greater than the flatness of the first sidewall, but less than the flatness of the first recessed area.

[0026] According to embodiments of this application, at least a portion of the first texture structure and / or the second texture structure has a gentle slope, the surface of the gentle slope has a substructure with an arcuate or polygonal profile, the substructure has a plurality of second recessed areas, and the second recessed areas overlap to form a second raised area.

[0027] According to embodiments of this application, the area of ​​the substructure with the arc-shaped profile accounts for 3 to 40% of the width or area of ​​the silicon substrate surface.

[0028] According to an embodiment of this application, at least a portion of the second protrusion region has a protruding end that protrudes outward from the silicon substrate, and the surface of the protruding end has a smooth transition surface.

[0029] According to embodiments of this application, the first sidewall extends along a first direction, with an extension length in the first direction greater than or equal to 2 μm and less than or equal to 300 μm; and / or, in a second direction intersecting the first direction, the width of the first sidewall is 0.5 to 3 μm, and the depth in the thickness direction of the silicon substrate is 0.1 to 10 μm; and / or, within a width range of 100 μm along the second direction, the number of first sidewalls is 1 to 200; and / or, the uniformity of the film layer on the silicon substrate is less than 10%, and the film layer includes a doped conductive layer and / or a passivation or antireflection layer.

[0030] According to an embodiment of this application, the solar cell further includes: a plurality of electrodes located on the surface of a silicon substrate, each electrode extending in the same or substantially the same direction as a first direction and spaced apart in a second direction; wherein, in the second direction, the number of first recessed areas covered by one electrode is 1 to 20.

[0031] According to an embodiment of this application, the solar cell further includes: a stacked film disposed on at least one side of a silicon substrate; the stacked film includes: a doped conductive layer extending along a first direction and spaced apart along a second direction, wherein the first textured structure is located on the surface of the silicon substrate corresponding to the doped conductive layer; and a passivation or antireflection layer located on the surface of the doped conductive layer away from the silicon substrate; wherein, in the second direction, the number of first recessed regions corresponding to one doped conductive layer is 10 to 100.

[0032] According to an embodiment of this application, the doped conductive layer includes N-type doped conductive layers and P-type doped conductive layers alternately arranged on one side of a silicon substrate; wherein, the first recessed region in the first texture structure corresponding to the P-type doped conductive layer is more sparsely distributed than the first recessed region in the first texture structure corresponding to the N-type doped conductive layer; and / or, the roughness of the first sidewall in the first texture structure corresponding to the N-type doped conductive layer is greater than the roughness of the first sidewall in the first texture structure corresponding to the P-type doped conductive layer; and / or, the number of first sidewalls in the first texture structure corresponding to the P-type doped conductive layer is less than the number of first sidewalls in the first texture structure corresponding to the N-type doped conductive layer.

[0033] According to an embodiment of this application, the doped conductive layer is a first doped conductive layer disposed on one side surface of a silicon substrate. The first doped conductive layer is located on the back side of the battery, and there is a first gap between adjacent first doped conductive layers. The stacked film further includes: a second doped conductive layer disposed on the other side surface of the silicon substrate, and the second doped conductive layer is located on the front side of the battery; wherein, the first texture structure is located on the silicon substrate corresponding to the first doped conductive layer and on the silicon substrate corresponding to the first gap, the first recessed area in the first texture structure corresponding to the first gap on one side surface of the silicon substrate is more densely distributed than the first recessed area in the first texture structure corresponding to the first doped conductive layer; and / or, the roughness of the first sidewall in the first texture structure corresponding to the first gap on one side surface of the silicon substrate is greater than the roughness of the first sidewall in the first texture structure corresponding to the first doped conductive layer; and / or, the number of first sidewalls in the first texture structure corresponding to the first gap on one side surface of the silicon substrate is greater than the number of first sidewalls in the first texture structure corresponding to the first doped conductive layer.

[0034] According to an embodiment of this application, the doped conductive layer is a second doped conductive layer disposed on another surface of the silicon substrate. The second doped conductive layer is located on the front side of the battery, and there is a second gap between adjacent second doped conductive layers. The stacked film further includes: a first doped conductive layer disposed on one side surface of the silicon substrate, and the first doped conductive layer is located on the back side of the battery; wherein, the first texture structure is located on the silicon substrate surface corresponding to the first doped conductive layer and on the silicon substrate surface corresponding to the second doped conductive layer, and the first recessed area in the first texture structure corresponding to the second doped conductive layer on the other side surface of the silicon substrate is more sparsely distributed than the first recessed area in the first texture structure corresponding to the first doped conductive layer on one side surface of the silicon substrate; and / or, the number of first sidewalls in the first texture structure corresponding to the second doped conductive layer on the other side surface of the silicon substrate is less than the number of first sidewalls in the first texture structure corresponding to the first doped conductive layer on one side surface of the silicon substrate; and / or, the roughness of the first sidewall in the first texture structure corresponding to the first doped conductive layer on one side surface of the silicon substrate is greater than the roughness of the first sidewall in the first texture structure corresponding to the second doped conductive layer on the other side surface of the silicon substrate.

[0035] According to an embodiment of this application, the doped conductive layer is a first doped conductive layer disposed on one side surface of a silicon substrate. The first doped conductive layer is located on the back side of the battery, and a first spacer region is formed between adjacent first doped conductive layers. The stacked film further includes: a second doped conductive layer extending along a first direction and spaced along a second direction on the other side surface of the silicon substrate. The second doped conductive layer is located on the front side of the battery, and a second spacer region is formed between adjacent second doped conductive layers. A first texture structure is located on the silicon substrate surfaces corresponding to the first doped conductive layer, the second doped conductive layer, the first spacer region, and the second spacer region. The first recessed area in the first texture structure corresponding to the first spacer region on one side surface of the silicon substrate is relatively... The first recessed region in the first texture structure corresponding to the first doped conductive layer is more densely distributed; and / or, the first recessed region in the first texture structure corresponding to the second spacer region on the other side surface of the silicon substrate is more densely distributed than the first recessed region in the first texture structure corresponding to the second doped conductive layer; and / or, the number of first sidewalls in the first texture structure corresponding to the first spacer region on one side surface of the silicon substrate is greater than the number of first sidewalls in the first texture structure corresponding to the first doped conductive layer; and / or, the roughness of the first sidewall in the first texture structure corresponding to the second spacer region on the other side surface of the silicon substrate is greater than the roughness of the first sidewall in the first texture structure corresponding to the second doped conductive layer.

[0036] According to an embodiment of this application, the second doped conductive layer is a P-type doped conductive layer; wherein, on the other side surface of the silicon substrate, the first recessed region in the first texture structure corresponding to the second doped conductive layer is more sparsely distributed than the first recessed region in the first texture structure corresponding to the first doped conductive layer on one side surface of the silicon substrate; and / or, the roughness of the first sidewall in the first texture structure corresponding to the first doped conductive layer on one side surface of the silicon substrate is greater than the roughness of the first sidewall in the first texture structure corresponding to the second doped conductive layer on the other side surface of the silicon substrate; and / or, the number of first sidewalls in the first texture structure corresponding to the second doped conductive layer on the other side surface of the silicon substrate is less than the number of first sidewalls in the first texture structure corresponding to the first doped conductive layer on one side surface of the silicon substrate.

[0037] According to an embodiment of this application, the solar cell further includes: a stacked film disposed on both sides of a silicon substrate, the stacked film including: a first doped conductive layer disposed entirely on one side of the silicon substrate, a first textured structure being located at least on the silicon substrate surface corresponding to the first doped conductive layer; a second doped conductive layer disposed entirely within the other side of the silicon substrate, the other side of the silicon substrate corresponding to the second doped conductive layer having a pyramid structure; and a passivation or antireflection layer located on the surface of the doped conductive layer away from the silicon substrate.

[0038] According to another embodiment of this application, a photovoltaic module is also provided, including the solar cell described above.

[0039] According to the embodiments of this application, the solar cell includes a silicon substrate with a first recessed region and a first raised region adjacent to the first recessed region, forming a first textured structure. The first recessed region extends into a strip and / or forms a sidewall with an undulating structure. While ensuring light trapping effect, the absence of sharp edges from traditional tower bases facilitates more uniform deposition of the film layer on the silicon substrate, improving the quality of the deposited film layer. This, in turn, enhances passivation effect, improves electrical contact performance, and increases the cell's conversion efficiency. Accordingly, the photovoltaic module including the solar cell of this application also has a high conversion efficiency. Attached Figure Description

[0040] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0041] Figure 1 This is an optical microscope image of the first texture structure of a silicon substrate according to an embodiment of this application;

[0042] Figure 2 The images shown are three-dimensional optical microscope images of the silicon substrate according to an embodiment of this application, wherein (a) is a continuously distributed first recessed region and (b) is a discontinuously distributed first recessed region.

[0043] Figure 3 This is a schematic diagram of the morphology of the first recessed region in an embodiment of this application;

[0044] Figure 4 This is a three-dimensional optical microscope image of a silicon substrate according to another embodiment of this application, wherein (a) is a bamboo-shaped multi-segment structure, (b) is a candied hawthorn-shaped multi-segment structure, (c) is a cross-shaped protrusion, (d) is a first protrusion area combining straight lines and curves, (e) is a dotted first protrusion area, (f) is a broken-line first protrusion area, and (g) is a candied hawthorn-shaped first protrusion area.

[0045] Figure 5 for Figure 4 A three-dimensional perspective view;

[0046] Figure 6 A scanning electron microscope (SEM) image of the first recessed area in a bamboo-joint shape, according to another embodiment of this application;

[0047] Figure 7 SEM image of the first recessed area in another embodiment of this application, which is shaped like a candied hawthorn skewer;

[0048] Figure 8 This is a schematic diagram of the morphology of the protrusion within the first recessed area according to an embodiment of this application.

[0049] Figure 9 This is a schematic diagram of the topography of the first protrusion region in an embodiment of this application;

[0050] Figure 10 This is a three-dimensional optical microscope image of a silicon substrate according to another embodiment of this application, wherein (a) is a first pit with a dotted distribution, (b) is a second pit with a groove shape, (c) is a second pit with a line shape, (d) is a second pit with a cross shape, and (e) is a third recessed area.

[0051] Figure 11 for Figure 10 A three-dimensional perspective view;

[0052] Figure 12 This is a graph showing the height variation of the first recessed area at the sampling location in yet another embodiment of this application.

[0053] Figure 13 This is a cross-sectional SEM image of the first recessed region in another embodiment of this application, wherein (a) is a cross-sectional SEM image and (b) is an optical microscope image;

[0054] Figure 14 This is an optical microscope image of a silicon substrate according to another embodiment of this application, wherein (a) shows a crack located in the first recessed region, (b) shows a crack located in the first protruding region, and (c) shows a crack located in the third recessed region.

[0055] Figure 15 This is a top SEM view of the first sidewall according to another embodiment of this application;

[0056] Figure 16 This is a magnified partial SEM image of the folded portion according to another embodiment of this application, wherein (a) is a side view of the folded portion including multiple layered structures, (b) is a top view of the folded portion including multiple dotted protrusions, (c) is a combination of layered structures and steps, and (d) is a combination of dotted protrusions and steps.

[0057] Figure 17 The following are top-view SEM images of the first sidewall extending continuously or discontinuously in another embodiment of this application, wherein (a) shows a continuous linear extension, (b) shows a discontinuous linear extension, (c) shows an extension into a ring shape, and (d) shows an extension into a C-shape.

[0058] Figure 18 This is a top SEM view of the first sidewall bifurcation structure and the second sidewall bifurcation structure according to another embodiment of this application;

[0059] Figure 19 This is a top-view SEM image of the first texture structure according to another embodiment of this application;

[0060] Figure 20This is a top-view SEM image of the second texture structure according to another embodiment of this application, wherein (a) and (b) are examples of different morphologies of the second recessed area, (c) is the second texture structure marked in (a), and (d) is the second texture structure marked in (b);

[0061] Figure 21 This is a side view SEM image of the second texture structure according to yet another embodiment of this application;

[0062] Figure 22 This is a side-view SEM image of the film layer on the silicon substrate according to an embodiment of this application;

[0063] Figure 23 This is a schematic diagram of the overall structure of the solar cell according to an embodiment of this application;

[0064] Figure 24 This is a schematic diagram of the overall structure of a solar cell according to another embodiment of this application;

[0065] Figure 25 This is a schematic diagram of the overall structure of a solar cell according to another embodiment of this application;

[0066] Figure 26 This is a schematic diagram of the overall structure of a solar cell according to another embodiment of this application.

[0067] In the above figures, the meanings of the reference numerals are as follows:

[0068] 100: Silicon substrate;

[0069] T1: First texture structure;

[0070] 110: First depression area;

[0071] 111: Protrusion, 112: First recess, 113: Second recess;

[0072] 114: Third pit; 115: Protrusion;

[0073] 120: First raised area;

[0074] 121: Gentle slope; 1211: Surface of gentle slope; 1212: Stripes on gentle hill.

[0075] 130: Crack;

[0076] 140: First sidewall,

[0077] 141: Folds;

[0078] 1411: Layered structure; 1412: Dot-like protrusions;

[0079] 142: Steps;

[0080] 150: First sidewall bifurcated structure;

[0081] 151: First child sidewall;

[0082] 160: Second sidewall bifurcated structure;

[0083] 161: Second child sidewall;

[0084] T2: Second texture structure;

[0085] 210: Second depression area;

[0086] 211: Sub-concave structure,

[0087] 220: Second protrusion area;

[0088] 221: Protruding end;

[0089] 102: Laminated membrane;

[0090] 1021: First doped conductive layer; 1022: Second doped conductive layer;

[0091] 1031: First interface passivation layer; 1032: Second interface passivation layer;

[0092] 104: Passivation or anti-reflection layer;

[0093] 1041: First passivation or anti-reflection layer; 1042: Second passivation or anti-reflection layer;

[0094] 200: Electrode;

[0095] 201: First electrode; 202: Second electrode;

[0096] S1: First direction, S2: Second direction. Detailed Implementation

[0097] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0098] In the following detailed description, numerous specific details are set forth for ease of explanation to provide a thorough understanding of the embodiments of this application. However, it will be apparent that one or more embodiments may be implemented without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.

[0099] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "comprising" as used herein indicates the presence of features, steps, or operations, but does not exclude the presence or addition of one or more other features.

[0100] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0101] In this application, the relative position between two components (e.g., a membrane or region), as referred to by terms such as "above," "on," or "above," can mean that the two components are in direct contact or that they are not in direct contact. Similarly, the relative position between two components, as referred to by terms such as "below," "under," or "below," can mean that the two components are in direct contact or that they are not in direct contact. For example, when one component (e.g., a membrane or region) is referred to as "on another component," it can be directly on the other component, or there may be other components between them. On the other hand, when a component is referred to as "directly on another component," there are no components between them. Furthermore, when one component is referred to as "on another component," the two components have a vertical relationship in the planar view, and this component can be above or below the other component, thus this vertical relationship depends on the orientation of the device.

[0102] In solar cells, the surface morphology of the silicon substrate affects the light reflectivity and the deposition quality of the film. Polished surfaces are more conducive to the deposition of high-quality films than textured surfaces; however, their reflectivity increases, resulting in poorer light trapping.

[0103] In the process of realizing the concept of this application, it was found that the traditional tower base structure formed on the polished surface has many sharp edges, which will affect the deposition of the film layer to a certain extent and is not conducive to further improvement of the electrical performance of solar cells.

[0104] Specifically, according to some embodiments of this application, a solar cell is provided, comprising: a silicon substrate, the silicon substrate including two opposing surfaces, at least one surface having a first textured structure.

[0105] According to some embodiments of this application, the silicon substrate can be an N-type, P-type, or intrinsic crystalline silicon substrate, and can be selected from a semiconductor material of monocrystalline silicon, polycrystalline silicon, and microcrystalline silicon. It can be further selected as an N-type or P-type monocrystalline silicon substrate. The cell conversion efficiency based on the monocrystalline silicon substrate is higher than that of other types such as polycrystalline silicon cells.

[0106] N-type silicon substrates are obtained by introducing donor impurities such as group VA elements like phosphorus (P), arsenic (As), or antimony (Sb) into these semiconductor materials, or p-type silicon substrates are obtained by introducing acceptor impurities such as group IIIA elements like boron (B), aluminum (Al), or gallium (Ga) into these semiconductor materials.

[0107] According to some embodiments of this application, the first textured structure can be distributed on one surface of the silicon substrate, or simultaneously distributed on two opposing surfaces of the silicon substrate. When the silicon substrate is used in a solar cell, the surface having the first textured structure can be a backlight surface or a light-receiving surface. Furthermore, the first textured structure can be distributed across the entire surface or partially on at least one surface, depending on the specific application scenario.

[0108] To facilitate the explanation of the first texture structure of the silicon substrate, Figure 1 This is an optical microscope image of a silicon substrate according to an embodiment of this application; Figure 2 This is a three-dimensional optical microscope image of the silicon substrate according to an embodiment of this application; as shown... Figure 1 and Figure 2 As shown, the first texture structure T1 includes a plurality of first recessed areas 110 and a plurality of first raised areas 120, wherein the first raised areas 120 are adjacent to the first recessed areas 110.

[0109] According to some embodiments of this application, each of the first recessed regions 110 extends into a strip shape along the first direction S1, and a plurality of first recessed regions 110 are distributed at intervals along the second direction S2 intersecting the first direction S1.

[0110] This application discovers that by selecting appropriate process conditions in the alkaline polishing process, such as controlling the polishing temperature, time, and polishing slurry composition, it is possible to suppress specific crystal phases, increasing the influence factor of line marks on the native silicon wafer during the polishing process. This allows for the regulation of the first texture structure of the polished surface, resulting in a first recessed region extending into a strip and a first raised region adjacent to the first recessed region on the surface of the silicon substrate. Because the first texture structure exhibits a roughly linear extension, the sharp edges are weakened, thus having fewer or even no sharp edges like those of a traditional pyramidal structure. This facilitates the more uniform deposition of films such as doped conductive layers, passivation layers, or antireflection layers on the silicon substrate, improving the quality of the deposited films. This approach can simultaneously improve light trapping effects, passivation effects, and electrical contact performance, thereby enhancing the conversion efficiency of the solar cell.

[0111] Since the film layers, such as a stacked film including a doped conductive layer, passivation layer, or antireflection layer, are conformally deposited on the silicon substrate 100, the same first texture structure can be observed on the surface of the solar cell. Therefore, the structure on the surface of the silicon substrate in this application can be obtained directly by testing the first texture structure in the solar cell product, or by removing the stacked film on the surface of the cell to expose the surface of the silicon substrate before testing. The testing method can be, for example, scanning electron microscopy (SEM) or optical microscopy.

[0112] According to some embodiments of this application, the first recessed region 110 may extend continuously and / or discontinuously into a strip shape along the first direction S1. For example... Figure 2 As shown in Figure (a), the first recessed region 110 extends continuously into a strip shape, while Figure (b) shows the first recessed region 110 extending discontinuously into a strip shape. However, it is not limited to this. It is understood that, due to the influence of actual processes, individual first recessed regions 110 may also have a partially non-strip-shaped distribution structure, such as being distributed in an island-like shape. The above-mentioned "strip shape" means that the extension length of the first recessed region 110 in the first direction S1 is greater than its width in the second direction S2. For example, the ratio of the length to the width of the first recessed region 110 can be at least greater than 2:1, 5:1, 10:1, or 20:1, etc., and further, it can be less than 200:1, 100:1, or 50:1, etc.

[0113] According to some embodiments of this application, for example... Figure 2 As shown in Figure (b), the first recessed area 110 has a protrusion 111 extending in the second direction, and the first recessed area 110 is divided into a multi-segment structure by the protrusion 111.

[0114] Thus, by configuring the first recessed region 110 as a multi-segment structure including protrusions 111, it helps to increase surface roughness. Therefore, when this multi-segment structure of the first recessed region 110 is applied to the light-receiving area, it can improve the light-trapping effect. The light-receiving area corresponds to the front and / or back of the battery, and can at least correspond to the non-electrode area of ​​that surface. Furthermore, when depositing a film or fabricating electrodes on the silicon substrate 100, this multi-segment structure also helps to disperse stress, promotes uniform film growth, and improves electrode quality, thereby improving passivation effect and electrical contact performance.

[0115] According to some embodiments of this application, the height of the protrusion 111 may be lower than the height of the first protrusion region 120, especially lower than the height of the first protrusion region 120 adjacent to the protrusion 111. Here, "height" refers to the dimension in the direction away from the surface of the silicon substrate 100. Thus, the protrusion 111 does not create sharp edges, thereby ensuring the deposition quality of the film layer. Simultaneously, when the protrusion 111 is applied to the light-receiving area, it positively enhances the light-trapping effect. The light-receiving area corresponds to the front and / or back of the battery, and may at least correspond to the non-electrode area of ​​that surface.

[0116] According to some embodiments of this application, the multi-segment structure can take the form of one or more combinations of various patterns, such as bamboo joint shape, candied hawthorn shape, etc. Figure 3 This is a schematic diagram of the morphology of the first recessed region according to an embodiment of this application; wherein, the dashed box shows the area where the first recessed region 110 is located, and the multi-segment structure can be presented as follows. Figure 3 The leftmost image shows a bamboo-like shape, or something similar. Figure 3 The second one from the left is shaped like a candied hawthorn, or like... Figure 3 The third image from the left shows a combination of bamboo-joint and candied hawthorn shapes. This is understandable. Figure 3 The accompanying drawing merely illustrates the multi-segment structure of different patterns; one or more patterns can be combined in one or more first recessed areas 110 according to the actual situation. However, this is not a limitation; the first recessed area can also adopt a multi-segment structure of other types of patterns, or the first recessed area can be as follows: Figure 3 The one on the right is a continuously extending strip.

[0117] For example, Figure 4 This is a three-dimensional optical microscope image of a silicon substrate according to another embodiment of this application; Figure 5 for Figure 4 A stereoscopic view, such as Figure 4 and Figure 5 As shown in the figures, (a) illustrates that the multi-segment structure can be bamboo-shaped, while (b) shows that it can be candied hawthorn-shaped. Of course, it is not limited to these shapes; other regular or irregular shapes are also possible. A multi-segment structure with a suitable morphology, while having appropriate surface roughness, helps to further reduce angular structures, thereby improving the deposition quality of the film layer on the silicon substrate 100 and the quality of the fabricated electrodes.

[0118] According to some embodiments of this application, in order to characterize the multi-segmented structure of the present application, which is shaped like bamboo joints or candied hawthorn skewers, the aforementioned optical microscope can be used for characterization. However, it is not limited to this; the aforementioned multi-segmented structure can also be observed using a scanning electron microscope (SEM). For example, Figure 6 This is a scanning electron microscope (SEM) image of the first recessed area in another embodiment of this application, showing a bamboo-like shape. Figure 6As shown, the multi-segment structure can be bamboo-shaped; or Figure 7 This is a SEM image of the first recessed area in another embodiment of the present application, which is shaped like a candied hawthorn skewer. Figure 7 As shown, the multi-segment structure can be shaped like a candied hawthorn skewer.

[0119] According to some embodiments of this application, the projection of the protrusion 111 on the first recessed area 110 can be at least one of the following: cross shape, straight line shape, curved shape, etc. Figure 8 This is a schematic diagram of the morphology of the protrusion within the first recessed area according to an embodiment of this application; wherein, the dashed box indicates the area where the first recessed area 110 is located, and the protrusion 111 can be shaped as follows: Figure 8 The leftmost line is a straight line, or as shown in the image. Figure 8 The second one from the left shows a cross shape, or the third one from the left shows a curved shape, or as shown in Figure 8. Figure 8 The rightmost example shows a combination of straight lines, intersections, and curves. It is understandable that... Figure 8 The protrusions 111 of different patterns are only illustrated schematically in the same figure. One or more of these patterns can be combined in one or more first recessed areas 110 according to the actual situation.

[0120] For example, Figure 4 As shown, (a) illustrates a curved protrusion 111, (b) illustrates a protrusion 111 combining straight and curved shapes, and (c) illustrates a cross-shaped protrusion 111. It is worth noting that the cross-shaped protrusion is beneficial for further improving surface roughness, thereby enhancing the light-trapping effect when the protrusion 111 is applied to the light-receiving area, which corresponds to the front and / or back of the battery, and can at least correspond to the non-electrode area of ​​that surface.

[0121] According to some embodiments of this application, the first texture structure T1 of this application includes a first protrusion region 120, and the projection of the first protrusion region 120 on the surface extension direction of the silicon substrate 100 is at least one of a straight line, a broken line, a curve, a candied hawthorn shape, and a dot shape. Figure 9 This is a schematic diagram of the topography of the first protruding region according to an embodiment of this application; wherein, the dashed box indicates the area where the first recessed region 110 is located. The first protruding region 120 can be as follows: Figure 9 The leftmost line is a straight line, or as shown in the image. Figure 9 The second one from the left is shaped like a candied hawthorn, or like... Figure 9 The curve shown in the third image on the left, or as... Figure 9 The second one from the right shows a broken line shape, or as shown in the image. Figure 9 The rightmost example shows a combination of straight lines and dotted protrusions. It is understandable that... Figure 9The first raised area 120 with different patterns is only illustrated schematically in the same figure. One or more patterns can be combined in one or more first raised areas 120 according to the actual situation.

[0122] For example, Figure 4 As shown in the figures, (d) illustrates a combination of straight lines and curves for the first protrusion region 120, (e) shows the first protrusion region 120 as dot-like protrusions, (f) shows the first protrusion region 120 as a broken line shape, and (g) shows the first protrusion region 120 as a candied hawthorn shape. However, it is not limited to these shapes. These morphologies of the first protrusion region 120 reduce the sharp edges of the first texture structure T1 on the silicon substrate 100, which is beneficial to improving the film deposition quality on the surface of the silicon substrate 100 and the quality of the fabricated electrodes.

[0123] According to other embodiments of this application, this application also provides a solar cell, including at least one silicon substrate with a first textured structure on its surface. Figure 10 This is a three-dimensional optical microscope image of a silicon substrate according to another embodiment of this application. Figure 11 for Figure 10 A stereoscopic view; such as Figure 10 Figure (a) and Figure 11 As shown in Figure (a), the first texture structure T1 of this application includes a plurality of first recessed regions 110, each extending in a strip shape along a first direction S1 and spaced apart along a second direction S2 intersecting the first direction S1. At least a portion of the first recessed regions 110 have a plurality of first pits 112, which are distributed in a dotted pattern along the first direction and do not extend along the first direction. The aforementioned "first pits 112" are recessed into the silicon substrate relative to the bottom surface of other areas of the first recessed region 110, forming a hole structure nested within the first recessed region 110. In this case, the opening of the first pit 112 is located at the bottom wall of the first recessed region 110.

[0124] By providing first pits 112 distributed in a dotted pattern in the first recessed area 110, it is beneficial to further increase the surface roughness of the first recessed area 110. When the first recessed area 110 with the first pits 112 is applied to the light-receiving area, the light trapping effect can be improved, and the electrical contact performance of the electrode can also be effectively improved. The light-receiving area corresponds to the front and / or back of the battery, and can at least correspond to the non-electrode area of ​​the surface.

[0125] Optionally, the number of first pits 112 located within a first recessed region 110 may be more than one, and may further be 1 to 30, for example, 1, 2, 4, 5, 8, 10, 13, 15, 18, 20, 22, 25, 28, 30, etc. By controlling the number of first pits 112 within a suitable range, it is beneficial to control the surface roughness within a suitable range, so as not to adversely affect the deposition of the film layer on the silicon substrate 100.

[0126] Of course, this is not the only possibility. At least a portion of the first recessed area 110 may also have at least one second recess 113 with other morphologies, such as a cross shape, a line shape, or a groove shape. The at least one second recess 113 may be randomly distributed and have an extensional feel along the distribution direction, such as the first direction S1, that is, the extension dimension of the second recess is greater than the dimension of the first recess. For example, as another example... Figure 10 and Figure 11 As shown in Figure (b), the second recess 113 is groove-shaped; in Figure (c), it is line-shaped; and in Figure (d), it is intersecting. Alternatively, at least a portion of the first recessed region 110 may have a combination of the first recess 112 and the second recess 113; the aforementioned "second recess 113" is recessed into the silicon substrate relative to the bottom surface of other areas of the first recessed region 110, forming a hole structure nested within the first recessed region 110. In this case, the opening of the second recess 113 is located at the bottom wall of the first recessed region 110. By setting the second recess 113, the light trapping effect can be improved when applied to the light-receiving area.

[0127] Further optionally, the number of second recesses 113 is less than the number of first recesses 112, so as to control the surface roughness of the silicon substrate 100 within a suitable range. Alternatively, at least a portion of the first recessed region 110 may not have recesses, for example, it may not have the first recess 112 or the second recess 113.

[0128] According to further embodiments of this application, this application also provides a solar cell, including at least one silicon substrate with a first textured structure on its surface, such as... Figures 1 to 10As shown, the first texture structure of this application includes a plurality of first recessed areas 110, each extending in a strip shape along a first direction S1 and spaced apart along a second direction S2 intersecting the first direction S1. The spacing between adjacent first raised areas 120 in the second direction S2 can be 0.5~10μm, for example, 0.5μm, 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, etc., and further, the spacing can be selected as 1~10μm. It can be understood that when no first sidewall is provided between the first recessed area 110 and the first raised area 120, or when there is no clear boundary between the first recessed area 110 and the first sidewall, this spacing is the width of the first recessed area 110; while when a first sidewall is provided between the first recessed area 110 and the first raised area 120, this spacing includes the sum of the width of the first recessed area 110 and the width of the first sidewall.

[0129] And / or, the depth of the first recessed region 110 is 0.1~10μm, for example, it can be 0.1μm, 0.2μm, 0.4μm, 0.6μm, 0.8μm, 1.0μm, 1.2μm, 1.4μm, 1.6μm, 1.8μm, 2.0μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, etc., and further, the depth can be selected as 0.2~2μm. Here, the "depth" of the first recessed region 110 refers to the dimension in the thickness direction of the silicon substrate 100.

[0130] Thus, by setting the first recessed region 110 within the micrometer-scale range, on the one hand, it is beneficial to obtain a suitable surface roughness, so that when the first recessed region 110 is applied to the light-receiving area, a certain light-trapping effect can be guaranteed, wherein the light-receiving area corresponds to the front and / or back of the battery, and can at least correspond to the non-electrode area of ​​the surface; on the other hand, it makes it easy to conformally deposit a thin film layer, such as nanometer-scale thickness, on the silicon substrate 100; and on yet another hand, it makes it easy to deposit or print high-quality electrodes on the silicon substrate 100.

[0131] According to some embodiments of this application, on the silicon substrate 100 of this application, the spacing between two adjacent first recessed regions 110 can be 0.5~10μm, for example, it can be 0.5μm, 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, etc., and further, the spacing can be 2~10μm. By adjusting the spacing of the first recessed regions 110 within a suitable range, it is beneficial to adjust the surface roughness of the silicon substrate 100 to a suitable level. Thus, when the first recessed regions 110 with a suitable spacing are applied to the light-receiving area, both the light-trapping effect and the film deposition effect can be taken into account. The light-receiving area corresponds to the front and / or back of the battery and can at least correspond to the non-electrode area of ​​the surface.

[0132] According to some embodiments of this application, on the surface of the silicon substrate 100, within a width range of 100 μm along the second direction, the number of first recessed regions 110 can be 1 to 40, for example, 1, 2, 5, 10, 15, 18, 20, 25, 30, 35, 40, etc.; the number of first recessed regions 110 can be further selected as 3 to 20. Similarly, by controlling the distribution density of the first recessed regions 110 within a suitable range, it is beneficial to control the surface roughness of the silicon substrate 100 to a suitable level, so that when the first recessed region is applied to the light-receiving area, both the light-trapping effect and the film deposition effect can be taken into account.

[0133] According to some embodiments of this application, the measurement of the width, depth, spacing, and number of the first recessed regions 110 on the surface of the silicon substrate 100 is not limited in this application, and those skilled in the art can measure them using conventional methods in the art. For example, it can be measured directly on the solar cell product using an optical microscope, or the stacked film on the surface of the cell can be removed to expose the surface of the silicon substrate before measurement. This allows for quantitative determination of the height variations of the first recessed regions 110 and the first raised regions 120. Specifically, a cross-section can be taken along the second direction S2, and the average height or 50% median height of the intersection line of the cross-section and the surface of the silicon substrate can be used as the zero point. The portion below the zero point is the recessed region, and the portion above the zero point is the first raised region. The position of the strip-shaped first recessed region 110 within the recessed region is determined, and the distance between the valley tops of the first recessed region 110 is used as its width, and the distance between the valley tops and valley bottoms is used as its depth, wherein the valley bottoms are farther from the zero point position than the valley tops. Optionally, two adjacent first depression regions 110 are identified within the depression region, with the distance between the valley tops of the two first depression regions 110 being used as their spacing. Optionally, the number of first depression regions 110 within the depression region is counted within a unit size range, such as 100 μm, as their distribution quantity.

[0134] For example, Figure 12 This is a height variation curve of the first recessed area at the sampling location according to another embodiment of this application, as shown in the figure. Figure 12 As shown, the depth of the first recessed region 110 is 0.28~0.78μm; the width is between 2~10μm.

[0135] According to further embodiments of this application, this application also provides a solar cell comprising at least one silicon substrate having a first textured structure on its surface. Figure 13 The image shows a first recessed region of an arc shape, as described in another embodiment of this application, where (a) is a cross-sectional SEM image and (b) is an optical microscope image. Figure 13 As shown, combined with Figure 1The first texture structure of this application includes a plurality of first recessed regions 110, each extending in a strip shape along a first direction S1 and spaced apart along a second direction S2 intersecting the first direction S1. The cross-sectional shape of the first recessed region 110 includes a V-shape and / or an arc shape. However, it is not limited to this; the cross-sectional shape of the first recessed region 110 can also be, for example, a rectangle, a trapezoid, or any combination of these other shapes with V-shapes and arc shapes.

[0136] Furthermore, such as Figure 13 As shown in Figure (b), a third pit 114 discontinuously distributed along the first direction may exist at the location where the first recessed region 110 and the first raised region connect. In this case, there is no clear boundary between the lowest point of the first recessed region and its sidewall. The aforementioned "third pit 114" is recessed into the silicon substrate relative to the first recessed region 110 along the normal direction of its sidewall, forming a hole structure nested in the sidewall of the first recessed region 110. In this case, the opening of the third pit 114 is located at the sidewall of the first recessed region 110. There is a protrusion 115 between adjacent third pits 114. The cross-section of the first recessed region 110 located at the protrusion 115 may be V-shaped and / or arc-shaped, and / or the cross-section of the first recessed region 110 located at the third pit 114 may be V-shaped and / or arc-shaped; and / or the cross-section of the remaining part of the first recessed region 110 other than the protrusion 115 and the third pit 114 may be V-shaped and / or arc-shaped.

[0137] Thus, by setting the cross-section of the first recessed region 110 to a suitable shape, it is beneficial to alleviate the growth stress of the film layer on the silicon substrate 100 and to avoid adverse effects on the film deposition on the silicon substrate 100.

[0138] According to some other embodiments of this application, in addition to the first texture structure described above, the surface of the silicon substrate 100 may also include a second texture structure T2, which includes a second recessed region 210. Here, the second texture structure is different from the first texture structure; for example, the first texture structure can be used to represent a deep line mark region, and the second texture structure can be used to represent a shallow line mark region.

[0139] Since the film layers, such as a stacked film including a doped conductive layer, passivation layer, or antireflection layer, are conformally deposited on the silicon substrate 100, the same second texture structure can be observed on the surface of the solar cell. Therefore, the structure on the surface of the silicon substrate in this application can be obtained directly by testing the second texture structure in the solar cell product, or by removing the stacked film on the surface of the cell to expose the surface of the silicon substrate before testing. The testing method can be, for example, scanning electron microscopy (SEM) or optical microscopy.

[0140] According to embodiments of this application, the first texture structure and the second texture structure are microstructures, where "microstructure" refers to at least one texture structure with a one-dimensional dimension at the micro-nano scale, such as hundreds of nanometers, several micrometers, or tens of micrometers. The one-dimensional dimension can be, for example, the width along the surface direction of the silicon substrate or the depth along the thickness direction of the silicon substrate.

[0141] For example, the one-dimensional dimension of the second recessed region 210 in the second texture structure T2 along the silicon substrate surface direction can be greater than or equal to the one-dimensional dimension of the first recessed region 110 in the first texture structure T1 along the second direction. For example, the width of the first recessed region 110 along the second direction S2 can be greater than 1 μm, and can be further selected as 1~10 μm. The one-dimensional dimension of the second recessed region 210 along the silicon substrate surface direction can be greater than 1 μm, and can be further selected as 1~15 μm.

[0142] For example, the depth to which the second recessed region 210 in the second textured structure T2 is recessed into the silicon substrate 100 is less than the depth to which the first recessed region 110 in the first textured structure T1 is recessed into the silicon substrate 100. For example, the depth of the first recessed region 110 is 0.2~2μm, and the depth of the second recessed region 210 is 0.1~1μm. Figure 10 and Figure 11 Figure (e) shows the location of the second recessed region 210. The second recessed region 210 of the silicon substrate 100 may include multiple sub-recessed structures 211, which are distributed nonlinearly. The depth of the second recessed region 210 is less than the depth of the first recessed region 110. This is more conducive to leveraging the control effect of the first recessed region 110 and the second recessed region 210 on the surface morphology of the silicon substrate 100, and can balance the film quality and light trapping effect.

[0143] According to an embodiment of this application, the second recessed area in the second texture structure T2 has no sense of extension, while the first recessed area 110 in the first texture structure T1 has a sense of extension along the first direction. For example, the extension length of the first recessed area 110 in the first texture structure T1 along the first direction is greater than the one-dimensional dimension of the second recessed area in the second texture structure T2 along the silicon substrate surface direction. For example, the extension length of the first recessed area 110 in the first texture structure T1 along the first direction is greater than 30 μm.

[0144] According to an embodiment of this application, the area percentage of the first recessed region 110 is less than the area percentage of the second recessed region 210; and / or, the area percentage of the first recessed region 110 can be 5% to 48%, for example, it can be 5%, 8%, 10%, 15%, 17%, 20%, 22%, 25%, 28%, 30%, 32%, 35%, 37%, 40%, 42%, 45%, 48%, etc., more preferably 17% to 37%.

[0145] By controlling the area ratio of the first recessed region 110 and the second recessed region 210 within the above range, it is more conducive to the control effect of the surface morphology of the battery body I. When the first recessed region 110 and the second recessed region 210 are applied to the light-receiving surface, the light trapping effect, passivation and electrical contact performance can be better balanced.

[0146] According to further embodiments of this application, this application also provides a solar cell comprising at least one silicon substrate having a first textured structure on its surface. Figure 14 An optical microscope image of a silicon substrate according to another embodiment of this application, as shown below. Figure 14 As shown, the first textured structure T1 of this application includes at least one crack 130, randomly distributed on the surface of the silicon substrate 100. Further, the crack 130 may exist in at least one of the first recessed region 110, the first raised region 120, and the second recessed region 210. Exemplarily, Figure 14 Figure (a) shows crack 130 located in the first recessed region 110, Figure (b) shows crack 130 located in the first raised region 120, and Figure (c) shows crack 130 located in the second recessed region 210. The setting of crack 130 is beneficial to further increase the surface roughness.

[0147] According to some embodiments of this application, for example... Figure 14 As shown, the extension direction of crack 130 is the same as or substantially the same as the first direction. Thus, when depositing a film on the silicon substrate 100, this increases the deposition area and improves the passivation effect, while also preventing the introduction of first texture structures extending in other directions on the silicon substrate surface, thus improving moiré patterns. Here, "substantially the same" means that the angle between the extension direction of crack 130 and the first direction is less than 45°, optionally less than 30°, and more preferably less than 10°, etc. Further optionally, the morphology of crack 130 can be, for example, at least one of a straight line, a curve, or a broken line.

[0148] The above description illustrates the surface morphology of the silicon substrate 100 in the solar cell of this application embodiment, and is not intended to limit the scope of the application. The surface morphology of the silicon substrate 100 described above can be obtained through a polishing process, which may specifically include the following operations:

[0149] First, the original silicon substrate is polished using a polishing alkaline solution at a temperature of 50~80℃, such as 50℃, 55℃, 60℃, 65℃, 70℃, 75℃, 80℃, etc., and for a polishing time of 50~900 s, such as 50s, 100s, 200s, 300s, 350s, 400s, 450s, 500s, 550s, 600s, 700s, 800s, 900s, etc. The polishing alkaline solution includes 0.5–15 wt% (e.g., 0.5 wt%, 1 wt%, 5 wt%, 10 wt%, 13 wt%, 15 wt%, etc.) of NaOH and 0.1–2 wt% (0.1 wt%, 0.2 wt%, 0.5 wt%, 0.8 wt%, 1.0 wt%, 1.3 wt%, 1.5 wt%, 1.8 wt%, 2.0 wt%, etc.) of polishing additives. These polishing additives may include surfactants, defoamers, stabilizers, corrosion inhibitors, and dispersants. Through the synergistic effect of the additives and polishing temperature and time, a first recessed region distributed in a strip-like pattern is formed by inhibiting a certain crystalline phase.

[0150] The polished silicon substrate 100 is then cleaned and dried to obtain the silicon substrate with the first textured structure of this application. The cleaning process may include, for example, ozone cleaning and mixed acid cleaning in sequence.

[0151] According to some embodiments of this application, the first texture structure T1 may include a first sidewall 140 located between the first recessed area 110 and the first raised area 120, and the first sidewall 140 has a folded portion 141. The aforementioned "folded portion 141" may be, for example, a textured structure that is wavy and / or wrinkled, such as a wrinkle-like or scale-like structure.

[0152] The first concave area can directly transition to the first convex area, at which point there is no clear boundary between the first concave area and the first sidewall. Alternatively, the first concave area can also transition to the first convex area via the first sidewall, in which case there is a clear boundary between the first concave area and the first sidewall.

[0153] The folds 141 on the first sidewall 140 are more likely to appear on steep slopes, where steep slopes refer to sidewall angles greater than or equal to 25°, such as slope structures of 25° to 75°. If the sidewall slopes on both sides of the first depression 110 are different, then the first sidewall 140 on the steep slope side will have folds 141.

[0154] During anisotropic etching of the silicon substrate, the first sidewall 140 tends to retain bevels along the (111) crystal plane, easily forming a structure with numerous bevels. This makes it difficult to uniformly cover the passivation or antireflection layer on it. Furthermore, the (111) crystal plane has high surface energy, making it prone to defects during film deposition, thus affecting the passivation effect. By forming the aforementioned wrinkles 141 on the first sidewall 140, more (100) crystal planes are retained on the first sidewall 140, resulting in a more uniform passivation or antireflection layer. This makes it easier to passivate dangling bonds on the silicon substrate, effectively reducing surface recombination. At the same time, reducing the proportion of (111) crystal planes lowers the surface recombination rate, thereby improving the open-circuit voltage and conversion efficiency. In addition, the aforementioned wrinkles also help improve the light trapping effect when applied to the light-receiving area, reducing reflection and increasing short-circuit current. The light-receiving area corresponds to the front and / or back of the battery, and can at least correspond to the non-electrode area of ​​that surface.

[0155] To facilitate understanding of the applicability of the first sidewall 140 in the first texture structure T1, the first recessed area 110 extending into a strip shape is used as an example for illustration. Figure 15 Here is a top SEM view of the first sidewall according to another embodiment of this application, as shown below. Figure 15 As shown, the first texture structure T1 includes a first recessed area 110 and a first raised area 120, with the first raised area 120 adjacent to the first recessed area 110. It can be seen that the first recessed area 110 extends into a strip shape. The first sidewall 140 has a wrinkled portion 141, which is easily observed in the SEM image due to alternating light and dark areas. However, this is not a limitation; the first recessed area 110 may not be limited to a strip shape, but may also be an island shape, a square shape, etc.

[0156] According to some embodiments of this application, the wrinkled portion 141 may include a plurality of layered structures protruding from the first sidewall 140, stacked along the thickness direction of the silicon substrate to form a linear transverse texture. The extension direction of the linear transverse texture is different from the thickness direction of the silicon substrate. Optionally, the plurality of layered structures extend along a first direction; and / or, the wrinkled portion 141 may include a plurality of dot-like protrusions, stacked on the first sidewall 140 to form a scale-like protrusion structure. Here, "transverse" means a direction that is the same as or approximately the same as the extension direction of the silicon substrate 100, for example, it may be a direction with an angle of less than or equal to 10°, or further less than or equal to 8°, or even further less than or equal to 5°, or even further less than or equal to 2° with the extension direction of the silicon substrate 100. Of course, the angle between the extension direction of the linear transverse texture and the extension direction of the silicon substrate can be larger, as long as the extension direction of the linear transverse texture is different from the thickness direction of the silicon substrate.

[0157] By configuring the wrinkled portion as including multiple layered structures or multiple dot-like protrusions, it is beneficial to retain more (100) surfaces. Since the passivation layer of the (100) surfaces is more uniform, dangling bonds are more easily passivated. Therefore, the wrinkled portion is more conducive to passivating the surface of the silicon substrate, reducing the surface recombination rate of charge carriers, and thus improving the open-circuit voltage and conversion efficiency when applied to solar cells. Furthermore, when applied to the light-receiving area, the wrinkled portion is more conducive to improving the light-trapping effect and also helps to increase the contact area with the electrode, thereby improving the collection and transport performance of charge carriers. It is worth mentioning that the scale-like protrusion structure formed by multiple dot-like protrusions is relatively dense, providing additional mechanical support for the wrinkled portion. Thus, when the wrinkled portion is applied to the first recessed area or the first protrusion area, it increases the mechanical stability of the first recessed area or the first protrusion area, which is beneficial to reducing the fragmentation rate.

[0158] According to embodiments of this application, the first sidewall 140 may further include multiple steps stacked along the thickness direction of the silicon substrate to form a stepped structure. Further optionally, at least a portion of the multiple layered structures 1411 or multiple dot-like protrusions 1412 are distributed on the steps. The stepped structure configuration is more conducive to improving the roughness of the first sidewall 140, thereby improving the light-trapping effect when applied to the light-receiving area. Furthermore, the combination of the layered structure or dot-like protrusions helps to better balance the passivation effect and the light-trapping effect.

[0159] For example, Figure 16 The image shown is a magnified partial SEM image of the folded portion according to another embodiment of this application, wherein (a) is a side view of the folded portion including multiple layered structures, (b) is a top view of the folded portion including multiple dotted protrusions, (c) is a combination of layered structures and steps, and (d) is a combination of dotted protrusions and steps. Figure 16 (a) shows that the fold 141 includes multiple layered structures 1411, which are stacked to form a linear transverse texture; (b) shows that the fold 141 includes multiple dotted protrusions 1412, which are stacked to form a scale-like protrusion structure; (c) shows a combination of multiple layered structures 1411 stacked to form a linear transverse texture and multiple steps 142 stacked to form a stepped structure, and it can be observed that layered structures 1411 are also distributed on the steps 142; (d) shows a combination of dotted protrusions 1412 forming a scale-like protrusion structure and multiple steps 142 stacked to form a stepped structure, and it can be observed that dotted protrusions 1412 are also distributed on the steps 142.

[0160] According to some embodiments of this application, when the first recessed area 110 extends continuously or discontinuously into a strip shape, the first sidewall 140 can extend continuously or discontinuously into a line shape. However, this is not a limitation. For example, when the first recessed area 110 is island-shaped, the first sidewall 140 can extend into a ring or a C-shape; or when the first protruding area 120 is island-shaped, the first sidewall 140 can extend into a ring or a C-shape. Further optionally, the line shape includes one or more combinations of straight lines, curves, and broken lines. The term "line shape" indicates that the length of the first sidewall 140 in the extending direction is greater than its width perpendicular to the extending direction. For example, the ratio of its length to width can be at least greater than 5:1, 10:1, or 20:1, and further, it can be less than 200:1, 100:1, etc. Generally, the length-to-width ratio of a line-shaped structure is greater than that of a strip-shaped structure. Unless otherwise specified, the width of the first sidewall 140 generally refers to the width of the first sidewall 140 directly measured from a top-down view of the silicon substrate or cell surface using methods such as SEM.

[0161] For example, Figure 17 This is a top-view SEM image showing the first sidewall extending continuously or discontinuously in another embodiment of this application, wherein (a) it extends continuously in a linear manner, (b) it extends discontinuously in a linear manner, (c) it extends into a ring shape, and (d) it extends into a C-shape. Figure 17 Figure (a) shows the first recessed area 110 extending continuously as a strip, while the first sidewall 140 extends continuously as a line, specifically a combination of straight and curved shapes. Figure (b) shows the first recessed area 110 extending discontinuously as a strip, while the first sidewall 140 extends discontinuously as a line, specifically a combination of straight and broken lines. Figure (c) shows the first recessed area 110 as an island, while the first sidewall 140 extends into a ring shape. Figure (d) shows the first protruding area 120 as an island, while the first sidewall 140 extends into a C-shape.

[0162] According to some embodiments of this application, for example... Figure 16 As shown in Figure (a), the wrinkled portion 141 may include multiple layered structures 1411, which are stacked along the thickness direction of the silicon substrate to form a linear lateral texture; the extension length of a single layered structure 1411 is greater than the thickness of a single layered structure 1411. Thus, in the layered stacked structure, by controlling the lateral dimension of the layered structure to be greater than the longitudinal dimension, it is beneficial to make the (100) crystal plane dominate, reduce the proportion of the (111) crystal plane, and improve the uniformity and integrity of the passivation layer.

[0163] According to an embodiment of this application, for example... Figure 16As shown in Figure (b), the height of the scale-like protrusions in the direction away from the first sidewall 140 is 0.1~1μm, for example, it can be 0.1μm, 0.2μm, 0.3μm, 0.4μm, 0.5μm, 0.6μm, 0.7μm, 0.8μm, 0.9μm, 1.0μm, etc. In this way, by adjusting the height of the protrusions in the scale-like protrusions, it is beneficial to adjust the proportion of the (100) crystal plane and improve the uniformity and integrity of the passivation layer.

[0164] According to some embodiments of this application, the wrinkled portion 141 located on the first sidewall 140 may include a plurality of layered structures 1411, stacked along the thickness direction of the silicon substrate to form a linear transverse texture; the first texture structure T1 may further include: a gentle slope adjacent to the first sidewall 140, the other side of which is connected to a steep slope, and may also be connected to a second texture structure T2. The surface of the gentle slope has gentle hill stripes, which intersect or are not parallel to the linear transverse texture. Here, "gentle slope" means a slope structure with a slope angle or inclination angle greater than 0 and less than 25°, based on the extension direction of the surface of the silicon substrate 100.

[0165] One side of the gentle slope is adjacent to the first sidewall 140, and the other side of the gentle slope can be connected to the steep slope. That is, the gentle slope can be part of the first texture structure T1, with a different inclination angle corresponding to the first sidewall. It has folds only on the first sidewall corresponding to the steep slope, but no folds on the surface of the gentle slope. Of course, the other side of the gentle slope can also be connected to the second texture structure T2. That is, the gentle slope is part of the second texture structure T2, and the first recessed area is located at the junction of the first texture structure T1 and the second texture structure T2.

[0166] For example, Figure 16 As shown in Figure (a), taking a gentle slope as part of a first texture structure T1 as an example, the first texture structure T1 may include a gentle slope 121 adjacent to a first sidewall 140. A steep slope connected to the other side of the gentle slope 121 is not shown in the figure. The surface 1211 of the gentle slope has gentle hill stripes 1212, which intersect or are not parallel to the linear transverse texture.

[0167] Thus, since the gentle slope 121 is adjacent to the first sidewall 140, and the surface 1211 of the gentle slope has gentle mound stripes that intersect or project with the linear transverse lines, on the one hand, it is beneficial to allow light to reach the first sidewall and the first recessed area smoothly when applied to the light-receiving area. After multiple refractions and reflections on the first sidewall, the light trapping effect is improved. On the other hand, when the electrode is fabricated on the silicon substrate, it is beneficial to guide the electrode paste to fully contact the first sidewall, thereby improving the contact performance of the electrode.

[0168] According to some embodiments of this application, the slope angle of the first sidewall 140 is greater than the slope angle of the surface 1211 of the gentle slope; and / or, the slope angle of the first sidewall 140 may be greater than or equal to 25° and less than or equal to 75°, for example, it may be 25°, 30°, 35°, 40°, 45°, 50°, 55°, 60°, 65°, 70°, 75°, etc.; and / or, the slope angle of the surface 1211 of the gentle slope may be less than 25° and greater than 2°, and may further be 3°, 5°, 8°, 10°, 12°, 15°, 18°, 20°, 23°, 24°, etc.

[0169] Thus, by setting the slope of the first sidewall within a suitable range, a better balance can be struck between the light-trapping effect when applied to the light-receiving area and the uniformity of film deposition, such as the passivation layer, on the first sidewall. Setting the slope of the gentle slope within a suitable range can alleviate thermal stress concentration and prevent film cracking caused by subsequent high-temperature processes. Therefore, the first sidewall is more conducive to improving the light-trapping effect when applied to the light-receiving area, and the gentle slope is more conducive to improving the quality of the passivation layer, thus achieving a balance between passivation and light-trapping effects. The light-receiving area corresponds to the front and / or back of the battery, and can at least correspond to the non-electrode area of ​​that surface.

[0170] According to the embodiments of this application, Figure 18 Here are top SEM views of the first and second sidewall bifurcation structures according to another embodiment of this application, as shown. Figure 18 As shown, the first sidewall 140 is further provided with: a first sidewall bifurcation structure 150, which includes a first sub-sidewall 151 extending from the first sidewall 140 toward the interior of the first recessed area 110; and the first sidewall 140 is further provided with: a second sidewall bifurcation structure 160, which includes a second sub-sidewall 161 extending from the first sidewall 140 toward the interior of the first protruding area 120.

[0171] Thus, by setting the first sidewall bifurcation structure 150 and / or the second sidewall bifurcation structure 160, it is beneficial to further increase the roughness of the first recessed area and / or the first protruding area. On the one hand, this is beneficial to improve the light trapping effect when applied to the light-receiving area, which corresponds to the front and / or back of the battery and can at least correspond to the non-electrode area of ​​the surface. On the other hand, when the electrode is fabricated on the silicon substrate 100, it is beneficial to improve the adhesion of the electrode paste, thereby improving the contact performance of the electrode.

[0172] Further optionally, the first sub-sidewall 151 and / or the second sub-sidewall 161 each have a plurality of dot-like protrusions, a plurality of layered structures, and / or a plurality of steps. The dot-like protrusions, layered structures, or steps located on the first sidewall bifurcation structure 150 and the second sidewall bifurcation structure 160 may have a similar extension direction and stacking morphology as those located on the first sidewall 140, and therefore will not be described in detail here.

[0173] Thus, based on the dot-like protrusions and / or layered structures on the first sub-sidewall 151 and / or the second sub-sidewall 161, it is beneficial to promote the (100) crystal plane to dominate, reduce the proportion of the (111) crystal plane, and improve the uniformity and integrity of the passivation layer. This achieves a balance between passivation effect and light trapping effect.

[0174] According to some embodiments of this application, one side of the first recessed area 110 is adjacent to a first sidewall 140, and the other side may be adjacent to another first sidewall 140, or adjacent to a gentle slope 121.

[0175] For example, Figure 19 This is a top-view SEM image of the first texture structure according to another embodiment of this application; as shown Figure 19 As shown, one side of the first recessed area 110 is adjacent to a first sidewall 140, and the other side may be adjacent to another first sidewall 140. It can be understood that one of the first sidewalls 140 adjacent to the first recessed area 110 can be replaced by a gentle slope 121.

[0176] With this configuration, the light trapping effect can be better improved when the first recessed area 110 is adjacent to the first sidewall 140 on both sides. When the first recessed area 110 is adjacent to the first sidewall 140 on one side and to the gentle slope 121 on the other side, it is more conducive to taking into account the uniformity of film deposition and ensuring the passivation effect.

[0177] According to an embodiment of this application, the surface of the silicon substrate 100 may further include a second texture structure T2. Here, the second texture structure T2 is different from the first texture structure T1. For example, the first texture structure T1 can be used to represent a deep line mark area, and the second texture structure T2 can be used to represent a shallow line mark area. As another example, the first texture structure T1 can be used to represent a steep slope area, and the second texture structure T2 can be used to represent a gentle slope area.

[0178] The flatness n3 of the second texture structure T2 is greater than the flatness n2 of the first sidewall 140, and less than the flatness n1 of the first recessed area 110. For example, as... Figure 19 As shown, the second texture structure T2 has a relatively flat base structure, and its flatness n3 is smaller than that of the relatively flat first recessed area 110. The first sidewall 140 has a folded portion 141, so its flatness n2 is smaller than that of the second texture structure T2. That is, the first recessed area 110 is the flattest, the second texture structure T2 is the second flattest, and the first sidewall 140 is the roughest.

[0179] At this point, since the second textured structure occupies most of the surface area of ​​the silicon substrate, its flatness needs to be ensured to improve the deposition quality of the film, such as film uniformity. At the same time, a certain degree of undulation must also be ensured so that the light-trapping effect can be taken into account when applied to the light-receiving area. The light-receiving area corresponds to the front and / or back of the battery, and can at least correspond to the non-electrode area of ​​the surface. Since the first sidewall 140 is sloped, it is easier to adsorb additives in the etching solution during the wet etching process to form the first sidewall 140, which makes the (111) crystal plane easy to be etched, leaving more (100) and (110) crystal planes. Since the (100) and (110) crystal planes are more conducive to the growth of the film layer on them, they are also beneficial to the growth quality of the film layer even when the flatness is low. Therefore, by controlling the flatness to meet the above relationship, the deposition uniformity of the film layer, such as passivation or antireflection layer, can be taken into account, while ensuring the passivation effect and the light-trapping effect when applied to the light-receiving area.

[0180] According to some embodiments of this application, Figure 20 This is a top-view SEM image of the second texture structure according to another embodiment of this application, where (a) and (b) are examples of different morphologies of the second recessed area, (c) is the second texture structure labeled in (a), and (d) is the second texture structure labeled in (b). Figure 20 As shown, at least a portion of the second texture structure T2 has substructures with arcuate and / or polygonal outlines, each substructure having a second recessed area 210, with adjacent second recessed areas 210 overlapping to form a second raised area 220. The polygon has a side length greater than 4, for example, it can be a pentagon, hexagon, heptagon, etc., and so on. For example, as... Figure 20 As shown in Figures (a) and (c), the multiple second depressions 210 on the left side are staggered, forming an staggered arc-shaped tower base structure. Figure 20 Figures (b) and (d) show that the second recessed area 210 forms an independent arc-shaped tower base structure. Of course, it is not limited to an arc-shaped tower base structure; the second recessed area 210 on the right side has a strip-shaped tower base structure.

[0181] With this configuration, at least a portion of the second texture structure T2 has substructures with arc-shaped or polygonal contours. Compared to traditional tower-based structures, the average included angle is larger and the angle is more gentle, which is more conducive to improving the uniformity of film quality on the silicon substrate 100, such as passivation or antireflection layers, thereby improving passivation performance. It is worth mentioning that the second texture structure, combined with the wrinkles, can balance film uniformity, passivation effect, and light-trapping effect when applied to the light-receiving area.

[0182] According to some embodiments of this application, Figure 21 This is a side-view SEM image of the second texture structure according to another embodiment of this application; as shown Figure 21 , combined Figure 20 As shown in Figures (a) and (b), the second texture structure T2 can also have a gentle slope. The meaning of "gentle slope" here is the same as described above and will not be repeated. For example, as... Figure 21 The slope angle shown is 16.9°. Thus, the substructure with the gentle slope can alleviate the problem of thermal stress concentration and prevent the membrane layer from cracking due to subsequent high-temperature processes.

[0183] According to some embodiments of this application, the surface of the gentle slope located in the first texture structure T1 and / or the second texture structure may further have substructures with arcuate or polygonal contours. Similar to the foregoing, the substructure has a plurality of second recessed areas 210, which may overlap to form second raised areas 220. It is understood that the gentle slope here may be part of the first texture structure T1 or part of the second texture structure T2.

[0184] According to some embodiments of this application, the area of ​​the substructure with the arc-shaped profile occupies 3% to 40% of the width or area of ​​the silicon substrate surface, for example, 3%, 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, etc. By adjusting the area ratio of the substructure with the arc-shaped profile relative to the solar cell surface within the above-mentioned suitable range, it is more beneficial to ensure the improvement of passivation effect.

[0185] According to some embodiments of this application, for example... Figure 21 As shown, at least a portion of the second protrusion region 220 has a protruding end 221 protruding outwards from the silicon substrate 100, the surface of which is a smooth transition surface. Thus, the second protrusion regions located between adjacent second recessed regions have a smooth protrusion structure, which can reduce defects at the interface, such as lattice mismatch, thereby reducing recombination loss and improving passivation effect. Furthermore, the smooth protrusion structure facilitates the formation of more continuous films, such as passivation layers, reducing leakage points. When applied to the light-receiving area, it also helps with light scattering and trapping, increasing the path length of light within the cell, thereby improving photoelectric conversion efficiency.

[0186] According to some embodiments of this application, the first sidewall 140 extends along a first direction, and in a second direction intersecting the first direction, the width of the first sidewall 140 on the silicon substrate surface can be 0.5~3μm, for example, it can be 0.5μm, 0.8μm, 1.0μm, 1.2μm, 1.5μm, 1.8μm, 2.0μm, 2.2μm, 2.5μm, 2.8μm, 3μm, etc., for example, as shown in the example. Figure 15As shown, the width of the first sidewall 140 on the surface of the silicon substrate 100 is 2.428 μm and 2.926 μm. The depth of the first sidewall 140 in the thickness direction of the silicon substrate can be 0.1~10 μm, for example, it can be 0.1 μm, 0.2 μm, 0.4 μm, 0.6 μm, 0.8 μm, 1.0 μm, 1.2 μm, 1.4 μm, 1.6 μm, 1.8 μm, 2.0 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, etc.; within a width range of 100 μm along the second direction... Within the enclosure, the number of first sidewalls 140 can be 1 to 200, for example, 1, 2, 5, 10, 15, 18, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80, 90, 100, 110, 120, 130, 140, 150, 160, 170, 180, 200, etc. By controlling the size of the first sidewalls within a suitable range, a balance between light-trapping and passivation effects can be achieved when the silicon substrate is applied to the light-receiving area.

[0187] According to some embodiments of this application, the first sidewall 140 extends along a first direction, and the extension length of the first sidewall 140 in the first direction S1 is greater than or equal to 2 μm, and can further be less than or equal to 300 μm, for example, it can be 2 μm, 5 μm, 10 μm, 50 μm, 80 μm, 100 μm, 120 μm, 150 μm, 180 μm, 200 μm, 220 μm, 250 μm, 280 μm, 300 μm, etc. Thus, by setting the extension length of the first recessed region 110 in the first direction within the above-mentioned suitable range, it is beneficial to guide the directional flow of the electrode paste when fabricating electrodes on the silicon substrate, which is beneficial to paste shaping, allowing the paste to better bond to the silicon substrate, and improving the electrode pull-out force. At the same time, it avoids excessively long extension length of the first recessed region, which could lead to local stress concentration and help reduce the risk of cracking.

[0188] According to some embodiments of this application, since the film layer on the (111) crystal plane is generally thicker, by providing a first textured structure with a first sidewall, the proportion of the (111) crystal plane can be reduced, thereby improving the uniformity of the film layer deposited on the silicon substrate or reducing the uniformity of the thin film layer. Furthermore, even when the thickness of the film layer on the silicon substrate is reduced, the uniformity of the film layer can still be controlled within a suitable range. The film layer includes, but is not limited to, one or more of the following: interface passivation layer, doped conductive layer, passivation layer, and antireflection layer. This application does not impose any limitations on the measurement of the uniformity of the film layer on the silicon substrate surface; those skilled in the art can measure it using conventional methods in the field. For example, SEM can be used to measure the thickness of a film layer, such as a doped conductive layer, passivation layer, or antireflection layer, on the silicon substrate within a cross-sectional SEM image of a silicon substrate. The film uniformity can be calculated based on the measured thickness. Specifically, multiple sampling points are randomly or at fixed intervals selected from the measurement area to measure the thickness. The uniformity is calculated based on the maximum, minimum, and average values ​​of the multiple measured thicknesses, such as the arithmetic mean, where uniformity = (maximum thickness - minimum thickness) / (2 * average thickness).

[0189] According to some embodiments of this application, the uniformity of the film layer located on the silicon substrate, such as a doped conductive layer, passivation layer, or antireflection layer, is less than 10%, for example, it can be 0%, 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, etc., and can be more than 5%. As the uniformity value increases, it indicates that the film layer uniformity is worse.

[0190] For example, Figure 22 These are side-view SEM images of the film layer on the silicon substrate according to an embodiment of this application, wherein (a) is the film layer on the silicon substrate with a conventional tower-based structure, and (b) is the film layer on the silicon substrate with the first texture structure of this application. Figure 22 As shown, the uniformity of the doped conductive layer on the silicon substrate based on the conventional tower-based structure and the doped conductive layer on the silicon substrate based on the first textured structure are comparable, both approaching 0%. The uniformity of the passivation or antireflection layer on the silicon substrate based on the conventional tower-based structure is 10%, while the uniformity of the passivation or antireflection layer on the silicon substrate based on the first textured structure is 4.8%. This indicates that compared to the conventional tower-based structure, the first textured structure of this application can significantly improve the uniformity of the film layers on the silicon substrate, especially the passivation or antireflection layer.

[0191] According to some embodiments of this application, in order to control the formation of wrinkles 141 on the first sidewall 140 of the first textured structure T1 on the silicon substrate, a texturing operation may be performed on the original silicon substrate before polishing it with a polishing alkali solution. The specific polishing operation is the same as described above and will not be repeated here.

[0192] According to some embodiments of this application, when texturing the original silicon substrate, the texturing temperature is 60~80℃, for example, 60℃, 65℃, 70℃, 75℃, 80℃, etc., and the texturing time is 100~1000 s, for example, 100 s, 200 s, 300 s, 350 s, 400 s, 450 s, 500 s, 550 s, 600 s, 700 s, 800 s, 900 s, 1000 s, etc.; the texturing alkaline solution includes 0.5~10wt% (for example, 0.5wt%, 1wt%, 5wt%, 10wt%, etc.) of NaOH and 0.1~2wt% (for example, 0.1wt%, 0.2wt%, 0.5wt%, 0.8wt%, 1.0wt%, 1.3wt%, 1.5wt%, 1.8wt%, 2.0wt%) of NaOH. Texturing additives (wt%, etc.). These texturing additives may include surfactants, defoamers, nucleating agents, corrosion inhibitors, and dispersants.

[0193] According to an embodiment of this application, for example... Figure 23 As shown, the solar cell may further include: a plurality of electrodes 200 located on at least one surface of the silicon substrate 100, each electrode 200 extending in a direction that is the same as or substantially the same as the first direction S1, and spaced apart along the second direction S2. Here, "substantially the same" means that the angle between the extension direction of the electrode 200 and the first direction S1 is less than 45°, optionally less than 30°, and further optionally less than 10°. Here, the electrode 200 refers to a current collector electrode that forms an ohmic contact with the doped conductive layer.

[0194] Thus, by setting the electrode 200 to be in the same or approximately the same direction as the extension of the first recessed area 110 or the first sidewall 140, moiré patterns on the electrode 200 can be avoided. The presence of moiré patterns increases the local resistance of the electrode 200, which can easily lead to damage to the electrode 200.

[0195] Understandably, when the solar cell is rectangular, the first direction S1 can be approximately parallel to the direction of the long side of the solar cell. Optionally, the electrode 200 can be a current collector electrode, suitable for connecting current-collecting structures, such as current-collecting electrodes or other current-collecting structures like solder ribbons. When welding other current-collecting structures onto the current collector electrode or current-collecting electrode subsequently, because the direction of the welding force is inconsistent with the extension direction of the first recessed area, it is less likely to cause cell cracking.

[0196] According to embodiments of this application, in the second direction S2, the number of first recessed regions 110 covered by one electrode 200 is 1 to 20, for example, 1, 2, 5, 8, 10, 12, 15, 18, or 20. By controlling the distribution density of the first recessed regions 110 within a suitable range, it is beneficial to control the surface roughness of the silicon substrate 100 to a suitable level, thereby balancing light trapping effect, film deposition quality, and electrode quality, and improving the electrical contact performance between the doped conductive layer and the electrode 200.

[0197] According to embodiments of this application, the electrode 200 can be made of copper, silver-plated copper, aluminum, or silver, and can be manufactured by methods such as printing or electrodeposition. For example, a metal paste can be printed onto the silicon substrate 100, and then the metal paste can be sintered to achieve metallization. The printing method can be, for example, screen printing or inkjet printing, with screen printing being the preferred method due to its lower cost.

[0198] According to further embodiments of this application, the solar cell may further include a multilayer film 102 disposed on at least one side of the silicon substrate 100, specifically disposed within or on the surface of the silicon substrate 100. Since the surface of the silicon substrate 100 has a first texture structure T1, and the multilayer film is conformally disposed on the surface of the silicon substrate 100, the solar cell also has the same or similar first texture structure. Thus, the first texture structure based on the first recessed region 110 and the first raised region 120 of the silicon substrate 100 helps to improve the film quality of the doped conductive layer and enhance the passivation effect.

[0199] Here, the stacked film 102 is suitable for selectively transporting charge carriers such as electrons or holes. When the stacked film 102 is suitable for selectively transporting electrons, it is located in the N-region; when it is suitable for selectively transporting holes, it is located in the P-region. Optionally, the stacked film 102 may include a doped conductive layer and a passivation or antireflection layer. Further optionally, the material of the doped conductive layer may include at least one semiconductor material selected from monocrystalline silicon, amorphous silicon, polycrystalline silicon, microcrystalline silicon, etc.

[0200] In some embodiments, the doped conductive layer may be deposited on the surface of the silicon substrate 100 by a chemical vapor deposition process, while in other embodiments, the doped conductive layer may be obtained within the surface of the silicon substrate 100 by a doping process.

[0201] To facilitate understanding of the structure of the stacked film 102, the stacked film 102 may include a first doped conductive layer 1021, which is disposed on one side surface of the silicon substrate 100, or spaced out on one side surface of the silicon substrate 100. The first doped conductive layer 1021 may be, for example, an N-type doped conductive layer, with the corresponding stacked film 102 located in the N-region, or the first doped conductive layer 1021 may be, for example, a P-type doped conductive layer, with the corresponding stacked film 102 located in the P-region. For example, N-type doping can be achieved by introducing donor impurities such as phosphorus (P), arsenic (As), or antimony (Sb) VA elements into the semiconductor material; or P-type doping can be achieved by introducing acceptor impurities such as boron (B), aluminum (Al), or gallium (Ga) IIIA elements into the aforementioned semiconductor material.

[0202] Optionally, the stacked film 102 may further include a second doped conductive layer 1022, disposed on the same side or opposite side of the silicon substrate 100, within or on the surface of the substrate. The second doped conductive layer 1022 and the first doped conductive layer 1021 have opposite conductivity types. For example, as... Figure 22 As shown, the first doped conductive layer 1021 and the second doped conductive layer 1022 are respectively disposed on the surface of opposite sides of the silicon substrate 100, and the corresponding solar cell is a double-sided contact cell; not limited thereto, the first doped conductive layer 1021 and the second doped conductive layer 1022 are alternately arranged on the surface of the same side of the silicon substrate 100, and the corresponding solar cell can be a back contact cell.

[0203] At this time, the first texture structure T1 can be located on the surface of the silicon substrate 100 corresponding to the stacked film 102, for example, it can be located on the surface of the silicon substrate 100 corresponding to the first doped conductive layer 1021, or it can be located on the surface of the silicon substrate 100 corresponding to the first doped conductive layer 1021 and the second doped conductive layer 1022 at the same time.

[0204] In another alternative embodiment, the stacked film 102 may include: a plurality of doped conductive layers disposed on one side surface of the silicon substrate 100, each extending in a direction substantially the same as the first direction S1 and spaced apart along the second direction S2.

[0205] Further optionally, the plurality of doped conductive layers may be a first doped conductive layer 1021, which may be further optionally an N-type or P-type doped polysilicon layer, to form a poly-finger structure with the electrode 200. Alternatively, the plurality of doped conductive layers may include alternating first doped conductive layers 1021 and second doped conductive layers 1022 to form a back contact structure with the electrode 200.

[0206] According to some embodiments of this application, for a poly-finger structure or a back contact structure, the number of the first recessed regions located on a doped conductive layer in the second direction is 10 to 100, for example, 10, 20, 30, 40, 50, 60, 80, 90, 100, etc. By setting the number of the first recessed regions 110 on the doped conductive layer within the above range, it is beneficial to effectively improve the passivation effect.

[0207] According to some embodiments of this application, the stacked film 102 may further include an interface passivation layer located between the silicon substrate 100 and the doped conductive layer, for selectively allowing charge carriers to pass through and achieving a field passivation effect, thereby improving the carrier separation and collection efficiency. Exemplarily, the interface passivation layer may be made of alumina, silicon oxide, titanium oxide, amorphous silicon, etc., and may form a tunneling oxide passivation contact (TOPCon) structure or a heterojunction contact structure with the doped conductive layer.

[0208] At this time, the interface passivation layer can be prepared by low-temperature chemical vapor deposition (LPCVD), and the thickness can be 0.5~10 nm, for example, 0.5 nm, 1 nm, 2 nm, 4 nm, 6 nm, 8 nm, 10 nm, etc.

[0209] According to some embodiments of this application, the multilayer film 102 may further include a passivation or antireflection layer located on the surface of the first doped conductive layer and / or the second doped conductive layer away from the silicon substrate 100. The passivation or antireflection layer can simultaneously provide protection and passivation for the underlying silicon substrate or functional layer, such as a P-type doped conductive layer or an N-type doped conductive layer, and reduce the reflection of light incident on the first surface 101a or the second surface 101b. Exemplarily, the passivation or antireflection layer may be a single-layer film formed of silicon dioxide, aluminum oxide, silicon nitride, or silicon oxynitride, or a multilayer film composed of one or more of the aforementioned materials.

[0210] According to embodiments of this application, the stacked film 102 may further include a transparent conductive layer (not shown in the figure) located on the surface of the first doped conductive layer and / or the second doped conductive layer away from the silicon substrate 100. The transparent conductive layer can improve the carrier transport effect of the stacked film 102. Exemplarily, the transparent conductive layer may be indium tin oxide (ITO), fluorine-doped tin oxide (FTO), aluminum-doped zinc oxide (AZO), carbon nanotubes, or graphene, etc.

[0211] According to an embodiment of this application, electrode 200 may include a first electrode 201 and a second electrode 202, wherein the first electrode 201 is located on the surface of the first doped conductive layer 1021 away from the silicon substrate 100 and is in electrical contact with the first doped conductive layer 1021; the second electrode 202 is located on the surface of the second doped conductive layer 1022 away from the silicon substrate 100 and is in electrical contact with the second doped conductive layer 1022.

[0212] According to some embodiments of this application, exemplarily, in the case of a back-contact solar cell, the stacked film 102 may include N-type doped conductive layers and P-type doped conductive layers alternately arranged on one side of a silicon substrate. Since the doping concentration of the P-type doped conductive layer is lower than that of the N-type doped conductive layer, resulting in a difference in passivation effect and electrical contact performance, the first texture structure T1 includes a plurality of first recessed regions 110 extending in a strip shape along the first direction S1. The first recessed regions 110 in the first texture structure T1 on one side surface of the silicon substrate 100 corresponding to the P-type doped conductive layer are more sparsely distributed than the first recessed regions 110 in the first texture structure T1 on the N-type doped conductive layer, which can facilitate the balance of carrier transport between the N-type stacked film and the P-type stacked film.

[0213] For example, the number of first recessed regions 110 on one side surface of the silicon substrate corresponding to the P-type doped conductive layer may be less than the number of first recessed regions 110 on the N-type doped conductive layer; and / or, the spacing between two adjacent first recessed regions 110 on the P-type doped conductive layer may be greater than the spacing between two adjacent first recessed regions on the N-type doped conductive layer; and / or, the number of protrusions 111 in the first recessed regions 110 on the P-type doped conductive layer may be less than the number of protrusions 111 in the first recessed regions 110 on the N-type doped conductive layer. Similarly, the number of first protrusions 120 has the same distribution pattern for the number of pits in the first recessed regions 110, including the first pit 112, the second pit 113, and / or the third pit 114.

[0214] According to some embodiments of this application, in the case of a back-contact solar cell, more attention is paid to the influence of the first texture structure on the passivation effect of the N-type doped conductive layer or the P-type doped conductive layer. Since the N-type or P-type doped conductive layer can be conformally deposited on the surface of the silicon substrate 100, the surface of the N-type or P-type doped conductive layer also has a first texture structure similar to that of the surface of the silicon substrate 100, that is, it can have adjacent first recessed regions 110 and first raised regions 120, and further, it can also have a first sidewall 140 located between the first recessed regions 110 and the first raised regions 120, which will not be described in detail here.

[0215] Because the doping concentration of the P-type doped conductive layer is lower than that of the N-type doped conductive layer, there is a difference in passivation effect and electrical contact performance. Therefore, in one optional embodiment, the roughness of the first sidewall in the first texture structure T1 corresponding to the N-type doped conductive layer on one side surface of the silicon substrate 100 may be greater than the roughness of the first sidewall in the first texture structure T1 corresponding to the P-type doped conductive layer. Specifically, the first sidewall corresponding to the N-type doped conductive layer may have more or larger layered structures, dotted protrusions, or steps. This is more conducive to improving the passivation and contact effect of the P-region and reducing the difference in passivation and contact performance between the P-region and the N-region.

[0216] In another alternative embodiment, the number of first sidewalls 140 in the first textured structure T1 corresponding to the P-type doped conductive layer on one side of the silicon substrate may be greater than the number of first sidewalls 140 in the first textured structure T1 corresponding to the N-type doped conductive layer. This is more conducive to improving the light utilization efficiency of the P-region and generating more photogenerated carriers. This can help balance the carriers between the N-region and the P-region and improve the problem of current mismatch between different regions.

[0217] According to some embodiments of this application, when the solar cell is a double-sided contact cell, the stacked film 102 may include a first doped conductive layer 1021 and a second doped conductive layer 1022. The first doped conductive layer 1021 may be disposed on one side of the surface of the silicon substrate 100, or the first doped conductive layers 1021 may be spaced apart on one side of the surface of the silicon substrate 100, with a first spacing region between adjacent first doped conductive layers 1021, which can cooperate with the electrode 200 to form a poly-finger structure; the second doped conductive layer 1022 may be disposed on the other side of the surface of the silicon substrate, or may be spaced apart on the other side of the surface of the silicon substrate, with a second spacing region between adjacent second doped conductive layers 1022, which can cooperate with the electrode 200 to form a poly-finger structure.

[0218] Similarly, the silicon substrate of the double-sided contact battery can also have a first texture structure T1 on the surface corresponding to the first doped conductive layer 1021 and the second doped conductive layer 1022. The first texture structure T1 includes an adjacent first recessed region 110 and a first raised region 120. Further, the first recessed region 110 can be extended into a strip shape, and / or can also have a first sidewall 140 located between the first recessed region 110 and the first raised region 120, which will not be described in detail here. At this time, for the double-sided contact battery, the front side of the battery is generally more concerned with generating more photogenerated carriers, while the back side of the battery is more concerned with passivation and contact performance. Therefore, the different requirements for light trapping, passivation and contact performance at the front and back of the battery can be met by the structural setting of the first texture structure T1 corresponding to the front or back of the battery.

[0219] In one optional implementation, such as Figure 23 As shown, the second doped conductive layer 1022 is disposed on the other side surface of the silicon substrate 100, for example, by doping into the surface of the silicon substrate 100 through a diffusion process. At this time, the second doped conductive layer 1022 is located on the front side of the cell, and the first doped conductive layer 1021 is disposed on one side surface of the silicon substrate. For example, it can be used to form a tunneling oxide passivation contact (TOPCon) structure. At this time, the first doped conductive layer 1021 is located on the back side of the cell.

[0220] Optionally, the first texture structure T1 of this application can be located on the back side of the battery, that is, the first texture structure T1 is present on one side surface of the silicon substrate corresponding to the first doped conductive layer 1021, and the front side of the battery has a pyramid structure, that is, the pyramid structure is present on the other side surface of the silicon substrate corresponding to the second doped conductive layer 1022. With this configuration, the first texture structure T1 and the pyramid structure of this application work synergistically, which is beneficial for improving the absorption of long-wavelength light. The first texture structure T1 may include an adjacent first recessed region 110 and a first raised region 120. Further, the first recessed region 110 may extend into a strip shape, and / or, the first texture structure T1 may also include a first sidewall 140 located between the first recessed region 110 and the first raised region 120, which will not be described in detail here.

[0221] Further optionally, the pyramid structure includes a base and a top disposed along the surface direction away from the battery body. The lateral dimension of the base is 0.5~2.5μm, for example, it can be 0.5μm, 0.8μm, 1.0μm, 1.2μm, 1.5μm, 1.8μm, 2.0μm, 2.2μm, 2.5μm, etc., and / or, the height between the base and the top is 0.5~2μm, for example, it can be 0.5μm, 0.8μm, 1.0μm, 1.2μm, 1.5μm, 1.8μm, 2.0μm, etc.; and / or, the apex angle of the top is 70~85°, for example, it can be 70°, 72°, 75°, 78°, 80°, 82°, 85°, etc.

[0222] In another alternative implementation, Figure 24 This is a schematic diagram of the overall structure of a solar cell according to another embodiment of this application, as shown below. Figure 24As shown, the second doped conductive layer 1022 is located within the surface of the silicon substrate 100 on the other side, for example, formed by doping into the surface of the silicon substrate 100 through a diffusion process. In this case, the second doped conductive layer 1022 is located on the front side of the battery, and the first doped conductive layers 1021 are spaced apart on the back side of the battery. For example, the first doped conductive layers 1021 form a poly-finger structure, in which case the first doped conductive layers 1021 are located on the surface of one side of the silicon substrate 100. The first texture structure T1 includes a plurality of first recessed regions 110 extending in a strip shape along the first direction S1 on the silicon substrate corresponding to the first doped conductive layer. The first recessed regions in the first texture structure T1 in the area outside the poly-finger on one side of the silicon substrate surface (i.e., the first spacing region between adjacent first doped conductive layers) are more densely packed than the first recessed regions in the first texture structure T1 corresponding to the first doped conductive layer (i.e., the poly-finger). This is more beneficial for light trapping in non-poly-finger areas, as well as passivation effect and film deposition quality in poly-finger areas.

[0223] In yet another alternative implementation, Figure 25 This is a schematic diagram of the overall structure of a solar cell according to another embodiment of this application, as shown below. Figure 25 As shown, the first doped conductive layer 1021 is located entirely on one side of the silicon substrate 100, at which point the first doped conductive layer 1021 is located on the back of the battery, for example, the first doped conductive layer 1021 has a TOPCon structure. The second doped conductive layer 1022 is spaced apart on the front of the battery, for example, the second doped conductive layer has a polyfinger structure. The first texture structure T1 may include multiple first recessed regions 110 extending in a strip shape along the first direction S1, at least corresponding to the silicon substrate of the first doped conductive layer 1021 and the second doped conductive layer 1022. Optionally, the second doped conductive layer 1022 is a P-type doped layer, and the first doped conductive layer 1021 is an N-type doped layer. The first texture structure T1 on the other side of the silicon substrate 100 corresponding to the second doped conductive layer 1022 is sparser than the first texture structure T1 on one side of the silicon substrate 100 corresponding to the first doped conductive layer 1021. This is more beneficial to the passivation effect of the P-type doped layer and reduces the difference in passivation effect between the P-region and the N-region. The dense distribution of the first recessed regions in the first texture structure T1 can be, for example, in the number of first recessed regions 110, the spacing between two adjacent first recessed regions 110, the number of protrusions 111, the number of pits, and the number of first protrusions 120, all exhibiting the same distribution pattern as described above. This is more advantageous in non-poly-finger multilayer films, balancing passivation effect, film deposition quality, and light trapping effect.

[0224] According to some embodiments of this application, when the solar cell is the aforementioned double-sided contact cell, an optional implementation is, for example... Figure 24 As shown, the second doped conductive layer 1022 is located within the surface of the silicon substrate 100 on the other side, for example, formed by doping into the surface of the silicon substrate 100 through a diffusion process, and is located on the front side of the battery. The first doped conductive layer 1021 is spaced apart on the back side of the battery and forms a poly-finger structure. At this time, the first texture structure T1 includes a first sidewall 140, located between the first recessed region 110 and the first raised region 120. The first texture structure T1 corresponds at least to the silicon substrate of the first doped conductive layer. At this time, the roughness of the first sidewall 140 in the first texture structure T1 on the area outside the poly-finger (i.e., the first spacing region) on one side surface of the silicon substrate is greater than the roughness of the first sidewall 140 in the first texture structure T1 on the first doped conductive layer (i.e., the poly-finger). This is more beneficial for the light trapping effect in the non-poly-finger region, as well as the passivation effect and film deposition quality in the poly-finger region. And / or, the number of first sidewalls 140 in the first textured structure T1 on the region outside the corresponding poly-finger (i.e., the first spacer region) on one side surface of the silicon substrate is greater than the number of first sidewalls 140 in the first textured structure T1 on the corresponding first doped conductive layer (i.e., the poly-finger). In this case, it is more advantageous to generate more photogenerated carriers in the non-poly-finger stacked film.

[0225] In another alternative implementation, for example... Figure 25As shown, the first doped conductive layer 1021 is entirely located on one side of the silicon substrate 100, at which point the first doped conductive layer 1021 is located on the back side of the battery, and the second doped conductive layers 1022 are spaced apart on the front side of the battery, for example forming a poly-finger structure. The first texture structure T1 includes a first sidewall 140 located between the first recessed region 110 and the first raised region 120, and the first texture structure T1 is located on both the front and back sides of the battery. Optionally, the second doped conductive layer 1022 is a P-type doped layer, and the first doped conductive layer 1021 is an N-type doped layer. In this case, the number of first sidewalls 140 in the first texture structure T1 corresponding to the second doped conductive layer 1022 on the other side surface of the silicon substrate 100 is less than the number of first sidewalls 140 in the first texture structure T1 on the first doped conductive layer 1021 on one side surface of the silicon substrate 100; and / or, the roughness of the first sidewall in the first texture structure T1 corresponding to the second doped conductive layer 1022 on the other side surface of the silicon substrate 100 is smaller than the roughness of the first sidewall in the first texture structure T1 corresponding to the first doped conductive layer 1021 on one side surface of the silicon substrate. Specifically, for example, the first sidewall of the second doped conductive layer 1022 may have fewer or smaller layered structures, dotted protrusions, or steps. This is more conducive to the passivation effect of the P-type doped layer, reducing the difference in passivation effects between the P-region and the N-region.

[0226] According to some embodiments of this application, when the solar cell is a double-sided contact cell, the stacked film 102 may include a first doped conductive layer 1021 and a second doped conductive layer 1022, which are arranged at intervals on both sides of the surface of the silicon substrate 100. For example, the two surfaces of the cell are respectively formed with poly-finger. The first texture structure T1 includes a plurality of first recessed regions 110 extending in the shape of strips along the first direction S1, which are at least on the silicon substrate corresponding to the first doped conductive layer 1021 and the second doped conductive layer 1022. Taking the first doped conductive layer 1021 located on the back of the battery and the second doped conductive layer 1022 located on the front of the battery as an example, the first recessed area in the first texture structure T1 on one side of the silicon substrate, excluding the poly-finger area, is denser than the first recessed area in the first texture structure T1 on the first doped conductive layer (i.e., the poly-finger); the first recessed area in the first texture structure T1 on the other side of the silicon substrate, excluding the poly-finger area, is denser than the first recessed area in the first texture structure T1 on the second doped conductive layer (i.e., the poly-finger), and the light trapping effect is given priority in this case; furthermore, when the second doped conductive layer is a P-type doped conductive layer, the sparseness and effect of the first texture structure T1 on the other side of the silicon substrate 100 corresponding to the second doped conductive layer 1022 compared to the first texture structure T1 on one side of the silicon substrate 100 corresponding to the first doped conductive layer 1021 are the same as those of the battery with the front poly-finger and the back topcon, which will not be elaborated here. The dense distribution of the first recessed regions in the first texture structure T1 can be, for example, in the number of first recessed regions 110, the spacing between two adjacent first recessed regions 110, the number of protrusions 111, and the number of pits, all exhibiting the same distribution pattern as described above. This is more conducive to achieving better passivation, film deposition quality, and light trapping effect on the front side of the battery.

[0227] According to some embodiments of this application, in the case of a double-sided contact solar cell, the first doped conductive layer 1021 and the second doped conductive layer 1022 are respectively arranged at intervals on both sides of the surface of the silicon substrate 100, for example, the two surfaces of the cell respectively form poly-fingers. The first texture structure T1 includes a first sidewall 140 located between the first recessed region 110 and the first raised region 120. The first texture structure T1 is located on both the front and back sides of the cell, at least corresponding to the poly-finger regions on the silicon substrate of the front and back sides. Taking the first doped conductive layer 1021 located on the back side of the cell and the second doped conductive layer 1022 located on the front side of the cell as an example, the number of first sidewalls in the first texture structure T1 on one side surface of the silicon substrate, excluding the poly-finger, is greater than the number of first sidewalls in the first texture structure T1 on the first doped conductive layer (i.e., the poly-finger); in this case, the light trapping effect is given priority, and more photogenerated carriers are generated on the front side of the cell. And / or, the roughness of the first sidewall in the first textured structure T1 on the other side surface of the silicon substrate, excluding the poly-finger, is greater than the roughness of the first sidewall in the first textured structure T1 on the second doped conductive layer (i.e., the poly-finger). Specifically, for example, the first sidewall in the first textured structure T1 on the region excluding the poly-finger may have a greater number or larger layered structures, dotted protrusions, or steps. In this case, passivation and contact performance on the back side of the battery are given priority, so that passivation effect, film deposition quality, and light trapping effect are better balanced on the back side of the battery.

[0228] Furthermore, when the second doped conductive layer 1022 is a P-type doped conductive layer, the roughness of the first sidewall corresponding to the first texture structure T1 on one side surface of the silicon substrate 100 is greater than the roughness of the first sidewall corresponding to the first texture structure T1 on the second doped conductive layer 1022 on the other side surface of the silicon substrate 100. Specifically, for example, the first sidewall corresponding to the first doped conductive layer 1021 may have more or larger layered structures, dotted protrusions, or steps; and or, the number of first sidewalls 140 on the second doped conductive layer 1022 is less than the number of first sidewalls on the first doped conductive layer 1021. This is more beneficial to the passivation effect of the P-type doped layer and reduces the difference in passivation effects between the P-region and the N-region.

[0229] To facilitate understanding of the overall structure of the solar cell in this application, the following example uses the TOPCon cell structure as an illustration. Figure 23As shown, the solar cell may include a silicon substrate 100, a multilayer film 102, and an electrode 200. The multilayer film 102 may include a first doped conductive layer 1021 and a second doped conductive layer 1022, respectively disposed on both sides of the silicon substrate 100. A first textured structure T1 may be present on the surface of the silicon substrate corresponding to the first doped conductive layer 1021. The first textured structure T1 may include an adjacent first recessed region 110 and a first raised region 120. Further, the first recessed region 110 may extend into a strip shape, and / or the first textured structure T1 may also include a first sidewall 140 located between the first recessed region 110 and the first raised region 120, which will not be described in detail here.

[0230] Optionally, the first doped conductive layer 1021 is an N-type doped polysilicon layer deposited on one side surface of the silicon substrate 100, and the second doped conductive layer 1022 is a P-type doped conductive layer formed in one side surface of the silicon substrate 100 by a boron diffusion process. However, this is not the only possibility. In other embodiments, for example, the first doped conductive layer 1021 may also be obtained by P-type doping of the silicon substrate 100 using an aluminum-containing electrode.

[0231] The stacked film 102 may further include a first interface passivation layer 1031 located between the silicon substrate 100 and the first doped conductive layer 1021. The stacked film 102 may further include a first passivation or antireflection layer 1041 and a second passivation or antireflection layer 1042, wherein the first passivation or antireflection layer 1041 is located on the surface of the first doped conductive layer 1021 away from the silicon substrate 100, and the second passivation or antireflection layer 1042 is located on the surface of the second doped conductive layer 1022 away from the silicon substrate 100.

[0232] For example, the following section will take a battery structure with TOPCon on both sides as an example, such as... Figure 25 As shown, the main difference from the aforementioned TOPCon battery is that the stacked film 102 may include multiple second doped conductive layers 1022, each extending in a direction approximately the same as the first direction S1 and spaced apart along the second direction S2. The second doped conductive layer 1022 may be a doped polycrystalline silicon layer, forming a poly-finger structure with the second electrode 202. In this case, the first texture structure T1 is simultaneously located on both the first doped conductive layer 1021 and the second doped conductive layer 1022.

[0233] The interface passivation layer 103 may include a first interface passivation layer 1031 and a second interface passivation layer 1032, wherein the first interface passivation layer 1031 is located between the first doped conductive layer 1021 and the silicon substrate 100; and the second interface passivation layer 1032 is located between the second doped conductive layer 1022 and the silicon substrate 100.

[0234] For example, by selecting suitable doped conductive layer and interface passivation layer materials, this application can be widely applied to various types of solar cells, such as other bifacial contact cells, like heterojunction with intrinsic thin-layer (HJT) cells. In this case, the first doped conductive layer 1021 and the second doped conductive layer 1022 can be N-type doped amorphous silicon layers and P-type doped amorphous silicon layers, respectively, and the first interface passivation layer 1031 and the second interface passivation layer 1032 can be intrinsic amorphous silicon layers, respectively. The stacked film 102 can also include a first transparent conductive layer and a second transparent conductive layer, wherein the first transparent conductive layer is located on the surface of the first doped conductive layer 1021 away from the silicon substrate 100, and the second transparent conductive layer is located on the surface of the second doped conductive layer 1022 away from the silicon substrate 100. It is understood that passivation or antireflection layers may not be provided.

[0235] Of course, it is not limited to this. It can also be a back contact battery, such as a back contact heterojunction (HBC) battery, a TBC (TopCon-Back Contact) battery, or a hybrid BC battery such as a hybrid battery combining TopCon-HJT (Heterojunction with Intrinsic Thin-layer, HJT).

[0236] Let's take TBC batteries as an example again. Figure 26 This is a schematic diagram of the overall structure of a solar cell according to another embodiment of this application, as shown below. Figure 26 As shown, the main difference from the aforementioned TOPCon cell is that the stacked film 102 includes a first doped conductive layer 1021 and a second doped conductive layer 1022 that can be alternately distributed on one side surface of the silicon substrate. These two layers are N-type and P-type doped polycrystalline silicon layers, respectively. In this case, the first texture structure T1 can be located simultaneously on the first doped conductive layer 1021 and the second doped conductive layer 1022.

[0237] Optionally, the stacked film 102 may further include a first interface passivation layer 1031 and a second interface passivation layer 1032. Both may be silicon oxide layers, thereby forming a tunneling oxide passivation contact structure between the first doped conductive layer 1021 and the first interface passivation layer 1031, and between the second doped conductive layer 1022 and the second interface passivation layer 1032.

[0238] Furthermore, the stacked film 102 may also include a passivation or antireflection layer 104 covering the first doped conductive layer 1021 and the second doped conductive layer 1022, and may further cover the spacer region located between the first doped conductive layer 1021 and the second doped conductive layer 1022.

[0239] By testing the efficiency and turn-on voltage of a TBC battery containing the aforementioned first texture structure T1 and a TBC battery containing a conventional tower base structure, it was found that the efficiency and turn-on voltage of the battery containing the first texture structure T1 of this application were improved. The turn-on voltage was 1.5mV higher than that of the conventional tower base structure, and the battery efficiency was improved by 0.05%. This indicates that the first texture structure T1 of this application, by reducing the angular structure, is beneficial to improving the film quality of the laminated film and improving the electrical contact performance between the electrode and the battery body.

[0240] Table 1

[0241]

[0242] According to another embodiment of this application, a photovoltaic module is provided, comprising: a silicon substrate as described above; or a plurality of solar cells as described above.

[0243] According to an embodiment of this application, the solar cells described above can be connected in series to form a solar cell string; and an encapsulation layer covers the outer periphery of the solar cells.

[0244] According to embodiments of this application, the number of solar cells connected in series can be 4 to 80, for example, 4, 24, 54, 72, or 78 cells. Multiple solar cells can form several solar cell strings, with the cells within each string connected in series. The solar cell strings can be connected in series or in parallel, and are connected to each other via busbars.

[0245] According to embodiments of this application, the encapsulation layer may include a backsheet, an encapsulating film, a glass panel, etc., to improve the stability of the solar cell string. The glass panel is located on the front of the solar cell string, and the backsheet is located on the back of the solar cell string, both serving a protective function. The adhesive film is the adhesive film between the solar cell and the glass panel and backsheet, serving a bonding and fixing function, and must be made of a transparent material.

[0246] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above descriptions are merely specific embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A solar cell, comprising: A silicon substrate, wherein the silicon substrate includes two opposing surfaces, at least one surface having a first textured structure, the first textured structure comprising: Multiple first depression areas; Multiple first protruding areas, each first protruding area being adjacent to the first recessed area; A first sidewall is located between the first recessed area and the first protruding area, and the first sidewall has a folded portion; In addition, a gentle slope adjacent to the first sidewall, the surface of which has gentle mound stripes, the gentle mound stripes intersecting or not facing the folds.

2. The solar cell according to claim 1, wherein, Each of the first recessed regions extends into a strip along a first direction, and the plurality of the first recessed regions are distributed at intervals along a second direction intersecting the first direction.

3. The solar cell according to claim 2, wherein, The first recessed area has a protrusion extending in a second direction, and the first recessed area is divided into a multi-segment structure by the protrusion.

4. The solar cell according to claim 3, wherein, The multi-segment structure is at least one of bamboo joint shape or candied hawthorn shape; And / or, the projection of the protrusion onto the first recessed area is at least one of the following: intersecting, linear, or curved.

5. The solar cell according to claim 3 or 4, wherein, The height of the protrusion is lower than the height of the first protrusion area adjacent to the protrusion.

6. The solar cell according to claim 1 or 2, wherein, At least a portion of the first recessed area has first pits distributed in a dotted pattern along a first direction; And / or, at least a portion of the plurality of first recessed regions has at least one second pit, the second pit having a shape of one or more combinations of cross-shaped, linear, and groove-shaped features; and / or, the cross-sectional shape of the first recessed region is a combination of one or more combinations of V-shaped, arc-shaped, rectangular, and trapezoidal features; And / or, at the location where the first recessed area and the first raised area are connected, there is a third pit discontinuously distributed along a first direction, and there is a raised area between adjacent third pits.

7. The solar cell according to claim 6, wherein, The number of the first pits located within a first recessed area is 1 to 30; and / or, the number of the second pits is less than the number of the first pits.

8. The solar cell according to claim 2, wherein, The spacing between adjacent first protrusions in the second direction is 1~10μm, and the depth of the first depression is 0.2~2μm; And / or, the distance between two adjacent first recessed regions is 2~10μm; And / or, within a width range of 100 μm along the second direction, the number of the first recessed regions is 3 to 20.

9. The solar cell according to claim 1 or 2, wherein, The surface of the silicon substrate further includes at least one crack, which is randomly distributed on the surface of the silicon substrate.

10. The solar cell according to claim 2, wherein, The projection of the first protrusion region onto the surface of the silicon substrate in the direction of extension is at least one of the following: linear, zigzag, curved, candied hawthorn-shaped, and dotted.

11. The solar cell according to claim 2, wherein, The surface of the silicon substrate further includes a second texture structure, the second texture structure including a second recessed region, the second recessed region including a plurality of sub-recessed structures, which are distributed in a non-linear manner; The depth of the second recessed area is less than the depth of the first recessed area.

12. The solar cell according to claim 1, wherein, The wrinkled portion includes a plurality of layered structures protruding from the first sidewall, the plurality of layered structures being stacked along the thickness direction of the silicon substrate to form a linear transverse texture; And / or, the folded portion includes a plurality of dot-like protrusions stacked on the first sidewall to form a scale-like protrusion structure; And / or, the first sidewall further includes multiple steps stacked in a stepped structure along the thickness direction of the silicon substrate.

13. The solar cell according to claim 12, wherein, The length of the layered structure along the surface of the silicon substrate is greater than the thickness of the layered structure; And / or, the height of the scale-like protrusions protruding in the direction away from the first sidewall is 0.1~1μm.

14. The solar cell according to claim 12, wherein, The gentle hill stripes and the linear transverse textures intersect or are not parallel.

15. The solar cell according to claim 1, wherein, The slope angle of the first sidewall is greater than the slope angle of the surface of the gentle slope; And / or, the slope angle of the first sidewall is greater than or equal to 25° and less than or equal to 75°, and the slope angle of the surface of the gentle slope is less than 25° and greater than 2°.

16. The solar cell according to claim 1, wherein, Part of the first recessed area or the first raised area is island-shaped, and the first sidewall extends into a ring or C-shape.

17. The solar cell according to claim 1, wherein, The first sidewall is further provided with: a first sidewall bifurcation structure, the first sidewall bifurcation structure including a first sub-sidewall extending from the first sidewall toward the first recessed area; And / or, the first sidewall is further provided with: a second sidewall bifurcation structure, the second sidewall bifurcation structure including a second sub-sidewall extending from the first sidewall toward the first protrusion area.

18. The solar cell according to claim 17, wherein, The first sub-sidewall and / or the second sub-sidewall each have multiple dot-like protrusions, multiple layered structures, and / or multiple steps.

19. The solar cell according to claim 1, wherein, One side of the first recessed area is adjacent to one of the first sidewalls, and the other side is adjacent to another of the first sidewalls, or to a gentle slope.

20. The solar cell according to claim 1, wherein, The surface of the silicon substrate also includes a second texture structure; The flatness of the second texture structure is greater than that of the first sidewall, but less than that of the first recessed area.

21. The solar cell according to claim 20, wherein, At least a portion of the first texture structure and / or the second texture structure has a gentle slope, the surface of which has a substructure with an arcuate or polygonal profile, the substructure having a plurality of second recessed areas, the second recessed areas overlapping to form a second raised area.

22. The solar cell according to claim 21, wherein, The area containing the arc-shaped substructure accounts for 3 to 40% of the width or area of ​​the silicon substrate surface.

23. The solar cell according to claim 21 or 22, wherein, At least a portion of the second protrusion region has a protruding end that protrudes outward from the silicon substrate, the surface of the protruding end having a smooth transition surface.

24. The solar cell according to claim 1, wherein, The first sidewall extends along a first direction, and the extension length in the first direction is greater than or equal to 2 μm and less than or equal to 300 μm; And / or, in a second direction intersecting the first direction, the width of the first sidewall is 0.5~3μm, and the depth in the thickness direction of the silicon substrate is 0.1~10μm; And / or, within a width range of 100 μm along the second direction, the number of the first sidewalls is 1 to 200; And / or, the uniformity of the film layer on the silicon substrate is less than 10%, and the film layer includes a doped conductive layer and / or a passivation or antireflection layer.

25. The solar cell according to claim 1, wherein, The solar cell also includes: Multiple electrodes are located on the surface of the silicon substrate, each of the multiple electrodes extending in the same direction as the first direction and spaced apart in the second direction; In the second direction, the number of the first recessed areas covered by one electrode is 1 to 20.

26. The solar cell according to any one of claims 1-4, 7-8, 10-22, 24-25, wherein, The solar cell further includes: a multilayer film disposed on at least one side of the silicon substrate; The laminated membrane comprises: A doped conductive layer extends along a first direction and is spaced apart along a second direction, wherein the first textured structure is located on the surface of the silicon substrate corresponding to the doped conductive layer; And a passivation or antireflection layer, located on the surface of the doped conductive layer away from the silicon substrate; In the second direction, the number of the first recessed regions corresponding to one doped conductive layer is 10 to 100.

27. The solar cell according to claim 26, wherein, The doped conductive layer includes an N-type doped conductive layer and a P-type doped conductive layer arranged alternately on one side of the silicon substrate. The first recessed region in the first texture structure corresponding to the P-type doped conductive layer on one side surface of the silicon substrate is more sparsely distributed than the first recessed region in the first texture structure corresponding to the N-type doped conductive layer. And / or, the roughness of the first sidewall in the first texture structure corresponding to the N-type doped conductive layer on one side surface of the silicon substrate is greater than the roughness of the first sidewall in the first texture structure corresponding to the P-type doped conductive layer. And / or, the number of first sidewalls in the first texture structure corresponding to the P-type doped conductive layer on one side surface of the silicon substrate is less than the number of first sidewalls in the first texture structure corresponding to the N-type doped conductive layer.

28. The solar cell according to claim 26, wherein, The doped conductive layer is a first doped conductive layer disposed on one side surface of the silicon substrate. The first doped conductive layer is located on the back side of the battery, and a first spacing region is formed between adjacent first doped conductive layers. The stacked film further includes: The second doped conductive layer is disposed on the other side surface of the silicon substrate, and the second doped conductive layer is located on the front side of the cell. Wherein, the first texture structure is located on the silicon substrate surface corresponding to the first doped conductive layer and on the silicon substrate surface corresponding to the first spacer region; the first recessed region in the first texture structure corresponding to the first spacer region on one side surface of the silicon substrate is more densely distributed than the first recessed region in the first texture structure corresponding to the first doped conductive layer; and / or, the roughness of the first sidewall in the first texture structure corresponding to the first spacer region on one side surface of the silicon substrate is greater than the roughness of the first sidewall in the first texture structure corresponding to the first doped conductive layer; and / or, the number of first sidewalls in the first texture structure corresponding to the first spacer region on one side surface of the silicon substrate is greater than the number of first sidewalls in the first texture structure corresponding to the first doped conductive layer.

29. The solar cell according to claim 26, wherein, The doped conductive layer is a second doped conductive layer disposed on another surface of the silicon substrate. The second doped conductive layer is located on the front side of the battery, and there is a second spacing region between adjacent second doped conductive layers. The stacked film further includes: a first doped conductive layer disposed on one side surface of the silicon substrate, and the first doped conductive layer is located on the back side of the battery. Wherein, the first texture structure is located on the silicon substrate surface corresponding to the first doped conductive layer and on the silicon substrate surface corresponding to the second doped conductive layer; the first recessed area in the first texture structure corresponding to the second doped conductive layer on the other side surface of the silicon substrate is more sparsely distributed than the first recessed area in the first texture structure corresponding to the first doped conductive layer on one side surface of the silicon substrate; and / or, the number of first sidewalls in the first texture structure corresponding to the second doped conductive layer on the other side surface of the silicon substrate is less than the number of first sidewalls in the first texture structure corresponding to the first doped conductive layer on one side surface of the silicon substrate; and / or, the roughness of the first sidewall in the first texture structure corresponding to the first doped conductive layer on one side surface of the silicon substrate is greater than the roughness of the first sidewall in the first texture structure corresponding to the second doped conductive layer on the other side surface of the silicon substrate.

30. The solar cell according to claim 26, wherein, The doped conductive layer is a first doped conductive layer disposed on one side surface of the silicon substrate. The first doped conductive layer is located on the back side of the battery, and a first spacing region is formed between adjacent first doped conductive layers. The stacked film further includes: The second doped conductive layer extends along the first direction and is spaced along the second direction on the other side surface of the silicon substrate. The second doped conductive layer is located on the front side of the cell, and there is a second spacing region between adjacent second doped conductive layers. Wherein, the first texture structure is located on the silicon substrate surface corresponding to the first doped conductive layer, the second doped conductive layer, the first spacer region, and the second spacer region, respectively; the first recessed area in the first texture structure corresponding to the first spacer region on one side surface of the silicon substrate is more densely distributed than the first recessed area in the first texture structure corresponding to the first doped conductive layer; and / or, the first recessed area in the first texture structure corresponding to the second spacer region on the other side surface of the silicon substrate is more densely distributed than the first recessed area in the first texture structure corresponding to the second doped conductive layer; and / or, the number of first sidewalls in the first texture structure corresponding to the first spacer region on one side surface of the silicon substrate is greater than the number of first sidewalls in the first texture structure corresponding to the first doped conductive layer; and / or, the roughness of the first sidewall in the first texture structure corresponding to the second spacer region on the other side surface of the silicon substrate is greater than the roughness of the first sidewall in the first texture structure corresponding to the second doped conductive layer.

31. The solar cell according to claim 30, wherein, The second doped conductive layer is a P-type doped conductive layer; The first recessed region in the first texture structure corresponding to the second doped conductive layer on the other side surface of the silicon substrate is more sparsely distributed than the first recessed region in the first texture structure corresponding to the first doped conductive layer on one side surface of the silicon substrate. And / or, the roughness of the first sidewall in the first texture structure corresponding to the first doped conductive layer on one side surface of the silicon substrate is greater than the roughness of the first sidewall in the first texture structure corresponding to the second doped conductive layer on the other side surface of the silicon substrate. And / or, the number of first sidewalls in the first texture structure corresponding to the second doped conductive layer on the other side surface of the silicon substrate is less than the number of first sidewalls in the first texture structure corresponding to the first doped conductive layer on one side surface of the silicon substrate.

32. The solar cell according to any one of claims 1-4, 7-8, 10-22, 24-25, wherein, The solar cell further includes: a stacked film disposed on both sides of the silicon substrate. The laminated membrane comprises: A first doped conductive layer is disposed on one side surface of the silicon substrate, and the first textured structure is located at least on the silicon substrate surface corresponding to the first doped conductive layer. The second doped conductive layer is disposed on the other side surface of the silicon substrate, and the other side surface of the silicon substrate corresponding to the second doped conductive layer has a pyramid structure. Additionally, a passivation or antireflection layer is located on the surface of the doped conductive layer away from the silicon substrate.

33. A photovoltaic module comprising a solar cell as claimed in any one of claims 1 to 32.

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