A semiconductor thermal processing integration method and system

Abstract

The application provides a semiconductor heat treatment integration method and system, and belongs to the technical field of semiconductor manufacturing. The method comprises the following steps: sampling a plurality of to-be-tested samples, the to-be-tested samples being wafers in a process and having a plurality of test keys thereon; setting a grain size threshold, detecting and obtaining the gate grain size of the to-be-tested samples, and screening out the to-be-tested samples with a gate grain size greater than the grain size threshold to obtain first-level samples; setting a first convergence threshold, obtaining the test key leakage current data of the first-level samples, screening out the first-level samples with a test key leakage current data convergence greater than the first convergence threshold to obtain second-level samples; setting a second convergence threshold, obtaining the gate-to-gate leakage current data of the second-level samples, screening out the second-level samples with a gate-to-gate leakage current data convergence greater than the second convergence threshold to obtain third-level samples; and performing reliability verification on the third-level samples, and adjusting the heat treatment parameters of the wafers according to the test data of the third-level samples.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor thermal processing integration method and system. Background Technology

[0002] To enable rapid product iteration and meet the demands of the relatively high-end market, flash memory is often incorporated as an embedded memory into the existing product process flow in the design and manufacturing of microcontroller units (MCUs). Introducing a new memory manufacturing process also introduces additional thermal budget.

[0003] Thermal budgeting is related to process temperature and temperature holding time, and controlling the thermal budget is quite difficult. If the temperature parameter in the thermal budget is too low or the temperature holding time is too short, it will not effectively oxidize residual polysilicon, posing a risk of ion penetration and affecting the data retention capability of the memory. If the temperature parameter in the thermal budget is too high or the temperature holding time is too long, it will also increase the risk of ion penetration.

[0004] Controlling the thermal budget requires a large sample size, a long experimental time, and is quite difficult, resulting in extremely high experimental costs. Summary of the Invention

[0005] The purpose of this invention is to provide a semiconductor thermal processing integration method and system that can improve the efficiency of thermal budget control and reduce testing costs.

[0006] To solve the above-mentioned technical problems, the present invention is achieved through the following technical solution:

[0007] This invention provides a semiconductor thermal processing integration method, comprising the following steps:

[0008] Multiple samples to be tested are obtained by sampling. The samples to be tested are wafers in the process, and the samples to be tested include multiple test bonds.

[0009] Set a grain size threshold, detect and obtain the gate grain size of the sample to be tested, and screen out some of the samples to be tested whose gate grain size is greater than the grain size threshold to obtain the first-level sample;

[0010] Set a first convergence threshold, obtain the test key leakage current data of the first-level samples, filter out the first-level samples whose convergence of the test key leakage current data is greater than the first convergence threshold, and obtain the second-level samples.

[0011] A second convergence threshold is set, the gate-to-gate leakage current data of the second-level samples is obtained, and the second-level samples whose convergence of the gate-to-gate leakage current data is greater than the second convergence threshold are filtered out to obtain the third-level samples; and

[0012] The reliability of the third-level sample is verified, and the thermal treatment parameters of the wafer are adjusted based on the test data of the third-level sample.

[0013] In one embodiment of the present invention, the heat treatment integration method includes:

[0014] Design the layout of the test bond, which includes a gate structure, a source region, and a drain region, wherein the length of the gate structure is greater than 3000 μm; and

[0015] The layout of the test bond is added to the design layout of the wafer, and the test bond is formed on the wafer simultaneously with the formation of the semiconductor device on the wafer; and

[0016] Obtain the layout of the wafer to be processed, and add a test key to the layout of the wafer to be processed.

[0017] In one embodiment of the present invention, the sample to be tested is an orthogonal experimental sample.

[0018] In one embodiment of the present invention, the step of obtaining the first-level sample includes:

[0019] Obtain an electron microscope image of the sample to be tested, wherein the sample to be tested includes multiple gate structures;

[0020] Based on the electron microscope images, the gate grain size of a portion of the gate structure is obtained;

[0021] A screening ratio threshold is set, and the proportion of failed products in all gate structures is obtained as the screening ratio, wherein the failed products are gate structures whose gate grain size is larger than the grain size threshold; and

[0022] When the screening ratio is greater than the screening ratio threshold, the current sample to be tested is screened out.

[0023] In one embodiment of the present invention, in the step of obtaining the first-level sample, the gate structure includes a control gate layer and a floating gate layer. When obtaining the gate grain size, the gate grain size of the control gate layer is obtained, and the grain size threshold is 40nm.

[0024] In one embodiment of the present invention, in the step of obtaining the second-level sample and the third-level sample, the convergence threshold includes a dispersion threshold and a leakage current threshold. The leakage current threshold is used to measure the leakage current data of the test key or the leakage current data between the gate structures. The dispersion threshold is used to measure the dispersion of the sample. When the leakage current data is greater than the leakage current threshold, or the dispersion is greater than the dispersion threshold, the current second-level sample or the third-level sample is filtered out.

[0025] In one embodiment of the present invention, in the step of obtaining the second-level sample, the first convergence threshold includes a first dispersion threshold and a first leakage current threshold, wherein the first dispersion threshold is 6E-12 and the first leakage current threshold is 1E-11 A / μm.

[0026] In one embodiment of the present invention, in the step of obtaining the third-level sample, the second convergence threshold includes a second dispersion threshold and a second leakage current threshold, wherein the second dispersion threshold is 8E-12 and the second leakage current threshold is 5E-12 A / μm.

[0027] In one embodiment of the present invention, the step of adjusting the heat treatment parameters of the wafer includes:

[0028] After obtaining the first-level sample, reduce the heat treatment temperature and / or heat treatment time of the screened test samples;

[0029] After obtaining the second-level samples, reduce the heat treatment temperature and / or heat treatment time of the screened first-level samples; and

[0030] After obtaining the third-level sample, the heat treatment temperature and / or heat treatment time of the screened second-level samples are increased.

[0031] This invention provides an integrated semiconductor thermal processing system, comprising:

[0032] A sampling unit is used to sample and obtain multiple test samples, wherein the test samples are wafers in the process, and the test samples include multiple test bonds.

[0033] The first-level screening unit is used to set a grain size threshold, detect and obtain the gate grain size of the sample to be tested, and screen out some of the samples to be tested whose gate grain size is greater than the grain size threshold to obtain the first-level sample.

[0034] The second-level filtering unit is used to set a first convergence threshold, obtain the test key leakage current data of the first-level samples, filter out the first-level samples whose convergence of the test key leakage current data is greater than the first convergence threshold, and obtain the second-level samples.

[0035] The third-level filtering unit is used to set a second convergence threshold, acquire the gate-to-gate leakage current data of the second-level samples, and filter out the second-level samples whose convergence of the gate-to-gate leakage current data is greater than the second convergence threshold to obtain the third-level samples; and

[0036] The parameter adjustment unit is used to perform reliability verification on the third-level sample and adjust the thermal treatment parameters of the wafer based on the test data of the third-level sample.

[0037] As described above, this invention provides a semiconductor thermal processing integration method and system. Its unexpected technical effect lies in the following: by experimentally adjusting the thermal budget parameters of a rapid thermal oxidation process, this invention can improve the molding yield of semiconductor devices. Furthermore, by testing die size, leakage current of long test bonds, and leakage current between gates, this invention screens orthogonal samples and performs tests directly after the rapid thermal oxidation process, thereby quickly determining suitable thermal processing parameters. Without performing electrical measurements, the direction for adjusting the thermal processing parameters is determined. This invention reduces experimental time and difficulty, thereby improving the efficiency and accuracy of thermal budget control and reducing its cost.

[0038] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0039] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a flowchart of a heat treatment integration method in one embodiment of the present invention.

[0041] Figure 2 This is a schematic diagram of the region distribution on a wafer in one embodiment of the present invention.

[0042] Figure 3 This is a schematic diagram of the layout of the test key in one embodiment of the present invention.

[0043] Figure 4 This is a magnified schematic diagram of the test key in one embodiment of the present invention.

[0044] Figure 5 This is an electron microscope schematic diagram of a gate structure tested in one embodiment of the present invention.

[0045] Figure 6 This is an electron microscope schematic diagram of a gate structure that failed the test in one embodiment of the present invention.

[0046] Figure 7 This is a convergence test diagram of leakage current testing in one embodiment of the present invention.

[0047] Figure 8 This is a schematic diagram of leakage current between floating gate layers in one embodiment of the present invention.

[0048] Figure 9 This is a schematic diagram of testing the gate leakage current data of adjacent columns in one embodiment of the present invention.

[0049] Figure 10 This is a schematic diagram of testing the gate leakage current data of adjacent rows in one embodiment of the present invention.

[0050] Figure 11 This is a schematic diagram of the structure of a heat treatment integrated system in one embodiment of the present invention.

[0051] In the diagram: 100, wafer; 101, chip area; 102, dicing area; 103, blank area; 200, thermal processing integration system; 201, sampling unit; 202, first-level screening unit; 203, second-level screening unit; 204, third-level screening unit; 205, parameter adjustment unit; FG, floating gate layer; CG, control gate layer; TK, test key. Detailed Implementation

[0052] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0053] Integrated circuit design is extremely complex. A single chip can use millions to billions of logic gates, and the electrical parameters of each logic gate and other components must simultaneously meet standards; otherwise, the chip may not function properly. A wafer typically contains hundreds of thousands to tens of thousands of chips, making process uniformity crucial. In wafer fabrication, monitoring critical electrical and physical properties requires not only that the entire wafer meet standards (SPEC), but also that each individual wafer produced meets these standards. Therefore, Process Control Monitoring (PCM) must be introduced to improve quality control. Wafer Acceptance Test (WAT) is performed after wafer fabrication and before quality inspection to measure the electrical parameters of test keys. The purpose of Wafer Acceptance Test is to examine the process status of each wafer by testing the electrical parameters of the test keys, assess the quality and stability of the semiconductor manufacturing process, and determine whether the wafer product meets the electrical specifications of the process technology platform. Therefore, WAT data can serve as a quality certificate for wafer product delivery. Furthermore, WAT data can reflect the actual production status of the production line. By collecting and analyzing WAT data, the production line's condition can be monitored, trends can be determined, and early warnings can be issued for potential issues. However, wafer acceptance testing has a long testing process, involves a large sample size, and can take up to three months. For wafer process development, risk production, and mass production, this experimental duration results in extremely high R&D costs.

[0054] Please see Figures 1 to 3 As shown, the present invention provides a semiconductor thermal processing integration method, the integration method including steps S10 to S50.

[0055] Step S10: Sampling and obtaining multiple test samples, which are wafers 100 in the process, including multiple test bonds TK.

[0056] Step S20: Set the grain size threshold, detect and obtain the gate grain size of the sample to be tested, and screen out some samples to be tested whose gate grain size is greater than the grain size threshold to obtain the first-level sample.

[0057] Step S30: Set the first convergence threshold, obtain the test key TK leakage current data of the first-level sample, filter out the first-level samples whose convergence of the test key TK leakage current data is greater than the first convergence threshold, and obtain the second-level sample.

[0058] Step S40: Set a second convergence threshold, obtain the gate-to-gate leakage current data of the second-level samples, filter out the second-level samples whose convergence of gate-to-gate leakage current data is greater than the second convergence threshold, and obtain the third-level samples.

[0059] Step S50: Verify the reliability of the third-level sample and adjust the heat treatment parameters of wafer 100 based on the test data of the third-level sample.

[0060] Please see Figure 1 and Figure 2 , Figure 8 As shown, in one embodiment of the present invention, the sample to be tested is wafer 100. Wafer 100 undergoes a rapid thermal oxidation process. In this embodiment, the rapid thermal oxidation process includes steps such as forming a tunnel oxide layer, depositing a floating gate layer (FG), forming a control gate layer (CG), and rapid thermal annealing. An additional thermal budget is introduced in the rapid thermal oxidation process. It should be noted that the semiconductor device on the sample to be tested in the present invention can be a memory device or various semiconductor devices based on MOSFETs. In this embodiment, as a memory device, the semiconductor device includes a gate structure, a drain region, and a source region, wherein the drain region and source region are doped regions disposed in the substrate of wafer 100. The present invention does not limit the doping type of the drain region and source region. The gate structure, drain region, and source region are led out and connected through structures such as contact plugs and metal layers to form an integrated circuit. In the gate structure, the gate structure includes a tunnel oxide layer, a floating gate layer (FG), an isolation layer, and a control gate layer (CG). The tunnel oxide layer is disposed on the substrate, the floating gate layer (FG) is disposed on the tunnel oxide layer, the isolation layer is disposed on the tunnel oxide layer, and the control gate layer (CG) is disposed on the isolation layer. The floating gate layer (FG) and the control gate layer (CG) are, for example, polysilicon. The tunnel oxide layer and the isolation layer are, for example, silicon oxide.

[0061] Please see Figures 1 to 4As shown, in one embodiment of the present invention, the wafer 100 includes a chip region 101, a blank region 103, and a dicing region 102. The chip region 101 is used to form semiconductor devices and integrated circuit structures, i.e., to form chip products. The blank region 103 is a blank region not used to form products. The dicing region 102 is adjacent to the chip region 101. After the wafer 100 is processed, the individual chip products can be separated by dicing the dicing region 102. A test bond TK is disposed in the dicing region 102. While forming semiconductor devices in the chip region 101, the test bond TK is also formed in the dicing region 102. In this embodiment, before step S10, the layout of the test bond TK is designed and transferred to the layout of the wafer 100 to be processed. The test bond TK includes a working region AA and a gate layer poly disposed on the working region AA. The working region AA is a doped region formed by ion implantation into a substrate, including a source region and a drain region. The gate layer poly is disposed on the working region and spans between the source and drain regions. In this embodiment, there are multiple gate layers poly distributed in parallel, and the length of the gate layer poly is greater than 3000 μm, thereby enabling more accurate testing of leakage current data. At least one test bond TK is provided in one diced region 102. Before step S10, the layout of the test bond TK is added to the design layout of the wafer 100, forming the test bond TK on the wafer 100 simultaneously with the formation of the semiconductor device. The photomask of the wafer 100 is adjusted synchronously to fabricate the test bond TK.

[0062] Please see Figure 1 , Figure 2 and Figure 8 As shown, in one embodiment of the present invention, in step S10, the sample to be tested is an orthogonal experimental sample. The distinguishing parameters for the orthogonal experimental sample can be the process temperature and temperature holding time during the rapid thermal oxidation process. Multiple parameter combinations are set according to the process temperature and temperature holding time to obtain the sample to be tested under multiple process temperatures and multiple temperature holding time combinations. The sample to be tested is a wafer 100 that has completed the rapid thermal oxidation step. The rapid thermal oxidation steps include, in sequence, the deposition process of forming a tunnel oxide layer, forming a floating gate layer FG, and rapid thermal annealing after forming a control gate layer CG. In this embodiment, the wafer 100 in the process refers to a wafer 100 that has not yet completed all process steps. In this embodiment, the sample to be tested is a wafer 100 that has formed the control gate layer CG and has been annealed.

[0063] Please see Figure 1 , Figure 2 and Figure 8As shown, in one embodiment of the present invention, in step S20, during the step of obtaining the first-level sample, an electron microscope (EM) image of the sample to be tested is obtained. In this embodiment, the EEM image can be obtained by means of an electron diffractometer, a transmission electron microscope (TEM), a particle size analyzer, etc., and the gate grain size of the gate structure can be calculated from the EEM image. In this embodiment, in step S20, the gate grain size of a portion of the gate structure is obtained. The gate structure may include a control gate layer (CG) and a floating gate layer (FG), or the gate structure may only include the control gate layer (CG). The gate grain size of the control gate layer (CG) is obtained. A grain size threshold is set. When the gate grain size of the control gate layer (CG) is greater than the grain size threshold, the current gate structure is marked as a failed product. The gate grain sizes of multiple control gate layers (CG) are compared sequentially until the sampled partial gate structures are traversed. The number of sampled gate structures is the first number, the number of failed products is the second number, and the ratio of the first number to the second number is the screening ratio. A screening ratio threshold is set. When the screening ratio is greater than the screening ratio threshold, the current sample to be tested is filtered out. Multiple test samples are processed sequentially until all test samples have been traversed. The remaining test samples after the screening process are the first-level samples.

[0064] Please see Figure 1 , Figure 5 and Figure 6 As shown, in one embodiment of the present invention, in step S20, in the step of obtaining the first-level sample, the grain size threshold is 40 nm. Figure 5 The gate structure shown has a gate grain size of less than 10 nm, and the gate structure contains multiple fine grains. When the temperature during rapid thermal oxidation is too high or the temperature holding time is too long, the gate grain size will be as follows: Figure 6 As shown, the gate grain size grows to over 40 nm. Due to the excessively large grains within the gate structure, it becomes difficult to observe features such as... Figure 5 The image shows multiple fine grains. [The text abruptly ends here.] Figure 6 Gate structures with this gate grain size are marked as failed products. In this embodiment, the maximum grain size inside the gate structure is obtained as the gate grain size of the gate structure.

[0065] Please see Figure 1 , Figure 2 and Figure 7As shown, in one embodiment of the present invention, the first-level samples are processed through a wafer 100 acceptability test to screen out the second-level and third-level samples. The second-level samples are obtained based on the first-level samples, and the third-level samples are obtained based on the second-level samples. In this embodiment, a convergence threshold is set, which includes a leakage current threshold and a dispersion threshold. The leakage current data represents the device current data monitored when the device is off. The dispersion threshold represents the distance of the sampled data of a single sample from the mean. In this embodiment, leakage current data is obtained through the wafer 100 acceptability test, where the leakage current data can be the total leakage current data of the current sample. The dispersion σ can be obtained based on the sample mean, the number of samples, and the sample value in the first-level samples. Specifically, the dispersion σ is calculated according to formula (1).

[0066] σ=Σ(X i -μ) 2 / n(1).

[0067] Please see Figures 1 to 3 , Figure 7 And as shown in equation (1), X i Let be the value of the i-th sample in the first-level sample, where i is an integer from 1 to n, μ is the sample mean in the first-level sample, and n is the number of samples in the first-level sample. In one embodiment of the present invention, the dispersion σ is the mean of the sum of squares of the distances of each data point in the sample from their mean. The dispersion σ is used to measure the degree of dispersion of the values ​​in the sample with respect to the mean. The larger the dispersion σ, the more dispersed the sample data distribution. The smaller the dispersion σ, the more concentrated the sample data distribution. The dispersion σ helps to measure the change in data distribution and assists in determining the statistical characteristics of the data. When used to test the leakage current of wafer 100, each data point can be represented as the leakage current data of each test bond TK in a single sample.

[0068] Please see Figure 1 , Figure 3 and Figure 7As shown, in one embodiment of the present invention, in step S30, a first convergence threshold is set, which includes a first dispersion threshold and a first leakage current threshold. The first dispersion threshold measures the data dispersion of the first-level sample, and the first leakage current threshold measures the leakage current data of the test key TK. In this embodiment, with the device off, the total leakage current data of multiple test keys TK in the first-level sample is sequentially acquired as the leakage current data of the test key TK in the first-level sample. When the leakage current data of the test key TK in the first-level sample is greater than the first leakage current threshold, the current first-level sample is filtered out. When the leakage current data of the test key TK in the first-level sample is less than or equal to the first leakage current threshold, the data dispersion of the first-level sample is continuously acquired. When the data dispersion of the first-level sample is greater than the first dispersion threshold, the current first-level sample is filtered out. When the data dispersion of the first-level sample is less than or equal to the first dispersion threshold, the current first-level sample is retained as a second-level sample. In this embodiment, the first dispersion threshold is 6E-12, and the first leakage current threshold is 1E-11 A / μm. After obtaining the calculated data, a convergence plot of all first-level samples can be further obtained, such as... Figure 7 As shown, Figure 7 The horizontal axis represents the number of the first-level sample, and the vertical axis represents the WAT data. Figure 7 In the diagram, the area of ​​the square represents the convergence of the sample. The smaller the area, the higher the convergence, and the more suitable the heat treatment parameters for rapid thermal oxidation. The larger the area, the lower the convergence, and the higher the heat treatment temperature or the longer the temperature holding time for the sample.

[0069] Please see Figure 1 and Figure 3 , Figures 7 to 10As shown, in one embodiment of the present invention, in step S40, a second convergence threshold is set, which includes a second dispersion threshold and a second leakage current threshold. The second dispersion threshold is 8E-12, and the second leakage current threshold is 5E-12 A / μm. The second dispersion threshold is used to measure the data dispersion of the second-level sample, and the second leakage current threshold is used to measure the leakage current data between gate structures. In this embodiment, with the device off, the total leakage current data between multiple gates in the second-level sample is sequentially acquired as the test key TK leakage current data of the second-level sample. The leakage current data between gates refers to the current data between the floating gate layers FG of adjacent gate structures. In this embodiment, the substrate bulk voltage is 0V, one floating gate layer FG is set to a high potential, for example, 1.5V, and the other floating gate layer FG is set to a low potential, for example, 0V. The current data between the two floating gate layers FG is then measured as the leakage current data between gates. In this embodiment, the leakage current data between adjacent floating gate layers FG is measured sequentially in the row direction, and then sequentially in the column direction. The gate structure is arranged in an array of rows and columns, such as Figure 9 As shown, leakage current data between adjacent columns of gate structures are obtained. Figure 10 As shown, leakage current data between gate structures in adjacent rows are acquired. The total leakage current data of the second-level sample is used as the gate-to-gate leakage current data of the second-level sample. If the leakage current data of the test key TK of the second-level sample is greater than a second leakage current threshold, the current second-level sample is discarded. If the leakage current data of the test key TK of the second-level sample is less than or equal to the second leakage current threshold, the data dispersion of the second-level sample is further acquired. If the data dispersion of the second-level sample is greater than a second dispersion threshold, the current second-level sample is discarded. If the data dispersion of the second-level sample is less than or equal to the second dispersion threshold, the current second-level sample is retained as the third-level sample. The gate-to-gate leakage current data is used to distinguish whether there is oxide residue on the floating gate layer FG.

[0070] Please see Figure 1 and Figure 2As shown, in one embodiment of the present invention, in step S50, during the adjustment of the heat treatment parameters of wafer 100, after obtaining the first-level sample, the heat treatment temperature and / or heat treatment time of the rejected test samples are reduced. After obtaining the second-level sample, the heat treatment temperature and / or heat treatment time of the rejected first-level sample are reduced. After obtaining the third-level sample, the heat treatment temperature and / or heat treatment time of the rejected second-level sample are increased. In this embodiment, during the reliability verification step of the third-level sample, the high-temperature service life after cycling, the low-temperature operating life after cycling, the low-temperature data retention storage life after cycling, the baking data retention time after cycling, etc., of the third-level sample are tested to further screen the final sample from the third-level sample. The heat treatment parameters of the final sample can be used as the process parameters for rapid thermal oxidation of the current product.

[0071] Please see Figures 1 to 3 and Figure 11 As shown, the present invention also provides a semiconductor thermal processing integrated system 200, which includes a sampling unit 201, a first-level screening unit 202, a second-level screening unit 203, a third-level screening unit 204, and a parameter adjustment unit 205. The sampling unit 201 is used to sample and acquire multiple test samples, which are wafers 100 in the process, and each test sample includes multiple test bonds TK. The first-level screening unit 202 is used to set a die size threshold, detect and acquire the gate die size of the test samples, and screen out some test samples whose gate die size is larger than the die size threshold to obtain first-level samples. The second-level screening unit 203 is used to set a first convergence threshold, acquire the test bond TK leakage current data of the first-level samples, and screen out first-level samples whose convergence of test bond TK leakage current data is greater than the first convergence threshold to obtain second-level samples. The third-level screening unit 204 is used to set a second convergence threshold, acquire the gate-to-gate leakage current data of the second-level samples, and filter out the second-level samples whose gate-to-gate leakage current data convergence is greater than the second convergence threshold to obtain the third-level samples. The parameter adjustment unit 205 is used to verify the reliability of the third-level samples and adjust the thermal treatment parameters of wafer 100 according to the test data of the third-level samples.

[0072] This invention provides a semiconductor thermal processing integration method and system. The method includes the following steps: sampling and acquiring multiple test samples, where each test sample is a wafer in the process of manufacturing, and each test sample includes multiple test bonds; setting a grain size threshold, detecting and acquiring the gate grain size of the test samples, and filtering out some test samples whose gate grain size is larger than the grain size threshold to obtain a first-level sample; setting a first convergence threshold, acquiring the test bond leakage current data of the first-level sample, and filtering out first-level samples whose convergence of test bond leakage current data is greater than the first convergence threshold to obtain a second-level sample; setting a second convergence threshold, acquiring the gate-to-gate leakage current data of the second-level sample, and filtering out second-level samples whose convergence of gate-to-gate leakage current data is greater than the second convergence threshold to obtain a third-level sample; and verifying the reliability of the third-level sample, and adjusting the wafer thermal processing parameters based on the test data of the third-level sample. This invention provides a semiconductor thermal processing integration method and system, and its unexpected technical effect is that: by experimentally adjusting the thermal budget parameters of a rapid thermal oxidation process, this invention can improve the forming yield of semiconductor devices. Furthermore, this invention screens orthogonal samples by testing the grain size, leakage current of long test bonds, and leakage current between gates. The tests are performed directly after the rapid thermal oxidation process, thereby quickly determining the appropriate heat treatment parameters. Without performing electrical measurements, the direction for adjusting the heat treatment parameters can be determined. This invention can reduce experimental time and difficulty, thereby improving the efficiency and accuracy of thermal budget control and reducing the cost of thermal budget control.

[0073] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A semiconductor thermal processing integration method, characterized in that, Includes the following steps: Multiple samples to be tested are obtained by sampling. The samples to be tested are wafers in the process, and the samples to be tested include multiple test bonds. Set a grain size threshold, detect and obtain the gate grain size of the sample to be tested, and screen out some of the samples to be tested whose gate grain size is greater than the grain size threshold to obtain the first-level sample; Set a first convergence threshold, obtain the test key leakage current data of the first-level samples, filter out the first-level samples whose convergence of the test key leakage current data is greater than the first convergence threshold, and obtain the second-level samples. A second convergence threshold is set, the gate-to-gate leakage current data of the second-level samples is obtained, and the second-level samples whose convergence of the gate-to-gate leakage current data is greater than the second convergence threshold are filtered out to obtain the third-level samples; and The reliability of the third-level sample is verified, and the thermal treatment parameters of the wafer are adjusted based on the test data of the third-level sample.

2. The semiconductor thermal processing integration method according to claim 1, characterized in that, The heat treatment integration method includes: Design the layout of the test bond, which includes a gate structure, a source region, and a drain region, wherein the length of the gate structure is greater than 3000 μm; and The layout of the test bond is added to the design layout of the wafer, and the test bond is formed on the wafer simultaneously with the formation of the semiconductor device on the wafer; and Obtain the layout of the wafer to be processed, and add a test key to the layout of the wafer to be processed.

3. The semiconductor thermal processing integration method according to claim 1, characterized in that, The sample to be tested is an orthogonal experimental sample.

4. The semiconductor thermal processing integration method according to claim 1, characterized in that, The steps to obtain the first-level sample include: Obtain an electron microscope image of the sample to be tested, wherein the sample to be tested includes multiple gate structures; Based on the electron microscope images, the gate grain size of a portion of the gate structure is obtained; A screening ratio threshold is set, and the proportion of failed products in all gate structures is obtained as the screening ratio, wherein the failed products are gate structures whose gate grain size is larger than the grain size threshold; and When the screening ratio is greater than the screening ratio threshold, the current sample to be tested is screened out.

5. A semiconductor thermal processing integration method according to claim 4, characterized in that, In the step of obtaining the first-level sample, the gate structure includes a control gate layer and a floating gate layer. When obtaining the gate grain size, the gate grain size of the control gate layer is obtained, and the grain size threshold is 40nm.

6. The semiconductor thermal processing integration method according to claim 4, characterized in that, In the step of acquiring the second-level sample and the third-level sample, the convergence threshold includes a dispersion threshold and a leakage current threshold. The leakage current threshold is used to measure the leakage current data of the test key or the leakage current data between the gate structures. The dispersion threshold is used to measure the dispersion of the sample. When the leakage current data is greater than the leakage current threshold, or the dispersion is greater than the dispersion threshold, the current second-level sample or the third-level sample is filtered out.

7. A semiconductor thermal processing integration method according to claim 6, characterized in that, In the step of obtaining the second-level sample, the first convergence threshold includes a first dispersion threshold and a first leakage current threshold, wherein the first dispersion threshold is 6E-12 and the first leakage current threshold is 1E-11A / μm.

8. A semiconductor thermal processing integration method according to claim 6, characterized in that, In the step of obtaining the third-level sample, the second convergence threshold includes a second dispersion threshold and a second leakage current threshold, wherein the second dispersion threshold is 8E-12 and the second leakage current threshold is 5E-12 A / μm.

9. A semiconductor thermal processing integration method according to claim 1, characterized in that, The steps for adjusting the heat treatment parameters of the wafer include: After obtaining the first-level sample, reduce the heat treatment temperature and / or heat treatment time of the screened test samples; After obtaining the second-level samples, reduce the heat treatment temperature and / or heat treatment time of the screened first-level samples; and After obtaining the third-level sample, the heat treatment temperature and / or heat treatment time of the screened second-level samples are increased.

10. A semiconductor thermal processing integrated system, characterized in that, include: A sampling unit is used to sample and obtain multiple test samples, wherein the test samples are wafers in the process, and the test samples include multiple test bonds. The first-level screening unit is used to set a grain size threshold, detect and obtain the gate grain size of the sample to be tested, and screen out some of the samples to be tested whose gate grain size is greater than the grain size threshold to obtain the first-level sample. The second-level filtering unit is used to set a first convergence threshold, obtain the test key leakage current data of the first-level samples, filter out the first-level samples whose convergence of the test key leakage current data is greater than the first convergence threshold, and obtain the second-level samples. The third-level filtering unit is used to set a second convergence threshold, acquire the gate-to-gate leakage current data of the second-level samples, and filter out the second-level samples whose convergence of the gate-to-gate leakage current data is greater than the second convergence threshold to obtain the third-level samples; and The parameter adjustment unit is used to perform reliability verification on the third-level sample and adjust the thermal treatment parameters of the wafer based on the test data of the third-level sample.

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