Wafer scheduling method and semiconductor device

Abstract

The invention provides a wafer scheduling method and semiconductor equipment. The method comprises the following steps: firstly, determining a bottleneck module of the semiconductor equipment; then, searching all schedulable target wafers by taking the current state of the semiconductor equipment as a base point; traversing each target wafer, and generating a scheduling branch corresponding to each target wafer; and finally, determining a target scheduling branch from the plurality of scheduling branches based on a branch screening rule and a bottleneck module, and controlling the plurality of target wafers to operate according to the target scheduling branch. Wherein the branch screening rule comprises a residence time minimum rule, an exchange priority rule and a bottleneck module priority loading rule. In the scheduling mode, when the plurality of scheduling branches are screened according to the branch screening rule, judgment of the bottleneck module is added, so that the target scheduling branch which can meet the highest utilization rate of the bottleneck module can be screened out according to different scene bottlenecks, and the productivity of semiconductor equipment is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a wafer scheduling method and semiconductor equipment. Background Art

[0002] At present, etching machine equipment mainly includes multiple modules such as wafer loading module, calibration module, vacuum lock module, process module, cooling module, first robot module and second robot module. In the process of etching multiple wafers, due to the different process flows of different wafers, the transmission paths generated by the wafers in the etching machine equipment are also different, and the processing capacity of each module is also different. How to control multiple modules to maximize the production output of the etching machine equipment is of great significance.

[0003] The existing method mainly uses a segmented search algorithm to perform system simulation on the etching machine equipment to determine the optimal path and transfer the wafer according to the optimal path. The scheduling process of a branch search is as follows: ① The search depth is set to N in each section, and the initial depth of the algorithm is 0. Based on the current state of the etching tool equipment, the processes that can be executed on all wafers in the etching tool equipment are obtained. For example, assume that a total of k wafers with executable processes are obtained; ② The algorithm simulates the execution of different executable processes and can obtain k types of tool system states after the execution of the processes; ③ If the algorithm search depth does not reach the set search depth N, the algorithm will continue to obtain all processes that can be executed on the wafer under these k different tool system states. After the second round of search, k*k different tool system states will be formed; ④ After completing the search with a depth of N, k to the power of N tool system states can be obtained, forming a large search tree; ⑤ Each path is evaluated based on the system process time efficiency. The system process time efficiency can be understood as the ratio of the time a wafer undergoes the process to the total time during the entire process from the wafer loading module to the wafer loading module; ⑥ The path with the highest system process time efficiency is regarded as the optimal path, and multiple modules are controlled to transfer wafers according to the optimal path.

[0004] In practice, while the above method can optimize wafer transport paths, it requires multiple recursive searches to find all possible paths. Even if the search depth is set, reaching that depth still requires an exponential number of searches, which reduces the efficiency of calculating the optimal path and, in turn, the throughput of the etching equipment. Therefore, how to quickly determine the optimal wafer transport path to maximize the throughput of the etching equipment is an urgent problem that needs to be solved. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a wafer scheduling method and semiconductor equipment to alleviate the above-mentioned problems. Based on the bottleneck module, different branch screening rules are adopted to determine the target scheduling branch from multiple scheduling branches, so that the target scheduling branch that can best meet the highest bottleneck module utilization can be screened out according to different scenario bottlenecks, thereby improving the production capacity of semiconductor equipment.

[0006] In a first aspect, an embodiment of the present invention provides a wafer scheduling method, comprising: determining a bottleneck module of a semiconductor device; wherein the bottleneck module is used to characterize the module that takes the longest process time for the semiconductor device to complete a single wafer, and includes one of the following: a loading module, a process module, and a transfer module; based on the current state of the semiconductor device, searching for all schedulable target wafers, and traversing each target wafer to generate a scheduling branch corresponding to each target wafer; wherein the scheduling branch is used to characterize a branch generated along the process path starting from the current position of the target wafer; based on the branch screening rules and the bottleneck module, determining the target scheduling branch from multiple scheduling branches. Branch, and control multiple target wafers to run according to the target scheduling branch; wherein, the branch screening rules include: minimum residence time rule, exchange priority rule and bottleneck module priority loading rule; the minimum residence time rule is used to represent that in each scheduling branch, the average waiting time of the transfer module transporting multiple target wafers in the scheduling branch is calculated, and the scheduling branch with the minimum average waiting time is used as the target scheduling branch; the exchange priority rule is used to represent the rule of using the scheduling branch with the most exchange operations as the target scheduling branch; the bottleneck module priority loading rule is used to represent the rule of using the scheduling branch containing wafers transported to the bottleneck module as the target scheduling branch.

[0007] Preferably, the step of determining the target scheduling branch from multiple scheduling branches based on the branch screening rule and the bottleneck module includes: judging whether the target scheduling branch is determined from multiple scheduling branches based on the minimum stay time rule; if not, based on the bottleneck module, determining the target scheduling branch from multiple scheduling branches according to the exchange priority rule or the bottleneck module priority loading rule.

[0008] Preferably, based on the bottleneck module, the step of determining the target scheduling branch from multiple scheduling branches according to the exchange priority rule or the bottleneck module priority loading rule includes: if the bottleneck module is a transfer module, determining the target scheduling branch from multiple scheduling branches according to the exchange priority rule.

[0009] Preferably, based on the bottleneck module, the step of determining the target scheduling branch from multiple scheduling branches according to the exchange priority rule or the bottleneck module priority loading rule includes: if the bottleneck module is a process module, then determining the target scheduling branch from multiple scheduling branches according to the bottleneck module priority loading rule.

[0010] Preferably, the step of traversing each target wafer and generating a scheduling branch corresponding to each target wafer includes: for any target wafer, taking the current position of the target wafer as the starting point, generating a branch along the process path until the wafer placement action occurs, and using the generated branch as the scheduling branch of the target wafer.

[0011] Preferably, the step of determining the bottleneck module of the semiconductor equipment includes: obtaining hardware information of the semiconductor equipment and process recipe information of the process task; wherein the hardware information includes: the module number and hardware time parameters of the process module, and the hardware time parameters include: the corresponding self-running time of the process module and / or the transfer module during the process; the process recipe information includes the process path and the process time, and the process path is used to characterize the movement sequence set of the wafer in the semiconductor equipment, and the process time includes: the time for the process module and / or the transfer module to perform process processing on the wafer; and determining the bottleneck module of the semiconductor equipment based on the hardware information and the process time.

[0012] Preferably, the step of determining the bottleneck module of the semiconductor equipment based on the hardware information and the process time includes: determining multiple module cycle times based on the number of modules, hardware time parameters and the process time; wherein the module cycle time is used to characterize the minimum time required for the module to complete the process of a wafer, including: a first module cycle time corresponding to the loading module, a second module cycle time corresponding to the process module and a third module cycle time corresponding to the transfer module; determining the bottleneck time of the semiconductor equipment based on the first module cycle time, the second module cycle time and the third module cycle time, and using the module corresponding to the bottleneck time as the bottleneck module.

[0013] Preferably, the step of determining the bottleneck time of the semiconductor device based on the first module cycle time, the second module cycle time and the third module cycle time includes: determining the maximum value of the first module cycle time, the second module cycle time and the third module cycle time as the bottleneck time of the semiconductor device.

[0014] In the second aspect, an embodiment of the present invention also provides a semiconductor device, including a controller and multiple modules communicatively connected to the controller; wherein the multiple modules include: a loading module, a process module and a transfer module; the controller is used to implement the steps of the wafer scheduling method of the first aspect mentioned above.

[0015] In a third aspect, an embodiment of the present invention further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the wafer scheduling method of the first aspect are executed.

[0016] The embodiments of the present invention bring the following beneficial effects:

[0017] An embodiment of the present invention provides a wafer scheduling method and semiconductor equipment. First, the bottleneck module of the semiconductor equipment is determined; then, based on the current state of the semiconductor equipment, all schedulable target wafers are searched; each target wafer is traversed, and a scheduling branch corresponding to each target wafer is generated; finally, based on the branch screening rules and the bottleneck module, a target scheduling branch is determined from multiple scheduling branches, and multiple target wafers are controlled to operate according to the target scheduling branch; wherein the branch screening rules include: a minimum stay time rule, an exchange priority rule, and a bottleneck module priority loading rule. In the above scheduling method, when screening multiple scheduling branches according to the branch screening rules, the judgment of the bottleneck module is added, so that the target scheduling branch that best meets the highest bottleneck module utilization can be screened out according to the different scenario bottlenecks, thereby improving the production capacity of the semiconductor equipment.

[0018] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description and the drawings.

[0019] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 A schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0022] Figure 2 A flowchart of a wafer scheduling method provided by an embodiment of the present invention;

[0023] Figure 3 A process flow chart of an etching machine device provided by an embodiment of the present invention;

[0024] Figure 4 A schematic diagram of a serial relationship provided by an embodiment of the present invention;

[0025] Figure 5 A schematic diagram of a parallel relationship provided by an embodiment of the present invention;

[0026] Figure 6An overall framework diagram of a wafer scheduling solution provided by an embodiment of the present invention;

[0027] Figure 7 A schematic diagram of a single wafer serial connection provided by an embodiment of the present invention;

[0028] Figure 8 A schematic diagram of a multi-wafer serial connection provided by an embodiment of the present invention;

[0029] Figure 9 A branch scene diagram of a robot carrying multiple wafers provided in an embodiment of the present invention;

[0030] Figure 10 Another branch scenario diagram of a robot carrying multiple wafers provided by an embodiment of the present invention;

[0031] Figure 11 A schematic structural diagram of another semiconductor device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0032] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0033] To facilitate understanding of this embodiment, the following first describes in detail the wafer scheduling method provided by an embodiment of the present invention. This method is applied to semiconductor equipment such as an etching machine, wherein the semiconductor equipment includes a controller and multiple modules communicating with the controller, including: a loading module, a process module, and a transfer module; the loading module can also be called a wafer loading module; the process module is used to represent the module that processes the wafer, including but not limited to: a process module, a process calibration module, a process cooling module, and a process vacuum lock module; the transfer module is used to represent the module that transfers the wafer, such as a robot, etc. The specific number and type of process modules, the number and type of transfer modules, etc. can be set according to actual conditions.

[0034] For ease of understanding, here we take the etching machine as an example to introduce the functions of each module. Figure 1 As shown, it includes: a wafer loading module (i.e., a loading module), a process calibration module, a process vacuum lock module, a process processing module, a process cooling module, a first robot and a second robot; specifically, the functions of each module are as follows:

[0035] (1) Wafer loading module: a module used to load unprocessed wafer transfer boxes (FOUPs) into the tool and unload them from the tool after the FOUP process. It is also called an LP (LoadPort) module and is located at the atmospheric end of the etching tool. For example, four LoadPort modules, LP1 to LP4, are shown here.

[0036] (2) Process calibration module; namely, the Aligner module, which is used to calibrate the angle of the wafer before the process and is located at the atmospheric end of the etching machine equipment;

[0037] (3) Process vacuum lock module; namely, LL (LoadLock) module, located between the atmospheric side and vacuum side of the etching machine equipment. When the wafer enters the LoadLock module from the atmospheric side, the LoadLock module performs an air pumping operation on the wafer until the air pressure in the LoadLock module is consistent with that in the vacuum side; when the wafer enters the LoadLock module from the vacuum side, the LoadLock module performs an air filling operation on the wafer until the air pressure in the LoadLock module is consistent with that in the atmospheric side. For example, two LoadLock modules are shown here, namely LLA and LLB.

[0038] (4) Process module; namely, PM (Process Module) module, which can also be called process chamber or processing chamber, is responsible for the etching process of the wafer; here, preferably there are four PM modules, namely PM1 to PM4;

[0039] (5) Process cooling module; namely, the Cooler module, which is used to characterize the position where the wafer after the process is completed leaves the vacuum end and is cooled at the atmospheric end. In actual applications, whether to perform the cooling process can be adaptively set according to the actual situation. For example, in some scenarios, the wafer can be set not to perform the cooling process;

[0040] (6) A first manipulator; a module for transporting wafers between the LoadPort module, the Aligner module, the LoadLock module, and the Cooler module at the atmospheric side, hereinafter referred to as an ATM (Atmosphere Transfer Module). In practical applications, one ATM is preferred;

[0041] (7) Second robot: A module for wafer handling between the PM module and the LoadLock module at the vacuum end, hereinafter referred to as VTM (Vacuum Transfer Module). In practical applications, two are preferred.

[0042] In actual applications, the controller is used to implement the steps of the following wafer scheduling method. When screening multiple scheduling branches according to the branch screening rules, the judgment of the bottleneck module is added so that the target scheduling branch that can best meet the highest bottleneck module utilization rate can be screened out according to different scenario bottlenecks, thereby improving the production capacity of semiconductor equipment.

[0043] Example 1:

[0044] Based on the above semiconductor equipment, an embodiment of the present invention provides a wafer scheduling method, such as Figure 2 As shown, the method includes the following steps:

[0045] Step S202, determining the bottleneck module of the semiconductor equipment;

[0046] Among them, the bottleneck module is used to characterize the module with the longest process time used by semiconductor equipment to complete a single wafer, that is, the bottleneck module is the busiest module in the semiconductor equipment that determines the production capacity. During the wafer scheduling process, the bottleneck module of the semiconductor equipment is determined first, and the judgment of the bottleneck module is added in the screening process of the target scheduling branch, so as to screen out the target scheduling branch that can best meet the highest utilization rate of the bottleneck module according to different scenario bottlenecks, thereby improving the production capacity of the semiconductor equipment.

[0047] It should be noted that, since the multiple modules of the semiconductor equipment mainly include: loading module, process module and transfer module, the type of bottleneck module here includes one of the following: loading module, process module and transfer module; in particular, since the process module includes: process processing module, process calibration module, process cooling module and process vacuum lock module, etc., the transfer module includes a first manipulator and a second manipulator, etc., the module position of the bottleneck module can be determined according to actual conditions.

[0048] Step S204, based on the current state of the semiconductor device, searching for all schedulable target wafers, traversing each target wafer, and generating a scheduling branch corresponding to each target wafer;

[0049] Specifically, based on the current state of the semiconductor device, wafers at various modules of the semiconductor device are searched, and schedulable target wafers are determined based on the positions of the wafers. For example, if the wafer is in the starting module or the middle module of the semiconductor device, the wafer has not yet completed the process processing. At this time, the wafer is a schedulable target wafer; on the contrary, if the wafer is in the final module of the semiconductor device, the wafer has completed the process processing, and it is determined that the wafer does not belong to the schedulable target wafer. Therefore, by searching the wafers and determining multiple schedulable target wafers, the scheduling efficiency of the semiconductor device is improved, thereby improving the production capacity of the semiconductor device.

[0050] Among them, the scheduling branch is used to represent the branch generated along the process path starting from the current position of the target wafer; specifically, for any target wafer, starting from the current position of the target wafer, a branch is generated along the process path until the wafer placement action occurs, and the generated branch is used as the scheduling branch of the target wafer. The wafer placement action here refers to the action of the target wafer being taken out by the robot after the process at the current position is completed and placed on the next target module. Therefore, the scheduling branch corresponding to each target wafer here is only used for the branch from the current position of the target wafer to the next target module. For the entire semiconductor device, after each target scheduling branch is executed, the target wafer is re-searched based on the state after execution, and each target wafer is traversed to generate a new scheduling branch for each target wafer, so as to re-determine the new target scheduling branch from multiple new scheduling branches, thereby improving the production capacity of semiconductor equipment.

[0051] Step S206 , based on the branch screening rule and the bottleneck module, determining a target scheduling branch from the multiple scheduling branches, and controlling the multiple target wafers to operate according to the target scheduling branch.

[0052] Among them, the branch screening rules include: the minimum dwell time rule, the exchange priority rule, and the bottleneck module priority loading rule; the minimum dwell time rule is used to represent the rule that, in each scheduling branch, the transfer module calculates the average waiting time for transporting multiple target wafers in the scheduling branch, and uses the scheduling branch with the minimum average waiting time as the target scheduling branch; the exchange priority rule is used to represent the rule that uses the scheduling branch with the most exchange operations as the target scheduling branch; the bottleneck module priority loading rule is used to represent the rule that uses the scheduling branch containing wafers transported to the bottleneck module as the target scheduling branch. Therefore, for the scheduling branches corresponding to the multiple target wafers traversed, the target scheduling branch is screened out from the multiple scheduling branches based on the branch screening rules and the bottleneck module, and the target scheduling branch that best meets the highest bottleneck module utilization rate is screened out according to the different scenario bottlenecks, thereby improving the production capacity of semiconductor equipment.

[0053] The wafer scheduling method provided by an embodiment of the present invention adds the judgment of the bottleneck module when screening multiple scheduling branches according to the branch screening rules, so that the target scheduling branch that can best meet the highest bottleneck module utilization rate can be screened out according to different scenario bottlenecks, thereby improving the production capacity of semiconductor equipment.

[0054] In one embodiment, the step of determining a target scheduling branch from multiple scheduling branches based on branch screening rules and a bottleneck module includes: determining whether the target scheduling branch is determined from multiple scheduling branches based on a minimum stay time rule; if not, based on the bottleneck module, determining the target scheduling branch from multiple scheduling branches according to an exchange priority rule or a bottleneck module priority loading rule.

[0055] Specifically, when determining a target scheduling branch from multiple scheduling branches, in order to achieve optimal scheduling of semiconductor equipment, the target scheduling branch is first screened from multiple scheduling branches according to the minimum residence time rule. If the target scheduling branch is screened out, multiple target wafers are controlled to operate according to the target scheduling branch; conversely, if the target scheduling branch cannot be screened out from multiple scheduling branches according to the minimum residence time rule, at this time, based on the module position of the bottleneck module, the target scheduling branch is determined from multiple scheduling branches according to the exchange priority rule or the bottleneck module priority loading rule.

[0056] Among them, when the target scheduling branch cannot be screened out from multiple scheduling branches according to the minimum residence time rule, at this time, if the bottleneck module is a transfer module, the target scheduling branch is determined from multiple scheduling branches according to the exchange priority rule; if the bottleneck module is a process module, the target scheduling branch is determined from multiple scheduling branches according to the bottleneck module priority loading rule.

[0057] In practical applications, transfer modules, such as manipulators (including the first manipulator ATM and the second manipulator VTM), can perform the following actions within other modules: ① PickMove: This occurs when a wafer is present in the target slot of the target module but the manipulator's hand is empty. The manipulator then takes the wafer from the target slot and places it in its hand, a wafer placement action. ② PlaceMove: This occurs when a wafer is present in the manipulator's hand but the target slot of the target module is empty. The manipulator then places the wafer in its hand in the target slot, a wafer placement action. ③ SwapMove: This includes two scenarios: one is when the target module has only one slot, there is a wafer 1 available in this slot, and there are two available manipulators. For semiconductor equipment, this scenario only applies to the vacuum side: the second manipulator VTM uses Arm 1 to remove wafer 1 and places wafer 2 on Arm 2 in the target slot. Another scenario occurs when the target module has multiple slots, there is a wafer 1 available in Slot 1, there is an empty Slot 2 available, and any available manipulator is available. At this time, for the first manipulator ATM side: ATM puts wafer2 in its hand into empty Slot2, and then takes out wafer1 from the target Slot1; for the second manipulator VTM side: VTM uses Arm1 to take out wafer1 from Slot1, and puts wafer2 on Arm2 into Slot1; that is, the manipulator performs the wafer changing action.

[0058] Therefore, when the bottleneck module is a transfer module such as the first manipulator or the second manipulator, since the sum of the execution times of PickMove and PlaceMove by the manipulator is greater than the time of SwapMove, that is, SwapMoveTime < PickMoveTime + PlaceMoveTime, at this time, it is more optimal for the manipulator to complete one film loading and unloading with SwapMove. That is, at this time, according to the swap priority rule, the target scheduling branch is determined from multiple scheduling branches, and the scheduling branch with the most SwapMove operations is used as the target scheduling branch.

[0059] Similarly, if the bottleneck module is a process module, such as a process processing module, a process calibration module, a process cooling module, or a process vacuum lock module, etc., at this time, the target scheduling branch is determined from multiple scheduling branches according to the bottleneck module first wafer loading rule, that is, the scheduling branch that includes transporting the wafer to the bottleneck module is used as the target scheduling branch to improve the production capacity of the semiconductor device.

[0060] In summary, for multiple scheduling branches, when screening multiple scheduling branches according to the branch screening rule, the judgment of the bottleneck module is added, so as to be able to screen out the target scheduling branch that can best meet the highest utilization rate of the bottleneck module according to different scenario bottlenecks. Compared with the existing single screening rule, the rule for screening scheduling branches is improved. Different branch screening rules are used for different scenarios, and a better branch solution, that is, the target scheduling branch, can be selected in the changing scheduling scenario, thereby improving the production capacity of the semiconductor device.

[0061] In one implementation, the steps of determining the bottleneck module of the semiconductor device include: obtaining the hardware information of the semiconductor device and the process recipe information of the process task; wherein, the hardware information includes: the number of process modules and the hardware time parameters, and the hardware time parameters include: the self-running time corresponding to the process module and / or the transfer module during the process; the process recipe information includes the process path and the process time, the process path is used to represent the set of movement sequences of the wafer in the semiconductor device, and the process time includes: the time for the process module and / or the transfer module to perform process processing on the wafer; determining the bottleneck module of the semiconductor device according to the hardware information and the process time.

[0062] Specifically, multiple module cycle times are determined based on the number of modules, hardware time parameters, and process time. The module cycle time represents the minimum time required for a module to complete a wafer process. The module cycle time includes a first module cycle time corresponding to the loading module, a second module cycle time corresponding to the processing module, and a third module cycle time corresponding to the transfer module. The bottleneck time of the semiconductor device is determined based on the first, second, and third module cycle times, and the module corresponding to the bottleneck time is designated as the bottleneck module. Because the bottleneck module is the busiest module in the semiconductor device and determines production capacity, the maximum of the first, second, and third module cycle times is determined as the bottleneck time of the semiconductor device.

[0063] It should be noted that since the process module includes a process processing module, a process calibration module, a process cooling module and a process vacuum lock module, etc., the second module cycle time also includes the cycle time corresponding to each process module, such as the cycle time corresponding to the process processing module, the cycle time corresponding to the process calibration module, the cycle time corresponding to the process cooling module and the cycle time corresponding to the process vacuum lock module, etc., and the maximum value of the multiple cycle times is used as the second module cycle time; similarly, the third module cycle time includes the cycle time corresponding to the first robot, the cycle time corresponding to the second robot, etc., and the maximum value of the cycle time is used as the third module cycle time.

[0064] For ease of understanding, here we take the etching machine as an example to illustrate the process of determining the bottleneck module. Figure 1 The etching equipment shown in the figure performs the process of the process task as shown in Figure 3, which is as follows: ① The material (ie wafer) of the same job is Foup (Front Opening Unified ① After the wafers are loaded into the LoadPort module as a unit (Pod, front-opening wafer transfer box), the first robot ATM transports the single wafer to the Aligner module; ② After the wafers complete the angle calibration in the Aligner module, the first robot ATM transports the wafers to the LoadLock module in the vent state; ③ The LoadLock module acts as a pump to convert the air pressure in the cavity into a vacuum state, and the second robot VTM takes out the wafers and transports them to the PM module; ④ After the PM module completes the process on the wafers, the second robot VTM takes out the wafers and transports them to the LoadLock module in the pump state (i.e., vacuum state); ⑤ After the LoadLock module acts as a vent to convert the air pressure in the cavity into atmospheric state, the first robot ATM transports the wafers to the Cooler module for post-process cooling; ⑥ The first robot ATM sends the cooled wafers back to the LoadPort module. After all wafers complete the above processes, the Foup is unloaded.

[0065] In addition, for Figure 1 The seven modules in the process are the wafer loading module LoadPort, the process alignment module Aligner, the process vacuum lock module LoadLock, the process processing module PM, the process cooling module Cooler, the first robot ATM, and the second robot VTM. In semiconductor equipment production, the following relationship also holds true at the same location: SwapMoveTime < PickMoveTime + PlaceMoveTime. In actual production, given a process path: LoadPort1 -> ATM -> Aligner -> ATM -> LoadLockA -> VTM -> PM1 / PM2 / PM3 / PM4 -> VTM -> LoadLockA -> ATM -> LoadPort1, there are two relationships within this process path:

[0066] (1) Serial relationship; For example, in the path Aligner->ATM->LoadLockA, there is a serial relationship between Aligner and LoadLockA. The wafer must complete the Alignment calibration in Aligner before it can enter LoadLockA for the next process. Figure 4 As shown, Aligner needs to perform the calibration process on wafer W2, and LoadLockA needs to perform the process on wafer W1. In the serial relationship, if Aligner completes the process at its position earlier than LoadLockA, because its subsequent modules have not completed the process, W2 can only stay at Aligner and wait for the next position to complete the process. It can be seen that the time W1 stays at LoadLockA is the time it takes for LoadLockA to complete the process of one wafer; the time W2 stays at Aligner is also the time it takes for LoadLockA to complete the process of one wafer. Therefore, in this serial relationship, the bottleneck time of the entire semiconductor equipment is determined by the cycle time CycleTime of LoadLockA. At this time, LoadLockA is the bottleneck module of this serial relationship;

[0067] (2) Parallel relationship; For example, PM1 / PM2 / PM3 / PM4 in the path, the four PMs are in a parallel relationship. Figure 5As shown, wafer W2 in LoadLockA can proceed to any of PM1, PM2, PM3, or PM4 for the next process step. PM1 processes wafer W1, and LoadLockA processes wafer W2. If LoadLockA completes processing before PM1, wafer W2 does not need to remain in LoadLockA and can proceed to any of PM2, PM3, or PM4 for further processing. The processing time for a single wafer at each of PM1, PM2, PM3, or PM4 is shared by the four parallel PMs. Therefore, the cycle time (CycleTime) of a PM pathpoint is the ratio of the CycleTime of a single PM to the number of parallel processing modules (4).

[0068] Therefore, for semiconductor equipment, the cycle time of each module can be analyzed based on its hardware information and the process recipe information of the process task, thereby determining the location of the bottleneck module. The hardware information includes: the module number of the process module and hardware time parameters; the module number of the process module includes the number of process processing modules PM_Num and the number of process vacuum lock modules LL_Num; the hardware time parameters include the corresponding self-operation time of the process module and / or transfer module during the process, including but not limited to: the inflation time LoadLockVentTime and the exhaust time LoadLockPumpTime corresponding to the process vacuum lock module, the cooling time CoolingTime corresponding to the process cooling module, the self-rotation operation time of the first manipulator, i.e., the first rotation time ATMRotateTime of the first manipulator rotating between the two modules, and the self-rotation operation time of the second manipulator, i.e., the second rotation time VTMRotateTime of the second manipulator rotating between the two modules.

[0069] In addition, the process recipe information mainly includes: process path and process time; the process path here is the set of movement sequences of the wafer in the semiconductor equipment. In actual applications, for each target wafer, starting from the current position of the target wafer, along the process path, when the wafer placement action occurs, the scheduling branch corresponding to the target wafer can be generated.

[0070] As for the process time, it includes the time for the process module and / or transfer module to perform process processing on the wafer, including but not limited to: the process calibration time AlignmentTime corresponding to the process calibration module, the process processing time PMProcessTime corresponding to the process processing module, the first exchange and movement wafer time ATMSwapMoveTime corresponding to the first robot, the second exchange and movement wafer time VTMSwapMoveTime corresponding to the second robot, and the pick-up time PickMoveTime and the placement time PlaceMoveTime corresponding to the first robot; among them, the first exchange and movement wafer time ATMSwapMoveTime is used to characterize the time for the first robot ATM to complete SwapMove, that is, the target module has multiple slots, and there is a wafer1 that can be taken in the target Slot1 for taking the wafer, and there is an empty Slot2 that can be placed. The ATM puts the wafer2 in its hand into the empty Slot2, and then takes out the wafer1 from the target Slot1.

[0071] Similarly, the second wafer swap move time (VTMSwapMoveTime) represents the time it takes the second robot (VTM) to complete a SwapMove. This means that if the target module has multiple slots and there is a retrievable wafer 1 in the target slot 1 for wafer removal, and an empty slot 2 for wafer placement, the VTM uses Arm 1 to remove wafer 1 from slot 1 and places wafer 2 on Arm 2 into slot 1. PickMoveTime represents the time it takes the ATM to execute a PickMove, and PlaceMoveTime represents the time it takes the ATM to execute a PlaceMove.

[0072] It should be noted that the hardware information of the above-mentioned semiconductor equipment can be pre-stored in the controller, or stored in a storage module such as a database that is communicated with the controller, and obtained when the semiconductor equipment starts working; and the process recipe information of the process task needs to be re-acquired according to the different process tasks executed by the semiconductor equipment.

[0073] After obtaining the module number, hardware time parameters and process time of the process module as mentioned above, multiple module cycle times CycleTime can be determined based on the module number, hardware time parameters and process time. Here, CycleTime is used to characterize the minimum time required for the module to complete the process of a wafer; then, the bottleneck time of the semiconductor equipment is determined based on the multiple module cycle times. In practical applications, since the bottleneck module is the busiest module in the semiconductor equipment that determines the production capacity, it is preferred to use the maximum value of the multiple module cycle times as the bottleneck time of the semiconductor equipment, and the module corresponding to the bottleneck time as the bottleneck module.

[0074] Specifically, the process for determining the module cycle time (CycleTime) of each module in the etching machine tool equipment is as follows:

[0075] (A1) The module cycle time of the wafer loading module, LoadPort_Cycle;

[0076] Specifically, for the wafer loading module LoadPort, the wafer is taken out by the ATM at the LoadPort position and put back to the LoadPort after the process is completed in other modules. To complete the process of a given process path, a wafer must occupy the LoadPort module ATM at the LoadPort position for the time of one wafer pick-up and one wafer placement. Among them, one wafer pick-up and one wafer placement at the LoadPort can be achieved through PickMove for wafer pick-up and PlaceMove for wafer placement, or through an ATMSwapMove to complete one wafer pick-up and one wafer placement simultaneously at the LoadPort. Since SwapMoveTime < PickMoveTime + PlaceMoveTime, the calculation formula for the module cycle time LoadPort_Cycle of the wafer loading module is as follows: LoadPort_Cycle = Min(PickMoveTime + PlaceMoveTime, ATMSwapMoveTime) = ATMSwapMoveTime; that is, the module cycle time LoadPort_Cycle of the wafer loading module can be calculated according to the first wafer exchange movement time ATMSwapMoveTime.

[0077] (A2) The module cycle time of the process calibration module, Aligner_Cycle;

[0078] Specifically, the minimum time for the wafer to be put into the Aligner position by the ATM and taken away by the ATM after the Alignment calibration is completed is the module cycle time Aligner_Cycle of the Aligner module. Since the Aligner module is a single-slot module and there is only one ATM at the atmospheric end, the wafer can only be picked up through PickMove and placed through PlaceMove at the Aligner position. Therefore, Aligner_Cycle = AlignmentTime + PickMoveTime + PlaceMoveTime; where AlignmentTime represents the process calibration time, PickMoveTime represents the wafer pick-up time, and PlaceMoveTime represents the wafer placement time.

[0079] (A3) The module cycle time of the process processing module, PM_Cycle;

[0080] Specifically, the wafer is placed at the PM position by the VTM. After the process is completed, the minimum time for the VTM to pick up the wafer is the module cycle time PM_Cycle of the PM module. Since there are two available VTMs at the vacuum end, SwapMove can be performed at the PM. Considering that SwapMoveTime < PickMoveTime + PlaceMoveTime, the minimum time for the PM to complete one wafer pick-up and one wafer placement is VTMSwapMoveTime. That is, PM_Cycle = (PMProcessTime + VTMSwapMoveTime) / PM_Num; where PMProcessTime represents the process processing time, VTMSwapMoveTime represents the second wafer swapping and moving time, and PM_Num represents the number of process processing modules.

[0081] (A4) The module cycle time LL_Cycle of the process vacuum lock module;

[0082] Specifically, the LoadLock module interacts with both the ATM and the VTM. To complete the process of 1 wafer at its position, it needs to perform one PumpMove (i.e., evacuation operation) and one VentMove (i.e., gas filling operation) of the LoadLock, as well as one wafer in / out operation in cooperation with the ATM and one wafer in / out operation in cooperation with the VTM. It is known that the minimum time for the ATM and the VTM to complete one wafer in / out operation at the LoadLock is their respective one SwapMoveTime. Therefore, the module cycle time LL_Cycle of the process vacuum lock module = (LoadLockVentTime + ATMSwapMoveTime + LoadLockPumpTime + VTMSwapMoveTime) / LL_Num; where LoadLockVentTime represents the gas filling time, LoadLockPumpTime represents the evacuation time, ATMSwapMoveTime represents the first wafer swapping and moving time, VTMSwapMoveTime represents the second wafer swapping and moving time, and LL_Num represents the number of process vacuum lock modules.

[0083] (A5) The module cycle time Cooler_Cycle of the process cooling module;

[0084] Specifically, the minimum time it takes for a wafer to be placed by the ATM in the cooler position, cool down, and be removed by the ATM after cooling is the cooler module's module cycle time, Cooler_Cycle. Since the cooler module is a single-slot module and has only one ATM on the atmospheric side, wafers can only be retrieved using PickMove and placed using PlaceMove. Therefore, Cooler_Cycle = CoolingTime + PickMoveTime + PlaceMoveTime; where CoolingTime represents the cooling time, PickMoveTime represents the wafer retrieval time, and PlaceMoveTime represents the wafer placement time.

[0085] (A6) module cycle time ATM_Cycle of the first manipulator;

[0086] Specifically, the first robot ATM serves as a transmission module. To complete the process of one wafer, it is necessary to transport the wafer through the three modules of LoadPort, Aligner and LoadLock respectively to complete the wafer picking and placing. Since there is only one slot at the Aligner position, the ATM can only perform PickMove and PlaceMove at this position. After the wafer is placed in the Aligner, if the ATM waits for the Aligner process at the current position, the ATM will stay for an AlignmentTime. Therefore, for situations where cooling is not required, the ATM will first go to the LoadLock module to complete wafer picking, complete wafer placing at the LoadPort, and then complete wafer picking at the Aligner, complete wafer placing at the LoadLock, and then complete wafer picking at the LockPort and wafer placing at the Aligner to complete the wafer transportation in the three modules. This process includes 6 rotations of the ATM between different modules.

[0087] Therefore, the module cycle time for ATM to complete the transportation of a wafer from the three modules of LoadPort, Aligner and LoadLock respectively, that is, the module cycle time of the first robot ATM_Cycle = 3*PickMoveTime+3*PlaceMoveTime+6*ATMRotateTime; among them, PickMoveTime represents the wafer picking time, PlaceMoveTime represents the wafer placing time, and ATMRotateTime represents the first rotation time.

[0088] (A7) module cycle time VTM_Cycle of the second manipulator;

[0089] Similarly, the second robot, the VTM, functions as a transfer module. To complete processing on a single wafer, it must transport the wafer between the PM and LoadLock modules, performing both a wafer removal and placement operation. Because the VTM has two arms, it can perform a SwapMove in both modules. The minimum time required for the VTM to complete a wafer removal and placement operation between the PM and LoadLock modules is the VTM's SwapMoveTime between the two locations plus two VTM rotations between the modules.

[0090] Therefore, the module cycle time VTM_Cycle of the second robot is 2*VTMSwapMoveTime+2*VTMRotateTime; wherein VTMSwapMoveTime represents the second exchange wafer movement time, and VTMRotateTime represents the second rotation time.

[0091] Furthermore, because the modules at each point in the process path are serially connected, the overall semiconductor device process time required to complete a single wafer depends on the module with the longest cycle time. Therefore, the bottleneck time (CycleTime) of the semiconductor device should be the maximum of the module cycle times. This module is the bottleneck module, and when selecting branches, the most efficient use of the bottleneck module should be considered. In actual applications, since no processes need to be executed at the LoadPort location, it will not become a bottleneck.

[0092] Therefore, the bottleneck time of the semiconductor device, CycleTime = Max(ATM_Cycle, LL_Cycle, VTM_Cycle, PM_Cycle, Cooler_Cycle, Aligner_Cycle), refers to the maximum module cycle time of multiple modules as the bottleneck time of the semiconductor device, and the module corresponding to the bottleneck time is determined as the bottleneck module. This bottleneck module determination method fully considers the module cycle time of each module in the semiconductor device and selects the module corresponding to the maximum module cycle time as the bottleneck module, improving the accuracy of bottleneck module determination, thereby improving the scheduling control accuracy of wafers in the semiconductor device and further increasing the production capacity of the semiconductor device.

[0093] Example 2:

[0094] Based on the above embodiment, the embodiment of the present invention provides another wafer scheduling method, which focuses on describing the process of executing the wafer scheduling method by a virtual machine device. Figure 6 As shown in the figure, it mainly includes the following five parts: system state machine, scheduling algorithm, bottleneck calculator, branch screening rules and branch executor; the functions of each part are as follows:

[0095] (1) System state machine: This is a virtual machine that is initially in an empty state, with only unprocessed wafers stored at the source of the material. The scheduling algorithm calculates and selects a branch that can be executed once (i.e., the target scheduling branch). The system state machine simulates the execution of this branch and saves the system state after execution to continue calling the algorithm to calculate the next action.

[0096] (2) Scheduling algorithm: Generate corresponding scheduling branches for all schedulable target wafers in the system state machine along their process paths; that is, for any target wafer, take the current position of the target wafer as the starting point, generate branches along the process path until the wafer placement action occurs, and use the generated branches as the scheduling branches for the target wafer.

[0097] For example, if the system state machine is Figure 1 For the etching machine equipment in, at this time, if the starting point of the target wafer wafer1 is PM1, the subsequent path of its Job is PM1->PM2->LoadLockA; at this time, if PM2 has no process sheet (i.e., wafer), the target wafer wafer1 can be placed in PM2 after being taken from PM1. The branches generated by the target wafer wafer1 along the process path include two actions, PM1 Pick and PM2Place, that is, the scheduling branch corresponding to the target wafer wafer1 at this time is Pick From PM1->Place To PM2.

[0098] In addition, if PM2 has wafer 2 that has completed the process, the target wafer wafer 1 cannot generate a Place action at the next node of the path after PM1 Pick. Instead, wafer 1 and wafer 2 are swapped through the VTM Swap action. At the same time, wafer 2 generates a Place action at LoadLockA along the subsequent path. The branches generated by wafer 1 along the process path include three actions: PM1 Pick, PM2 Swap, and LoadLockA Place. That is, the scheduling branch corresponding to the target wafer wafer 1 at this time is Pick From PM1->Swap In PM2->Place To LoadLockA.

[0099] Therefore, for each schedulable target wafer, a corresponding scheduling branch can be generated along the process path, starting from the current position.

[0100] (3) a bottleneck calculator; used to calculate the module cycle time of each module in the virtual machine equipment, determine the bottleneck time based on multiple module cycle times, and determine the module corresponding to the bottleneck time as the bottleneck module; the specific calculation of the module cycle time and bottleneck time can refer to the bottleneck module determination process of the etching machine equipment in the aforementioned embodiment, and the embodiment of the present invention will not be described in detail here;

[0101] (4) Branch screening rules; including: minimum stay time rule, swap priority rule (i.e., swap priority rule) and bottleneck module priority on-chip rule; among them, in order to achieve the optimal scheduling of the serial system, the priority of the minimum stay time rule is set higher than the swap priority rule and bottleneck module priority on-chip rule, that is, the minimum stay time rule is prioritized for screening. If the target scheduling branch cannot be screened out according to the minimum stay time rule, then the swap priority rule or bottleneck module priority on-chip rule is used for screening.

[0102] Specifically, the process of each screening rule determining the target scheduling branch is as follows:

[0103] ① Minimum stay time rule;

[0104] Assume that the system state machine has five serial modules A to E, and each module needs to process the wafer. The wafer is moved between different modules by a robot. After the wafer completes the process in the current module, it can be moved to the next module for processing. Figure 7 As shown in the figure, in the serial relationship of a single wafer, the wafer at position A needs to be moved to position E. After the process in module A is completed, the robot must immediately move it to module B for processing, and continue to move it after the process at position B is completed until it reaches position E and completes all processes.

[0105] In addition, for the case of multiple wafers in series, there are multiple movable wafers. For example, multiple wafers at position A need to be moved to position E. For each position node, there is a relationship that the wafer at position A moves to position B, the wafer at position B moves to position C, the wafer at position C moves to position D, and the wafer at position D moves to position E. Figure 8 As shown, there are wafers at positions A and C that need to be moved to the next position, and there are multiple wafers at position A, that is, the black shadow and gray shadow in A are used to represent wafers, black represents wafers that have completed the process, and gray represents wafers that have not completed the process.

[0106] Assume that the process at position A still requires 3 seconds to complete, and position C requires another 5 seconds to complete. The robot takes 5 seconds to complete a wafer pick-up and 5 seconds to complete a wafer placement. If the wafer at position C is moved first, followed by the wafer at position A, the wafer at position C can be removed by the robot 5 seconds later and placed in position D. The robot then moves to position A to move the wafer. The time required for the entire system to complete the scheduling of the two wafers is the robot's dwell time of 5 seconds at position C, the transfer time of 10 seconds at position C, and the transfer time of 10 seconds at position A, for a total of 25 seconds. If the wafer at position A is moved first, the robot's dwell time at position A is 3 seconds. After 3 seconds, the wafer can be removed by the robot and placed in position B. The robot then moves to position C to move the wafer. The time required for the entire system to complete the scheduling of the two wafers is the waiting time of 3 seconds at position A, the transfer time of 10 seconds at position A, and the transfer time of 10 seconds at position C, for a total of 23 seconds.

[0107] Therefore, in the serial relationship of multiple wafers, the robot prioritizes the wafer that has completed the process earlier and transports it to the next module as soon as possible, so that the entire system can complete the process of all wafers more efficiently. The time the robot waits for the module process is the time the robot stays in the module. If the robot completes the handling of multiple wafers in one branch, such as Figure 9 As shown, wafers at both positions A and B can be handled. The process at position A requires 3 seconds, while the process at position B requires 2 seconds. Therefore, two scheduling branches can be generated: Branch 1: Pick From A -> Swap In B -> Place To C; and Branch 2: Pick From B -> Place To C. The robot's dwell time in Branch 1 is 3 seconds, while in Branch 2 it is 2 seconds. However, after completing the handling of two wafers in Branch 1, each wafer waits an average of 1.5 seconds for the process; while in Branch 2, each wafer waits an average of 2 seconds for the process. Therefore, according to the minimum dwell time rule, Branch 1 should be the target scheduling branch.

[0108] It should be noted that the above-mentioned minimum residence time rule can also be called the minimum residence time rule for the robot, that is, for each scheduling branch, the average waiting time of the robot in transporting multiple wafers in the scheduling branch is calculated respectively, and the scheduling branch with the minimum average waiting time is used as the target scheduling branch, thereby achieving the optimal scheduling of the wafer serial system and improving the production capacity of the system state machine.

[0109] ②Exchange priority rules;

[0110] When the target scheduling branch cannot be selected from multiple scheduling branches according to the above minimum residence time rule, at this time, the judgment of the bottleneck module is added. Specifically, if the bottleneck module is a transfer module, that is, if the bottleneck module is the first manipulator or the second manipulator, at this time, the target scheduling branch is determined from multiple scheduling branches according to the swap priority rule.

[0111] For the manipulator, since there is a relationship of SwapMoveTime < PickMoveTime + PlaceMoveTime, it is more optimal for the manipulator to complete one wafer loading and unloading with SwapMove. At this time, for multiple scheduling branches, analyze the SwapMove existing in each scheduling branch respectively, and take the scheduling branch with the largest number of SwapMove as the target scheduling branch. For example, for multiple scheduling branches, when the target scheduling branch cannot be selected according to the minimum residence time rule (such as the average waiting time of the manipulator in multiple scheduling branches is the same), however, it is determined that the bottleneck module is the first manipulator ATM. At this time, calculate the number of SwapMove completed by ATM in each scheduling branch respectively, and take the scheduling branch with the largest number of SwapMove completed by ATM as the target scheduling branch, so as to improve the production capacity of the system state machine as much as possible.

[0112] ③ Bottleneck module first wafer loading rule;

[0113] When the target scheduling branch cannot be selected from multiple scheduling branches according to the above minimum residence time rule, at this time, the judgment of the bottleneck module is added. Specifically, if the bottleneck module is a process module, that is, if the bottleneck module is a process processing module, a process calibration module, a process cooling module, or a process vacuum lock module, at this time, the target scheduling branch is determined from multiple scheduling branches according to the bottleneck module first wafer loading rule, that is, for multiple scheduling branches, the principle of preferentially transporting the wafer to the bottleneck module is used to determine the target scheduling branch from multiple scheduling branches.

[0114] For the convenience of understanding, an example is given here. As Figure 10 shown, there is W1 (black shaded part) that has completed the process at position A, W2 that has completed the process at position C, and W3 that has completed the process at position D; then the scheduling branches for each wafer can be generated as follows:

[0115] W1 generates scheduling branch one: Pick From A -> Place To B;

[0116] W2 generates scheduling branch two: Pick From C -> Swap In D -> Place To E;

[0117] W3 generates scheduling branch three: Pick From D->Place To E.

[0118] Since the above-mentioned wafers W1, W2 and W3 have all completed the process, they are first screened according to the minimum dwell time rule. The robot dwell time of the three scheduling branches is all 0. Therefore, the target scheduling branch cannot be screened out from the three scheduling branches according to the minimum dwell time rule. At this time, if the bottleneck module is located in the robot, it is screened according to the exchange priority rule, and the scheduling branch two is the target scheduling branch; if the bottleneck module is in module B, it is screened according to the bottleneck module priority loading principle, and the scheduling branch one is the target scheduling branch. In addition, if there is no bottleneck module in the scheduling branch, for example, the bottleneck module is located in C, it is screened according to the bottleneck module priority loading principle. At this time, the bottleneck module priority loading requires that there is a wafer at position B, so the scheduling branch one is determined as the target scheduling branch.

[0119] In summary, when screening the target scheduling branch, it is first screened according to the minimum residence time rule. If the optimal scheduling branch is not screened out, it is further screened according to the exchange priority rule or the bottleneck module priority loading principle. If the bottleneck module is located in the robot, it is further screened according to the exchange priority rule. If the bottleneck module is located in the process module such as the process processing module or the process vacuum lock module, it is further screened according to the bottleneck module priority loading principle. Therefore, when screening multiple scheduling branches according to the screening rules, the judgment of the bottleneck module is introduced, so that the scheduling branch that can best meet the highest bottleneck module utilization can be screened out according to the different scenario bottlenecks, thereby improving the overall capacity of the system state machine.

[0120] (5) Branch executor; used to simulate the execution of the selected target scheduling branch, and after the execution is completed, redetermine the schedulable wafers in the system state machine according to the state after execution, and regenerate the branch of each wafer, and determine the target scheduling branch corresponding to the next state, and simulate the execution of the selected branch through the branch executor; and so on, until all wafers used in the process task have completed the simulated process task, and generate a total Move sequence according to the execution branches corresponding to each state or moment, so that the controller controls the process tasks in the system state machine according to the total Move sequence, thereby improving the capacity of the system state machine.

[0121] In summary, the above wafer scheduling method introduces the judgment of the bottleneck module when screening multiple scheduling branches according to the screening rules, so that the scheduling branch that can best meet the highest bottleneck module utilization can be screened out according to different scenario bottlenecks, thereby improving the overall production capacity of the system state machine.

[0122] An embodiment of the present invention further provides a semiconductor device, including a processor and a memory, wherein the memory stores machine-executable instructions that can be executed by the processor, and the processor executes the machine-executable instructions to implement the above-mentioned wafer scheduling method.

[0123] See also Figure 11 As shown, the semiconductor device includes a processor 100 and a memory 101 . The memory 101 stores machine executable instructions that can be executed by the processor 100 . The processor 100 executes the machine executable instructions to implement the above wafer scheduling method.

[0124] Furthermore, Figure 11 The semiconductor device shown further includes a bus 102 and a communication interface 103 , and the processor 100 , the communication interface 103 , and the memory 101 are connected via the bus 102 .

[0125] Among them, the memory 101 may include high-speed random access memory (RAM), and may also include non-volatile memory (non-volatile memory), such as at least one disk storage. The communication connection between the system network element and at least one other network element is realized through at least one communication interface 103 (which can be wired or wireless), and the Internet, wide area network, local area network, metropolitan area network, etc. can be used. The bus 102 can be an ISA (Industrial Standard Architecture, industrial standard structure bus) bus, PCI (Peripheral Component Interconnect, peripheral component interconnect standard) bus or EISA (Enhanced Industry Standard Architecture, extended industry standard architecture) bus, etc. The above-mentioned bus can be divided into an address bus, a data bus, a control bus, etc. For the convenience of representation, Figure 11 Only one bidirectional arrow is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0126] The processor 100 may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by hardware integrated logic circuits in the processor 100 or software instructions. The above processor 100 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the method disclosed in conjunction with the embodiments of the present invention can be directly implemented and executed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium well-known in the art, such as a random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or register. The storage medium is located in the memory 101. The processor 100 reads the information in the memory 101 and, in conjunction with its hardware, completes the steps of the method of the aforementioned embodiment.

[0127] This embodiment also provides a machine-readable storage medium, which stores machine-executable instructions. When the machine-executable instructions are called and executed by a processor, the machine-executable instructions prompt the processor to implement the above-mentioned wafer scheduling method.

[0128] The wafer scheduling method and computer program product of the semiconductor device provided by the embodiments of the present invention include a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the methods described in the previous method embodiments. For specific implementation, please refer to the method embodiments and will not be repeated here.

[0129] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems and devices can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0130] In addition, in the description of the embodiments of the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; they may refer to mechanical connections or electrical connections; they may refer to direct connections or indirect connections through an intermediate medium; and they may refer to internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0131] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0132] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0133] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the above-described embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily conceive of changes to the technical solutions described in the above-described embodiments within the technical scope disclosed by the present invention, or replace some of the technical features therein with equivalents. Such modifications, changes, or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.

Claims

1. A wafer scheduling method, characterized in that: include: Determine a bottleneck module of a semiconductor device; wherein the bottleneck module is used to characterize the module that takes the longest process time to complete a single wafer of the semiconductor device, and includes one of the following: a loading module, a process module, and a transfer module; Taking the current state of the semiconductor device as a starting point, searching for all schedulable target wafers, and traversing each target wafer to generate a scheduling branch corresponding to each target wafer; wherein the scheduling branch is used to represent a branch generated along the process path starting from the current position of the target wafer; Based on the branch screening rules and the bottleneck module, a target scheduling branch is determined from the multiple scheduling branches, and the multiple target wafers are controlled to run according to the target scheduling branch; wherein the branch screening rules include: a minimum stay time rule, an exchange priority rule and a bottleneck module priority loading rule; the minimum stay time rule is used to characterize that in each scheduling branch, the average waiting time of the transfer module for transporting the multiple target wafers in the scheduling branch is calculated, and the scheduling branch with the minimum average waiting time is used as the target scheduling branch; the exchange priority rule is used to characterize the rule of taking the scheduling branch with the most exchange operations as the target scheduling branch; the bottleneck module priority loading rule is used to characterize the rule of taking the scheduling branch containing wafers transported to the bottleneck module as the target scheduling branch.

2. The method according to claim 1, characterized in that The step of determining a target scheduling branch from the plurality of scheduling branches based on the branch screening rule and the bottleneck module includes: determining whether to determine a target scheduling branch from the plurality of scheduling branches based on the minimum stay time rule; If not, the target scheduling branch is determined from the plurality of scheduling branches based on the bottleneck module and in accordance with the switching priority rule or the bottleneck module priority loading rule.

3. The method according to claim 2, characterized in that The step of determining the target scheduling branch from the plurality of scheduling branches based on the bottleneck module and according to the switching priority rule or the bottleneck module priority loading rule includes: If the bottleneck module is the transfer module, the target scheduling branch is determined from the plurality of scheduling branches according to the switching priority rule.

4. The method according to claim 2, characterized in that The step of determining the target scheduling branch from the plurality of scheduling branches based on the bottleneck module and according to the switching priority rule or the bottleneck module priority loading rule includes: If the bottleneck module is the process module, the target scheduling branch is determined from the plurality of scheduling branches according to the bottleneck module priority loading rule.

5. The method according to claim 1, wherein The step of traversing each target wafer and generating a scheduling branch corresponding to each target wafer includes: For any of the target wafers, a branch is generated along the process path with the current position of the target wafer as the starting point until a wafer placement action occurs, and the generated branch is used as the scheduling branch for the target wafer.

6. The method according to claim 1, characterized in that The step of determining the bottleneck module of the semiconductor equipment includes: Obtaining hardware information of the semiconductor device and process recipe information of the process task; wherein the hardware information includes: the module number and hardware time parameters of the process module, and the hardware time parameters include: the corresponding running time of the process module and / or the transfer module during the process; the process recipe information includes the process path and process time, wherein the process path is used to represent the movement sequence set of the wafer in the semiconductor device, and the process time includes: the time for the process module and / or the transfer module to process the wafer; A bottleneck module of the semiconductor equipment is determined according to the hardware information and the process time.

7. The method according to claim 6, characterized in that The step of determining the bottleneck module of the semiconductor equipment according to the hardware information and the process time includes: Determining a plurality of module cycle times according to the number of modules, the hardware time parameters, and the process time; wherein the module cycle time is used to represent the minimum time required for the module to complete a wafer process, including: a first module cycle time corresponding to the loading module, a second module cycle time corresponding to the process module, and a third module cycle time corresponding to the transfer module; The bottleneck time of the semiconductor device is determined according to the first module cycle time, the second module cycle time, and the third module cycle time, and the module corresponding to the bottleneck time is used as the bottleneck module.

8. The method according to claim 7, characterized in that The step of determining the bottleneck time of the semiconductor device according to the first module cycle time, the second module cycle time and the third module cycle time comprises: A maximum value among the first module cycle time, the second module cycle time, and the third module cycle time is determined as the bottleneck time of the semiconductor equipment.

9. A semiconductor device, characterized in that: The system comprises a controller and a plurality of modules in communication with the controller; wherein the plurality of modules comprise a loading module, a process module and a transfer module; The controller is used to implement the steps of the wafer scheduling method described in any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the wafer scheduling method according to any one of claims 1 to 8 are executed.

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