A simulated sine wave inverter circuit

Abstract

The application discloses a kind of analog sine wave inverter circuit, it is related to inverter technical field, including micro control module, control positive period module and negative period module to the direct current energy of power module access carry out stepped voltage regulation and output four stepped wave state electric energy, by voltage regulation and output waveform close to sine wave alternating current energy of voltage output module, fault detection module carries out voltage change rate detection, and when voltage change rate exceeds the first voltage threshold set, it indicates that the square wave state electric energy change abnormality is output at this time by stepped voltage regulation, and according to the stepped voltage regulation state of positive period module and negative period module, change the transmission path of electric energy, control positive period module and negative period module change stepped regulation quantity, and provide two stepped wave state electric energy.The application discloses analog sine wave inverter circuit can reduce high harmonic, when switch element fails, maintain ac power supply, improve power supply efficiency.

Description

Technical Field

[0001] This invention relates to the field of inverter technology, specifically to an analog sine wave inverter circuit. Background Technology

[0002] A simulated sine wave inverter is a device that converts direct current (DC) into alternating current (AC), and the AC waveform it outputs is a modified square wave or stepped wave to closely approximate the standard sine wave in a household power grid. This allows it to power simple appliances such as lighting, charging mobile phones, and operating electric blankets or rice cookers, and it is relatively inexpensive. However, the stepped wave output by this simulated sine wave inverter contains certain high-order harmonics, which can cause electronic equipment malfunctions. Furthermore, if the driving switching elements fail during inverter operation, it will lead to abnormal power supply and reduce inverter efficiency. Therefore, improvements are needed. Summary of the Invention

[0003] This invention provides a simulated sinusoidal inverter circuit to solve the problems mentioned in the background art.

[0004] According to an embodiment of the present invention, a simulated sine wave inverter circuit is provided, comprising:

[0005] The power module is used to connect to DC power.

[0006] The positive cycle module, connected to the power supply module and the fault detection module, is used to perform step voltage regulation of DC power through positive cycle switching elements and output the first power in the second-order wave state or the second power in the fourth-order wave state. When the first fault signal is received from the fault detection module, the first power in the second-order wave state is output.

[0007] The negative cycle module, connected to the power supply module and the fault detection module, is used to perform step voltage regulation of DC power through negative cycle switching elements and output the third power in the second-order wave state or the fourth power in the fourth-order wave state. When the first fault signal is received from the fault detection module, the third power in the second-order wave state is output.

[0008] The transformer output module, connected to the positive cycle module and the negative cycle module, is used to transform and output the first electrical energy and the third electrical energy, or the second electrical energy and the fourth electrical energy.

[0009] The fault detection module, connected to the transformer output module and the microcontroller module, is used to perform voltage division sampling of the electrical energy output by the transformer output module and amplify the sampled signal to output a first detection signal. The first detection signal is then subjected to voltage change rate detection, and if the voltage change rate of the first detection signal is greater than a set first voltage threshold, a second detection signal is output. When the second detection signal is output and the positive cycle module performs the first or third step voltage adjustment, or the negative cycle module performs the first or third step voltage adjustment, a first fault signal is self-locked out. When the positive cycle module performs the second or fourth step voltage adjustment, or the negative cycle module performs the second or fourth step voltage adjustment, a second fault signal is output.

[0010] The microcontroller module, connected to the positive cycle module and the negative cycle module, is used to control the positive cycle module and the negative cycle module to generate the second electrical energy and the fourth electrical energy in the fourth-order wave state, respectively. When a first fault signal or a second fault signal is received, the microcontroller module adjusts the conduction angle of the switching elements of the positive cycle module and the negative cycle module and controls the positive cycle module and the negative cycle module to generate the first electrical energy and the third electrical energy in the second-order wave state, respectively. When the first fault signal and the second fault signal are received, the microcontroller module stops controlling the positive cycle module and the negative cycle module.

[0011] As a further embodiment of the present invention: the power supply module includes a power interface; the positive cycle module includes a first power transistor, a first resistor, a second power transistor, a first thyristor, a fifth thyristor, a third power transistor, a second resistor, a fourth power transistor, a second thyristor, and a sixth thyristor; the microcontroller module includes a first controller;

[0012] Preferably, the first end of the power interface is connected to the drain of the first power transistor, the drain of the second power transistor, the drain of the third power transistor, and the drain of the fourth power transistor. The anode of the first power transistor is connected to the cathode of the first thyristor through a first resistor. The source of the second power transistor is connected to the anode of the first thyristor and the anode of the fifth thyristor. The source of the third power transistor is connected to the cathode of the second thyristor through a second resistor. The source of the fourth power transistor is connected to the anode of the second thyristor and the anode of the sixth thyristor. The control terminal of the fifth thyristor is connected to the control terminal of the sixth thyristor. The control terminal of the first thyristor is connected to the control terminal of the second thyristor and the IO9 terminal of the first controller. The gates of the first power transistor, the second power transistor, the third power transistor, and the fourth power transistor are respectively connected to the IO1, IO2, IO3, and IO4 terminals of the first controller.

[0013] As a further embodiment of the present invention: the negative cycle module includes a fifth power transistor, a sixth power transistor, a seventh power transistor, an eighth power transistor, a third resistor, a fourth resistor, a third thyristor, a fourth thyristor, a seventh thyristor, and an eighth thyristor.

[0014] Preferably, the drain of the fifth power transistor is connected to the drains of the sixth, seventh, and eighth power transistors and the first terminal of the power interface; the source of the fifth power transistor is connected to the anodes of the third and seventh thyristors; the source of the sixth power transistor is connected to the cathode of the third thyristor through a third resistor; the source of the seventh power transistor is connected to the anodes of the fourth and eighth thyristors; the source of the eighth power transistor is connected to the cathode of the fourth thyristor through a fourth resistor; the control terminal of the fourth thyristor is connected to the control terminal of the third thyristor and the IO9 terminal of the first controller; the control terminal of the seventh thyristor is connected to the control terminal of the eighth thyristor; and the gates of the fifth, sixth, seventh, and eighth power transistors are respectively connected to the IO5, IO6, IO7, and IO8 terminals of the first controller.

[0015] As a further embodiment of the present invention: the transformer output module includes a first transformer and an output port;

[0016] Preferably, the first, second, third, fourth, fifth, sixth, seventh, eighth, and ninth terminals of the primary side of the first transformer are respectively connected to the cathodes of the first, fifth, second, and sixth thyristors, the second terminal of the power interface, the cathodes of the seventh, third, eighth, and fourth thyristors, and the first and second terminals of the secondary side of the first transformer are respectively connected to the first and second terminals of the output port.

[0017] As a further embodiment of the present invention: the fault detection module includes a first inverter;

[0018] Preferably, the output terminal of the first inverter is connected to the control terminals of the seventh and sixth thyristors, and the input terminal of the first inverter is connected to the IO8 terminal of the first controller.

[0019] As a further embodiment of the present invention: the fault detection module further includes a fifth resistor, a sixth resistor, a first operational amplifier, a seventh resistor, an eighth resistor, a ninth resistor, a second operational amplifier, a third operational amplifier, a first capacitor, and a tenth resistor;

[0020] Preferably, one end of the fifth resistor is connected to the first end of the output port, the other end of the fifth resistor is connected to the inverting input of the first operational amplifier and connected to the second end of the output port through the sixth resistor, the non-inverting input of the first operational amplifier is connected to one end of the seventh resistor and grounded through the sixth resistor, the output end of the first operational amplifier is connected to the other end of the seventh resistor and connected to one end of the ninth resistor and the inverting input of the second operational amplifier through the eighth resistor, the non-inverting inputs of the second and third operational amplifiers are both grounded, the other end of the ninth resistor is connected to the output end of the third operational amplifier and connected to the inverting input of the third operational amplifier and one end of the tenth resistor through the first capacitor, and the other end of the tenth resistor is connected to the output end of the second operational amplifier.

[0021] As a further embodiment of the present invention: the fault detection module further includes an absolute value device, a first reference power supply, a first comparator, a first logic device, a second logic device, a first diode, a second diode, a third diode, a fourth diode, a fifth diode, a sixth diode, a seventh diode, an eighth diode, and a self-locking device.

[0022] Preferably, the input terminal of the absolute value device is connected to the output terminal of the second operational amplifier, the output terminal of the absolute value device is connected to the non-inverting input of the first comparator, the inverting input of the first comparator is connected to the first reference power supply, the output terminal of the first comparator is connected to the A terminal of the first logic unit and the B terminal of the second logic unit, the B terminal of the first logic unit is connected to the cathodes of the first diode, the second diode, the third diode, and the eighth diode, the A terminal of the second logic unit is connected to the cathodes of the fourth diode, the seventh diode, the fifth diode, and the sixth diode, the anodes of the first diode, the second diode, the third diode, the fourth diode, the fifth diode, the sixth diode, the seventh diode, and the eighth diode are respectively connected to the IO1, IO3, IO6, IO4, IO5, IO7, IO2, and IO8 terminals of the first controller, the Y terminal of the first logic unit is connected to the input terminal of the self-locking device, the Y terminal of the second logic unit is connected to the IO10 terminal of the first controller, and the output terminal of the self-locking device is connected to the input terminal of the first inverter and the IO9 terminal of the first controller.

[0023] Compared with the prior art, the beneficial effects of the present invention are as follows: The simulated sinusoidal inverter circuit of the present invention can be controlled by a microcontroller module to perform stepped voltage regulation on the DC power input to the power supply module by the positive cycle module and the negative cycle module respectively, and output power in a four-step wave state within the positive and negative cycles. The transformer output module performs transformer regulation and outputs AC power. The waveform of the AC power is close to a sine wave and can reduce high-order harmonics. The fault detection module detects the voltage change rate of the power output when the positive cycle module and the negative cycle module are performing stepped voltage regulation. When the voltage change rate exceeds the set first voltage threshold, it indicates that the square wave state power output during stepped voltage regulation is abnormal. Based on the stepped voltage regulation state of the positive cycle module and the negative cycle module, the power transmission path is changed, the number of stepped regulation steps of the positive cycle module and the negative cycle module is changed, and power in a two-step wave state is provided to maintain AC power supply and improve power supply efficiency. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic block diagram of a simulated sine wave inverter circuit provided in an embodiment of the present invention.

[0026] Figure 2 A circuit diagram of a simulated sine wave inverter circuit provided for an embodiment of the present invention.

[0027] Figure 3 The circuit diagram is provided for a fault detection module in an embodiment of the present invention. Detailed Implementation

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] In one embodiment, see Figure 1 A simulated sinusoidal inverter circuit, comprising:

[0030] Power module 1 is used to connect to DC power.

[0031] Positive cycle module 2, connected to power supply module 1 and fault detection module 5, is used to perform step voltage regulation of DC power through positive cycle switching elements and output the first power in the second-order wave state or the second power in the fourth-order wave state. When the first fault signal output by fault detection module 5 is received, the first power in the second-order wave state is output.

[0032] The negative cycle module 3 is connected to the power supply module 1 and the fault detection module 5. It is used to perform step voltage regulation of DC power through the negative cycle switching element and output the third power in the second-order wave state or the fourth power in the fourth-order wave state. When the first fault signal output by the fault detection module 5 is received, the third power in the second-order wave state is output.

[0033] Transformer output module 4, connected to positive cycle module 2 and negative cycle module 3, is used to transform the first electrical energy and the third electrical energy or to transform the second electrical energy and the fourth electrical energy and output them.

[0034] The fault detection module 5, connected to the transformer output module 4 and the microcontroller module 6, is used to perform voltage division sampling on the electrical energy output by the transformer output module 4 and amplify the sampled signal to output a first detection signal. The first detection signal is then subjected to voltage change rate detection, and if the voltage change rate of the first detection signal is greater than a set first voltage threshold, a second detection signal is output. When the second detection signal is output and the positive cycle module 2 performs the first or third step voltage adjustment, or the negative cycle module 3 performs the first or third step voltage adjustment, a first fault signal is self-locked out. When the second or fourth step voltage adjustment is performed during the positive cycle, or the second or fourth step voltage adjustment is performed during the negative cycle, a second fault signal is output.

[0035] The microcontroller module 6 is connected to the positive cycle module 2 and the negative cycle module 3. It is used to control the positive cycle module 2 and the negative cycle module 3 to generate the second electrical energy and the fourth electrical energy in the fourth-order wave state, respectively. When a first fault signal or a second fault signal is received, it adjusts the conduction angle of the switching elements of the positive cycle and the negative cycle and controls the positive cycle module 2 and the negative cycle module 3 to generate the first electrical energy and the third electrical energy in the second-order wave state, respectively. When the first fault signal and the second fault signal are received, it stops controlling the positive cycle module 2 and the negative cycle module 3.

[0036] In a specific embodiment, the power supply module 1 can be a power circuit composed of power ports to receive DC power; the positive cycle module 2 can be a positive cycle circuit composed of field-effect transistors, resistors, and thyristors. During the positive cycle, the microcontroller module 6 can perform step-wise voltage regulation control, outputting square wave power with step-wise rises and falls, which can be divided into first-step voltage regulation, second-step voltage regulation, third-step voltage regulation, and fourth-step voltage regulation, and can control the direction of power transmission and change the number of steps; the negative cycle module 3 can be a negative cycle circuit composed of field-effect transistors, resistors, and thyristors. During the negative cycle, the microcontroller module 6 can perform step-wise voltage regulation control, outputting square wave power with step-wise rises and falls, which can be divided into first-step voltage regulation, second-step voltage regulation, third-step voltage regulation, and fourth-step voltage regulation, and can control the direction of power transmission and change the number of steps; the transformer output module 4 can be... The transformer output circuit, composed of a transformer and an output port, can perform voltage regulation and output AC power with a waveform close to a sine wave. The fault detection module 5 can be a fault detection circuit composed of resistors, operational amplifiers, capacitors, logic devices, comparators, etc. It can perform voltage division sampling and amplification processing on the power output from the transformer output module 4, detect the voltage change rate of the processed signal, compare the voltage change rate with the voltage of the set first voltage threshold, and control the positive cycle module 2 and negative cycle module 3 to change the power transmission path when the voltage change rate is greater than the first voltage threshold and according to the step voltage regulation stage of the positive cycle module 2 and negative cycle module 3, and control the positive cycle module 2 and negative cycle module 3 to generate power in a second-order wave state. The microcontroller module 6 can be a microcontroller circuit composed of a single-chip microcomputer, which integrates many components such as an arithmetic unit, a controller, a memory, and input / output devices to realize functions such as signal processing, data storage, module control, and timing control.

[0037] In another embodiment, please refer to Figure 1 , Figure 2 and Figure 3 The power module 1 includes a power interface; the positive cycle module 2 includes a first power transistor Q1, a first resistor R1, a second power transistor Q2, a first thyristor S1, a fifth thyristor S5, a third power transistor Q3, a second resistor R2, a fourth power transistor Q4, a second thyristor S2, and a sixth thyristor S6; the microcontroller module 6 includes a first controller U1;

[0038] Specifically, the first end of the power interface is connected to the drain of the first power transistor Q1, the drain of the second power transistor Q2, the drain of the third power transistor Q3, and the drain of the fourth power transistor Q4. The anode of the first power transistor Q1 is connected to the cathode of the first thyristor S1 through the first resistor R1. The source of the second power transistor Q2 is connected to the anode of the first thyristor S1 and the anode of the fifth thyristor S5. The source of the third power transistor Q3 is connected to the cathode of the second thyristor S2 through the second resistor R2. The source of the fourth power transistor Q4 is connected to the anode of the second thyristor S2 and the anode of the sixth thyristor S6. The control terminal of the fifth thyristor S5 is connected to the control terminal of the sixth thyristor S6. The control terminal of the first thyristor S1 is connected to the control terminal of the second thyristor S2 and the IO9 terminal of the first controller U1. The gates of the first power transistor Q1, the second power transistor Q2, the third power transistor Q3, and the fourth power transistor Q4 are respectively connected to the IO1, IO2, IO3, and IO4 terminals of the first controller U1.

[0039] In a specific embodiment, the first power transistor Q1, the second power transistor Q2, the third power transistor Q3, and the fourth power transistor Q4 can all be N-channel MOSFETs, respectively performing first-step voltage regulation, second-step voltage regulation, third-step voltage regulation, and fourth-step voltage regulation control, and the electrical energy output by the first-step voltage regulation, second-step voltage regulation, third-step voltage regulation, and fourth-step voltage regulation is all in square wave state; the first thyristor S1, the second thyristor S2, the fifth thyristor S5, and the sixth thyristor S6 can all be unidirectional thyristors; the first controller U1 can be an STM32 microcontroller; the voltage drops of the first resistor R1, the fifth thyristor S5, the second thyristor S2, the second resistor R2, the sixth thyristor S6, and the first thyristor S1 are all equal.

[0040] Furthermore, the negative cycle module 3 includes a fifth power transistor Q5, a sixth power transistor Q6, a seventh power transistor Q7, an eighth power transistor Q8, a third resistor R3, a fourth resistor R4, a third thyristor S3, a fourth thyristor S4, a seventh thyristor S7, and an eighth thyristor S8.

[0041] Specifically, the drain of the fifth power transistor Q5 is connected to the drain of the sixth power transistor Q6, the drain of the seventh power transistor Q7, the drain of the eighth power transistor Q8, and the first terminal of the power interface. The source of the fifth power transistor Q5 is connected to the anode of the third thyristor S3 and the anode of the seventh thyristor S7. The source of the sixth power transistor Q6 is connected to the cathode of the third thyristor S3 through the third resistor R3. The source of the seventh power transistor Q7 is connected to the anode of the fourth thyristor S4 and the anode of the eighth thyristor S8. The source of the eighth power transistor Q8 is connected to the cathode of the fourth thyristor S4 through the fourth resistor R4. The control terminal of the fourth thyristor S4 is connected to the control terminal of the third thyristor S3 and the IO9 terminal of the first controller U1. The control terminal of the seventh thyristor S7 is connected to the control terminal of the eighth thyristor S8. The gates of the fifth power transistor Q5, the sixth power transistor Q6, the seventh power transistor Q7, and the eighth power transistor Q8 are respectively connected to the IO5, IO6, IO7, and IO8 terminals of the first controller U1.

[0042] In a specific embodiment, the fifth power transistor Q5, the sixth power transistor Q6, the seventh power transistor Q7, and the eighth power transistor Q8 can all be N-channel MOSFETs, which respectively perform first-step voltage regulation, second-step voltage regulation, third-step voltage regulation, and fourth-step voltage regulation control, and the electrical energy output by the first-step voltage regulation, second-step voltage regulation, third-step voltage regulation, and fourth-step voltage regulation is in square wave state; the third thyristor S3, the fourth thyristor S4, the seventh thyristor S7, and the eighth thyristor S8 can all be unidirectional thyristors; the voltage drops of the third resistor R3, the fourth resistor R4, the third thyristor S3, the seventh thyristor S7, and the eighth thyristor S8 are equal.

[0043] Furthermore, the transformer output module 4 includes a first transformer B1 and an output port;

[0044] Specifically, the first, second, third, fourth, fifth, sixth, seventh, eighth, and ninth terminals of the primary side of the first transformer B1 are respectively connected to the cathodes of the first thyristor S1, the fifth thyristor S5, the second thyristor S2, the sixth thyristor S6, the second terminal of the power interface, the cathode of the seventh thyristor S7, the cathode of the third thyristor S3, the cathode of the eighth thyristor S8, and the cathode of the fourth thyristor S4. The first and second terminals of the secondary side of the first transformer B1 are respectively connected to the first and second terminals of the output port.

[0045] In a specific embodiment, the fifth terminal of the first transformer B1 is the middle terminal, which is connected to the second terminal of the power interface, and the second terminal of the power interface is the negative terminal.

[0046] Furthermore, the fault detection module 5 includes a first inverter INV1;

[0047] Specifically, the output terminal of the first inverter INV1 is connected to the control terminal of the seventh thyristor S7 and the control terminal of the sixth thyristor S6, and the input terminal of the first inverter INV1 is connected to the IO8 terminal of the first controller U1.

[0048] In a specific embodiment, the first inverter INV1 described above can be a NOT gate.

[0049] Furthermore, the fault detection module 5 also includes a fifth resistor R5, a sixth resistor R6, a first operational amplifier OP1, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a second operational amplifier OP2, a third operational amplifier OP3, a first capacitor C1, and a tenth resistor R10.

[0050] Specifically, one end of the fifth resistor R5 is connected to the first terminal of the output port, and the other end of the fifth resistor R5 is connected to the inverting input of the first operational amplifier OP1 and connected to the second terminal of the output port through the sixth resistor R6. The non-inverting input of the first operational amplifier OP1 is connected to one end of the seventh resistor R7 and grounded through the sixth resistor R6. The output terminal of the first operational amplifier OP1 is connected to the other end of the seventh resistor R7 and connected to one end of the ninth resistor R9 and the inverting input of the second operational amplifier OP2 through the eighth resistor R8. The non-inverting inputs of the second operational amplifier OP2 and the third operational amplifier OP3 are both grounded. The other end of the ninth resistor R9 is connected to the output terminal of the third operational amplifier OP3 and connected to the inverting input of the third operational amplifier OP3 and one end of the tenth resistor R10 through the first capacitor C1. The other end of the tenth resistor R10 is connected to the output terminal of the second operational amplifier OP2.

[0051] In a specific embodiment, the first operational amplifier OP1, the second operational amplifier OP2, and the third operational amplifier OP3 can all be selected as OP07 operational amplifiers. The first operational amplifier OP1, together with the seventh resistor R7 and the sixth resistor R6, performs signal amplification processing. The second operational amplifier OP2 and the third operational amplifier OP3, together with the eighth resistor R8, the ninth resistor R9, the first capacitor C1, and the tenth resistor R10, form an inverse function type differential detection circuit to perform voltage change rate detection. When the voltage does not change, the output is zero potential.

[0052] Furthermore, the fault detection module 5 also includes an absolute value device, a first reference power supply VF1, a first comparator A1, a first logic unit J1, a second logic unit J2, a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a fifth diode D5, a sixth diode D6, a seventh diode D7, an eighth diode D8, and a self-locking device.

[0053] Specifically, the input of the absolute value device is connected to the output of the second operational amplifier OP2, the output of the absolute value device is connected to the non-inverting input of the first comparator A1, the inverting input of the first comparator A1 is connected to the first reference power supply VF1, the output of the first comparator A1 is connected to the A terminal of the first logic unit J1 and the B terminal of the second logic unit J2, the B terminal of the first logic unit J1 is connected to the cathodes of the first diode D1, the second diode D2, the third diode D3, and the eighth diode D8, and the A terminal of the second logic unit J2 is connected to the cathodes of the fourth diode D4, the seventh diode D7, the fifth diode D5, and the sixth diode D6. The anodes of diodes D1, D2, D3, D4, D5, D6, D7, and D8 are respectively connected to the IO1, IO3, IO6, IO4, IO5, IO7, IO2, and IO8 terminals of the first controller U1. The Y terminal of the first logic unit J1 is connected to the input terminal of the self-locking device, and the Y terminal of the second logic unit J2 is connected to the IO10 terminal of the first controller U1. The output terminal of the self-locking device is connected to the input terminal of the first inverter INV1 and the IO9 terminal of the first controller U1.

[0054] In a specific embodiment, the absolute value device can be composed of diodes, operational amplifiers, resistors, and capacitors to perform absolute value processing on the input positive or negative signals; the first comparator A1 can be an LM358 comparator; the first reference power supply VF1 provides a first voltage threshold, which determines the voltage change rate detection accuracy; the first logic unit J1 and the second logic unit J2 can both be AND gates; the self-locking device can be composed of transistors and resistors to perform self-locking processing on the input high-level signals.

[0055] In this embodiment of a simulated sinusoidal inverter circuit, DC power is connected through the power interface. Since the input of the first inverter INV1 is low, it triggers the conduction of the fifth thyristor S5, the sixth thyristor S6, the seventh thyristor S7, and the eighth thyristor S8. Because one cycle is 360 degrees, divided into positive and negative cycles, the positive cycle is 180 degrees and the negative cycle is 180 degrees. During the positive cycle, there are three switching elements: the first power transistor Q1, the second power transistor Q2, the third power transistor Q3, and the fourth power transistor Q4. Therefore, the IO1, IO2, IO3, and IO4 terminals of the first controller U1 control the conduction angles of the first power transistor Q1, the second power transistor Q2, the third power transistor Q3, and the fourth power transistor Q4 at 45-degree angles, respectively. The conduction states of the first power transistor Q1, the second power transistor Q2, the third power transistor Q3, and the fourth power transistor Q4 are controlled sequentially to achieve first-step voltage regulation, second-step voltage regulation, third-step voltage regulation, and fourth-step voltage regulation, outputting a square wave with a stepped increase in voltage. Then, the IO4, IO3, IO2, and IO1 terminals of the first controller U1 are respectively controlled at 45 degrees to adjust the conduction angles of the fourth power transistor Q4, the third power transistor Q3, the second power transistor Q2, and the first power transistor Q1, outputting a square wave with a stepped decrease in voltage. The dead time of the first power transistor Q1, the second power transistor Q2, the third power transistor Q3, and the fourth power transistor Q4 is constant, resulting in a four-step voltage output. Similarly, the IO8, IO7, IO6, and IO5 terminals of the first controller U1 control the conduction angles of the eighth power transistor Q8, the seventh power transistor Q7, the sixth power transistor Q6, and the fifth power transistor Q5 at 45 degrees respectively, and sequentially control the conduction of the eighth power transistor Q8, the seventh power transistor Q7, the sixth power transistor Q6, and the fifth power transistor Q5, thereby realizing the first, second, third, and fourth step voltage regulation, and outputting power in a step-increasing square wave state. Then, the fifth power transistor Q5, the sixth power transistor Q6, the seventh power transistor Q7, and the eighth power transistor Q8 are sequentially controlled at 45 degrees, outputting power in a step-decreasing square wave state. The positive cycle module 2 and the negative cycle module 3 output... The electrical energy is transformed by the first transformer B1 to obtain AC energy close to a sine wave, which is then output through the port interface. At this time, the fifth resistor R5 and the sixth resistor R6 perform voltage division sampling. After being amplified by the first operational amplifier OP1, the sixth resistor R6 and the seventh resistor R7, the voltage change rate is detected by the second and third operational amplifiers OP3, the eighth resistor R8, the ninth resistor R9, the first capacitor C1 and the tenth resistor R10. The absolute value device performs absolute value processing. When the processed voltage change rate is greater than the first voltage threshold set by the first reference power supply VF1, the first transformer B1 outputs a high level. At this time, the first controller U1 is in the state of driving the first power transistor Q1, the third power transistor Q3, the sixth power transistor Q6 or the eighth power transistor Q8.The first logic unit J1 outputs a high level. After being self-locked by the self-locking device, it outputs a first fault signal, triggering the fifth thyristor S5, the sixth thyristor S6, the seventh thyristor S7, and the eighth thyristor S8 to turn off, while the first thyristor S1, the second thyristor S2, the third thyristor S3, and the fourth thyristor S4 turn on. The IO9 terminal of the first controller U1 receives this signal. Similarly, the IO1, IO3, IO6, and IO8 terminals of the first controller U1 stop driving the first power transistor Q1, the third power transistor Q3, the sixth power transistor Q6, and the eighth power transistor Q8. Furthermore, the IO2 and IO4 terminals of the first controller U1 re-control the second power transistor Q2 and the fourth power transistor Q4 at 90-degree angles to perform stepped rise and fall operations, respectively. The IO5 and IO7 terminals of the first controller U1 also... The fifth power transistor Q5 and the seventh power transistor Q7 are controlled to operate in a stepped rise and fall pattern, and the output AC power, after being varied by the first transformer B1, is close to a sine wave. Similarly, when the first transformer B1 outputs a high level and the IO2, IO4, IO5, and IO7 terminals of the first controller U1 are driven, the second logic unit J2 outputs a high level, stopping the output signals from the IO2, IO4, IO5, and IO7 terminals. The IO1, IO3, IO6, and IO8 terminals of the first controller U1 then control the first power transistor Q1, the third power transistor Q3, the sixth power transistor Q6, and the eighth power transistor Q8 at 90-degree angles to operate in a stepped rise and fall pattern with positive and negative cycles, maintaining the output AC power close to a sine wave.

[0056] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0057] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A simulated sinusoidal inverter circuit, characterized in that, The circuit includes: The power module is used to connect to DC power. The positive cycle module, connected to the power supply module and the fault detection module, is used to perform step voltage regulation of DC power through positive cycle switching elements and output the first power in the second-order wave state or the second power in the fourth-order wave state. When the first fault signal is received from the fault detection module, the first power in the second-order wave state is output. The negative cycle module, connected to the power supply module and the fault detection module, is used to perform step voltage regulation of DC power through negative cycle switching elements and output the third power in the second-order wave state or the fourth power in the fourth-order wave state. When the first fault signal is received from the fault detection module, the third power in the second-order wave state is output. The transformer output module, connected to the positive cycle module and the negative cycle module, is used to transform and output the first electrical energy and the third electrical energy, or the second electrical energy and the fourth electrical energy. The fault detection module, connected to the transformer output module and the microcontroller module, is used to perform voltage division sampling of the electrical energy output by the transformer output module and amplify the sampled signal to output a first detection signal. The first detection signal is then subjected to voltage change rate detection, and if the voltage change rate of the first detection signal is greater than a set first voltage threshold, a second detection signal is output. When the second detection signal is output and the positive cycle module performs the first or third step voltage adjustment, or the negative cycle module performs the first or third step voltage adjustment, a first fault signal is self-locked out. When the positive cycle module performs the second or fourth step voltage adjustment, or the negative cycle module performs the second or fourth step voltage adjustment, a second fault signal is output. The microcontroller module, connected to the positive cycle module and the negative cycle module, is used to control the positive cycle module and the negative cycle module to generate the second electrical energy and the fourth electrical energy in the fourth-order wave state, respectively. When a first fault signal or a second fault signal is received, the microcontroller module adjusts the conduction angle of the switching elements of the positive cycle module and the negative cycle module and controls the positive cycle module and the negative cycle module to generate the first electrical energy and the third electrical energy in the second-order wave state, respectively. When the first fault signal and the second fault signal are received, the microcontroller module stops controlling the positive cycle module and the negative cycle module.

2. The analog sine wave inverter circuit according to claim 1, characterized in that, The power module includes a power interface; the positive cycle module includes a first power transistor, a first resistor, a second power transistor, a first thyristor, a fifth thyristor, a third power transistor, a second resistor, a fourth power transistor, a second thyristor, and a sixth thyristor; the microcontroller module includes a first controller; The first end of the power interface is connected to the drain of the first power transistor, the drain of the second power transistor, the drain of the third power transistor, and the drain of the fourth power transistor. The anode of the first power transistor is connected to the cathode of the first thyristor through a first resistor. The source of the second power transistor is connected to the anode of the first thyristor and the anode of the fifth thyristor. The source of the third power transistor is connected to the cathode of the second thyristor through a second resistor. The source of the fourth power transistor is connected to the anode of the second thyristor and the anode of the sixth thyristor. The control terminal of the fifth thyristor is connected to the control terminal of the sixth thyristor. The control terminal of the first thyristor is connected to the control terminal of the second thyristor and the IO9 terminal of the first controller. The gates of the first power transistor, the second power transistor, the third power transistor, and the fourth power transistor are respectively connected to the IO1, IO2, IO3, and IO4 terminals of the first controller.

3. The analog sine wave inverter circuit according to claim 2, characterized in that, The negative cycle module includes a fifth power transistor, a sixth power transistor, a seventh power transistor, an eighth power transistor, a third resistor, a fourth resistor, a third thyristor, a fourth thyristor, a seventh thyristor, and an eighth thyristor. The drain of the fifth power transistor is connected to the drain of the sixth, seventh, and eighth power transistors and the first terminal of the power interface. The source of the fifth power transistor is connected to the anode of the third and seventh thyristors. The source of the sixth power transistor is connected to the cathode of the third thyristor through a third resistor. The source of the seventh power transistor is connected to the anode of the fourth and eighth thyristors. The source of the eighth power transistor is connected to the cathode of the fourth thyristor through a fourth resistor. The control terminal of the fourth thyristor is connected to the control terminal of the third thyristor and the IO9 terminal of the first controller. The control terminal of the seventh thyristor is connected to the control terminal of the eighth thyristor. The gates of the fifth, sixth, seventh, and eighth power transistors are respectively connected to the IO5, IO6, IO7, and IO8 terminals of the first controller.

4. The analog sine wave inverter circuit according to claim 3, characterized in that, The transformer output module includes a first transformer and an output port; The first, second, third, fourth, fifth, sixth, seventh, eighth, and ninth terminals of the primary side of the first transformer are respectively connected to the cathodes of the first, fifth, second, and sixth thyristors, the second terminal of the power interface, the cathodes of the seventh, third, eighth, and fourth thyristors, and the first and second terminals of the secondary side of the first transformer are respectively connected to the first and second terminals of the output port.

5. The analog sine wave inverter circuit according to claim 4, characterized in that, The fault detection module includes a first inverter; The output terminal of the first inverter is connected to the control terminals of the seventh and sixth thyristors, and the input terminal of the first inverter is connected to the IO8 terminal of the first controller.

6. The analog sine wave inverter circuit according to claim 5, characterized in that, The fault detection module also includes a fifth resistor, a sixth resistor, a first operational amplifier, a seventh resistor, an eighth resistor, a ninth resistor, a second operational amplifier, a third operational amplifier, a first capacitor, and a tenth resistor; One end of the fifth resistor is connected to the first terminal of the output port, and the other end of the fifth resistor is connected to the inverting input of the first operational amplifier and then connected to the second terminal of the output port through the sixth resistor. The non-inverting input of the first operational amplifier is connected to one end of the seventh resistor and then grounded through the sixth resistor. The output terminal of the first operational amplifier is connected to the other end of the seventh resistor and then connected to one end of the ninth resistor and the inverting input of the second operational amplifier through the eighth resistor. The non-inverting inputs of the second and third operational amplifiers are both grounded. The other end of the ninth resistor is connected to the output terminal of the third operational amplifier and then connected to the inverting input of the third operational amplifier and one end of the tenth resistor through the first capacitor. The other end of the tenth resistor is connected to the output terminal of the second operational amplifier.

7. The analog sine wave inverter circuit according to claim 6, characterized in that, The fault detection module also includes an absolute value device, a first reference power supply, a first comparator, a first logic unit, a second logic unit, a first diode, a second diode, a third diode, a fourth diode, a fifth diode, a sixth diode, a seventh diode, an eighth diode, and a self-locking device; The input terminal of the absolute value device is connected to the output terminal of the second operational amplifier. The output terminal of the absolute value device is connected to the non-inverting input of the first comparator. The inverting input of the first comparator is connected to the first reference power supply. The output terminal of the first comparator is connected to the A terminal of the first logic unit and the B terminal of the second logic unit. The B terminal of the first logic unit is connected to the cathodes of the first diode, the second diode, the third diode, and the eighth diode. The A terminal of the second logic unit is connected to the cathodes of the fourth diode, the seventh diode, the fifth diode, and the sixth diode. The anodes of the first diode, the second diode, the third diode, the fourth diode, the fifth diode, the sixth diode, the seventh diode, and the eighth diode are respectively connected to the IO1, IO3, IO6, IO4, IO5, IO7, IO2, and IO8 terminals of the first controller. The Y terminal of the first logic unit is connected to the input terminal of the self-locking device. The Y terminal of the second logic unit is connected to the IO10 terminal of the first controller. The output terminal of the self-locking device is connected to the input terminal of the first inverter and the IO9 terminal of the first controller.

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