Edge acceleration circuit capable of being automatically turned off

Abstract

The invention discloses an edge acceleration circuit capable of being automatically turned off, and relates to the technical field of electronics, the edge acceleration circuit comprises a basic circuit, a rising edge acceleration circuit and a falling edge acceleration circuit, the basic circuit comprises a control logic converter and an output end OUT, the control logic converter is turned on or turned off by an enable signal, and the output end OUT is connected with the rising edge acceleration circuit. Receiving an input signal and converting the input signal into an internal signal DATAn; the rising edge acceleration circuit receives the signal DATAn and processes the signal DATAn to obtain a signal PDRI, and sends the signal PDRI to an output end OUT through an MOS tube PM1; the falling edge acceleration circuit receives the signal DATAn, processes the signal DATAn to obtain a signal NDRI, and sends the signal NDRI to an output end OUT through an MOS tube NM1; according to the scheme, the influence that the signal edge is too slow under the condition of a heavy-load capacitor can be effectively solved, and the signal transmission speed is increased.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to an edge acceleration circuit capable of self-shutdown. Background Art

[0002] With the advancement of communication technology, modern electronic systems have increasingly stringent requirements for signal transmission speed, quality, and power consumption, and their application environments are becoming more complex. To improve signal transmission speed, edge acceleration circuits can be used to reduce the rise and fall times of signals. This effectively mitigates the effects of slow signal edges under heavy load capacitance, improving signal transmission speed. However, because conventional driver circuits often enable both P-type and N-type MOS transistors simultaneously, power consumption is also high at high speeds. In applications with light load capacitance, edge acceleration circuits can be omitted to improve signal transmission quality and reduce the likelihood of electromagnetic interference. Summary of the Invention

[0003] In view of this, the present application provides an edge acceleration circuit capable of self-shutdown, so as to effectively solve the influence of slow signal edges under heavy load capacitance conditions and improve the signal transmission speed.

[0004] The present application provides an edge acceleration circuit capable of self-shutdown, the edge acceleration circuit comprising a basic circuit, a rising edge acceleration circuit, and a falling edge acceleration circuit. The basic circuit comprises a control logic converter and an output terminal OUT. The control logic converter is turned on or off by an enable signal, receives an input signal, and converts it into an internal signal DATA_n; the rising edge acceleration circuit receives the signal DATA_n and processes it to obtain a signal PDRI, and sends the signal PDRI to the output terminal OUT through the MOS transistor PM1; the falling edge acceleration circuit receives the signal DATA_n and processes it to obtain a signal NDRI, and sends the signal NDRI to the output terminal OUT through the MOS transistor NM1; when the control logic converter is in a disabled state, the MOS transistors PM1 and NM1 are always in a turned-off state, and the edge acceleration circuit remains turned off; when the control logic converter is in an enabled state, the edge acceleration circuit is turned on.

[0005] For example, in the edge acceleration circuit provided by the present disclosure, the rising edge acceleration circuit receives a signal DATA_n through a common gate terminal of MOS transistors PM2 and NM2 and a second input terminal of a NOR gate NOR1. The MOS transistor PM2 is configured such that: its source is connected to a power supply VCC; its drain is connected to a source terminal of a MOS transistor PM3; and is connected to an input terminal of a buffer BUFF1 through a resistor R1. The MOS transistor PM3 is configured such that: its gate is connected to a common terminal of an inverter INV1 and a buffer BUFF2; the output terminal of the buffer BUFF2 is connected to the input terminal of the inverter INV1; its drain is connected to the source terminal of the MOS transistor NM2 and the input terminal of the buffer BUFF1; and the drain of the MOS transistor NM2 is grounded.

[0006] For example, in the edge acceleration circuit provided by the present disclosure, the MOS transistor PM3 receives the signal FB_n and sends the signal NET1; the output end of the buffer BUFF2 sends the signal FB_n to the input end of the inverter INV1; the drain of the MOS transistor PM3 is connected to the source stage of the MOS transistor NM2 and sends the signal NET1 to the input end of the buffer BUFF1.

[0007] For example, in the edge acceleration circuit provided by the present disclosure, the output end of the buffer BUFF1 is connected to the first input end of the NOR gate NOR1; the output end of the NOR gate NOR1 is connected to the first input end of the NAND gate NAND1; the output end of the NAND gate NAND1 is connected to the gate of the MOS transistor PM1; the source of the MOS transistor PM1 is connected to the power supply VCC, and the drain is connected to the output end OUT of the edge acceleration circuit.

[0008] For example, in the edge acceleration circuit provided by the present disclosure, the output end of the buffer BUFF1 sends a signal NET2 to the first input end of the NOR gate NOR1; the output end of the NOR gate NOR1 sends a signal NET3 to the first input end of the NAND gate NAND1; the output end of the NAND gate NAND1 sends a signal PDRI to the gate of the MOS transistor PM1.

[0009] For example, in the edge acceleration circuit provided by the present disclosure, the falling edge acceleration circuit receives a signal DATA_n through a common gate terminal of MOS transistors PM4 and NM4 and a second input terminal of a NAND gate NAND2. The MOS transistor PM4 is configured such that: a source terminal is connected to a power supply VCC, and a drain terminal is connected to a source terminal of a MOS transistor NM3. The MOS transistor NM3 is configured such that: a gate terminal is connected to an output terminal of an inverter INV1, a drain terminal is connected to a source terminal of the MOS transistor NM4, and is connected to an input terminal of a buffer BUFF3 via a resistor R2. The drain terminal of the MOS transistor NM4 is grounded.

[0010] For example, in the edge acceleration circuit provided by the present disclosure, the MOS transistor NM3 receives the signal FB and sends the signal NET4; the signal FB is connected to the inverter INV1 to send the signal FB to the gate of the MOS transistor NM3; the signal NET4, the source of the MOS transistor NM3 is connected to the drain of the MOS transistor PM4 and sends the signal NET4 to the input end of the buffer BUFF3.

[0011] For example, in the edge acceleration circuit provided by the present disclosure, the output end of the buffer BUFF3 is connected to the first input end of the NAND gate NAND2; the output end of the NAND gate NAND2 is connected to the second input end of the NOR gate NOR2; the output end of the NOR gate NOR2 is connected to the gate of the MOS transistor NM1; the drain of the MOS transistor NM1 is grounded, and the source is connected to the output end OUT of the edge acceleration circuit and the drain of the MOS transistor PM1.

[0012] For example, in the edge acceleration circuit provided herein, the output of buffer BUFF3 sends signal NET5 to the first input of NAND gate NAND2. The output of NAND gate NAND2 sends signal NET6 to the second input of NOR gate NOR2. The output of NOR gate NOR2 sends signal NDRI to the gate of MOS transistor NM1.

[0013] For example, in the edge acceleration circuit provided by the present disclosure, the output end OUT of the edge acceleration circuit is connected to the input end of the Schmitt trigger SCHIT1, the output end of the Schmitt trigger SCHIT1 is connected to the input end of the buffer BUFF2, and the output end of the buffer BUFF2 is connected to the second input end of the NAND gate NAND1 and the first input end of the NOR gate NOR2. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0015] Figure 1 is a schematic diagram of an edge acceleration circuit provided by the present disclosure; Figure 2 This is a schematic diagram of a rising edge acceleration-related signal waveform provided by the present disclosure; Figure 3 This is a schematic diagram of a falling edge acceleration-related signal waveform provided by the present disclosure. DETAILED DESCRIPTION

[0016] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0017] In this application, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0018] Example like Figure 1 , Figure 1 This is a schematic diagram of an edge acceleration circuit. In this circuit, the enable signal is responsible for turning the entire module on and off. Depending on the control logic design, the enable signal can be high or low. The input signal is converted into the internal signal DATA_n after passing through the control logic. When the module is disabled, MOS transistors PM1 and NM1 are always off and have no effect on the signal edge. If further explanation is needed, please attach Figure 1 The three stages of all MOS tubes in the figure are represented by characters in the prior art, where G is the gate, S is the source, and D is the drain.

[0019] Figure 2 It is a schematic diagram of a rising edge acceleration related signal waveform; Figure 3 This is a schematic diagram of the waveform of the falling edge acceleration related signal. When the edge acceleration circuit is turned on, the circuit works as follows, and the waveform of the circuit is as follows: Figure 2 and Figure 3 As shown: The first state When the input signal is 0 and the output signal is 0, the status of the internal signals is: signal DATA_n is 1, signal NET1 is 0, signal NET2 is 0, signal NET3 is 0, signal FB_n is 1, signal PRDI is 1, signal NET4 is 0, signal NET5 is 0, signal NET6 is 1, and signal NDRI is 0.

[0020] According to the above circuit state, the MOS transistors PM1, PM3 and NM1 are in the off state, the MOS transistor NM3 is in the on state, and the entire circuit is in the non-operating state.

[0021] The second state When the input signal changes from 0 to 1, the output signal will also change from 0 to 1 due to the load capacitance and transmission delay. The changes in the internal signals are as follows: the signal DATA_n changes from 1 to 0, the signal NET1 changes from 0 to 1 after a delay, the signal NET2 changes from 0 to 1 after a delay, the signal NET3 generates a high-level pulse, the signal FB_n changes from 1 to 0 after a delay, the signal PRDI generates a low-level pulse, the signal NET4 changes from 0 to 1, the signal NET5 changes from 0 to 1, the signal NET6 remains 1, and the signal NDRI is 0.

[0022] According to the function, it is divided into two parts: rising edge acceleration part and falling edge acceleration part, and the above two parts are analyzed separately.

[0023] During the state transitions in the aforementioned circuit, signal NET1's transition from 0 to 1 is slow due to the influence of resistor R1 and the circuit's parasitic capacitance. This results in a significant propagation delay for signal NET2 to reach 1. Consequently, the input signal to NOR gate NOR1 is simultaneously at 0 for a period of time, causing NOR gate NOR1's output to form a high-level pulse. When output terminal OUT fails to rise in time due to the external heavy-load capacitor and the presence of Schmitt trigger SCHIT1, signal FB_n is at 1 for a period of time. When this FB_n 1 period overlaps with the high-level pulse output by NOR gate 1, signal PDRI generates a low-level pulse, turning on MOSFET PM1, increasing its drive capability and accelerating the rise of output terminal OUT. Until output terminal OUT completes its rise, signal FB_n remains at 1, and MOSFET PM3 remains off, causing signal NET1 to continue its slow rise. When the output terminal OUT reaches the high level of the Schmitt trigger SCHIT and the signal FB_n changes from 1 to 0, the NAND gate NAND1 outputs 1 immediately, turning off the MOS transistor PM1. The circuit then considers the rising edge of the signal to have completed the conversion. Simultaneously, when the signal FB_n reaches 0, the MOS transistor PM3 turns on, short-circuiting resistor R1. This causes the signal NET1 to quickly rise to 1, the signal NET2 to become 1, and the NOR gate NOR1 output signal NET3 to become 0, thus achieving a stable state.

[0024] During the state change of the above circuit, the input signal changes from 0 to 1, and the signal DATA_n changes from 1 to 0. Signal NET4 quickly changes from 0 to 1, and signal NET5 changes from 0 to 1. The input signal DATA_n of NAND gate NAND2 changes before signal NET5, so the output signal NET6 of NAND gate NAND2 remains at 1. This, in turn, causes the output signal NDRI of NOR gate NOR2 to remain at 0, keeping MOSFET NM1 off. Changes in signal FB_n and MOSFET NM3 do not affect the above process; they simply turn off MOSFET NM3 after the output terminal OUT completes its rise.

[0025] From the above analysis, we can see that when the MOS transistor PM1 is turned on for edge acceleration, the MOS transistor NM1 does not work, so that the MOS transistors PM1 and NM1 are not turned on at the same time, thereby achieving the effect of reducing the dynamic power consumption of the system.

[0026] The third state When the input signal is 1 and the output signal is 1, the status of the internal signals is: signal DATA_n is 0, signal NET1 is 1, signal NET2 is 1, signal NET3 is 0, signal FB_n is 0, signal PRDI is 1, signal NET4 is 1, signal NET5 is 1, signal NET6 is 1, and signal NDRI is 0.

[0027] According to the above circuit state, MOS tubes PM1, NM3 and NM1 are in the off state, PM3 is in the on state, and the entire circuit is in the non-operating state.

[0028] The fourth state When the input signal changes from 1 to 0, the output signal will also change from 1 to 0 due to the load capacitance and transmission delay. The changes in the internal signals are as follows: the signal DATA_n changes from 0 to 1, the signal NET1 changes from 1 to 0, the signal NET2 changes from 1 to 0, the signal NET3 remains 0, the signal PDRI remains 1, the signal NET4 changes from 1 to 0 after a delay, the signal NET5 changes from 1 to 0 after a delay, the signal NET6 generates a low-level pulse signal, the signal FB_n changes from 0 to 1 after a delay, and the signal NDRI generates a high-level pulse signal.

[0029] During the circuit state change described above, the input signal changes from 1 to 0, and the signal DATA_n changes from 0 to 1. Signal NET1 quickly changes from 1 to 0, and signal NET2 changes from 1 to 0. The input signal DATA_n to NOR gate NOR1 changes before signal NET2, so the output signal NET3 of NOR gate NOR1 remains 0. This, in turn, causes the output signal PDRI of NAND gate NAND1 to remain 1, keeping MOSFET PM1 off. Changes in signal FB_n and MOSFET PM3 do not affect the above process; they simply remain off after their voltages have fallen.

[0030] During the state transitions in the aforementioned circuit, signal NET4's transition from 1 to 0 is slow due to the influence of resistor R2 and the circuit's parasitic capacitance. This results in a significant propagation delay for signal NET5 to reach 0. The input signal to NAND2 is simultaneously at 1 for a period of time, causing NAND2's output to form a low-level pulse. When output OUT fails to rise in time due to the external heavy-load capacitor and the presence of Schmitt trigger SCHIT1, signal FB_n is at 0 for a period of time. When this FB_n 0 period overlaps with the low-level pulse output by NAND2, signal NDRI generates a high-level pulse, turning on MOSFET NM1, increasing its drive capability and accelerating the falling edge of OUT. Until OUT completes its falling edge, signal FB_n remains at 0, and MOSFET NM3 remains off, causing signal NET4 to continue its slow rise. When the output terminal OUT reaches the low level of Schmitt trigger SCHIT1 and the signal FB_n changes from 0 to 1, the NOR gate NOR2 immediately outputs 0, turning off MOS transistor NM1. The circuit then deems the rising edge of the signal to have completed the transition. Simultaneously, when the signal FB_n reaches 1, MOS transistor NM3 turns on, short-circuiting resistor R2. This causes signal NET4 to quickly drop to 0, signal NET5 to 0, and the NAND gate NAND2 outputs signal NET6 to 1, thus achieving a stable state.

[0031] Through the above functional description, the beneficial effects of the present disclosure can be clearly obtained. In the design of the present disclosure, due to the existence of the Schmitt trigger SCHIT1 and the global design, the circuit can self-shut down in time, thereby improving the switching speed of the circuit.

[0032] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computing software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0033] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0034] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An edge acceleration circuit capable of self-shutdown, characterized in that: The edge acceleration circuit includes a basic circuit, a rising edge acceleration circuit, and a falling edge acceleration circuit. The basic circuit includes a control logic converter and an output terminal OUT. The control logic converter is turned on or off by an enable signal, and receives an input signal and converts it into an internal signal DATA_n. The rising edge acceleration circuit receives the signal DATA_n and processes it to obtain the signal PDRI, and sends the signal PDRI to the output terminal OUT through the MOS transistor PM1; The falling edge acceleration circuit receives the signal DATA_n and processes it to obtain the signal NDRI, and sends the signal NDRI to the output terminal OUT through the MOS transistor NM1; When the control logic converter is in a disabled state, the MOS transistors PM1 and NM1 are always in an off state, and the edge acceleration circuit remains off; When the control logic converter is in an enabled state, the edge acceleration circuit is turned on.

2. The edge acceleration circuit capable of self-shutdown according to claim 1, characterized in that: The rising edge acceleration circuit receives a signal DATA_n through the common gate terminal of the MOS tube PM2, NM2 and the second input terminal of the NOR gate NOR1; The MOS transistor PM2 is configured as follows: the source is connected to the power supply VCC, the drain is connected to the source of the MOS transistor PM3, and is connected to the input end of the buffer BUFF1 through the resistor R1; The MOS transistor PM3 is configured as follows: the gate is connected to the common end of the inverter INV1 and the buffer BUFF2, the output end of the buffer BUFF2 is connected to the input end of the inverter INV1; the drain is connected to the source of the MOS transistor NM2 and the input end of the buffer BUFF1; the drain of the MOS transistor NM2 is grounded.

3. The edge acceleration circuit capable of self-shutdown according to claim 2, characterized in that: The MOS transistor PM3 receives the signal FB_n and sends the signal NET1; Signal FB_n, the output end of the buffer BUFF2 sends the signal FB_n to the input end of the inverter INV1; The drain of the MOS transistor PM3 is connected to the source of the MOS transistor NM2 and sends the signal NET1 to the input end of the buffer BUFF1.

4. The edge acceleration circuit capable of self-shutdown according to claim 2, characterized in that: The output end of the buffer BUFF1 is connected to the first input end of the NOR gate NOR1; The output end of the NOR gate NOR1 is connected to the first input end of the NAND gate NAND1; The output end of the NAND gate NAND1 is connected to the gate of the MOS transistor PM1; The source of the MOS transistor PM1 is connected to the power supply VCC, and the drain is connected to the output terminal OUT of the edge acceleration circuit.

5. The edge acceleration circuit capable of self-shutdown according to claim 4, characterized in that: The output end of the buffer BUFF1 sends a signal NET2 to the first input end of the NOR gate NOR1; The output end of the NOR gate NOR1 sends a signal NET3 to the first input end of the NAND gate NAND1; The output end of the NAND gate NAND1 sends a signal PDRI to the gate of the MOS transistor PM1.

6. The edge acceleration circuit capable of self-shutdown according to claim 1, characterized in that: The falling edge acceleration circuit receives the signal DATA_n through the common gate terminal of the MOS transistors PM4 and NM4 and the second input terminal of the NAND gate NAND2; The MOS transistor PM4 is configured as follows: the source is connected to the power supply VCC, and the drain is connected to the source of the MOS transistor NM3; The MOS transistor NM3 is configured as follows: a gate connected to the output end of the inverter INV1 , a drain connected to the source of the MOS transistor NM4 and to the input end of the buffer BUFF3 via the resistor R2 ; and a drain of the MOS transistor NM4 is grounded.

7. The edge acceleration circuit capable of self-shutdown according to claim 6, characterized in that: The MOS transistor NM3 receives a signal FB and sends a signal NET4; Signal FB, connected to inverter INV1, sends signal FB to the gate of MOS tube NM3; The source of the MOS transistor NM3 is connected to the drain of the MOS transistor PM4 and sends the signal NET4 to the input end of the buffer BUFF3.

8. The edge acceleration circuit capable of self-shutdown according to claim 6, characterized in that: The output end of the buffer BUFF3 is connected to the first input end of the NAND gate NAND2; The output terminal of the NAND gate NAND2 is connected to the second input terminal of the NOR gate NOR2; The output end of the NOR gate NOR2 is connected to the gate of the MOS transistor NM1; The drain of the MOS transistor NM1 is grounded, and the source is connected to the output terminal OUT of the edge acceleration circuit and the drain of the MOS transistor PM1.

9. The edge acceleration circuit capable of self-shutdown according to claim 8, characterized in that: The output end of the buffer BUFF3 sends a signal NET5 to the first input end of the NAND gate NAND2; The output end of the NAND gate NAND2 sends a signal NET6 to the second input end of the NOR gate NOR2; The output end of the NOR gate NOR2 sends a signal NDRI to the gate of the MOS transistor NM1.

10. The edge acceleration circuit capable of self-shutdown according to claim 4 or 8, characterized in that: The output end OUT of the edge acceleration circuit is connected to the input end of the Schmitt trigger SCHIT1, the output end of the Schmitt trigger SCHIT1 is connected to the input end of the buffer BUFF2, and the output end of the buffer BUFF2 is connected to the second input end of the NAND gate NAND1 and the first input end of the NOR gate NOR2.

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