Control structure suitable for low-power-consumption Bluetooth receiving circuit

Abstract

The invention discloses a control structure suitable for a low-power-consumption Bluetooth receiving circuit, which belongs to the technical field of Bluetooth receiving circuit design, and comprises a main processor, a system bus, a baseband processing module, an APB interface, an APB-to-SPI module, an SPI selection module, an SPI module and a physical layer module, after the BLE chip is powered on, the main processor accesses the system bus through the AHB interface, and configures the initialization module, the radio frequency calibration module, the demodulation module and the modulation module in the physical layer module through the APB interface output by the system bus and the APB-to-SPI module. According to the invention, the dual-path SPI is adopted, so that the main processor can conveniently carry out various configurations on the BLE physical layer, and the requirement of BLE fast frequency hopping can be met.

Description

Technical Field

[0001] The present invention belongs to the technical field of Bluetooth receiving circuit design, and in particular relates to a control structure suitable for a low-power Bluetooth receiving circuit. Background Art

[0002] In the complex 2.4 GHz ISM band, Bluetooth Low Energy (BLE) devices must coexist with multiple co- and adjacent-frequency devices, such as Wi-Fi and ZigBee, making them highly susceptible to external radio frequency interference. To improve link reliability, BLE devices employ frequency hopping (FHSS) technology based on spread spectrum. During communication, they rapidly switch between multiple channels in a predetermined sequence, dispersing interference across both time and frequency, thereby reducing bit error rates. Therefore, BLE chips must be capable of fast frequency hopping.

[0003] In the actual design of BLE chips, the phase-locked loop (PLL) circuit in the RF front-end requires a lock time of tens of microseconds, so the PLL frequency control word needs to be configured in advance. However, the main processor in the BLE chip is usually busy with other tasks and cannot configure the PLL in time, which cannot meet the BLE frequency hopping requirements.

[0004] The present invention relates to a control structure among a main processor, a baseband processing module and a physical layer module, and in particular to a control structure implemented in a BLE chip. Summary of the Invention

[0005] The purpose of the present invention is to provide a control structure suitable for a low-power Bluetooth receiver circuit. In different working stages of the BLE chip, the main processor and the baseband processing module respectively configure the physical layer module through their respective SPIs, which can not only meet the needs of quickly configuring the PLL frequency control word, but also facilitate other configurations of the physical layer module, and can solve the problems raised in the above background technology.

[0006] To achieve the above-mentioned object, the present invention provides the following technical solutions: a control structure suitable for a low-power Bluetooth receiving circuit, the control structure comprising a main processor, a system bus, a baseband processing module, an APB interface, an APB to SPI module, an SPI selection module, an SPI module and a physical layer module; After the BLE chip is powered on, the main processor accesses the system bus through the AHB interface, and configures the initialization module, RF calibration module, demodulation module, and modulation module in the physical layer module through the APB interface output by the system bus and the APB to SPI module. After the configuration is complete, the main processor will switch the SPI path in the SPI selection module from the APB to SPI path to the SPI interface output by the baseband processing module. At the same time, the main processor will write the PLL frequency control word corresponding to the subsequent BLE frequency hopping into the shared SRAM; When the BLE protocol stack is working, the baseband processing module reads the PLL frequency control word from the shared SRAM in advance when hopping frequencies, and configures the phase-locked loop (PLL) module in the physical layer module through the SPI interface.

[0007] Preferably, the control structure applicable to the low-power Bluetooth receiving circuit has the following specific processing flow: In the first step, after the BLE chip is powered on, the SPI selection module selects the APB to SPI path by default. At this time, the main processor initializes and configures the physical layer module through the SPI interface of the APB to SPI path; In the second step, after the physical layer module completes initialization configuration, the main processor continues to configure the RF calibration module within the physical layer module through the SPI interface. The RF calibration module then starts calibration of RF-related components. The main processor queries the status signal related to RF calibration through the SPI interface. When the calibration completion signal is read, the process proceeds to the third step. In the third step, the main processor configures the demodulation module in the physical layer module through the SPI interface. The configuration content includes but is not limited to turning on the receiving clock and turning on the ADC. After the configuration is completed, the fourth step is entered; In the fourth step, the main processor configures the modulation module in the physical layer module through the SPI interface. The configuration content includes but is not limited to configuring the modulation rate, transmit power and GFSK modulation frequency deviation. After the configuration is completed, the process proceeds to the fifth step; In the fifth step, the main processor switches the SPI path of the SPI selection module to the SPI interface output by the baseband processing module, and enters the sixth step; In the sixth step, the main processor writes the PLL frequency control word that needs to be configured when BLE frequency hopping into the shared SRAM. The main processor notifies the baseband processing module of the address pointer of the PLL frequency control word in the shared SRAM and enters the seventh step; In the seventh step, the main processor configures the baseband processor module according to the software program of the BLE protocol stack. The configuration content includes but is not limited to the BLE event type, start time, timeout time, frequency hopping interval and channel mapping table. After the configuration is completed, it proceeds to the eighth step; In the eighth step, after the baseband processing module receives the startup time parameters configured by the main processor, when the internal counter counts to the startup time, the BLE event is started. The physical layer module is responsible for the modulation and demodulation of the wireless signal, and the baseband processing module is responsible for protocol parsing or generation. When the BLE frequency hops, the baseband processing module reads the PLL frequency control word from the shared SRAM in advance and configures it to the phase-locked loop PLL module in the physical layer module through the SPI interface. Since the PLL frequency control word is configured in advance, when the BLE chip hops, the PLL is already locked, and the ninth step is entered; In the ninth step, after the baseband processing module completes the processing of this BLE event, it stores the processed data in the shared SRAM and notifies the main processor through an interrupt signal that this BLE event has ended. The main processor performs subsequent processing based on the data stored in the shared SRAM.

[0008] Preferably, in the sixth step, the main processor notifies the baseband processing module of the address pointer of the PLL frequency control word in the shared SRAM. At this time, the main processor notifies the baseband processing module that the transmission starting path of the signal is the main processor, AHB interface, system bus, AHB interface and is delivered to the baseband processing module in sequence.

[0009] Preferably, in the eighth step, the advance time for the baseband processing module to read the PLL frequency control word from the shared SRAM in advance is 40-60 microseconds.

[0010] Compared with the prior art, the present invention has the following beneficial effects: The present invention provides a control structure suitable for a low-power Bluetooth receiver circuit, which adopts a dual-channel SPI, can facilitate the main processor to perform various configurations on the BLE physical layer, and can meet the requirements of BLE fast frequency hopping. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is a structural diagram of an implementation of a control structure applicable to a low-power Bluetooth receiving circuit of the present invention.

[0012] Figure 2 This is a specific processing flow chart of a control structure applicable to a low-power Bluetooth receiving circuit of the present invention. DETAILED DESCRIPTION

[0013] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0014] like Figure 1As shown, the present invention provides a control structure suitable for a low-power Bluetooth receiver circuit. After the chip is powered on, the main processor accesses the system bus through the AHB (Advanced High Performance Bus) interface and configures the initialization, RF calibration, demodulation, and modulation modules in the physical layer module through the APB (Advanced Peripheral Bus) interface output by the system bus after passing through the APB to SPI module. After the configuration is completed, the main processor switches the SPI path of the SPI selection module from the APB to SPI path to the SPI of the baseband processing module. At the same time, the main processor writes the PLL frequency control word corresponding to the subsequent BLE frequency hopping into the shared SRAM (Static Random-Access Memory). When the BLE protocol stack is in operation, the baseband processing module reads the PLL frequency control word from the shared SRAM in advance when hopping and configures the PLL in the physical layer module through the SPI interface.

[0015] like Figure 2 As shown, the present invention is a control structure applicable to a low-power Bluetooth receiving circuit, and the specific processing flow is as follows: The first step is to power on the BLE chip. When the SPI selection module is powered on, the APB to SPI path is selected by default. At this time, the main processor initializes and configures the physical layer module through this SPI path. In the second step, after completing the initialization configuration, the main processor continues to configure the RF calibration module in the physical layer module through SPI. The RF calibration module then starts calibration of RF-related components. The main processor can query the status signal related to RF calibration through SPI. After reading the calibration completion signal, it enters the third step; In the third step, the main processor configures the demodulation module in the physical layer module through SPI, such as turning on the receiving clock and the ADC (Analog to Digital Converter). After the configuration is completed, it proceeds to the fourth step; In the fourth step, the main processor configures the modulation module in the physical layer module through SPI, such as the modulation rate, transmit power, GFSK (Gauss Frequency Shift Keying) modulation frequency deviation and other parameters. After the configuration is completed, it proceeds to the fifth step; In the fifth step, the main processor switches the SPI path of the SPI selection module to the SPI interface output by the baseband processing module, and enters the sixth step; In the sixth step, the main processor writes the PLL frequency control word that needs to be configured when BLE frequency hopping into the shared SRAM. The main processor informs the baseband processing module of the address pointer of these PLL frequency control words in the shared SRAM through AHB->system bus->AHB->baseband processing module, and then enters the seventh step; In the seventh step, the main processor configures the baseband processor module according to the software program of the BLE protocol stack, configures parameters such as BLE event type, start time, timeout time, frequency hopping interval, channel mapping table, and enters the eighth step; In the eighth step, after receiving the startup time parameters configured by the main processor, the baseband processing module waits for the internal counter to count to the startup time and starts the BLE event. The physical layer module is responsible for modulation and demodulation of the wireless signal, and the baseband processing module is responsible for protocol parsing or generation. When the BLE frequency hops, the baseband processing module reads the PLL frequency control word from the shared SRAM tens of microseconds in advance (usually 40 to 60 microseconds) and configures it to the PLL in the physical layer module through the SPI interface. Since the PLL frequency control word is configured in advance, when the BLE chip hops, the PLL is already locked, and the process proceeds to the ninth step. In the ninth step, after the baseband processing module completes the processing of this BLE event, it stores the processed data in the shared SRAM and notifies the main processor through an interrupt signal that this BLE event has ended. The main processor performs subsequent processing based on the data stored in the shared SRAM.

[0016] The present invention provides a control structure suitable for a low-power Bluetooth receiver circuit, which adopts a dual-channel SPI, can facilitate the main processor to perform various configurations on the BLE physical layer, and can meet the requirements of BLE fast frequency hopping.

[0017] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0018] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A control structure suitable for a low-power Bluetooth receiving circuit, characterized in that: The control structure includes a main processor, a system bus, a baseband processing module, an APB interface, an APB to SPI module, an SPI selection module, an SPI module and a physical layer module; After the BLE chip is powered on, the main processor accesses the system bus through the AHB interface, and configures the initialization module, RF calibration module, demodulation module, and modulation module in the physical layer module through the APB interface output by the system bus and the APB to SPI module. After the configuration is complete, the main processor will switch the SPI path in the SPI selection module from the APB to SPI path to the SPI interface output by the baseband processing module. At the same time, the main processor will write the PLL frequency control word corresponding to the subsequent BLE frequency hopping into the shared SRAM; When the BLE protocol stack is working, the baseband processing module reads the PLL frequency control word from the shared SRAM in advance when hopping frequencies, and configures the phase-locked loop (PLL) module in the physical layer module through the SPI interface.

2. A control structure suitable for a low-power Bluetooth receiving circuit according to claim 1, characterized in that: This control structure is suitable for low-power Bluetooth receiving circuits. The specific processing flow is as follows: In the first step, after the BLE chip is powered on, the SPI selection module selects the APB to SPI path by default. At this time, the main processor initializes and configures the physical layer module through the SPI interface of the APB to SPI path; In the second step, after the physical layer module completes initialization configuration, the main processor continues to configure the RF calibration module within the physical layer module through the SPI interface. The RF calibration module then starts calibration of RF-related components. The main processor queries the status signal related to RF calibration through the SPI interface. When the calibration completion signal is read, the process proceeds to the third step. In the third step, the main processor configures the demodulation module in the physical layer module through the SPI interface. The configuration content includes but is not limited to turning on the receiving clock and turning on the ADC. After the configuration is completed, the fourth step is entered; In the fourth step, the main processor configures the modulation module in the physical layer module through the SPI interface. The configuration content includes but is not limited to configuring the modulation rate, transmit power and GFSK modulation frequency deviation. After the configuration is completed, the process proceeds to the fifth step; In the fifth step, the main processor switches the SPI path of the SPI selection module to the SPI interface output by the baseband processing module, and enters the sixth step; In the sixth step, the main processor writes the PLL frequency control word that needs to be configured when BLE frequency hopping into the shared SRAM. The main processor notifies the baseband processing module of the address pointer of the PLL frequency control word in the shared SRAM and enters the seventh step; In the seventh step, the main processor configures the baseband processor module according to the software program of the BLE protocol stack. The configuration content includes but is not limited to the BLE event type, start time, timeout time, frequency hopping interval and channel mapping table. After the configuration is completed, it proceeds to the eighth step; In the eighth step, after the baseband processing module receives the startup time parameters configured by the main processor, when the internal counter counts to the startup time, the BLE event is started. The physical layer module is responsible for the modulation and demodulation of the wireless signal, and the baseband processing module is responsible for protocol parsing or generation. When the BLE frequency hops, the baseband processing module reads the PLL frequency control word from the shared SRAM in advance and configures it to the phase-locked loop PLL module in the physical layer module through the SPI interface. Since the PLL frequency control word is configured in advance, when the BLE chip hops, the PLL is already locked, and the ninth step is entered; In the ninth step, after the baseband processing module completes the processing of this BLE event, it stores the processed data in the shared SRAM and notifies the main processor through an interrupt signal that this BLE event has ended. The main processor performs subsequent processing based on the data stored in the shared SRAM.

3. The control structure for a low-power Bluetooth receiving circuit according to claim 2, characterized in that: In the sixth step, the main processor notifies the baseband processing module of the address pointer of the PLL frequency control word in the shared SRAM. At this time, the main processor notifies the baseband processing module that the transmission starting path of the signal is the main processor, AHB interface, system bus, AHB interface and is delivered to the baseband processing module.

4. The control structure for a low-power Bluetooth receiving circuit according to claim 2, characterized in that: In the eighth step, the baseband processing module reads the PLL frequency control word from the shared SRAM in advance by 40-60 microseconds.

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