Memory structure

Abstract

The invention provides a memory structure. The memory structure includes a magnetic tunnel junction and a metal line electrically connected in series or in parallel, and when the memory structure is in a write state, the magnetic tunnel junction has a breakdown voltage, the metal line has a fusing voltage, and voltage values of the breakdown voltage and the fusing voltage are different. Through the method and the device, the problem that a nonvolatile memory based on an OTP working principle in the prior art does not have a multi-time programmable capability is solved.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a memory structure. Background Art

[0002] OTP (One-Time Programmable) memory is programmable (OTP) memory that can only be written once, with data permanently valid. OTP memory is commonly used within chips to store stable data that needs to be read repeatedly, such as boot programs, encryption keys, product serial numbers, and configuration parameters. OTP memory is typically implemented in two ways: fuse-type (eFuse) and antifuse-type. Fuse-type devices use a high-density current flowing through a narrow metal or polysilicon layer to cause electromigration fusing, resulting in a low-resistance state before programming and a high-resistance state after programming. Antifuse devices use a dielectric (oxide) breakdown mechanism, resulting in a high-resistance state before programming and a low-resistance state after programming. Compared to fuse-type devices, antifuse devices offer higher security and lower power consumption. However, OTP memory also has inherent drawbacks. For example, incorrectly programmed OTP memory cannot be reprogrammed and must be discarded, increasing the cost of programming waste. Furthermore, design changes, updates, and revisions are common during engineering, and if the memory can be reprogrammed multiple times, costs can be significantly reduced. Therefore, a non-volatile memory based on the OTP working principle but with multi-time programmable capability is needed. Summary of the Invention

[0003] The main purpose of the present invention is to provide a memory structure to solve the problem in the prior art that non-volatile memories based on the OTP working principle do not have multi-time programmability.

[0004] In order to achieve the above-mentioned purpose, according to one aspect of the present invention, a memory structure is provided, which includes: an electrically connected magnetic tunnel junction and a metal line, the electrical connection being a series connection or a parallel connection, and when the memory structure is in a write state, the magnetic tunnel junction has a breakdown voltage, the metal line has a fuse voltage, and the breakdown voltage and the fuse voltage have different voltage values.

[0005] Optionally, when the electrical connection is a series connection, the breakdown voltage is lower than the fusing voltage.

[0006] Optionally, when the electrical connection is a parallel connection, the breakdown voltage is higher than the fusing voltage.

[0007] Optionally, the memory structure includes at least one first storage unit, each first storage unit includes a first write module and a second write module connected in parallel, the first write module is a first metal wire, the second write module is a second metal wire and a first magnetic tunnel junction connected in series, the magnetic tunnel junction includes a first magnetic tunnel junction, and the metal wire includes a first metal wire and a second metal wire.

[0008] Optionally, the memory structure includes at least one second storage unit, each second storage unit includes a third write module and a fourth write module connected in parallel, the third write module is a second magnetic tunnel junction and a third metal wire connected in series, the fourth write module is a third magnetic tunnel junction and a fourth metal wire connected in series, the magnetic tunnel junction includes a second magnetic tunnel junction and a third magnetic tunnel junction, and the metal wire includes a third metal wire and a fourth metal wire.

[0009] Optionally, when the second storage unit includes a plurality of units, any two of the plurality of second storage units are connected in parallel.

[0010] Optionally, the second magnetic tunnel junction in each third write module is stacked with the third metal wire, and the third magnetic tunnel junction in each fourth write module is stacked with the fourth metal wire. The memory structure includes a first conductive layer and a second conductive layer. Any two second magnetic tunnel junctions and third magnetic tunnel junctions in a plurality of second storage cells are located side by side between the first conductive layer and the second conductive layer along the first direction, and the second magnetic tunnel junction and the third magnetic tunnel junction in each second storage cell are respectively in contact with the first conductive layer, and the third metal wire and the fourth metal wire in each second storage cell are respectively in contact with the second conductive layer.

[0011] Optionally, the second magnetic tunnel junction in each third write module is stacked with the third metal wire, and the third magnetic tunnel junction in each fourth write module is stacked with the fourth metal wire. The memory structure includes a third conductive layer and a fourth conductive layer. Any two second magnetic tunnel junctions in a plurality of second storage cells are located side by side between the third conductive layer and the fourth conductive layer along the second direction, and the second magnetic tunnel junction and the third magnetic tunnel junction in each second storage cell are in contact with the third conductive layer, respectively, and the third metal wire and the fourth metal wire in each second storage cell are in contact with the fourth conductive layer, respectively.

[0012] Optionally, the second magnetic tunnel junction in each third write module is stacked with the third metal wire, and the third magnetic tunnel junction in each fourth write module is stacked with the fourth metal wire. The memory structure includes a fifth conductive layer and a sixth conductive layer. The multiple second storage units include at least two, any two second magnetic tunnel junctions and the third magnetic tunnel junctions in one of the at least two second storage units are located side by side between the fifth conductive layer and the sixth conductive layer along a third direction, and any two second magnetic tunnel junctions and the third magnetic tunnel junctions in another of the at least two second storage units are located side by side between the fifth conductive layer and the sixth conductive layer along a fourth direction, the third direction and the fourth direction intersect, and the second magnetic tunnel junction and the third magnetic tunnel junction in each second storage unit are respectively in contact with the fifth conductive layer, and the third metal wire and the fourth metal wire in each second storage unit are respectively in contact with the sixth conductive layer.

[0013] Optionally, in the case where the plurality of second storage cells includes four, except for one of the second storage cells among at least two and another of the at least two second storage cells, any two second magnetic tunnel junctions and the third magnetic tunnel junction in the third second storage cell among the four second storage cells are located side by side along the fifth direction between the fifth conductive layer and the sixth conductive layer, and any two second magnetic tunnel junctions and the third magnetic tunnel junction in the fourth second storage cell among the four second storage cells are located side by side along the sixth direction between the fifth conductive layer and the sixth conductive layer, and the third direction, the fourth direction, the fifth direction and the sixth direction are in the shape of a "M".

[0014] The technical solution of the present invention is applied to provide a memory structure in which, when the memory structure is in a write state, the breakdown of the magnetic tunnel junction and the fusing of the metal line can each serve as one-time programming of the memory structure. Therefore, in order to enable the same memory structure to have a multi-time programmable function, the same memory structure can simultaneously include the above-mentioned magnetic tunnel junction and metal line, and the magnetic tunnel junction can be set to have a breakdown voltage, and the metal line can be set to have a fusing voltage, with the breakdown voltage and the fusing voltage being different values ​​of the fusing voltage. Thus, in the same memory structure, the breakdown of the magnetic tunnel junction and the fusing of the metal line do not occur simultaneously, allowing the same memory structure to be programmed twice. Therefore, through this application, the problem that non-volatile memories based on the OTP operating principle in the prior art do not have multi-time programmable capabilities is solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings, which constitute part of the present invention, are intended to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are intended to explain the present invention and do not constitute an undue limitation of the present invention. In the accompanying drawings:

[0016] Figure 1A schematic diagram showing a bit cell circuit including a memory structure according to an embodiment of the present invention is shown;

[0017] Figure 2 A schematic diagram showing a bit cell circuit including another memory structure according to an embodiment of the present invention is shown;

[0018] Figure 3 A schematic diagram of a bit cell circuit including yet another memory structure according to an embodiment of the present invention is shown;

[0019] Figure 4 A schematic diagram of a bit cell circuit including another memory structure according to an embodiment of the present invention is shown;

[0020] Figure 5 A schematic diagram of a bit cell circuit including another memory structure according to an embodiment of the present invention is shown;

[0021] Figure 6 A schematic diagram of a bit cell circuit including another memory structure according to an embodiment of the present invention is shown;

[0022] Figure 7 A schematic diagram of a bit cell circuit including another memory structure according to an embodiment of the present invention is shown;

[0023] Figure 8 A schematic diagram of a bit cell circuit including another memory structure according to an embodiment of the present invention is shown;

[0024] Figure 9 A schematic diagram of a bit cell circuit including another memory structure according to an embodiment of the present invention is shown;

[0025] Figure 10 Shown Figure 9 A top view of a memory structure is shown;

[0026] Figure 11 A top view of another memory structure according to an embodiment of the present invention is shown;

[0027] Figure 12 A top view of another memory structure according to an embodiment of the present invention is shown;

[0028] Figure 13 A top view of another memory structure according to an embodiment of the present invention is shown.

[0029] The above drawings include the following reference numerals:

[0030] 101. Metal contact hole; 102. First storage unit; 1021. First write module; 1022. Second write module; 103. Second storage unit; 104. Third write module; 105. Fourth write module; 10. First conductive layer; 20. Second conductive layer; 30. Fourth conductive layer. DETAILED DESCRIPTION

[0031] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments of the present invention can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0032] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0033] It should be noted that the terms "first," "second," and the like in the specification and claims of the present invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate for the embodiments of the present invention described herein. In addition, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatuses.

[0034] As described in the background art, conventional OTP memories comprised of a single fuse or antifuse cannot be reprogrammed or errors in routing programming corrected. Error-programmed OTP memories must be discarded, resulting in excessively high manufacturing costs. To address the aforementioned technical issues, the present invention proposes that if OTP memories with programming errors can be reprogrammed, the cost of programming waste can be reduced. Furthermore, design changes, updates, or revisions often occur in engineering projects. If memories can be programmed multiple times and reused, costs can be significantly reduced. Therefore, the present invention provides a memory structure.

[0035] In some optional embodiments, the memory structure includes: an electrically connected magnetic tunnel junction and a metal line, the electrical connection is a series connection or a parallel connection, and when the memory structure is in a write state, the magnetic tunnel junction has a breakdown voltage, the metal line has a fuse voltage, and the breakdown voltage and the fuse voltage have different voltage values.

[0036] In the above embodiment, when the memory structure is in a write state, the breakdown of the magnetic tunnel junction and the fusing of the metal line can each serve as one-time programming of the memory structure. Therefore, to enable the same memory structure to have multi-time programmability, the same memory structure can include both the magnetic tunnel junction and the metal line, and the magnetic tunnel junction can be configured to have a breakdown voltage and the metal line to have a fusing voltage, with the breakdown voltage and the fusing voltage being different values. This prevents the breakdown of the magnetic tunnel junction and the fusing of the metal line from occurring simultaneously within the same memory structure, allowing the same memory structure to be programmed twice.

[0037] In some optional embodiments, the magnetic tunnel junction MTJ (represented by a capacitor symbol) and the metal line M (represented by a resistor symbol) in the same memory structure are connected in series, and the breakdown voltage of the magnetic tunnel junction MTJ can be lower than the melting voltage of the metal line M.

[0038] In other optional embodiments, such as Figure 1 As shown, the memory structure in the above embodiment (the metal wire M is connected in series with the magnetic tunnel junction MTJ) may further include a transistor, which may be located on the side of the metal wire M away from the magnetic tunnel junction MTJ and connected in series with the metal wire M. At this time, the breakdown voltage of the magnetic tunnel junction MTJ may be higher than the melting voltage of the metal wire M. Moreover, in the case where the above memory structure is located in a bit cell circuit, the magnetic tunnel junction MTJ in the memory structure may be connected to the bit line BL, one end of the metal wire M in the memory structure may be connected in series with the magnetic tunnel junction MTJ, the other end of the metal wire M in the memory structure may be connected in series with the drain end of the above transistor, the source end of the transistor may be connected to the source line SL, and the gate of the transistor may be connected to the word line WL. Figure 1 On the basis of further Figure 2 As shown, a metal contact hole 101 may be included between the metal line M and the transistor, so that the magnetic tunnel junction MTJ, the metal line M, the metal contact hole 101 and the transistor are sequentially connected in series. The metal contact hole 101 is used to electrically connect different conductive layers.

[0039] Alternatively, when the memory structure includes the above-mentioned transistor, the above-mentioned transistor can be located on the side of the magnetic tunnel junction MTJ away from the metal line M and connected in series with the magnetic tunnel junction MTJ. And when the memory structure is located in a bit cell circuit, one end of the metal line M in the memory structure can be connected to the bit line BL in the bit cell circuit, and the other end of the metal line M in the memory structure can be connected in series with the magnetic tunnel junction MTJ in the memory structure. The magnetic tunnel junction MTJ is also connected to the drain of the transistor in the memory structure, the source of the transistor is connected to the source line SL in the bit cell circuit, and the gate of the transistor is connected to the word line WL in the bit cell circuit. Furthermore, a metal contact hole 101 is provided between the above-mentioned metal line M and the bit line BL, so that the metal contact hole 101, the metal line M, the magnetic tunnel junction MTJ and the transistor are connected in series in sequence.

[0040] In summary, if the memory structure does not include transistors, the breakdown voltage of the magnetic tunnel junction must be lower than the melting voltage of the metal wire. However, if the memory structure includes transistors, the breakdown voltage of the magnetic tunnel junction can be higher than the melting voltage of the metal wire. The reason is as follows: the breakdown of the MTJ is high voltage and low current, while the melting of the metal wire is low voltage and high current. Therefore, even if the melting voltage of the metal wire is lower than the breakdown voltage of the magnetic tunnel junction MTJ, when the magnetic tunnel junction breaks down, the memory structure (OTP) becomes a low-resistance state. Due to the voltage division and current limiting effect of the transistor, the voltage division of the memory structure (OTP) will quickly decrease and fall below the melting voltage of the metal wire, so that the metal wire will not be melted. Therefore, when performing the second programming, the gate voltage of the transistor can be increased to make the voltage division of the memory structure (OTP) reach the melting voltage of the metal wire to achieve writing.

[0041] In some optional embodiments, the magnetic tunnel junction MTJ (represented by a capacitor symbol) and the metal line M (represented by a resistor symbol) in the same memory structure are connected in parallel. At this time, the breakdown voltage of the above-mentioned magnetic tunnel structure MTJ is higher than the fuse voltage of the above-mentioned metal line M.

[0042] Similarly, in other optional implementations, such as Figure 3As shown, the memory structure in the above embodiment (the magnetic tunnel junction MTJ and the metal line M are connected in parallel) may further include a transistor, which may be connected in series with the metal line M and the magnetic tunnel junction MTJ connected in parallel. In this case, the breakdown voltage of the magnetic tunnel structure MTJ is still higher than the melting voltage of the metal line M. The reason is as follows: when the magnetic tunnel junction MTJ is connected in parallel with the metal line M, the melting voltage of the metal line M must be lower than the breakdown voltage of the magnetic tunnel junction MTJ; otherwise, the magnetic tunnel junction MTJ will breakdown at the same time as the metal line M melts.

[0043] Furthermore, when the above-mentioned memory structure is located in a bit cell circuit, one end of the metal line M and the magnetic tunnel junction MTJ connected in parallel in the memory structure can be connected to the bit line BL in the bit cell circuit, and the other end of the metal line M and the magnetic tunnel junction MTJ connected in parallel in the memory structure can be connected in series to the drain end of the above-mentioned transistor, the source end of the transistor is connected to the source line SL in the bit cell circuit, and the gate of the transistor is connected to the word line WL in the bit cell circuit. Figure 3 On the basis of further Figure 4 As shown, the metal line M and the magnetic tunnel junction MTJ are connected in parallel through a metal contact hole 101 .

[0044] It should be noted that when the above-mentioned magnetic tunnel junction MTJ and metal wire M are simultaneously present in the same memory structure, since the breakdown of the magnetic tunnel junction MTJ is based on the breakdown of the insulating dielectric layer in the magnetic tunnel junction MTJ, when the breakdown of the magnetic tunnel junction MTJ is used as a one-time programming of the memory structure, the magnetic tunnel junction MTJ before programming presents a high-resistance state, and the magnetic tunnel junction MTJ after programming presents a low-resistance state; and the metal wire M is blown based on the high-density current passing through the narrow metal or polysilicon to cause electromigration blowing, so that when the metal wire M is blown as a one-time programming of the memory structure, the metal wire M before programming presents a low-resistance state, and the metal wire M after programming presents a high-resistance state.

[0045] Therefore, if the moment when the magnetic tunnel junction MTJ in the same memory structure is desired to be broken down occurs before the moment when the metal wire M is blown, and the memory structure can be programmed a second time by breaking down the metal wire M after the magnetic tunnel junction MTJ is broken down, then the electrical connection relationship between the magnetic tunnel junction MTJ and the metal wire M can be set to a series connection; similarly, if the moment when the metal wire M in the same memory structure is desired to be blown occurs before the moment when the magnetic tunnel junction MTJ is broken down, and the memory structure can be programmed a second time by breaking down the magnetic tunnel junction MTJ after the metal wire M is blown, then the electrical connection relationship between the magnetic tunnel junction MTJ and the metal wire M can be set to a parallel connection.

[0046] It can be seen from the above content that when the magnetic tunnel junction MTJ and the metal wire M are connected in series, the magnetic tunnel junction MTJ can be broken down first, and when the magnetic tunnel junction MTJ and the metal wire M are connected in parallel, the metal wire M can be blown first. Therefore, in order to enable the memory structure to be programmed at least three times, in some optional embodiments, the above-mentioned memory structure may include at least one first storage unit, each of the above-mentioned first storage unit includes a first write module and a second write module connected in parallel, the above-mentioned first write module is a first metal wire, the above-mentioned second write module is a second metal wire and a first magnetic tunnel junction connected in series, the above-mentioned magnetic tunnel junction MTJ includes the above-mentioned first magnetic tunnel junction, and the above-mentioned metal wire includes the above-mentioned first metal wire and the above-mentioned second metal wire.

[0047] That is, in the above embodiment, Figure 5 As shown, the first metal wire M1 (represented by a resistor symbol) is first recorded as the first write module 1021, and the structure after the first magnetic tunnel junction MTJ (represented by a capacitor symbol) and the second metal wire M2 (represented by a resistor symbol) are connected in series is recorded as the second write module 1022. Then, by connecting the first write module 1021 and the second write module 1022 in parallel, three-way programming of the memory structure is achieved. And the three-way programming order of the memory structure can be: the first programming is achieved by first fusing the first metal wire M1 connected in parallel, then the second programming is achieved by breaking down the first magnetic tunnel junction MTJ in the second write module 1022, and finally the third programming is achieved by fusing the second metal wire M2 in the second write module 1022.

[0048] Among them, Figure 5As shown, the above memory structure may further include a transistor, and the transistor is connected in series with the first memory cell 102. Furthermore, when the memory structure is located in a bit cell circuit, one end of the first memory cell 102 is connected to the bit line BL in the bit cell circuit, the other end of the first memory cell 102 is connected to the drain end of the transistor, the source end of the transistor is connected to the source line SL in the bit cell circuit, and the gate of the transistor is connected to the word line WL in the bit cell circuit. Figure 5 On the basis of further Figure 6 As shown, the first magnetic tunnel junction MTJ and the second metal line M2 (ie Figure 5 The second writing module 1022 is shown to be connected in parallel with the first metal line M1 through the metal contact hole 101.

[0049] It should be noted that in some optional embodiments, if the memory structure does not include a transistor, when the magnetic tunnel junction MTJ and the metal line M are connected in parallel, the breakdown voltage of the magnetic tunnel junction MTJ is higher than the melting voltage of the metal line M; when the magnetic tunnel junction MTJ and the metal line M are connected in series, the breakdown voltage of the magnetic tunnel junction MTJ is lower than the melting voltage of the metal line M. Therefore, when the memory structure is in a write state, the melting voltage of the first metal line M1 connected in parallel is the lowest, the breakdown voltage of the first magnetic tunnel junction MTJ connected in parallel is greater than the melting voltage of the first metal line M1 connected in parallel, and the melting voltage of the second metal line M2 connected in series is greater than the breakdown voltage of the first magnetic tunnel junction MTJ connected in series.

[0050] In some other optional embodiments, if the memory structure includes transistors, when the magnetic tunnel junction MTJ and the metal line M are connected in parallel, the breakdown voltage of the magnetic tunnel junction MTJ is higher than the melting voltage of the metal line M; when the magnetic tunnel junction MTJ and the metal line M are connected in series, the breakdown voltage of the magnetic tunnel junction MTJ can be higher than the melting voltage of the metal line M. For example, Figure 5 As shown, when the memory structure is in the write state, the first metal line M1 in the first write module 1021 can have the lowest fuse voltage, and the breakdown voltage of the first magnetic tunnel junction MTJ in the second write module 1022 can be greater than the fuse voltage of the second metal line M2 in the second write module 1022. The reason is the same as above and will not be repeated here.

[0051] Specifically, the breakdown voltage of the magnetic tunnel junction MTJ can be adjusted by the thickness and material of the insulating dielectric layer in the magnetic tunnel junction MTJ, and the fusing voltage of the metal line M can be adjusted by the material, thickness and width of the metal line M.

[0052] In order to enable the memory structure to be programmed at least four times, in some optional implementations, such as Figure 7 As shown, the memory structure includes at least one second storage unit 103, each of the second storage unit 103 includes a third write module 104 and a fourth write module 105 connected in parallel, the third write module 104 is a second magnetic tunnel junction MTJ1 and a third metal wire M1 connected in series, the fourth write module 105 is a third magnetic tunnel junction MTJ2 and a fourth metal wire M2 connected in series, the magnetic tunnel junction MTJ includes a second magnetic tunnel junction MTJ1 and a third magnetic tunnel junction MTJ2, and the metal wire M includes a third metal wire M1 and a fourth metal wire M2.

[0053] That is, in the above embodiment, Figure 7 As shown, the structure in which the second magnetic tunnel junction MTJ1 (represented by a capacitor symbol) and the third metal wire M1 (represented by a resistor symbol) are connected in series is denoted as the third write module 104; and the structure in which the third magnetic tunnel junction MTJ2 (represented by a capacitor symbol) and the fourth metal wire M2 (represented by a resistor symbol) are connected in series is denoted as the fourth write module 105. By connecting the third write module 104 and the fourth write module 105 in parallel, four-way programming of the memory structure is achieved.

[0054] Specifically, the four programming sequences of the memory structure may include any one of the following two situations:

[0055] The first case may be: the first programming is firstly achieved by the breakdown of the second magnetic tunnel junction MTJ1 of the third write module 104, then the second programming is achieved by the third metal line M1 of the third write module 104 being blown, then the third programming is achieved by the breakdown of the third magnetic tunnel junction MTJ2 of the fourth write module 105, and finally the fourth programming is achieved by the blown fourth metal line M2 of the fourth write module 105;

[0056] For example, in some optional embodiments, the memory structure does not include a transistor. In this case, when the memory structure is located in a bit cell circuit, one end of the second memory cell 103 is connected to the bit line BL of the bit cell circuit, and the other end of the second memory cell 103 is connected to the source line SL in the bit cell circuit (or through a metal contact hole).

[0057] On this basis, the breakdown voltage of the second magnetic tunnel junction MTJ1 of the third write module 104 is lower than the breakdown voltage of the third magnetic tunnel junction MTJ2 of the fourth write module 105, the fuse voltage of the third metal wire M1 of the third write module 104 is higher than the breakdown voltage of the second magnetic tunnel junction MTJ1 in the third write module 104, the fuse voltage of the third metal wire M1 of the third write module 104 is lower than the breakdown voltage of the third magnetic tunnel junction MTJ2 of the fourth write module 105, and the fuse voltage of the fourth metal wire M2 of the fourth write module 105 is lower than the breakdown voltage of the second magnetic tunnel junction MTJ1 of the third write module 104.

[0058] It can be understood that if the second magnetic tunnel junction MTJ1 in the third write module 104 in the memory structure is broken down first, the first programming of the memory structure is realized, and at the same time, the third magnetic tunnel junction MTJ2 in the fourth write module 105 is equivalent to being short-circuited instantly. At this time, the voltage across the third magnetic tunnel junction MTJ2 in the fourth write module drops sharply, and the divided voltage does not reach the breakdown voltage of the third magnetic tunnel junction MTJ2. Then, by applying current to the memory structure, the third metal wire M1 in the third write module 104 can be blown, realizing the second programming of the memory structure. Thereafter, applying voltage to the memory structure again can cause the third magnetic tunnel junction MTJ2 in the fourth write module 105 to be broken down, realizing the third programming of the memory structure. Finally, by applying current to the memory structure, the fourth metal wire M2 in the fourth write module 105 can be blown, realizing the fourth programming of the memory structure.

[0059] For example, in some other optional implementations, the memory structure further includes transistors, such as Figure 7 At this time, in the case of the memory structure bit cell circuit, one end of the second storage unit 103 is connected to the bit line BL of the bit cell circuit, the other end of the second storage unit 103 (or through a metal contact hole) is electrically connected to the drain end of the transistor, the source end of the transistor is connected to the source line SL in the bit cell circuit, and the gate of the transistor is connected to the word line WL in the bit cell circuit. Figure 7 On the basis of further Figure 8 As shown, the third write module 104 and the fourth write module 105 are connected in parallel through the metal contact hole 101 and the metal line M (the third metal line M1 and the fourth metal line M2 are electrically connected).

[0060] exist Figure 7Based on the structure shown, the fusing voltage of the third metal wire M1 of the third write module 104 can be lower than the breakdown voltage of the third magnetic tunnel junction MTJ2 of the fourth write module 105; and the fusing voltage of the fourth metal wire M2 of the fourth write module 105 can be lower than the breakdown voltage of the second magnetic tunnel junction MTJ1 of the third write module 104. The reason is as follows: after the magnetic tunnel junction in any write module in the same memory structure breaks down, the resistance of the write module including the magnetic tunnel junction drops rapidly, and the resistance value of the transistor is much greater than the resistance value of the write module including the magnetic tunnel junction. The voltage divider of the write module including the magnetic tunnel junction in the memory structure will drop sharply and cannot reach the fusing voltage of the metal wire in the write module including the magnetic tunnel junction. Therefore, the fusing voltage of the fourth metal wire M2 of the fourth write module 105 can be lower than the breakdown voltage of the second magnetic tunnel junction MTJ1 of the third write module 104. At this time, if a second programming is to be performed, the gate voltage of the transistor can be increased to increase the current of the write module including the broken-down magnetic tunnel junction, thereby causing the voltage division of the write module to reach the fusing voltage of the metal line.

[0061] The second situation may be: the first programming is achieved by the third magnetic tunnel junction MTJ2 of the fourth write module 105 being broken down first, then the second programming is achieved by the fourth metal wire M2 of the fourth write module 105 being blown, and then the third programming is achieved by the second magnetic tunnel junction MTJ1 of the third write module 104 being broken down, and finally the fourth programming is achieved by the third metal wire M1 of the third write module 104 being blown.

[0062] For example, in some optional embodiments, the memory structure does not include a transistor. In this case, the breakdown voltage of the third magnetic tunnel junction MTJ2 of the fourth write module 105 is lower than the breakdown voltage of the second magnetic tunnel junction MTJ1 of the third write module 104, the fusing voltage of the fourth metal wire M2 of the fourth write module 105 is lower than the breakdown voltage of the second magnetic tunnel junction MTJ1 of the third write module 104, and the fusing voltage of the third metal wire M1 of the third write module 104 is lower than the breakdown voltage of the third magnetic tunnel junction MTJ2 of the fourth write module 105.

[0063] For example, in some other optional embodiments, the memory structure includes transistors. In this case, the fusing voltage of the fourth metal wire M2 of the fourth write module 105 can be lower than the breakdown voltage of the second magnetic tunnel junction MTJ1 of the third write module 104, and the fusing voltage of the third metal wire M1 of the third write module 104 can be lower than the breakdown voltage of the third magnetic tunnel junction MTJ2 of the fourth write module 105. The reasons are the same as above and will not be repeated here.

[0064] exist Figure 7On the basis of further Figure 8 As shown, the third write module 104 and the fourth write module 105 are connected in parallel through the metal contact hole 101 and the metal line M (the third metal line M1 and the fourth metal line M2 are electrically connected).

[0065] Since the breakdown voltage of the magnetic tunnel junction MTJ can be adjusted by the thickness and material of the insulating dielectric layer of the magnetic tunnel junction MTJ, that is, the breakdown voltages of the second magnetic tunnel junction MTJ1 and the third magnetic tunnel junction MTJ2 in any two second storage cells can be adjusted in the above manner, so that the breakdown voltages of the second magnetic tunnel junction MTJ1 in any two second storage cells can be different, and / or the breakdown voltages of the third magnetic tunnel junction MTJ2 in any two second storage cells can be different. Therefore, in some optional embodiments, when the second storage cell includes a plurality of cells, any two of the plurality of second storage cells are connected in parallel.

[0066] It should be noted that, when the memory structure does not include transistors, the maximum value of the fuse voltage of the metal line M in all modules of all second storage cells is greater than the minimum value of the breakdown voltage of the magnetic tunnel junction MTJ in all modules of all second storage cells; when the memory structure includes transistors, the maximum value of the fuse voltage of the metal line M in all modules of all second storage cells may be less than the minimum value of the breakdown voltage of the magnetic tunnel junction MTJ in all modules of all second storage cells.

[0067] In order to connect the plurality of second storage units in parallel in pairs in the memory structure, save the area of ​​the memory structure, and increase the storage capacity, in some optional implementations, such as Figure 8 As shown, the second magnetic tunnel junction MTJ1 in each of the third write modules 104 is stacked with the third metal wire M1, and the third magnetic tunnel junction MTJ2 in each of the fourth write modules 105 is stacked with the fourth metal wire M2.

[0068] exist Figure 8 On the basis of Figure 9As shown, the memory structure includes a first conductive layer 10 and a second conductive layer 20, any two of the second magnetic tunnel junctions MTJN (MTJ1, ..., MTJN, N is greater than or equal to 1) and the third magnetic tunnel junction MTJ2N (MTJ2, ..., MTJ2N, N is greater than or equal to 1) in the plurality of second storage cells 103 are arranged side by side along a first direction A between the first conductive layer 10 and the second conductive layer 20, and the second magnetic tunnel junction MTJN (MTJ1) in each of the second storage cells is arranged side by side. , ..., MTJN, N is greater than or equal to 1) and the third magnetic tunnel junction MTJ2N (MTJ2, ..., MTJ2N, N is greater than or equal to 1) are respectively in contact with the first conductive layer 10, and the third metal wire MN (M1, ..., MN, N is greater than or equal to 1) and the fourth metal wire MN (M2, ..., M2N, N is greater than or equal to 1) in each of the second storage cells 103 are respectively in contact with the second conductive layer 20 (through the metal contact hole 101) (wherein the third metal wire and the fourth metal wire may be electrically connected). For example, as Figure 9 As shown, the memory structure may further include a transistor, so that when the memory structure is located in a bit cell circuit, the first conductive layer 10 may be connected to the bit line BL in the bit cell circuit, the second conductive layer 20 may be connected to the drain of the transistor, the source of the transistor may be connected to the source line SL in the bit cell circuit, and the gate of the transistor may be connected to the word line WL in the bit cell circuit. It is understandable that Figure 9 The corresponding top view can be Figure 10 shown.

[0069] In order to connect the plurality of second storage units in parallel in pairs in the memory structure, save the area of ​​the memory structure, and improve the storage capacity, in other optional embodiments, the second magnetic tunnel junction in each of the third write modules is stacked with the third metal line, and the third magnetic tunnel junction in each of the fourth write modules is stacked with the fourth metal line, and the memory structure includes a third conductive layer and a fourth conductive layer, such as Figure 11As shown, any two of the second magnetic tunnel junctions MTJN (MTJ1, ..., MTJN, N is greater than or equal to 1) in the plurality of the second storage cells are located side by side along the second direction B between the third conductive layer (not shown in the figure, it can be understood that the third conductive layer is located on the side of the magnetic tunnel junction away from the metal wire) and the fourth conductive layer 30, and the second magnetic tunnel junction MTJN (MTJ1, ..., MTJN, N is greater than or equal to 1) and the third magnetic tunnel junction MTJ2N (MTJ2, ..., MTJ2N, N is greater than or equal to 1) in each of the second storage cells are in contact with the third conductive layer, respectively, and the third metal wire and the fourth metal wire in each of the second storage cells are in contact with the sixth conductive layer, respectively.

[0070] In order to connect the plurality of second storage units in parallel in pairs in the memory structure, save the area of ​​the memory structure, and improve the storage capacity, in some further optional embodiments, the second magnetic tunnel junction in each of the third write modules is stacked with the third metal line, and the third magnetic tunnel junction in each of the fourth write modules is stacked with the fourth metal line, and the memory structure includes a fifth conductive layer and a sixth conductive layer, such as Figure 12 As shown, the plurality of second storage cells include at least two, any two of the second magnetic tunnel junctions (MTJ1) and the third magnetic tunnel junction (MTJ2) in at least one of the two second storage cells are located side by side along a third direction C between the fifth conductive layer (not shown in the figure, it can be understood that the fifth conductive layer is located on the side of the magnetic tunnel junction away from the metal line) and the sixth conductive layer (not shown in the figure, it can be understood that the sixth conductive layer is located on the side of the metal line away from the magnetic tunnel junction), and any two of the second magnetic tunnel junctions (MTJ3) and the third magnetic tunnel junction (MTJ4) in at least another one of the two second storage cells are located side by side along a fourth direction D between the fifth conductive layer and the sixth conductive layer, the third direction C and the fourth direction D intersect, and the second magnetic tunnel junction (MTJ1 or MTJ3) and the third magnetic tunnel junction (MTJ2 or MTJ4) in each of the second storage cells are in contact with the fifth conductive layer, respectively, and the third metal line and the fourth metal line in each of the second storage cells are in contact with the sixth conductive layer, respectively.

[0071] In order to connect the plurality of second storage units in parallel in pairs in the memory structure, save the area of ​​the memory structure, and improve the storage capacity, in some optional embodiments, when the plurality of the second storage units include four, in addition to one of the at least two second storage units and another of the at least two second storage units, Figure 12 On the basis of further Figure 13 As shown, any two of the second magnetic tunnel junctions (MTJ5) and the third magnetic tunnel junction (MTJ8) in the third of the four second storage cells are located side by side along the fifth direction E between the fifth conductive layer and the sixth conductive layer, and any two of the second magnetic tunnel junctions (MTJ6) and the third magnetic tunnel junction (MTJ7) in the fourth of the four second storage cells are located side by side along the sixth direction F between the fifth conductive layer and the sixth conductive layer, and the third direction C, the fourth direction D, the fifth direction E and the sixth direction F are in the shape of a "M".

[0072] In addition, when the memory structure in any of the above-mentioned embodiments is located in a bit cell circuit, the transistor in the memory structure can play a current limiting role, thereby avoiding the phenomenon that the metal line is immediately melted after the magnetic tunnel junction MTJ in the memory structure is broken down. Therefore, it can be applicable to the case where the melting voltage of the metal line is higher than the breakdown voltage of the magnetic tunnel junction MTJ, and it can also be applicable to the case where the metal line and the magnetic tunnel junction are connected in series and the melting voltage of the metal line is lower than the breakdown voltage of the magnetic tunnel junction MTJ.

[0073] Moreover, in the same bit cell circuit, the same transistor can simultaneously control N magnetic tunnel junctions MTJs and multiple metal wires, thereby achieving 2N programming times, where N is greater than or equal to 1. It is noted that the magnetic tunnel junction MTJ in this solution may include a free layer, an insulating dielectric layer (spacer layer), and a fixed layer that are stacked. In the case where the magnetic tunnel junction MTJ is connected in series with the metal wire, the metal wire in the magnetic tunnel junction MTJ may be connected in series with the free layer, that is, the metal wire is located on the side of the free layer of the magnetic tunnel junction MTJ away from the insulating dielectric layer, and is in contact with the free layer; or, the metal wire in the magnetic tunnel junction MTJ may be connected in series with the fixed layer, that is, the metal wire is located on the side of the fixed layer of the magnetic tunnel junction MTJ away from the insulating dielectric layer, and is in contact with the fixed layer.

[0074] Specifically, the free layer may include materials such as cobalt iron boron (CoFeB), cobalt iron (CoFe), and nickel iron (NiFe). The insulating dielectric layer may include materials such as magnesium oxide (MgO), aluminum oxide (Al2O3), hafnium dioxide (HfO2), magnesium aluminum oxide (MgAlO), and copper oxide (CuO). The pinned layer may include a magnetic reference layer and a synthetic antiferromagnetic structure.

[0075] The magnetic reference layer in the fixed layer may include materials such as cobalt iron boron (CoFeB), cobalt iron (CoFe), and nickel iron (NiFe).

[0076] The synthetic antiferromagnetic structure in the pinned layer may include a first ferromagnetic structure, an antiferromagnetic coupling layer, and a second ferromagnetic structure that are stacked. For example, the first ferromagnetic structure and the second ferromagnetic structure may each include a cobalt-platinum alloy (Co / Pt), and the antiferromagnetic coupling layer may include ruthenium (Ru), so that the synthetic antiferromagnetic structure may be [Co / Pt]. m / Ru / [Co / Pt] n .

[0077] The metal wire in this solution can be any one or more materials selected from copper (Cu), platinum (Pt), tantalum (Ta), tungsten (W), titanium nitride (TiN) and tantalum nitride (TaN).

[0078] From the above description, it can be seen that the above embodiments of the present invention achieve the following technical effects:

[0079] The present application discloses a memory structure in which, when the memory structure is in a write state, the breakdown of the magnetic tunnel junction and the fusing of the metal wire can each serve as a one-time programming of the memory structure. Therefore, in order to enable the same memory structure to have a multi-time programmable function, the same memory structure can simultaneously include the above-mentioned magnetic tunnel junction and metal wire, and the magnetic tunnel junction can be set to have a breakdown voltage, the metal wire can have a fusing voltage, and the breakdown voltage and the fusing voltage can be different fusing voltages, so that the breakdown of the magnetic tunnel junction and the fusing of the metal wire in the same memory structure will not occur at the same time, and the same memory structure can be programmed twice. Therefore, the present application solves the problem in the prior art that non-volatile memories based on the OTP working principle do not have multi-time programmable capabilities.

[0080] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A memory structure, characterized in that: The memory structure includes: A magnetic tunnel junction and a metal line are electrically connected, wherein the electrical connection is a series connection or a parallel connection, and when the memory structure is in a write state, the magnetic tunnel junction has a breakdown voltage, the metal line has a fuse voltage, and the breakdown voltage and the fuse voltage have different voltage values.

2. The memory structure according to claim 1, wherein: When the electrical connection is the series connection, the breakdown voltage is lower than the fusing voltage.

3. The memory structure according to claim 1, wherein: When the electrical connection is the parallel connection, the breakdown voltage is higher than the fusing voltage.

4. The memory structure according to claim 1, wherein: The memory structure includes at least one first storage unit, each of the first storage unit includes a first write module and a second write module connected in parallel, the first write module is a first metal line, the second write module is a second metal line and a first magnetic tunnel junction connected in series, the magnetic tunnel junction includes the first magnetic tunnel junction, and the metal line includes the first metal line and the second metal line.

5. The memory structure according to claim 1, wherein: The memory structure includes at least one second storage unit, each of the second storage units includes a third write module and a fourth write module connected in parallel, the third write module is a second magnetic tunnel junction and a third metal line connected in series, the fourth write module is a third magnetic tunnel junction and a fourth metal line connected in series, the magnetic tunnel junction includes the second magnetic tunnel junction and the third magnetic tunnel junction, and the metal lines include the third metal line and the fourth metal line.

6. The memory structure according to claim 5, characterized in that In the case where the second storage unit includes a plurality of units, any two of the plurality of second storage units are connected in parallel.

7. The memory structure according to claim 6, wherein: The second magnetic tunnel junction in each of the third write modules is stacked with the third metal wire, and the third magnetic tunnel junction in each of the fourth write modules is stacked with the fourth metal wire. The memory structure includes a first conductive layer and a second conductive layer. Any two of the second magnetic tunnel junctions and the third magnetic tunnel junctions in a plurality of the second storage units are located side by side between the first conductive layer and the second conductive layer along a first direction, and the second magnetic tunnel junction and the third magnetic tunnel junction in each of the second storage units are in contact with the first conductive layer, respectively, and the third metal wire and the fourth metal wire in each of the second storage units are in contact with the second conductive layer, respectively.

8. The memory structure according to claim 6, wherein: The second magnetic tunnel junction in each of the third write modules is stacked with the third metal wire, and the third magnetic tunnel junction in each of the fourth write modules is stacked with the fourth metal wire. The memory structure includes a third conductive layer and a fourth conductive layer. Any two of the second magnetic tunnel junctions in a plurality of the second storage units are located side by side between the third conductive layer and the fourth conductive layer along the second direction, and the second magnetic tunnel junction and the third magnetic tunnel junction in each of the second storage units are in contact with the third conductive layer, respectively, and the third metal wire and the fourth metal wire in each of the second storage units are in contact with the fourth conductive layer, respectively.

9. The memory structure according to claim 6, wherein: The second magnetic tunnel junction in each of the third write modules is stacked with the third metal line, and the third magnetic tunnel junction in each of the fourth write modules is stacked with the fourth metal line. The memory structure includes a fifth conductive layer and a sixth conductive layer. The plurality of second storage units include at least two, and any two of the second magnetic tunnel junctions and the third magnetic tunnel junctions in at least one of the two second storage units are located side by side between the fifth conductive layer and the sixth conductive layer along a third direction, and any two of the second magnetic tunnel junctions and the third magnetic tunnel junction in at least another one of the two second storage units are located side by side between the fifth conductive layer and the sixth conductive layer along a fourth direction. The third direction intersects with the fourth direction, and the second magnetic tunnel junction and the third magnetic tunnel junction in each of the second storage units are respectively in contact with the fifth conductive layer, and the third metal line and the fourth metal line in each of the second storage units are respectively in contact with the sixth conductive layer.

10. The memory structure according to claim 9, wherein: In the case where the plurality of second storage units includes four, except for one of the at least two second storage units and another of the at least two second storage units, any two of the second magnetic tunnel junctions and the third magnetic tunnel junction in the third of the four second storage units are located side by side between the fifth conductive layer and the sixth conductive layer along the fifth direction, and any two of the second magnetic tunnel junctions and the third magnetic tunnel junction in the fourth of the four second storage units are located side by side between the fifth conductive layer and the sixth conductive layer along the sixth direction, and the third direction, the fourth direction, the fifth direction and the sixth direction form a "M" shape.

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