Gate formation method, semiconductor device, and electronic apparatus

Abstract

The application relates to a gate forming method, a semiconductor device and an electronic equipment, and comprises the following steps: providing a substrate, the substrate comprising a plurality of interlayer dielectric layers and a plurality of gate trenches arranged alternately along a first direction; the bottom of the gate trench comprises first ions left after wet etching; performing a first plasma treatment process on the substrate to synchronously remove the first ions and form a group containing second ions at the bottom of the gate trench; performing a second plasma treatment process on the substrate after the first plasma treatment process to make the second ions in the group react in situ to generate target polarity groups; forming a work function layer covering the interlayer dielectric layers and the inner surface of the gate trench; and in the process of forming the work function layer, the adsorption probability of the work function layer at the bottom of the gate trench is greater than the original probability. The formation of voids in the MG process can be avoided, which plays an important role in yield stability and improvement.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a gate formation method, semiconductor device, and electronic device. Background Technology

[0002] With the continuous development of semiconductor technology, the size of circuit devices is constantly shrinking as chip integration increases. In advanced chip manufacturing, high-k metal gate (HKMG) is the mainstream process technology that allows Moore's Law to continue. Among them, the gate-last process does not require high-temperature steps, allowing for more freedom in setting and adjusting the work function value of the gate electrode material, resulting in higher chip stability and reliability.

[0003] However, the aforementioned miniaturization increases the complexity of semiconductor manufacturing, making the "back gate" process face more process challenges and design limitations throughout the manufacturing process. The work function materials used are difficult to deposit uniformly at small feature sizes. Summary of the Invention

[0004] Therefore, it is necessary to provide a gate formation method, semiconductor device, and electronic device to address the technical problems in the prior art, which can at least improve the deposition uniformity of the metal gate work function layer.

[0005] In a first aspect, this application provides a gate formation method, comprising: providing a substrate, wherein the substrate includes a plurality of interlayer dielectric layers and a plurality of gate trenches alternately arranged along a first direction parallel to a first surface of the substrate; the bottom of the gate trench includes first ions remaining from wet etching;

[0006] A first plasma treatment process is performed on the substrate to simultaneously remove the first ions and form groups containing the second ions at the bottom of the gate trench;

[0007] A second plasma treatment process is performed on the substrate after the first plasma treatment process, so that the second ions in the group undergo an in-situ reaction to generate the target polar group;

[0008] Forming a dielectric layer covering the interlayer and a work function layer on the inner surface of the gate trench;

[0009] In the process of forming the work function layer, the adsorption probability of the work function layer at the bottom of the gate trench is greater than the original probability; the original probability is used to characterize the probability of the work function layer undergoing chemisorption in the trench without target polar group modification.

[0010] In the above embodiments, compared to the process flow of directly depositing the work function layer after removing the dummy gate filler in related technologies, the method provided in this application adds a two-stage plasma treatment process (first plasma treatment and second plasma treatment) before depositing the work function layer in the original process. The first plasma treatment effectively removes the ions (first ions) remaining in the wet-etched gate trenches, while leaving the second ions; the second plasma treatment of the second ions forms target polar groups at the bottom of the gate trenches, enhancing the interaction between the surface and the precursor, thereby increasing the adsorption probability of the work function layer. This improves the uniformity of the subsequent deposition process, avoids the formation of voids, and plays an important role in stabilizing and improving the yield.

[0011] In some embodiments, the gate trench includes:

[0012] The dielectric layer is located at the bottom of the gate trench;

[0013] A barrier layer is located on the top surface of the dielectric layer and on the sidewalls of the gate trench;

[0014] The first ion is located on the top surface of the barrier layer within the gate trench.

[0015] In some embodiments, the first ion includes a fluoride ion;

[0016] Perform a first plasma processing procedure on the substrate, including:

[0017] Based on the set first gas flow rate and first processing time, ammonia plasma containing inert gas is used to perform a first plasma treatment on the inner surface of multiple grid trenches.

[0018] In some embodiments, a second plasma processing process is performed on the substrate after the first plasma processing process, including:

[0019] Based on the set second gas flow rate and second processing time, a second plasma treatment is performed on the inner surface of multiple grid trenches using nitrous oxide plasma containing inert gas.

[0020] In some embodiments, the first gas flow rate is not greater than the second gas flow rate;

[0021] The first processing time should not be less than the second processing time.

[0022] In some embodiments, the first plasma processing process includes a first high-frequency power and a first low-frequency power applied simultaneously;

[0023] The second plasma processing technology includes the simultaneous application of a second high-frequency power and a second low-frequency power.

[0024] In some embodiments, the range of the first high-frequency power is 500W-900W, and the range of the first low-frequency power is 200W-500W;

[0025] The first high-frequency power range is 500W-800W, and the first low-frequency power range is 200W-400W.

[0026] In some embodiments, the work function layer includes metal ions;

[0027] The formalized function layer includes:

[0028] A work function layer is formed by a deposition process, covering the inner surface of multiple gate trenches and the top surface of multiple interlayer dielectric layers.

[0029] Secondly, this application also provides a semiconductor device including a gate formed by the method described in any of the above embodiments.

[0030] In the above embodiments, without additional structural or material changes, the deposition uniformity of the work function layer is improved through a two-stage plasma treatment (first plasma treatment process and second plasma treatment process), eliminating coverage voids caused by uneven nucleation and reducing local thickness fluctuations or defects in the gate. This effectively improves the yield of device manufacturing and long-term operational reliability, ensures consistent threshold voltage regulation of the work function metal, reduces the risk of device parameter drift, and improves threshold voltage stability, providing a key process solution for advanced semiconductor manufacturing.

[0031] In some embodiments, the substrate includes a first active region and a second active region arranged sequentially along a first direction;

[0032] The gate is located on the substrate within the second active region.

[0033] Thirdly, this application also provides an electronic device, including a gate formed by the method described in any of the above embodiments; or a semiconductor device as described in the above embodiments.

[0034] In the above embodiments, the improved yield and reliability of gate or semiconductor devices enhance the operational reliability of electronic devices, while reducing leakage current optimizes energy efficiency, providing underlying technical support for the long lifespan and low power consumption design of electronic devices.

[0035] The gate formation method, semiconductor device, and electronic device provided in this application have the following unexpected technical effects:

[0036] In response to the problem in related technologies that residual water stains or acid at the bottom of the etched gate trench affects the subsequent deposition of the work function layer, the embodiments provided in this application modify the inner surface of the etched gate trench in advance through a first plasma treatment process and a second plasma treatment process.

[0037] According to the preset process sequence, the first plasma treatment removes the residual first ions, leaving the second ions; the second plasma then reacts with the second ions, causing the target polar groups to grow in situ within the gate trench, thereby increasing the adsorption probability of the deposited work function layer material at the bottom of the gate trench. This results in a more uniform deposition of the work function layer throughout the entire gate trench, with better thickness consistency, thereby reducing the probability of voids caused by poor coverage, improving device yield, and laying a solid foundation for obtaining stable threshold voltage and reliable device performance. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 A cross-sectional structural diagram of each step in the gate formation process of the back gate process of related technologies;

[0040] Figure 2a for Figure 1 One of the schematic diagrams of a partial cross-section of the central gate electron microstructure;

[0041] Figure 2b for Figure 1 Schematic diagram of a partial cross-section of the middle gate electron microstructure (Part 2);

[0042] Figure 2c for Figure 1 Schematic diagram of a partial cross-section of the middle gate electron microstructure (Part 3);

[0043] Figure 3 This is a flowchart of a semiconductor structure fabrication method provided in one embodiment;

[0044] Figure 4a This is a schematic cross-sectional view of the structure obtained after forming a TiN layer in step S102 of the semiconductor structure fabrication method provided in one embodiment;

[0045] Figure 4b This is a schematic cross-sectional view of the structure obtained after forming a gate trench in step S102 of the semiconductor structure fabrication method provided in one embodiment;

[0046] Figure 5 for Figure 4b A cross-sectional schematic diagram of the structure obtained after the first plasma processing is performed.

[0047] Figure 6 for Figure 5 A cross-sectional schematic diagram of the structure obtained after the second plasma processing is performed.

[0048] Figure 7 for Figure 6 A schematic diagram of the cross-section of the structure obtained after the successful completion of the intermediate-shape function layer;

[0049] Figure 8 for Figure 7 A schematic diagram of the cross-section of the structure after the gate conductive layer is formed.

[0050] Explanation of reference numerals in the attached figures:

[0051] 10. Substrate; 11. Interlayer dielectric layer; 20. Gate trench; 12. Dielectric layer; 13. Barrier layer; 14. Sacrificial layer; 15. Work function layer; 21. First ion; 22. Second ion; 23. Target polar group; 31. Gate conductive layer. Detailed Implementation

[0052] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0054] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0055] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0056] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0057] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of this application, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of this application.

[0058] In this embodiment, the substrate may include a first surface located on the front side and a back surface, i.e., a second surface, opposite to the front side. Ignoring the flatness of the first and second surfaces, a first direction parallel to the first surface is defined, and the direction toward the substrate includes a second direction perpendicular to the first surface of the substrate. In this embodiment, the first direction is defined as the Y-axis direction, the second direction as the Z-axis direction, and the third direction as the X-axis direction.

[0059] Please see Figure 1 , Figure 1 This is a schematic cross-sectional view of each step in the gate fabrication process of the post-gate technology. For example... Figure 1 As shown, in related technologies, after the dummy gate is removed, titanium nitride (TiN) is deposited in the dummy gate trench to adjust the PMOS work function, and then a patterned photoresist layer is formed. Using the patterned photoresist layer as a mask, the TiN in the NMOS region is removed by a dry / wet process, the patterned photoresist layer is removed, and a work function layer is formed in the NMOS region.

[0060] However, this TiN removal process easily leads to residual fluoride-containing acid and water stains, such as... Figure 2a and Figure 2b As shown, interface bulging is induced through chemical corrosion and gas generation mechanisms, which then transforms into [the following] during NMOS work function layer deposition. Figure 2c The voids and pits shown indicate defects that lead to a decrease in yield.

[0061] Based on this, please refer to Figures 3-8 This application provides a gate formation method, comprising:

[0062] Step S102: Provide a substrate 10, which includes a plurality of interlayer dielectric layers 11 and a plurality of gate trenches 20 arranged alternately along the OY direction parallel to the first surface of the substrate; the bottom of the gate trenches 20 includes first ions 21 left over from wet etching.

[0063] Step S104: Perform a first plasma processing on the substrate 10 to simultaneously remove the first ions 21 and form a group containing the second ions 22 at the bottom of the gate trench 20.

[0064] Step S106: Perform a second plasma treatment process on the substrate 10 after the first plasma treatment process, so that the second ion 22 in the group undergoes an in-situ reaction to generate the target polar group 23.

[0065] Step S108: Form a covering interlayer dielectric layer 11 and a work function layer 15 on the inner surface of the gate trench 20; wherein, during the formation of the work function layer 15, the adsorption probability of the work function layer 15 at the bottom of the gate trench 20 is greater than the original probability; the original probability is used to characterize the probability of the work function layer 15 undergoing chemisorption in the trench without the target polar group 23 modification.

[0066] The semiconductor structure obtained after steps S102-S108 can be found in [reference]. Figure 7 For ease of understanding this application, Figures 4a to 7 This is a schematic diagram illustrating the steps of an exemplary gate formation method provided in an embodiment of this application, wherein, Figure 7 This application provides an example of a gate fabricated using the method described herein. Other suitable examples of gate fabricated using the method described herein are also possible, and no limitations are imposed herein.

[0067] The following is combined Figures 4a to 7 The present application provides a detailed description of the gate provided in the embodiments.

[0068] In the extended step of step S102, an interlayer dielectric layer 11 is formed on the top surface of the substrate 10 using a deposition process. Subsequently, photolithography and etching processes are performed to form gate trenches 20 spaced apart along the OY direction in the interlayer dielectric layer 11.

[0069] Furthermore, using a deposition process, a dielectric layer 12, a barrier layer 13, and a sacrificial layer 14 are sequentially formed within the gate trench 20: the dielectric layer 12 is located at the bottom of the gate trench 20; the barrier layer 13 is located on the top surface of the dielectric layer 12 and on the sidewalls of the gate trench 20, resulting in... Figure 4a The structure shown is as follows. Finally, the sacrificial layer 14 within part of the gate trench is selectively removed using a wet etching process to obtain the structure shown. Figure 4b The structure shown. At this time, residual water stains or residual acid (containing the first ion 21) remain at the bottom of the gate trench 20.

[0070] In addition, in some embodiments, before forming the interlayer dielectric layer 11, an interface layer (IL) (not shown) is formed on the top surface of the substrate 10 to improve the interface characteristics between the dielectric layer 12 and the substrate 10.

[0071] For example, substrate 10 includes a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer located beneath a thin semiconductor layer that serves as the active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor typically include the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., GaxAl1). x As, Ga x Al 1-x N、In x Ga 1-x As, etc.) or combinations thereof. The substrate 10 may include other device structures (not shown), such as isolation trench structures. Those skilled in the art can select the substrate specifically according to the transistor type, therefore the type of substrate should not limit the scope of protection of this application.

[0072] For example, the interlayer dielectric layer 11 is typically a dielectric material, including but not limited to silicon nitride (SiN), silicon oxide (SiO2), or silicon oxynitride (SiO2). x N y Materials for dielectric layer 12 include, but are not limited to, materials with high k dielectric constant, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), titanium oxide (TiO2), or silicon oxide (SiO2); materials for barrier layer 13 include, but are not limited to, silicon oxide (SiO2), doped oxides (such as silicon phosphosilicate glass (PSG), borosilicate glass (BPSG)), or silicon nitride (SiN).

[0073] The specific type of the first ion 21 depends on the etching process, including but not limited to chloride ions (Cl). - phosphate PO4³ - fluoride ions F - or bromide ions Br - wait.

[0074] For example, in this embodiment, the solution used in the wet etching is a hydrofluoric acid (HF) solution, and the first ion 21 includes fluoride ions F. - .

[0075] Please see Figure 5 In the extension step of step S104, the first plasma processing process includes:

[0076] Based on the set first gas flow rate and first processing time, the inner surfaces of multiple grid trenches 20 are subjected to first plasma treatment using ammonia (NH3) plasma containing inert gas.

[0077] For example, the processing temperature range is 350℃-400℃.

[0078] For example, the processing temperature of NH3 plasma treatment can be 350°C, 360°C, 370°C, 380°C, 390°C, or 400°C, etc.

[0079] For example, the range of the first gas flow rate is 500 sccm-1000 sccm.

[0080] For example, the gas flow rate of NH3 can be 500 sccm, 700 sccm, 800 sccm, 900 sccm, or 1000 sccm, etc.

[0081] For example, the first processing time ranges from 10s to 60s.

[0082] For example, the first processing time can be 10s, 20s, 40s, or 60s, etc.

[0083] In the above embodiments, during the first plasma treatment process, NH3 is reacted with the first ion 21 (fluoride ion F) at a fixed power. - In the generator, it reacts and decomposes into gaseous ammonium fluoride (NH4F) and second ions 22 (H2O). + The ammonium fluoride (NH4F) is then removed. The specific reaction equation is as follows:

[0084] Substrate-F+NH3→Substrate-H+NH4F(g);

[0085] Additionally, one or more of argon (Ar), helium (He), or nitrogen (N) can be introduced as a protective gas during this process. In this embodiment, the protective gas is argon (Ar), and its flow rate ranges from 1000 sccm to 5000 sccm, for example, it can be 1000 sccm, 2000 sccm, 3000 sccm, 4000 sccm, or 5000 sccm, etc.

[0086] Furthermore, the first plasma processing technology includes a first high-frequency power and a first low-frequency power applied simultaneously.

[0087] For example, the range of the first high-frequency power is 500W-900W.

[0088] For example, the first high-frequency power can be 500W, 600W, 700W, 800W or 900W, etc.

[0089] For example, the range of the first low-frequency power is 200W-500W.

[0090] For example, the first low-frequency power can be 200W, 300W, 400W or 500W, etc.

[0091] In plasma processing, single high-frequency power can more effectively ionize gas, generating high plasma density. However, ions collide with sidewalls randomly and cannot reach the bottom of the trench in a directional manner. At low frequencies, ions have sufficient time to respond to changes in the electric field and form directional motion, but the plasma ionization rate is low. Based on this, the above embodiment adopts dual-frequency power technology, using a high-frequency source to maintain plasma density and a low-frequency source to guide the directional motion of plasma, achieving a balanced optimization of plasma density and directionality, ensuring that the first ions are fully reacted. This power superposition scheme effectively improves etching uniformity and morphology control, and is particularly suitable for the precise processing of high aspect ratio structures, providing more ideal surface conditions for subsequent deposition processes.

[0092] Please see Figure 6 In the extension step of step S106, the second plasma processing process includes:

[0093] Based on the set second gas flow rate and second processing time, a second plasma treatment is performed on the inner surface of multiple grid trenches 20 using nitrous oxide (N2O) plasma containing an inert gas.

[0094] For example, the range of the second gas flow rate is 1000 sccm-5000 sccm.

[0095] For example, the gas flow rate of N2O can be 1000 sccm, 2000 sccm, 3000 sccm, 4000 sccm or 5000 sccm, etc.

[0096] For example, the first processing time ranges from 3s to 10s.

[0097] For example, the first processing time can be 3s, 5s, 7s, 9s, or 10s, etc.

[0098] In the above embodiments, the second plasma treatment process uses the same processing temperature and protective gas settings as the first plasma treatment process, which will not be elaborated further here. During the second plasma treatment process, N₂O reacts with the second ions ₂(H₂O)... + The target polar group 23 (-OH) and gaseous nitrogen (N2) react in situ in the generator, and the nitrogen (N2) is then removed. The specific reaction equation is as follows:

[0099] Substrate-H+N2O→Substrate-OH+N2;

[0100] In some embodiments, the second plasma processing process includes a second high-frequency power and a second low-frequency power applied simultaneously.

[0101] For example, the range of the second high-frequency power is 500W-800W.

[0102] For example, the second high-frequency power can be 500W, 600W, 700W or 800W, etc.

[0103] For example, the second low-frequency power ranges from 200W to 400W.

[0104] For example, the second low-frequency power can be 200W, 300W, or 400W, etc.

[0105] Please see Figure 7 In the extension step of step S108, one or more of the following processes can be used to form the functional layer 15: chemical vapor deposition (CVD), atomic layer deposition (ALD), or high density plasma deposition (HDP).

[0106] For example, the work function layer 15 may be formed of a material including metal ions, including but not limited to titanium carbide (TiC), tantalum carbide (TaC), tantalum gold (Ta-Au) alloy, titanium aluminum (TiAl), tantalum copper (Ta-Cu), titanium aluminum carbide (TiAlC) or tantalum nitride (TaN) or combinations thereof.

[0107] In the above embodiments, since there is a target polar group (-OH) at the bottom of the gate trench 20, the appropriate OH bond can enhance wettability and there is a stronger chemical interaction (such as hydrogen bond, dipole-dipole interaction, coordination interaction) between it and the work function layer precursor of the organometallic compound. This leads to an accelerated adsorption rate of the work function layer 15 at the bottom of the gate trench 20, which is significantly higher than the probability of chemisorption (i.e. the original probability) in the trench without the target polar group modification, thereby achieving the purpose of improving the step coverage capability of the work function layer.

[0108] In some embodiments, this application provides a semiconductor device including a gate fabricated by the method described in any of the foregoing embodiments.

[0109] Please see Figure 8 In some embodiments, the substrate 10 includes a first active region (not shown) and a second active region arranged sequentially along the OY direction; the gate is located on the substrate 10 within the second active region.

[0110] For example, the first active region is a P-type active region, and the second active region is an N-type active region. The specific process of the gate is as described in the gate formation method above. It should be understood that in the extension step of step S102, removing part of the sacrificial layer 14 includes: forming a patterned photoresist layer to cover the first active region, and using the patterned photoresist as a mask, selectively removing the sacrificial layer 14 of the second active region by a wet etching process. The remaining steps are the same as steps S104 and S108, and will not be described in detail here.

[0111] For example, the material of the sacrificial layer 14 includes titanium nitride (TiN).

[0112] Please see Figure 8 In some embodiments, after step S108, the method further includes:

[0113] After removing the patterned photoresist layer, a gate conductive layer 31 is formed in the gate trench 20 by combining deposition and chemical mechanical polishing processes.

[0114] For example, the material of the gate conductive layer 31 includes, but is not limited to, gold (Au), silver (Ag), molybdenum (Mo), or copper (Cu).

[0115] In the above embodiments, the metal gate defects prepared by the above gate formation method are improved by more than 90%, and the number of voids in the work function layer is controlled to be less than 20.

[0116] In some embodiments, this application also provides an electronic device including a gate fabricated as described in any of the foregoing embodiments; or a semiconductor device as described in the foregoing embodiments. Since the foregoing gate formation method, semiconductor device, and electronic device are based on the same inventive configuration, the electronic device employing such a gate or semiconductor device has all the advantages of the gate formation method provided by this invention, which will not be elaborated upon here.

[0117] The gate formation method, semiconductor device, and electronic device provided in this application have the following unexpected technical effects:

[0118] In the embodiments provided in this application, a two-stage plasma treatment process is used to pre-treat the inner surface of the gate trench before the work function layer deposition. Through the chemical reaction between plasma and residual ions (including first and second ions), residual water stains and / or residual acid from wet etching are removed, while target polar groups are generated in situ at the bottom of the gate trench. These target polar groups enhance the chemisorption capacity of the work function layer precursor at the bottom of the trench, effectively improving the step coverage of the work function layer within the gate trench and preventing voids or bulges caused by uneven work function layer deposition. Compared to traditional technologies, the metal gate defect improvement achieved by the above gate formation method exceeds 90%, and the number of voids in the work function layer is controlled to below 20, playing a crucial role in improving transistor performance consistency, device yield, and long-term reliability.

[0119] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0120] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for forming a gate, characterized in that, include: A substrate is provided, the substrate including a plurality of interlayer dielectric layers and a plurality of gate trenches arranged alternately along a first direction parallel to a first surface of the substrate; the bottom of the gate trenches includes first ions left over from wet etching; A first plasma treatment process is performed on the substrate to simultaneously remove the first ions and form groups containing second ions at the bottom of the gate trench; A second plasma treatment process is performed on the substrate after the first plasma treatment process, so that the second ions in the group undergo an in-situ reaction to generate the target polar group; A work function layer is formed covering the interlayer dielectric layer and the inner surface of the gate trench; In the process of forming the work function layer, the adsorption probability of the work function layer at the bottom of the gate trench is greater than the original probability; the original probability is used to characterize the probability that the work function layer undergoes chemisorption in the trench without the target polar group modification.

2. The forming method according to claim 1, characterized in that, The gate trench includes: A dielectric layer is located at the bottom of the gate trench; A barrier layer is located on the top surface of the dielectric layer and on the sidewall of the gate trench; The first ion is located on the top surface of the barrier layer within the gate trench.

3. The forming method according to claim 2, characterized in that, The first ion includes fluoride ions; Performing a first plasma processing process on the substrate includes: Based on the set first gas flow rate and first processing time, the inner surfaces of the plurality of grid trenches are subjected to a first plasma treatment using ammonia plasma containing inert gas; and / or A second plasma processing process is performed on the substrate after the first plasma processing process, including: Based on the set second gas flow rate and second processing time, the inner surfaces of the plurality of grid trenches are subjected to a second plasma treatment using nitrous oxide plasma containing inert gas.

4. The forming method according to claim 3, characterized in that, The flow rate of the first gas is not greater than the flow rate of the second gas; The first processing time is not less than the second processing time.

5. The forming method according to claim 1, characterized in that, The first plasma processing technology includes a first high-frequency power and a first low-frequency power applied simultaneously; The second plasma processing technology includes the simultaneous application of a second high-frequency power and a second low-frequency power.

6. The forming method according to claim 5, characterized in that, The first high-frequency power ranges from 500W to 900W, and the first low-frequency power ranges from 200W to 500W. The first high-frequency power ranges from 500W to 800W, and the first low-frequency power ranges from 200W to 400W.

7. The forming method according to any one of claims 1-6, characterized in that, The work function layer includes metal ions; Forming the work function layer includes: A work function layer is formed by a deposition process, covering the inner surfaces of the plurality of gate trenches and the top surfaces of the plurality of interlayer dielectric layers.

8. A semiconductor device, characterized in that, include: The gate formed by the method as described in any one of claims 1-7.

9. The semiconductor device according to claim 8, characterized in that, The substrate includes a first active region and a second active region arranged sequentially along the first direction; The gate is located on the substrate within the second active region.

10. An electronic device, characterized in that, include: The gate formed by the method as described in any one of claims 1-7; or The semiconductor device as described in any one of claims 8-9.

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