Light-emitting element and display device using same

Abstract

A light-emitting element and a display device using the same, the light-emitting element comprising a light-emitting diode wafer having a first surface and a second surface opposite to each other, and a plurality of sidewalls connecting the first surface and the second surface; the insulating structure covers the first surface, the second surface and the plurality of side walls; and an electrical connection pad located on the first surface, wherein the insulating structure includes: a cladding portion covering a portion of the plurality of sidewalls; the plurality of protruding parts are arranged on the plurality of side walls, and the plurality of protruding parts protrude from the coating part and transversely extend; the protrusion lengths of at least two of the plurality of protrusions are different from each other.

Description

[0001] This application is a divisional application of a patent application with an application date of June 10, 2021, application number 202110647203.X, and invention name “Light-emitting element and display device using the same”. Technical Field

[0002] The present disclosure relates to a light-emitting element and a display device using the same, and more particularly to a light-emitting diode (LED) light-emitting element and a display device using the same. Background Art

[0003] Light-emitting diodes (LEDs) are a type of semiconductor device. Their advantages, such as being lightweight, thin, short, self-luminous, having a short response time, a long lifespan, and low power consumption, have led to the rapid development of LEDs.

[0004] Micro-LEDs are light-emitting devices with dimensions down to the micron (μm) scale. During the display device manufacturing process, the micro-LED wafer is placed onto another substrate (e.g., a carrier substrate) using mass transfer technology. To improve process reliability, the micro-LEDs are encapsulated with an insulating layer as a protective layer. Summary of the Invention

[0005] According to some embodiments of the present disclosure, a light-emitting element includes a light-emitting diode chip having a first surface and a second surface opposite to each other, and a plurality of sidewalls connecting the first surface and the second surface. The light-emitting element also includes an insulating structure covering the first surface, the second surface, and the plurality of sidewalls. The light-emitting element also includes an electrical connection pad located on the first surface. The insulating structure includes a covering portion covering a portion of the plurality of sidewalls and a plurality of protrusions disposed on the plurality of sidewalls. The plurality of protrusions protrude from the covering portion and extend laterally. At least two of the plurality of protrusions have different protrusion lengths.

[0006] In some embodiments, the insulating structure includes a stacked combination of two insulating materials having different refractive indices.

[0007] In some embodiments, the plurality of sidewalls include a first portion and a second portion, the first portion is closer to the first surface than the second portion, and the plurality of protrusions protrude outward from the second portion.

[0008] In some embodiments, the light emitting diode chip includes an undoped semiconductor layer, a first doped semiconductor layer, a light emitting layer, and a second doped semiconductor layer stacked in sequence, wherein the first portion includes a portion of a sidewall of the undoped semiconductor layer.

[0009] In some embodiments, the second portion includes another portion of a sidewall of the undoped semiconductor layer.

[0010] In some embodiments, the protrusions have a protrusion length of at least 0.5 microns.

[0011] In some embodiments, the plurality of protrusions have a third surface and a fourth surface opposite to each other, the third surface is closer to the first surface of the LED chip than the fourth surface, and the third surface is between the first and second surfaces of the LED chip.

[0012] In some embodiments, the encapsulation has a fifth surface and a sixth surface opposite to each other, the fifth surface contacts the second surface of the LED chip, and the fourth surface of the plurality of protrusions is between the first surface of the LED chip and the sixth surface of the encapsulation.

[0013] In some embodiments, the second surface of the LED chip is a rough surface.

[0014] According to some embodiments of the present disclosure, a display device includes a carrier substrate and the aforementioned light-emitting element, wherein the light-emitting element is disposed on the carrier substrate.

[0015] Embodiments of the present disclosure provide a light-emitting device structure in which an insulating layer completely covers the semiconductor surface of the light-emitting diode chip within the light-emitting device, providing more complete protection and electrical isolation for the light-emitting device, thereby improving the quality of the light-emitting device. Furthermore, the structural design of the insulating layer, such as the formation of protrusions and the length of the protrusions, can help improve the reliability of the light-emitting device manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The following embodiments should be read in conjunction with the accompanying drawings to clearly understand the concepts of this disclosure. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity of discussion. Furthermore, like reference numerals denote like elements.

[0017] Figure 1A A top view of a light emitting device according to some embodiments of the present disclosure is shown;

[0018] Figure 1B To illustrate the light emitting device along some embodiments of the present disclosure Figure 1A A cross-sectional view of the section line AA;

[0019] Figure 1C To illustrate the light emitting device along some embodiments of the present disclosure Figure 1A A cross-sectional view along the section line BB;

[0020] Figures 2 to 16Cross-sectional views of light-emitting devices at different manufacturing stages are shown according to some embodiments of the present disclosure.

[0021]

Explanation of symbols

[0022] 100: Light-emitting element

[0023] 110: Light-emitting diode chip

[0024] 110A: Light-emitting diode materials

[0025] 110B: Patterned LED Materials

[0026] 110P: LED wafer morphology

[0027] 112: first semiconductor layer

[0028] 112A: Undoped semiconductor layer

[0029] 112B: doped semiconductor layer

[0030] 114: Luminescent layer

[0031] 116: Second semiconductor layer

[0032] 118: Electrode

[0033] 118A: first electrode

[0034] 118B: Second electrode

[0035] 120: Electrical connection pad

[0036] 120A: First electrical connection pad

[0037] 120B: Second electrical connection pad

[0038] 130: first insulating layer

[0039] 140: Second insulation layer

[0040] 140A: Second insulation layer material

[0041] 142: Covering

[0042] 144: protrusion

[0043] 144A: protrusion

[0044] 144B: protrusion

[0045] 146: Interface layer

[0046] 200:Substrate

[0047] 510: first adhesive layer

[0048] 520: first carrier substrate

[0049] 700: Anchor

[0050] 700P: Anchor morphology

[0051] 1000: Sacrificial layer

[0052] 1002: Open

[0053] 1100: Support layer

[0054] 1102: Support frame

[0055] 1104: base part

[0056] 1110: second adhesive layer

[0057] 1120: Second carrier substrate

[0058] 1300: Cantilever structure

[0059] 1302: Device Department

[0060] 1304: Cantilever

[0061] 1306: Anchoring part

[0062] 1400: Extraction

[0063] 1410: Direction

[0064] 1510: Direction

[0065] 1600: Display device

[0066] 1620: third carrier substrate

[0067] D1, D2: protrusion length

[0068] L1, L2, L3, L4: Length

[0069] S1: First surface

[0070] S2: Second surface

[0071] S3: Third surface

[0072] S4: Fourth surface

[0073] S5: Fifth Surface

[0074] S6: Sixth surface

[0075] S7: Seventh Surface

[0076] S8: Eighth Surface

[0077] T1, T2, T3: thickness

[0078] W,W1,W2,W3,W4: side walls

[0079] X, Y, Z: axis DETAILED DESCRIPTION

[0080] The following drawings illustrate various embodiments of the present disclosure. For clarity, many practical details are included in the following description. However, it should be understood that these practical details are not intended to limit the present disclosure. In other words, these practical details are not essential for some embodiments of the present disclosure. Furthermore, to simplify the drawings, some commonly used structures and components are depicted in simplified schematic form.

[0081] Micro-LEDs (light-emitting diodes) are light-emitting devices with dimensions down to the micrometer (μm) scale. These LEDs are manufactured individually in wafer form. During display device manufacturing, the LED wafers are transferred to another substrate (e.g., a carrier substrate) using mass transfer technology.

[0082] In existing light-emitting device structures, electrical connection pads are placed on the LED chip to provide electrical connection between the LED chip and the outside world. An insulating layer is also used to cover a portion of the semiconductor surface of the LED chip to protect the LED chip and reduce the risk of leakage. The present disclosure utilizes a multiple-pass coating process to fully cover the semiconductor surface of the LED chip with an insulating layer, thereby further improving process reliability.

[0083] Please also refer to Figure 1A and Figure 1B , Figure 1A To illustrate a top view of a light emitting device 100 according to some embodiments of the present disclosure, Figure 1B According to some embodiments of the present disclosure, the light emitting device 100 is shown along Figure 1A Cross-sectional view along section line AA.

[0084] like Figure 1A As shown, the light emitting device 100 includes a light emitting diode chip 110, a plurality of electrical connection pads 120 disposed on the light emitting diode chip 110, a first insulating layer 130 covering the light emitting diode chip, and a second insulating layer 140 covering the light emitting diode chip 110. It should be noted that due to Figure 1A From the perspective of the second insulating layer 140, only the protrusion 144 ( Figure 1B ).

[0085] The LED chip 110 has a first surface S1 and a second surface S2 that oppose each other, and a plurality of sidewalls W (e.g., sidewalls W1, W2, W3, and W4) connecting the first surface S1 and the second surface S2. Electrical connection pads 120 are disposed on the first surface S1. In some embodiments, the second surface S2 of the LED chip 110 has a rough texture. In some embodiments, the rough texture of the second surface S2 may have a regular pattern. In some embodiments, the rough texture of the second surface S2 may have a random pattern, in other words, a pattern that is irregular. In some embodiments, the second surface S2 serves as a light-emitting surface.

[0086] The LED wafer 110 may include a multi-layer structure sequentially formed by a first semiconductor layer 112, a light-emitting layer 114, and a second semiconductor layer 116. In some embodiments, the first semiconductor layer 112 includes an undoped semiconductor layer 112A and a doped semiconductor layer 112B, wherein the second surface S2 is on the undoped semiconductor layer 112A, and the doped semiconductor layer 112B is interposed between the undoped semiconductor layer 112A and the light-emitting layer 114. In some other embodiments, the undoped semiconductor layer 112A may be omitted, in which case the second surface S2 is on the doped semiconductor layer 112B.

[0087] In some embodiments, the first semiconductor layer 112 may be a Group III-V semiconductor layer. For example, the Group III-V semiconductor layer may include a binary epitaxial material such as gallium arsenide (GaAs), gallium nitride (GaN), gallium phosphide (GaP), indium arsenide (InAs), aluminum nitride (AlN), indium nitride (InN), or indium phosphide (InP), or a ternary or quaternary epitaxial material such as aluminum gallium nitride (AlGaN), aluminum gallium arsenide (AlGaAs), indium gallium phosphide (InGaP), indium gallium nitride (InGaN), aluminum indium gallium nitride (AlInGaN), aluminum indium gallium phosphide (AlInGaP), or indium gallium arsenide phosphide (InGaAsP). In some embodiments, the undoped semiconductor layer 112A may be an undoped Group III-V semiconductor layer, and the doped semiconductor layer 112B may be an N-type Group III-V semiconductor layer. An N-type Group III-V semiconductor layer can be formed by doping the Group III-V semiconductor layer with a Group IVA element (e.g., silicon).

[0088] The light-emitting layer 114 is disposed on the first semiconductor layer 112. Specifically, the light-emitting layer 114 is disposed on the doped semiconductor layer 112B. In some embodiments, the light-emitting layer 114 may include a multiple quantum well (MQW), a single quantum well (SQW), a homojunction, a heterojunction, or other similar structures, but the present disclosure is not limited to the foregoing. In some embodiments, light generated by the light-emitting layer 114 may pass through the second surface S2.

[0089] The second semiconductor layer 116 is disposed on the light-emitting layer 114. The second semiconductor layer 116 has a different doping type than the first semiconductor layer 112. In some embodiments, when the first semiconductor layer 112 is an N-type Group III-V semiconductor layer, the second semiconductor layer 116 may be the aforementioned P-type Group III-V semiconductor layer. Similarly, when the first semiconductor layer 112 is a P-type Group III-V semiconductor layer, the second semiconductor layer 116 may be the aforementioned N-type Group III-V semiconductor layer.

[0090] In an embodiment of a gallium nitride-based light-emitting diode, the undoped semiconductor layer 112A may be an undoped gallium nitride layer (u-GaN), the doped semiconductor layer 112B may be an n-type gallium nitride layer (n-GaN), and the second semiconductor layer 116 may be a p-type gallium nitride layer (p-GaN). The structure of the light-emitting layer 114 may be a multiple quantum well structure formed by alternating multiple layers of indium gallium nitride (InGaN) and multiple layers of gallium nitride (GaN).

[0091] In an implementation where the undoped semiconductor layer 112A is omitted, the doped semiconductor layer 112B may be a P-type gallium phosphide (GaP) layer, and the second semiconductor layer 116 may be an N-type aluminum gallium indium phosphide (AlGaInP) layer.

[0092] The LED wafer 110 further includes electrodes 118. The electrodes 118 include a first electrode 118A and a second electrode 118B, which respectively contact the first semiconductor layer 112 and the second semiconductor layer 116 in the LED wafer 110. The electrodes 118 include any suitable conductive material, such as a metal oxide (i.e., indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), etc.), a metal (i.e., titanium (Ti), nickel (Ni), aluminum (Al), gold (Au), platinum (Pt), chromium (Cr), silver (Ag), copper (Cu), etc.), or a metal alloy.

[0093] The first insulating layer 130 is disposed on the first surface S1 and a portion of the sidewall W of the light-emitting diode chip 110. Specifically, the first insulating layer 130 may cover the first surface S1 and a portion of the sidewall W of the first semiconductor layer 112, the light-emitting layer 114, and the second semiconductor layer 116, thereby providing electrical isolation, protection, or light reflection. Furthermore, the first insulating layer 130 only covers a portion of the electrode 118 to facilitate the subsequent formation of the electrical connection pad 120 on the electrode 118 for electrical connection. The material of the first insulating layer 130 may include silicon oxide (SiO2), aluminum oxide (Al2O3), titanium dioxide (TiO2), hafnium dioxide (HfO2), silicon nitride (Si3N4), or a stacked combination of two materials with different refractive indices, but the present disclosure is not limited to the above list.

[0094] The electrical connection pads 120 are disposed on the first surface S1 and include a first electrical connection pad 120A and a second electrical connection pad 120B separated from each other. Specifically, the electrical connection pads 120 contact the first surface S1 and protrude from the first insulating layer 130. In some embodiments, a portion of the electrical connection pads 120 is disposed on the first insulating layer 130. Depending on the product design, the first electrical connection pads 120A and the second electrical connection pads 120B contact the corresponding first electrodes 118A and second electrodes 118B, respectively, to electrically connect the first semiconductor layer 112 and the second semiconductor layer 116 of the LED chip 110. The electrical connection pads 120 may include aluminum, copper, nickel, gold, platinum, titanium, or other suitable metals, or combinations thereof.

[0095] The second insulating layer 140 is disposed on the second surface S2 and the sidewall W. In some embodiments, the second insulating layer 140 disposed on the sidewall W may partially overlap with the first insulating layer 130 (not shown). In some embodiments, the second insulating layer 140 is disposed on another portion of the sidewall W relative to the first insulating layer 130, such as Figure 1B shown.

[0096] The second insulating layer 140 includes a covering portion 142 and a plurality of protrusions 144. The covering portion 142 completely covers the second surface S2 and covers another portion of the sidewall W (e.g., length L1). The protrusions 144 are disposed on the sidewall W, protruding from the covering portion 142 and extending laterally (e.g., parallel to the X-axis). The protrusions 144 may surround the LED chip 110. In other words, the protrusions 144 may be disposed on the sidewalls W1, W2, W3, and W4.

[0097] In some embodiments, the thickness T1 of the coating portion 142 is between approximately 0.5 microns and approximately 2.0 microns. When the thickness T1 is less than the aforementioned lower limit, electrical insulation cannot be provided. When the thickness T1 is greater than the aforementioned upper limit, the light extraction efficiency from the second surface S2 may be affected. In some embodiments, the thickness T2 of the protrusion 144 is between approximately 0.5 microns and approximately 2.0 microns. In some embodiments, the thickness T1 of the coating portion 142 is substantially the same as the thickness T2 of the protrusion 144.

[0098] The protrusion length D1 of each protrusion 144 is the distance from the outer surface of the first insulating layer 130 to the end point of the protrusion 114. In some embodiments, the protrusion length D1 of each protrusion 144 is at least approximately 0.5 microns. In some embodiments, the protrusion length D1 of at least one of the protrusions 144 is between approximately 1 and approximately 10 times the thickness T2 of the covering portion 142. For example, when the thickness T2 of the covering portion 142 is between approximately 0.5 microns and approximately 2.0 microns, the protrusion length D1 of at least one of the protrusions 144 may be between approximately 0.5 microns and approximately 20 microns.

[0099] Since the material properties of the first insulating layer 130 and the second insulating layer 140 vary depending on the process environment (even if the first insulating layer 130 and the second insulating layer 140 are made of the same material in some embodiments), there is a risk of cracking between the first insulating layer 130 and the second insulating layer 140, for example Figure 11 The force applied during the bonding process may cause cracking of the first insulating layer 130 and the second insulating layer 140. Therefore, the possibility of such cracking can be avoided by forming the protrusion length D1 to have at least about 0.5 microns, thereby helping to improve the reliability of the light emitting device 100 manufacturing process.

[0100] The protrusion 144 has opposing third and fourth surfaces S3 and S4, while the covering portion 142 has opposing fifth and sixth surfaces S5 and S6. Taking the first surface S1 of the LED chip 110 as a reference, the third surface S3 of the protrusion 144 is closer to the first surface S1 than the fourth surface S4, while the fifth surface S5 of the covering portion 142 is closer to the first surface S1 than the sixth surface S6. In some embodiments, the fifth surface S5 of the covering portion 142 physically contacts the second surface S2 of the LED chip 110.

[0101] The protrusion 144 is located closer to the first surface S1 of the LED chip 110 than the covering portion 142. In other words, the third surface S3 and the fourth surface S4 of the protrusion 144 are located between the first surface S1 of the LED chip 110 and the sixth surface S6 of the covering portion 142.

[0102] The protrusion 144 is further described. In some embodiments, the third surface S3 of the protrusion 144 is located between the first surface S1 and the second surface S2 of the LED chip 110. The distance between the third surface S3 of the protrusion 144 and the second surface S2 of the LED chip 110 is a length L1. In some embodiments, the length L1 may be within a range of approximately 0.1 micrometers to approximately 4.5 micrometers. In further embodiments, the length L1 may be within a range of approximately 0.2 micrometers to approximately 1.0 micrometers. Alternatively, the ratio of the length L1 to the thickness T3 of the LED chip 110 may be within a range of approximately 0.02 to approximately 0.90. In further embodiments, the ratio of the length L1 to the thickness T3 of the LED chip 110 may be within a range of approximately 0.04 to approximately 0.20.

[0103] It should be noted that the length L1 is not only the distance between the third surface S3 of the protrusion 144 and the second surface S2 of the LED chip 110 , but also substantially the length of the covering portion 142 disposed on the sidewall W.

[0104] On the other hand, the fourth surface S4 of the protrusion 144 is located between the first surface S1 of the LED chip 110 and the sixth surface S6 of the cladding portion 142. The distance between the fourth surface S4 of the protrusion 144 and the sixth surface S6 of the cladding portion 142 is a length L2. In some embodiments, the length L2 may be within a range of approximately 0.1 micrometers to approximately 4.5 micrometers. In further embodiments, the length L2 may be within a range of approximately 0.2 micrometers to approximately 1.0 micrometers. Alternatively, the ratio of the length L2 to the thickness T3 of the LED chip 110 may be within a range of approximately 0.02 to approximately 0.90. In further embodiments, the ratio of the length L2 to the thickness T3 of the LED chip 110 may be within a range of approximately 0.04 to approximately 0.20. In some embodiments, the length L2 is substantially equal to the length L1.

[0105] The material of the second insulating layer 140 may include a dielectric material such as silicon oxide, aluminum oxide, titanium dioxide, hafnium dioxide, silicon nitride, other suitable materials, or combinations thereof. In some embodiments, the first insulating layer 130 and the second insulating layer 140 may be made of different materials. In some embodiments, the first insulating layer 130 and the second insulating layer 140 may be made of the same material. In some embodiments, the second insulating layer 140 may be made of silicon oxide.

[0106] Please also refer to Figure 1A and Figure 1C , Figure 1A To illustrate a top view of a light emitting device 100 according to some embodiments of the present disclosure, Figure 1C According to some embodiments of the present disclosure, the light emitting device 100 is shown along Figure 1A Cross-sectional view along section line BB.

[0107] In some embodiments, the plurality of protrusions 144 may be disposed on different sidewalls W and have different protrusion lengths. In other words, the protrusion lengths of at least two of the protrusions 144 are different from each other. In some embodiments, the protrusion lengths of at least two of the protrusions 144 differ by at least about 1 micron.

[0108] For example, if Figure 1A and Figure 1C In the illustrated embodiment, the protrusion 144B on the sidewall W4 has a protrusion length D2, and the protrusion 114A on the sidewall W2 has a protrusion length D1, wherein the protrusion length D2 on the sidewall W4 is greater than the protrusion length D1 on the sidewall W2 by at least about 1 micron. It should be noted that Figure 1C The protrusion length D1 shown is substantially Figure 1B The protruding length D1.

[0109] In embodiments where the protrusion 144B has a longer protrusion length D2, the protrusion length D2 of the protrusion 144B is between about 1 and about 10 times the thickness T1 of the covering portion 142. For example, when the thickness T1 of the covering portion 142 is between about 0.5 micrometers and about 2.0 micrometers, the protrusion length D2 of the protrusion 144B may be between about 0.5 micrometers and about 20 micrometers.

[0110] The protrusion 144B with the longer protrusion length D2 can function as a cantilever in the process of forming the light emitting device 100 (eg Figure 14 The protrusion length D2 of the protrusion 144B can be substantially the length of the cantilever. Figure 14 During the operation of pressing the light-emitting device 100 to break the protrusion 144B, if the protrusion length D2 is too short (e.g., less than 0.5 microns), the pressing torque is too small to generate sufficient force to break the protrusion 144B. If the protrusion length D2 is too long (e.g., greater than 20 microns), the pressing torque is too large, causing the light-emitting device 100 to deviate from the intended resting position. Therefore, setting an appropriate protrusion length D2 can help improve the reliability of the light-emitting device 100 manufacturing process.

[0111] The difference between the protrusion 144B located on the sidewall W4 and the protrusion 144A located on the sidewall W2 is only the sidewall location and length. Other features, such as the third surface S3 and thickness T2, are substantially the same.

[0112] Figures 2 to 16 To illustrate the cross-sectional views of the light emitting device 100 at different process stages according to some embodiments of the present disclosure, the cross-sectional positions are referenced to Figure 1A Section line BB.

[0113] It should be noted that when Figures 2 to 16 When depicted or described as a series of operations or events, the order in which these operations or events are described should not be limited. For example, some operations or events may be performed in a different order than that disclosed herein, some operations or events may occur simultaneously, some operations or events may not be required, and / or some operations or events may be repeated. Furthermore, the actual process may require additional steps before, during, or after forming the light-emitting element 100 to fully form the light-emitting element 100. Therefore, the present disclosure may briefly describe some of these additional steps. Furthermore, unless otherwise stated, Figures 1A to 16 The same instructions discussed can be directly applied to other images.

[0114] Please refer to Figure 2 First, a substrate 200 is prepared. A light-emitting diode material 110A is formed on the substrate 200. The substrate 200 contacts the eighth surface S8 of the light-emitting diode material 110A. The surface morphology of the eighth surface S8 depends on the surface morphology of the substrate 200 (discussed later). Figure 2 In the embodiment shown, the eighth surface S8 is shown as a rough texture, but the present disclosure is not limited to the rough texture. In some other embodiments, the eighth surface S8 may be a plane.

[0115] The LED material 110A is a multi-layer structure, including the aforementioned material for the first semiconductor layer 112 (not shown), the aforementioned material for the light-emitting layer 114 (not shown), and the aforementioned material for the second semiconductor layer 116 (not shown). To clearly illustrate the subsequent manufacturing processes, the multi-layer structure of the LED chip 110 is simplified and omitted in the following figures.

[0116] The substrate 200 may include a sapphire substrate, a gallium nitride substrate, an aluminum nitride substrate, a silicon substrate, a gallium arsenide substrate, a silicon carbide substrate, or other suitable substrate materials. In some embodiments, the substrate 200 may be a growth substrate for forming the LED wafer 110. In this embodiment, the substrate 200 is typically a sapphire substrate. When the substrate 200 is a growth substrate, the surface morphology of the substrate 200 may be planar or rough. The surface (e.g., the eighth surface S8) on which the LED material 110A is formed may have a surface morphology similar to that of the substrate 200.

[0117] Please refer to Figure 3 Then, a patterned LED material 110B is formed. The LED material 110A is subjected to a patterning process to remove a portion of the LED material 110A, thereby forming the patterned LED material 110B. The patterned LED material 110B has a LED wafer topography 110P, such as a first surface S1 and a sidewall W (at Figure 3 The viewing angle is the sidewall W2 and the sidewall W4). In addition, the patterned LED material 110B further includes an anchor morphology 700P connected to the LED chip morphology 110P. The LED chip morphology 110P is the previous stage of the LED chip 110, and the anchor morphology 700P is the anchor 700 ( Figure 7 ) stage before.

[0118] The anchor feature 700P is adjacent to at least two LED wafer features 110P. Figure 3 From the perspective of FIG, anchor feature 700P is adjacent to two LED chip features 110P. A third length L3 is separated from one of the two LED chip features 110P and anchor feature 700P. This third length L3 depends on product design and process conditions. Generally speaking, third length L3 should be sufficient to ensure that the final light-emitting device 100 has the aforementioned protrusion length D2. In other words, third length L3, like the previous stage of protrusion length D2, can affect the actual length of protrusion length D2.

[0119] Please refer to Figure 4 Then, a first insulating layer 130 and an electrical connection pad 120 are formed on the light-emitting diode wafer topography 110P.

[0120] The formation of the first insulating layer 130 may include a deposition process, a patterning process, an etching process, other suitable processes, or a combination thereof. The deposition process may include chemical vapor deposition, printing, coating, or other suitable techniques. For example, a first insulating layer material (not shown) is first conformally deposited onto the patterned LED material 110B, then a portion of the first insulating layer material is removed through a patterned mask, and finally, the first insulating layer 130 is formed on the LED wafer topography 110P.

[0121] After forming the first insulating layer 130, the electrical connection pads 120 are then formed. The electrical connection pads 120 can be formed using a method similar to that used to form the first insulating layer 130, which may include a deposition process, a patterning process, an etching process, other suitable processes, or a combination thereof. The deposition process may include sputtering, evaporation, electroplating, or other suitable techniques.

[0122] Please refer to Figure 5 Next, a first adhesive layer 510 and a first carrier substrate 520 are formed on the patterned LED material 110B. Thus, the first adhesive layer 510 is formed between the first carrier substrate 520 and the patterned LED material 110B, and the first carrier substrate 520 can be bonded to the patterned LED material 110B via the first adhesive layer 510.

[0123] In some embodiments, the material of the first adhesive layer 510 has a different etching selectivity than the light-emitting diode material 110B. For example, in a subsequent removal process (e.g., Figure 7 ), the removal rate of the first adhesive layer 510 can be greater than the removal rate of the LED material 110B. Consequently, after the removal process, a height difference can be created between the first adhesive layer 510 and the LED material 110B. The first adhesive layer 510 can include benzocyclobutene (BCB), epoxy, silicone, polyimide (PI), acrylic resin (poly(methyl 2-methylpropenoate) PMMA), or other suitable adhesive materials, but the present disclosure is not limited thereto. In some embodiments, the first adhesive layer 510 is benzocyclobutene. The first carrier substrate 520 can include a glass substrate, a silicon substrate, a sapphire substrate, or other types of substrates.

[0124] Please refer to Figure 6 Then, the substrate 200 is removed. After the substrate 200 is removed, the eighth surface S8 is exposed. It should be noted that Figure 6 The structure is Figure 5 In some embodiments, the substrate 200 may be removed by any suitable method, such as laser lift-off (LLO), grinding, or etching.

[0125] Please refer to Figure 7 Then, a portion of the patterned LED material 110B and a portion of the first adhesive layer 510 are removed.

[0126] Specifically, a portion of the patterned LED material 110B is removed from the eighth surface S8, disconnecting and disjointing the previously connected LED chip features 110P and anchor features 700P, thereby forming separate (non-contacting) LED chips 110 and anchors 700. After the removal, the LED chip 110 has a second surface S2. In some embodiments, the second surface S2 maintains a surface topography similar to that of the eighth surface S8, such as maintaining a similar planar surface or a similarly rough surface. In some embodiments, when the eighth surface S8 has a planar surface topography, leaving the second surface S2 similarly planar, the second surface S2 may be roughened to impart a rough texture to the second surface S2.

[0127] The removal process may include an etching process or other suitable process. Etching methods may include dry etching, wet etching, and / or other suitable processes. In some embodiments, a dry etching process such as inductively coupled plasma (ICP) or reactive ion etching (RIE) is used. In further embodiments, in order to create a difference in etching rate between the first adhesion layer 510 and the LED material 110B, in addition to material selection, the dry etching process may use a process method with chemical etching characteristics.

[0128] Because in the embodiments of the present disclosure, the etchant used in the removal process and the material with a larger etching selectivity relative to the light-emitting diode material 110B are selected to form the first adhesive layer 510, the combination of the above-mentioned etchant and material makes the first adhesive layer 510 more responsive to the removal process than the patterned light-emitting diode material 110B. In some embodiments, after the removal process, the second surface S2 of the light-emitting diode chip 110 and the seventh surface S7 of the first adhesive layer 510 are non-coplanar. In other words, the second surface S2 of the light-emitting diode chip 110 and the seventh surface S7 of the first adhesive layer 510 have a height difference (for example, a length L4). In some embodiments, the length L4 is substantially equal to the length L1 (see Figure 1B The height difference (e.g., length L4) is determined in the subsequent process ( Figure 14 ) can help to cantilever ( Figure 14 The breaking point of the cantilever 1304) is controlled to be close to the anchoring part ( Figure 14The anchor portion 1306 is located at the edge of the breakpoint. Controlling the breakpoint location can improve process reliability. If the breakpoint is close to the LED chip 110, the subsequently formed insulating layer 140 may crack and fail to cover the LED chip 110 as expected. If the insulating layer 140 cracks, environmental impurities (e.g., moisture) may enter the LED chip 110, causing degradation of the LED chip 110. Therefore, by controlling the breakpoint location away from the LED chip 110 (e.g., controlling the breakpoint close to the anchor portion as described above), process reliability is improved.

[0129] Please refer to Figure 8 Next, a second insulating layer material 140A is deposited on the LED wafer 110, the anchor 700, and the first adhesive layer 510. In some embodiments, the second insulating layer material 140A conformally covers the LED wafer 110, the anchor 700, and the first adhesive layer 510. The second insulating layer material 140A can be deposited using chemical vapor deposition, printing, coating, or other suitable techniques.

[0130] Please refer to Figure 9 Then, a second insulating layer 140 is formed. A patterning process is performed on the second insulating layer material 140A to remove a portion of the second insulating layer material 140A, thereby forming the second insulating layer 140. Figure 9 In the illustrated embodiment, the second insulating layer 140 includes a covering portion 142 , a protruding portion 144 , and an interface layer 146 , wherein the interface layer 146 is disposed on the anchor 700 .

[0131] Protrusion 144 includes protrusion 144A and protrusion 144B, wherein protrusion 144B connects to and contacts LED chip 110 and anchor 700. The protrusion length of protrusion 144A can be adjusted by controlling the patterning process, such as using an appropriate mask. In some embodiments, protrusion 144A has the aforementioned protrusion length D1.

[0132] Please refer to Figure 10 Then, a sacrificial layer 1000 is formed on the first adhesive layer 510. Specifically, the sacrificial layer 1000 covers Figure 9 structure, but at least a portion of the interface layer 146 is exposed to form an opening 1002.

[0133] The sacrificial layer 1000 may be formed using a deposition process, a patterning process, an etching process, other suitable processes, or a combination thereof. In some embodiments, the sacrificial layer 1000 may include an organic material, such as benzocyclobutene (BCB), polyimide (PI), or the like.

[0134] Please refer to Figure 11Then, a support layer 1100 , a second adhesive layer 1110 and a second carrier substrate 1120 are sequentially formed on the sacrificial layer 1000 .

[0135] The support layer 1100 may include a base portion 1104 and a support frame 1102 protruding from the base portion 1104. Specifically, the support frame 1102 is filled in Figure 10 The support frame 1102 is disposed in the opening 1002 and contacts the interface layer 146. In some embodiments, the support frame 1102 may be a cylindrical or polygonal column. In some embodiments, the support layer 1100 may comprise an insulating material, a metallic material, or other supporting material. For example, insulating materials include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and epoxy resin; metallic materials include, but are not limited to, aluminum, titanium, gold, platinum, chromium, or nickel.

[0136] A second adhesive layer 1110 is formed between the support layer 1100 and the second carrier substrate 1120. The second carrier substrate 1120 can be bonded to the support layer 1100 via the second adhesive layer 1110. The second adhesive layer 1110 can include benzocyclobutene, epoxy resin, silicone resin, polyimide, acrylic resin, or other suitable adhesive materials, but the present disclosure is not limited thereto. The second carrier substrate 1120 can include a glass substrate, a silicon substrate, a sapphire substrate, a thin film transistor substrate, or other types of substrates.

[0137] Please refer to Figure 12 , then, remove the first adhesive layer 510 and the first carrier substrate 520. After removing the first adhesive layer 510 and the first carrier substrate 520, the electrical connection pads 120 and the first insulating layer 130 are exposed. It should be noted that, Figure 12 The structure is Figure 11 The result of flipping the structure upside down and mirroring it.

[0138] Please refer to Figure 13 Next, the sacrificial layer 1000 is removed. Removing the sacrificial layer 1000 in contact with the support frame 1102 allows the light-emitting element 100 to be supported by the support frame 1102 and separated from the base portion 1104. In other words, after removing the sacrificial layer 1000, a portion of the support frame 1102 is exposed, and the light-emitting element 100 is suspended on the base portion 1104 via the support frame 1102 and the second insulating layer 140. In some embodiments, the space left after the sacrificial layer 1000 is removed is sufficient to allow the light-emitting element 100 to be broken and separated from the support frame 1102 during subsequent processing.

[0139] During this stage of the manufacturing process, the second insulating layer 140 can also serve as a tether structure 1300 to provide support for the light-emitting element 100. The encapsulating portion 142 disposed on the second surface S2 serves as the device portion 1302 of the cantilever structure 1300; the longer protruding portion 144B serves as the cantilever 1304 of the cantilever structure 1300; and the interface layer 146 between the support frame 1102 and the anchor 700 serves as the anchor portion 1306 of the cantilever structure 1300.

[0140] In some embodiments, the sacrificial layer 1000 can be removed by any suitable method, such as using wet etching. In some embodiments, the sacrificial layer 1000 is removed using selective etching.

[0141] Please refer to Figure 14 Then, the picking member 1400 presses the plurality of light emitting devices 100 in a direction (eg, direction 1410 ) approaching the second carrier substrate 1120 .

[0142] After being pressed by the capture member 1400, the cantilever 1304 of the cantilever structure 1300 breaks, thereby separating the light-emitting device 100 from the anchor portion 1306 of the cantilever structure 1300. In some embodiments, the fracture surface of the cantilever 1304 is adjacent to the sidewall of the anchor 700, and the broken cantilever 1304 becomes the protrusion 144B of the light-emitting device 100. In some embodiments, the length of the cantilever 1304 is substantially the same as the protrusion length D2 of the protrusion 144B.

[0143] In some embodiments, the capture member 1400 may include polydimethylsiloxane (PDMS). The capture member 1400 may have a plurality of capture ends 1402, and the surface of each capture end 1402 is adhesive, so that the light-emitting element 100 can be temporarily fixed on the surface of the capture end 1402. The capture ends 1402 may be arranged in an array, that is, these capture ends 312 can be aligned one-to-one with multiple light-emitting elements 100. In some embodiments, the capture member 1400 can capture all light-emitting elements 100. In some embodiments, the capture member 1400 can selectively capture part of the light-emitting element 100, for example, Figure 14 In the embodiment, the picking member 1400 selectively picks up two of the light emitting elements 100. In some other embodiments, the picking member 1400 may also be a vacuum picking member having a plurality of vacuum suction members, so each picking end 1402 is also a vacuum suction member.

[0144] Please refer to Figure 15Then, when the capturing member 1400 moves away from the second carrier substrate 1120 (eg, direction 1510 ), the captured light-emitting element 100 moves along with the capturing member 1400 and away from the second carrier substrate 1120 .

[0145] Please refer to Figure 16 Next, the capture element 1400 is moved to the third carrier substrate 1620, and the light-emitting elements 100 are placed on the third carrier substrate 1620. In subsequent manufacturing processes, the light-emitting elements 100 are further disposed on the third carrier substrate 1620. The third carrier substrate 1620 may include a glass substrate, a silicon substrate, a sapphire substrate, a thin-film transistor substrate, or other types of substrates. In some embodiments, the third carrier substrate 1620 may be a thin-film transistor substrate. In some embodiments, the light-emitting elements 100 are arrayed on the thin-film transistor substrate to form the display device 1600.

[0146] This disclosure provides a light-emitting device structure in which an insulating layer completely covers the semiconductor surface of the light-emitting diode chip within the light-emitting device, providing more complete protection and electrical isolation for the light-emitting device, thereby improving the quality of the light-emitting device. Furthermore, the structural design of the insulating layer, such as the formation of protrusions and control of the protrusion length, can help improve the reliability of the light-emitting device manufacturing process.

[0147] The above briefly describes the features of several embodiments of the present disclosure, making it easier for those skilled in the art to understand the present disclosure. Anyone skilled in the art will appreciate that this description can readily serve as a basis for modifying or designing other structures or processes to achieve the same objectives and / or advantages as the embodiments of the present disclosure. Anyone skilled in the art will also appreciate that equivalent structures to those described above do not depart from the spirit and scope of protection of the present disclosure, and that modifications, substitutions, and alterations are possible without departing from the spirit and scope of the present disclosure.

Claims

1. A light-emitting element, characterized in that: include: A light emitting diode chip having a first surface and a second surface opposite to each other, and a plurality of sidewalls connecting the first surface and the second surface; an insulating structure covering the first surface, the second surface and the plurality of sidewalls; as well as an electrical connection pad located on the first surface; The insulating structure includes: a covering portion covering a portion of the plurality of side walls; and a plurality of protrusions disposed on the plurality of side walls, the plurality of protrusions protruding from the covering portion and extending laterally; Protrusion lengths of at least two of the plurality of protrusions are different from each other.

2. The light-emitting element according to claim 1, wherein The insulating structure includes a stacked combination of two insulating materials with different refractive indices.

3. The light-emitting element according to claim 1, wherein The plurality of side walls include a first portion and a second portion. The first portion is closer to the first surface than the second portion. The plurality of protrusions protrude outward from the second portion.

4. The light-emitting element according to claim 3, wherein The light emitting diode chip comprises an undoped semiconductor layer, a first doped semiconductor layer, a light emitting layer and a second doped semiconductor layer stacked in sequence; The first portion includes a portion of a side wall of the undoped semiconductor layer.

5. The light-emitting element according to claim 4, wherein The second portion includes another portion of the sidewall of the undoped semiconductor layer.

6. The light-emitting element according to claim 1, wherein The protrusions have a protrusion length of at least 0.5 micrometers.

7. The light-emitting element according to claim 1, wherein The plurality of protrusions have a third surface and a fourth surface opposite to each other. The third surface is closer to the first surface of the LED chip than the fourth surface. The third surface is located between the first surface and the second surface of the LED chip.

8. The light-emitting element according to claim 7, wherein The covering portion has a fifth surface and a sixth surface opposite to each other. The fifth surface contacts the second surface of the LED chip, wherein the fourth surface of the plurality of protrusions is located between the first surface of the LED chip and the sixth surface of the covering portion.

9. The light-emitting element according to claim 1, wherein The second surface of the light emitting diode chip is a rough surface.

10. A display device, characterized in that: include: a carrier substrate; as well as A plurality of light-emitting elements according to any one of claims 1 to 9, wherein the light-emitting elements are disposed on the carrier substrate.

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