Multilayer ceramic capacitor and method for manufacturing multilayer ceramic capacitor

Abstract

The present invention can suppress a decrease in effective capacitance in a capacitor including an intermediate layer containing Fe. A capacitor according to one embodiment of the present invention includes a main body, a first external electrode provided in the main body, and a second external electrode provided in the main body. The main body has: a first internal electrode layer containing Fe at a first concentration; a second internal electrode layer; a dielectric layer disposed between the first internal electrode layer and the second internal electrode layer in the first direction; and a first intermediate layer provided between the first internal electrode layer and the dielectric layer and containing Fe at a second concentration. The first external electrode is electrically connected to the first internal electrode layer, and the second external electrode is electrically connected to the second internal electrode layer. The first external electrode includes an Ni plating layer. The first concentration is 0.01 at% or more. The second concentration is 3 times or more and 2 at% or less of the first concentration.

Description

Technical Field

[0001] Cross-reference This application claims priority based on Japanese Patent Application No. 2023-042031 (filed on March 16, 2023), the contents of which are incorporated herein by reference in their entirety.

[0002] The invention disclosed in this specification mainly relates to a laminated ceramic capacitor and a method for manufacturing the laminated ceramic capacitor. The disclosure in this specification also relates to a circuit assembly including the laminated ceramic capacitor and an electronic device including the circuit assembly. Background Art

[0003] As electronic devices become increasingly miniaturized, the multilayer ceramic capacitors used in these devices are required to increase their capacitance without increasing their size. A multilayer ceramic capacitor has a capacitance generating portion consisting of a dielectric layer and internal electrode layers sandwiching the dielectric layer. By thinning the dielectric layer, the capacitance can be increased without increasing the size of the capacitor.

[0004] However, when the dielectric layer is made thinner, the insulation reliability of the capacitor may be reduced. Therefore, it has been proposed to provide an intermediate layer containing a trace amount of metal elements between the dielectric layer and the internal electrode layer, using this intermediate layer to improve the Schottky barrier between the dielectric layer and the internal electrode layer, thereby improving the insulation reliability of the capacitor. For example, Japanese Patent Publication No. 2017-5021 (Patent Document 1) describes adding a metal element to the internal electrode layer so that the added metal element is present at a higher ratio at the interface between the internal electrode layer and the dielectric layer than in the central region in the thickness direction of the internal electrode layer. The publication describes that by adding the metal element preferentially at the interface between the internal electrode layer and the dielectric layer, alloying of Ni, the main component of the internal electrode layer, with the added metal element occurs at this interface, thereby improving the insulation reliability of the capacitor. As added metal elements for improving the Schottky barrier between the dielectric layer and the internal electrode layer, Fe, V, Y, and Cu are listed in Patent Document 1.

[0005] Prior art literature Patent Literature Patent Document 1: Japanese Patent Application Laid-Open No. 2017-005021 Summary of the Invention

[0006] Technical problem to be solved by the invention When an intermediate layer containing Fe is formed between the dielectric layer and the internal electrode layer, Fe is easily mixed into the interior of the dielectric layer. This poses a problem in that the Fe contained in the dielectric layer reduces the effective capacitance of the capacitor.

[0007] By reducing the amount of Fe added to the raw materials, it is expected that the proportion of Fe within the dielectric layer will be reduced, thereby suppressing the decrease in effective capacitance. However, when the amount of Fe added to the raw materials is reduced, there is a possibility that the Schottky barrier formed between the dielectric layer and the internal electrode layer may not be sufficiently enhanced, resulting in a decrease in the insulation reliability of the capacitor.

[0008] The invention disclosed in this specification aims to solve or alleviate at least part of the above-mentioned problems. One of the more specific objects of the invention disclosed in this specification is to suppress the reduction of effective capacitance in a capacitor having an intermediate layer containing Fe. One of the more specific objects of the invention disclosed in this specification is to achieve both excellent effective capacitance and excellent insulation reliability in a capacitor. The various inventions disclosed in this specification are sometimes collectively referred to as the "present invention."

[0009] The invention's objectives other than those described above will become clear from the entire specification. The invention disclosed in this specification may also address technical problems beyond those described in the "Technical Problems to be Solved by the Invention" section. When the description of the effects of an embodiment is provided in this specification, the technical problem of the invention corresponding to that embodiment can be understood from those effects.

[0010] Means for solving technical problems A capacitor according to one embodiment of the present invention includes a body, a first external electrode disposed on the body, and a second external electrode disposed on the body. The body includes a first internal electrode layer containing Fe at a first concentration, a second internal electrode layer, a dielectric layer disposed between the first and second internal electrode layers in a first direction, and a first intermediate layer disposed between the first and second internal electrode layers and containing Fe at a second concentration. The first external electrode is electrically connected to the first internal electrode layer, and the second external electrode is electrically connected to the second internal electrode layer. The first external electrode includes a Ni plating layer. The first concentration is 0.01 at% or greater. The second concentration is 3 times or greater than the first concentration and 2 at% or less.

[0011] Effects of the Invention According to one embodiment of the invention disclosed in this specification, a decrease in effective capacitance can be suppressed in a capacitor having an intermediate layer containing Fe. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a perspective view schematically showing a capacitor according to one embodiment of the present invention.

[0013] Figure 2 It schematically indicates that Figure 1 This is a cross-sectional view of a capacitor cut along line II.

[0014] Figure 3 It will Figure 2 An enlarged cross-sectional view showing an enlarged portion of the cross section (region A).

[0015] Figure 4 It will Figure 2 An enlarged cross-sectional view showing an enlarged portion of the cross section (region B).

[0016] Figure 5 This is an example of a line profile obtained through EDS mapping.

[0017] Figure 6 This is a flowchart showing the flow of a method for manufacturing a capacitor according to one embodiment of the present invention. DETAILED DESCRIPTION

[0018] Below, various embodiments of the present invention will be described with appropriate reference to the accompanying drawings. For the same components in multiple drawings, the same or similar reference figures are marked in the multiple drawings. It should be noted that, for the sake of convenience of explanation, the drawings are not necessarily recorded to an accurate scale. The embodiments described below do not necessarily limit the technical solutions in the claims. The various elements described in the following embodiments are not necessarily necessary for the solution of the technical solution.

[0019] For convenience of explanation, the drawings may sometimes depict mutually orthogonal L-axis, W-axis, and T-axis. In this specification, the dimensions, arrangement, shape, and other features of the components of the multilayer ceramic capacitor 1 are sometimes described with reference to the L-axis, W-axis, and T-axis.

[0020] 1 Multilayer Ceramic Capacitor 1 1-1 Basic Structure of Multilayer Ceramic Capacitors Reference Figure 1 and Figure 2 , the basic structure of the multilayer ceramic capacitor 1 according to the first embodiment will be described. Figure 1 It is a perspective view of the multilayer ceramic capacitor 1 according to the first embodiment. Figure 2 This is a cross-sectional view schematically showing a cross section of the multilayer ceramic capacitor 1 cut along line II.

[0021] The multilayer ceramic capacitor 1 includes a main body 10 and a first external electrode 31 and a second external electrode 32 provided on the main body 10. The first external electrode 31 and the second external electrode 32 are arranged with a gap therebetween. Figure 2 In the illustrated example, the first external electrode 31 is arranged spaced apart from the second external electrode 32 in the L-axis direction.

[0022] The body 10 has an upper surface 10a, a lower surface 10b, a first end surface 10c, a second end surface 10d, a first side surface 10e, and a second side surface 10f. The outer surface of the body 10 is defined by the upper surface 10a, the lower surface 10b, the first end surface 10c, the second end surface 10d, the first side surface 10e, and the second side surface 10f.

[0023] The upper surface 10a and the lower surface 10b respectively form the ends of the main body 10 in the height direction (T-axis direction). In other words, the upper surface 10a and the lower surface 10b face each other in the T-axis direction. The first end surface 10c and the second end surface 10d respectively form the ends of the main body 10 in the length direction (L-axis direction). In other words, the first end surface 10c and the second end surface 10d face each other in the L-axis direction. The first side surface 10e and the second side surface 10f respectively form the ends of the main body 10 in the width direction (W-axis direction). In other words, the first side surface 10e and the second side surface 10f face each other in the W-axis direction. The upper surface 10a and the lower surface 10b separate the height dimension of the main body 10, the first end surface 10c and the second end surface 10d separate the length dimension of the main body 10, and the first side surface 10e and the second side surface 10f separate the width dimension of the main body 10.

[0024] The main body 10 includes a plurality of dielectric layers 11, a plurality of first internal electrode layers 21, and a plurality of second internal electrode layers 22. The main body 10 is constructed by stacking the dielectric layers 11, the first internal electrode layers 21, and the second internal electrode layers 22 along a stacking direction. In the illustrated embodiment, the dielectric layers 11, the first internal electrode layers 21, and the second internal electrode layers 22 are stacked along the T-axis. The stacking direction can be along the T-axis as shown, or along the L-axis or W-axis. The dielectric layers 11 arranged at both ends of the stacking direction among the plurality of dielectric layers 11 are sometimes referred to as cover layers. The dielectric layer 11 is arranged between the first internal electrode layer 21 and the second internal electrode layer 22 adjacent to the first internal electrode layer 21. In this specification, when it is not necessary to distinguish between the first internal electrode layer 21 and the second internal electrode layer 22, the first internal electrode layer 21 and the second internal electrode layer 22 are sometimes collectively referred to as "internal electrode layers."

[0025] In the illustrated embodiment, the main body 10 is constructed by stacking a dielectric layer 11, a first internal electrode layer 21, and a second internal electrode layer 22 along the T-axis. Therefore, the T-axis direction may also be referred to as the stacking direction. An upper cover layer 12 may be provided on the upper surface of the stack. A lower cover layer 13 may be provided on the lower surface of the stack. The upper cover layer 12 and the lower cover layer 13 may be made of the same material as the dielectric layer 11. The upper cover layer 12 and the lower cover layer 13 may also be part of the main body 10.

[0026] One end of the first internal electrode layer 21 is drawn out to the outside of the main body 10. The first internal electrode layer 21 is connected to a first external electrode 31 provided on the surface of the main body 10. One end of the second internal electrode layer 22 is drawn out to the outside of the main body 10. The second internal electrode layer 22 is connected to a second external electrode 32 provided on the surface of the main body 10. In the illustrated embodiment, the first internal electrode layer 21 is drawn out to the outside of the main body 10 from one end in the L-axis direction. The first internal electrode layer 21 is connected to the first external electrode 31 at one end in the L-axis direction of the main body 10. The second internal electrode layer 22 is drawn out to the outside of the main body 10 from the other end in the L-axis direction. The second internal electrode layer 22 is connected to the second external electrode 32 at the other end in the L-axis direction of the main body 10. In the illustrated embodiment, the first internal electrode layer 21 and the second internal electrode layer 22 are respectively extended to the opposing first end surface 10c and second end surface 10d. However, the first internal electrode layer 21 and the second internal electrode layer 22 can be extended from various surfaces of the main body 10 in accordance with the arrangement and shape of the first external electrode 31 and the second external electrode 32. For example, when the first external electrode 31 and the second external electrode 32 are both arranged on the lower surface 10b, the first external electrode 31 and the second external electrode 32 are both extended from the lower surface. The first external electrode 31 and the second external electrode 32 can be provided on any surface of the main body 10 as long as they are spaced apart from each other.

[0027] When a voltage is applied between the first external electrode 31 and the second external electrode 32 , electrostatic capacitance is generated between the first internal electrode layer 21 and the second internal electrode layer 22 .

[0028] As will be described later, a first intermediate layer 41 containing Fe is disposed between the dielectric layer 11 and the first internal electrode layer 21, and a second intermediate layer 42 containing Fe is disposed between the dielectric layer 11 and the second internal electrode layer 22. Figure 1 and Figure 2 In the figure, the first intermediate layer 41 and the second intermediate layer 42 are omitted.

[0029] exist Figure 2 In the figure, five first internal electrode layers 21 and five second internal electrode layers 22 are shown for simplicity. However, the multilayer ceramic capacitor 1 can have any number of layers. For example, it can include 300 to 1000 first internal electrode layers 21 and second internal electrode layers 22. In other words, the multilayer ceramic capacitor 1 can have 300 to 1000 layers.

[0030] The multilayer ceramic capacitor 1 can be mounted on an electronic circuit board. An electronic circuit board equipped with the multilayer ceramic capacitor 1 is sometimes referred to as a circuit assembly. Various electronic components other than the multilayer ceramic capacitor 1 may also be mounted in the circuit assembly. This circuit assembly can be mounted in various electronic devices. Electronic devices that can be equipped with the circuit assembly include smartphones, tablet computers, game consoles, automotive electrical components, servers, and various other electronic devices.

[0031] In one embodiment, the main body 10 may be configured to have a rectangular parallelepiped shape. In this specification, the term "rectangular parallelepiped" or "rectangular parallelepiped shape" does not necessarily refer to a "rectangular parallelepiped" in the strict mathematical sense. As described later, the corners and / or sides of the main body 10 may also be curved. The size and shape of the main body 10 are not limited to those explicitly described in this specification.

[0032] In one embodiment, the dimension (length) of the multilayer ceramic capacitor 1 in the L-axis direction is in the range of 0.2 mm to 2.5 mm, the dimension (width) in the W-axis direction is in the range of 0.1 mm to 3.5 mm, and the dimension (height) in the T-axis direction is in the range of 0.1 mm to 3.0 mm. In one embodiment, the length dimension of the multilayer ceramic capacitor 1 may be larger than the width dimension. In one embodiment, the height dimension of the multilayer ceramic capacitor 1 may be larger than the width dimension. In one embodiment, the width dimension of the multilayer ceramic capacitor 1 may be larger than the length dimension.

[0033] 1-2 Dielectric layer 11 Dielectric layer 11 contains an oxide represented by the chemical formula ABO3 as a main component. This oxide may have a perovskite structure. A component comprising 50% by weight or more of the total mass of dielectric layer 11 can be considered the main component of dielectric layer 11. When the oxide represented by the chemical formula ABO3 comprises 50% by weight or more of the dielectric layer 11, dielectric layer 11 can be said to contain the oxide represented by the chemical formula ABO3 as a main component. Dielectric layer 11 preferably contains 60% by weight or more, 70% by weight or more, 80% by weight or more, or 90% by weight or more of the oxide represented by the chemical formula ABO3.

[0034] In the chemical formula ABO3, "A" is at least one element selected from Ba (barium), Sr (strontium), Ca (calcium), and Mg (magnesium). In the chemical formula ABO3, "B" is at least one element selected from Ti (titanium), Zr (zirconium), and Hf (hafnium). When the oxide represented by the chemical formula ABO3 has a perovskite structure, elements "A" and "B" are located at the A and B sites of the perovskite structure, respectively. Examples of oxides primarily contained in dielectric layer 11 include BaTiO3 (barium titanate), CaZrO3 (calcium zirconate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), and MgTiO3 (magnesium titanate).

[0035] The oxide contained as a main component in the dielectric layer 11 may also be a material having the chemical formula Ba 1-x-y Ca x Sr y Ti 1- z Zr z An oxide represented by O3 (0≤x≤1, 0≤y≤1, 0≤z≤1). Examples of such oxides include barium strontium titanate, barium calcium titanate, barium zirconate, barium titanate zirconate, calcium titanate zirconate, and barium calcium titanate zirconate.

[0036] In addition to the oxide of the main component, dielectric layer 11 may also contain additive elements. In one embodiment, the additive element contained in dielectric layer 11 is at least one element selected from Fe (iron), Ni (nickel), Mo (molybdenum), Nb (niobium), Ta (tantalum), W (tungsten), Mg (magnesium), Mn (manganese), V (vanadium), and Cr (chromium). Dielectric layer 11 may contain two or more of the above additive elements.

[0037] In addition to the oxide of the main component, dielectric layer 11 may also contain an oxide of a rare earth element. The rare earth element oxide contained in dielectric layer 11 may be an oxide of at least one rare earth element selected from the group consisting of Y (yttrium), Sm (samarium), Eu (europium), Gd (gadolinium), Tb (terbium), Dy (dysprosium), Ho (holmium), Er (erbium), Tm (thulium), and Yb (ytterbium). Dielectric layer 11 may contain oxides of two or more rare earth elements.

[0038] The dielectric layer 11 may also contain other oxides. For example, the dielectric layer 11 may contain an oxide of at least one element selected from Co (cobalt), Ni (nickel), Li (lithium), B (boron), Na (sodium), K (potassium), and Si (silicon). The dielectric layer 11 may contain oxides of two or more of these elements.

[0039] The dielectric layer 11 may contain glass containing at least one element selected from the group consisting of Co, Ni, Li, B, Na, K, and Si.

[0040] In one embodiment, the film thickness (dimension in the T-axis direction) of the dielectric layer 11 is not less than 0.2 μm and not more than 10 μm.

[0041] 1-3 First internal electrode layer 21 and second internal electrode layer 22 In one embodiment, the first internal electrode layer 21 contains Ni (nickel) as a main component. A component comprising 50 wt% or more of the first internal electrode layer 21, based on the total mass of the first internal electrode layer 21, can be considered the main component of the first internal electrode layer 21. The first internal electrode layer 21 preferably contains 60 wt% or more, 70 wt% or more, 80 wt% or more, or 90 wt% or more of a base metal as a main component.

[0042] The first internal electrode layer 21 contains Fe in addition to Ni. In addition to Ni and Fe, the first internal electrode layer 21 may also contain accessory elements. Examples of accessory elements that may be included in the first internal electrode layer 21 include one or more elements selected from the group consisting of As (arsenic), Au (gold), Co, Cr, Cu, Fe, In (indium), Ir (iridium), Mg, Os (osmium), Pd (palladium), Pt (platinum), Re (rhenium), Rh (rhodium), Ru (ruthenium), Se (selenium), Sn, Ge (germanium), Te (tellurium), W, Y (yttrium), Zn (zinc), Ag (silver), and Mo.

[0043] The description about the composition of the first internal electrode layer 21 also applies to the composition of the second internal electrode layer 22 .

[0044] In one embodiment, the thickness (dimension in the T-axis direction) of the first internal electrode layer 21 and the thickness (dimension in the T-axis direction) of the second internal electrode layer 22 are both 0.1 μm or more and 2 μm or less. The description regarding the thickness of the first internal electrode layer 21 also applies to the second internal electrode layer 22.

[0045] 1-4 First external electrode 31 and second external electrode 32 In one embodiment, the first external electrode 31 and the second external electrode 32 can be formed by applying a conductive paste on the main body 10 and heating the conductive paste. The conductive paste can contain at least one substance selected from Ag, Pd, Au, Pt, Ni, Sn, Cu, W, Ti, and alloys thereof.

[0046] The first external electrode 31 may include a Ni plating layer. This Ni plating layer may be formed on the surface of the base electrode layer formed by heating the conductive paste using electrolytic plating or electroless plating. Similarly, the second external electrode 32 may include a Ni plating layer.

[0047] 1-5 First intermediate layer 41 and second intermediate layer 42 Next, refer to Figures 3 to 5 , the first intermediate layer 41 and the second intermediate layer 42 are described.

[0048] First, refer to Figure 3 The first intermediate layer 41 will be described. Figure 3 It will Figure 2 The figure shows an enlarged cross-sectional view of region A of the cross section of the main body 10. Region A encompasses one of the plurality of first internal electrode layers 21 included in the main body 10 and the dielectric layers 11 located above and below the first internal electrode layer 21. In other words, region A extends from the dielectric layer 11 located below the first internal electrode layer 21, through the first internal electrode layer 21, to the dielectric layer 11 located above the first internal electrode layer 21. As described above, the thickness t21 of the first internal electrode layer 21 can be between 0.1 μm and 2 μm.

[0049] As shown in the figure, a first intermediate layer 41 containing Fe is provided between the dielectric layer 11 and the first internal electrode layer 21. The first intermediate layer 41 can enhance the Schottky barrier formed between the dielectric layer 11 and the first internal electrode layer 21. Furthermore, by enhancing the Schottky barrier formed between the dielectric layer 11 and the first internal electrode layer 21, leakage current can be suppressed, resulting in improved insulation reliability of the multilayer ceramic capacitor 1. In other words, the life of the multilayer ceramic capacitor 1 can be extended.

[0050] Next, refer to Figure 4 The second intermediate layer 42 will be described. Figure 4 It will Figure 2 The enlarged cross-sectional view shown is an enlarged cross-sectional view showing a region B of the cross section of the main body 10. The region B is a region extending from the plurality of second internal electrode layers 22 included in the main body 10 to the dielectric layer 11 located thereunder.

[0051] As shown in the figure, a second intermediate layer 42 containing Fe is provided between the dielectric layer 11 and the second internal electrode layer 22. The second intermediate layer 42 can enhance the Schottky barrier formed between the dielectric layer 11 and the second internal electrode layer 22, thereby improving the insulation reliability of the multilayer ceramic capacitor 1.

[0052] The thickness (dimension in the stacking direction) t41 of the first intermediate layer 41 is, for example, not less than 0.2 nm and not more than 3.0 nm. The lower limit of the thickness t41 of the first intermediate layer 41 may be 0.3 nm, 0.4 nm, or 0.5 nm. The upper limit of the thickness t41 of the first intermediate layer 41 may be 2.0 nm, 1.5 nm, or 1.3 nm. The thickness t42 of the second intermediate layer 42 may be approximately the same as the thickness t41 of the first intermediate layer 41.

[0053] In the illustrated embodiment, the main body 10 includes a first intermediate layer 41 and a second intermediate layer 42. Therefore, the Schottky barrier can be improved in both the region between the dielectric layer 11 and the first internal electrode layer 21 and the region between the dielectric layer 11 and the second internal electrode layer 22. Alternatively, the main body 10 may include the first intermediate layer 41 but not the second intermediate layer 42. In this case, the Schottky barrier between the dielectric layer 11 and the first internal electrode layer 21 can be improved. Alternatively, the main body 10 may include the second intermediate layer 42 but not the first intermediate layer 41. In this case, the Schottky barrier between the dielectric layer 11 and the second internal electrode layer 22 can be improved.

[0054] The first intermediate layer 41 may cover the entire first internal electrode layer 21. Alternatively, the first intermediate layer 41 may cover only a portion of the first internal electrode layer 21. To suppress leakage current, the first intermediate layer 41 preferably covers at least 80% of the total area of ​​the upper and lower surfaces of the first internal electrode layer 21. Similarly, the second intermediate layer 42 may cover the entire second internal electrode layer 22. Alternatively, the second intermediate layer 42 may cover only a portion of the second internal electrode layer 22. To suppress leakage current, the second intermediate layer 42 preferably covers at least 80% of the total area of ​​the upper and lower surfaces of the second internal electrode layer 22.

[0055] If the first intermediate layer 41 cannot be seen in the electron microscope image, an observation region extending from the first internal electrode layer 21 to the dielectric layer 11 can be set in the cross section of the body 10, and TEM-EDS (Transmission Electron Microscope-Energy Dispersive X-ray Spectroscopy) can be performed in this observation region. The presence of the first intermediate layer 41 can be confirmed based on the elemental mapping data of the quantitative elements obtained by this TEM-EDS. An example of the observation region is Figure 3 The inspection of the first intermediate layer 41 by TEM-EDS analysis can be performed, for example, in the following manner.

[0056] (1) First, the main body 10 is sliced ​​into thin slices so that the surface parallel to the plane containing the T axis (e.g., the LT plane) serves as the observation surface. An observation region A1 extending from the first internal electrode layer 21 to the dielectric layer 11 is defined in the observation surface of the sliced ​​analysis sample. TEM-EDS is performed on this observation region A1 to obtain elemental surface distribution data for quantitative elements contained in the observation region A1. The observation region A1 is, for example, a square region measuring 15 nm square. The quantitative elements include elements contained in the main component oxide of the dielectric layer 11 (e.g., Ba, Ti, and O in the case where the main component oxide is BaTiO3), Ni, which is the main component metal of the first internal electrode layer 21, and Fe.

[0057] (2) Next, line analysis is performed based on the acquired elemental surface distribution data. Specifically, the elemental surface distribution data for the quantitative elements is reconstructed along a scan line SL extending from the first internal electrode layer 21 to the dielectric layer 11 within the observation area A1 to create a line profile for each quantitative element. The length of the scan line SL is, for example, 8 nm. The length of the scan line used to obtain the line profile can be varied as appropriate. Figure 5 An example of line distribution obtained by reconstructing elemental surface distribution data acquired by TEM-EDS in the analysis sample region A1 along the scanning line SL is shown. Figure 5 The line distribution is a graph obtained by reconstructing the elemental surface distribution data of Ba, Ti, O, Ni and Fe obtained by TEM-EDS on a sample prepared from a multilayer ceramic capacitor 1 whose dielectric layer 11 contains BaTiO3 as the main component along the scanning line SL. Figure 5 In FIG, the horizontal axis represents the detection position on the scanning line SL, and the vertical axis represents the detection intensity calculated based on the count value of each of Ba, Ti, O, Ni, and Fe at each detection position.

[0058] (3) Next, if a peak of the Fe line distribution exists near the intersection (hereinafter referred to as the "distribution intersection") where the line distribution of an element other than oxygen (e.g., Ba) that is the main component of the oxide of the dielectric layer 11 intersects with the line distribution of Ni that is the main component of the first internal electrode layer 21, it can be determined that the first intermediate layer 41 exists in the multilayer ceramic capacitor 1 from which the analysis sample was collected. For example, if the distance between the position of the distribution intersection and the peak position of the Fe line distribution is less than a predetermined threshold value, it can be determined that the peak of the Fe line distribution is located near the distribution intersection. The predetermined threshold value can be, for example, 1 nm, 0.9 nm, 0.8 nm, 0.7 nm, 0.6 nm, or 0.5 nm.

[0059] exist Figure 5In the example shown, the Ba distribution line of BaTiO₃, the main component of dielectric layer 11, intersects the Ni distribution line of the main component of first internal electrode layer 21 at a position approximately 4.1 nm from the scan start position. In other words, the intersection 52 of the Ba and Ni distribution lines is located approximately 4.1 nm from the scan start position. Furthermore, a peak 51 of the Fe distribution line appears approximately 3.9 nm from the scan start position. Since peak 51 of the Fe distribution line is located approximately 0.2 nm away from intersection 52, which is less than the threshold value, it is determined that the first intermediate layer 41 is present in the region containing peak 51. The presence of the second intermediate layer 42 between dielectric layer 11 and second internal electrode layer 22 can be determined using the same method.

[0060] When a peak appears in the Fe line distribution, the positions on both sides of the peak, where the count value (or intensity) of the peak is halfway, can be used as the boundary between the first intermediate layer 41 and the dielectric layer 11, and the boundary between the first intermediate layer 41 and the first internal electrode layer 21, respectively. The boundary between the second intermediate layer 42 and the dielectric layer 11, and the boundary between the second intermediate layer 42 and the second internal electrode layer 22 can be determined using the same method.

[0061] In this specification, when there is no need to distinguish the first intermediate layer 41 and the second intermediate layer 42 from each other, the first intermediate layer 41 and the second intermediate layer 42 are sometimes collectively referred to as “intermediate layer”.

[0062] 1-6 Fe concentration Next, the concentration of Fe in the first intermediate layer 41 and the first internal electrode layer 21 will be described.

[0063] First, the Fe concentration in the first intermediate layer 41 will be described. As described above, providing the first intermediate layer 41 containing Fe between the dielectric layer 11 and the first internal electrode layer 21 can enhance the Schottky barrier formed between the dielectric layer 11 and the first internal electrode layer 21, thereby improving the insulation reliability of the multilayer ceramic capacitor 1. As described later, the first intermediate layer 41 can be formed by Fe diffusing from the interior of the internal electrode pattern, which serves as a precursor to the first internal electrode layer 21, toward the interface with the dielectric green sheet, which serves as a precursor to the dielectric layer 11, during firing. This leads to Fe concentration (enrichment) at this interface. Increasing the amount of Fe diffusing from the interior of the internal electrode pattern toward the interface increases the Fe concentration in the first intermediate layer 41, thereby enhancing the Schottky barrier. On the other hand, some of the Fe diffusing from the interior of the internal electrode pattern toward the interface also diffuses into the interior of the dielectric green sheet. Fe diffused into the dielectric green sheet forms a solid solution in the main component oxide (e.g., the B site of BaTiO3) in the fired dielectric layer 11, hindering polarization reversal of the main component oxide and thus causing a decrease in the effective capacitance of the multilayer ceramic capacitor 1. Increasing the Fe concentration in the first intermediate layer 41 increases the amount of Fe entering the dielectric layer 11, thereby reducing the effective capacitance of the multilayer ceramic capacitor 1.

[0064] As described above, the improvement in insulation reliability achieved by enhancing the Schottky barrier between the first internal electrode layer 21 and the dielectric layer 11 using the first intermediate layer 41 is in a trade-off relationship with the reduction in effective capacitance. Therefore, it is desirable to improve the insulation reliability of the multilayer ceramic capacitor 1 using a mechanism different from the mechanism of enhancing the Schottky barrier by increasing the Fe concentration in the first intermediate layer 41.

[0065] The inventors have discovered that, when the first external electrode 31 comprises a Ni plating layer, the insulation reliability of the multilayer ceramic capacitor 1 is improved by containing 0.01 at% or more of Fe within the first internal electrode layer 21. The mechanism by which the insulation reliability of the multilayer ceramic capacitor 1 is improved by the 0.01 at% or more of Fe within the first internal electrode layer 21 is believed to be as follows. When the Ni plating layer is formed on the surface of the base electrode layer of the first external electrode 31 by electrolytic plating, the base electrode layer acts as a cathode. Consequently, hydrogen gas is generated around the base electrode layer and then enters the base electrode layer. The first internal electrode layer 21, which is connected to the base electrode layer, is primarily composed of Ni, which readily absorbs hydrogen. Therefore, hydrogen absorbed from the base electrode layer migrates to the first internal electrode layer 21 and is absorbed by the abundant Ni within the first internal electrode layer 21. During use of the multilayer ceramic capacitor 1, the hydrogen absorbed by the first internal electrode layer 21 diffuses into the dielectric layer 11, releasing electrons there, thereby reducing the insulation properties of the dielectric layer 11. Therefore, when a large amount of hydrogen enters the first internal electrode layer 21, the insulation reliability of the multilayer ceramic capacitor 1 degrades. According to the present inventors' research, when the first internal electrode layer 21 contains 0.01 at % or more of Fe, the Ni plating layer prevents the transformation and deformation of the metal lattice within the internal electrode during formation, thereby inhibiting hydrogen absorption in the first internal electrode layer 21. Consequently, it is possible to suppress degradation of the insulation reliability of the multilayer ceramic capacitor 1 caused by hydrogen absorbed in the first internal electrode layer 21.

[0066] In one embodiment, the first internal electrode layer 21 contains Fe at a first concentration of 0.01 at% or higher, and the first intermediate layer 41 contains Fe at a concentration of at least three times the first concentration and no more than 2 at%. By limiting the Fe concentration (second concentration) in the first intermediate layer 41 to no more than 2 at%, diffusion of Fe into the dielectric layer 11 can be suppressed, thereby minimizing a decrease in the effective capacitance of the multilayer ceramic capacitor 1. Furthermore, since the Fe concentration (second concentration) in the first intermediate layer 41 is at least three times the Fe concentration (first concentration) in the first internal electrode layer 21, the Schottky barrier formed between the dielectric layer 11 and the first internal electrode layer 21 is enhanced, thereby improving the insulation reliability of the multilayer ceramic capacitor 1. Furthermore, since the first internal electrode layer 21 contains Fe at a first concentration of 0.01 at% or higher, a decrease in insulation reliability caused by hydrogen diffusion from the first internal electrode layer 21 can be suppressed.

[0067] In one embodiment, the second internal electrode layer 22 contains Fe at a third concentration of 0.01 at % or higher, and the second intermediate layer 42 contains Fe at a fourth concentration of at least three times the third concentration and no more than 2 at %. This improves the Schottky barrier formed between the dielectric layer 11 and the second internal electrode layer 22, thereby enhancing the insulation reliability of the multilayer ceramic capacitor 1. Furthermore, since the second internal electrode layer 22 contains Fe at a third concentration of 0.01 at % or higher, it is possible to suppress a decrease in insulation reliability caused by hydrogen diffusion from the second internal electrode layer 22.

[0068] The concentration of Fe in the first internal electrode layer 21 is described below. In one embodiment, the concentration of Fe in a portion of the first internal electrode layer 21 can be quantified, and the quantified concentration of Fe in the portion can be used as the concentration of Fe in the first internal electrode layer 21. For example, Figure 3 The figure shows a region A2 located near the center of the first internal electrode layer 21 in the T-axis direction (stacking direction). Region A2 can be defined by defining a virtual line segment VL1 extending from one end of the first internal electrode layer 21 to the other end along the T-axis, so that the virtual line segment VL1's midpoint P1 in the T-axis direction is included. Region A2 is, for example, a 15 nm square. The Fe concentration in region A2 can be used as the Fe concentration in the first internal electrode layer 21. Alternatively, multiple regions A2 can be defined in the first internal electrode layer 21, and the average value of the Fe concentrations in each of the multiple regions A2 can be used as the Fe concentration in the first internal electrode layer 21. The Fe concentration in the second internal electrode layer 22 can also be calculated in the same manner as the Fe concentration in the first internal electrode layer 21.

[0069] The concentration of Fe contained in the first internal electrode layer 21 refers to the atomic ratio (at %) of the Fe element relative to 100 at % for Ni, the main component of the first internal electrode layer 21. In this specification, unless otherwise specified, the concentration (at %) of Fe is expressed as the atomic ratio relative to 100 at % for the main component metal element (e.g., Ni) in the first internal electrode layer 21.

[0070] The Fe concentration in the internal electrode layers (i.e., the first internal electrode layer 21 and the second internal electrode layer 22 ) and the first and second intermediate layers 41 and 42 can be quantified using known analytical methods. These methods may include TEM-EDS, STEM-EDS, three-dimensional atom probe (3DAP) analysis, and secondary ion mass spectrometry (SIMS).

[0071] 2. Method for Manufacturing Multilayer Ceramic Capacitor 1 Next, refer to Figure 6 An example of a method for manufacturing the multilayer ceramic capacitor 1 will be described. Figure 6 This is a flowchart showing the flow of a method for manufacturing a capacitor according to one embodiment of the present invention.

[0072] right Figure 6 The manufacturing method shown in FIG. 1 is briefly described. First, in step S11, a laminate is formed as a precursor of the body 10. This laminate includes a dielectric green sheet, which serves as a precursor of the dielectric layer 11, and internal electrode patterns, which serve as precursors of the first internal electrode layer 21 and the second internal electrode layer 22. The internal electrode patterns contain nickel and iron. Next, the laminate is fired in steps S12 to S14. In step S15, a nickel plating layer is formed on the external electrodes of the fired laminate, thereby obtaining the laminated ceramic capacitor 1.

[0073] Then, Figure 6 The steps shown in FIG. 1 are described in more detail. In step S11, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are first added to dielectric powder and wet-mixed to form a slurry. This slurry is then applied to a substrate film using, for example, a die coating or doctor blade method. The applied slurry is then dried to form a dielectric green sheet. This dielectric green sheet serves as a precursor for dielectric layer 11.

[0074] The dielectric powder used as the raw material powder for the dielectric green sheet is, for example, barium titanate powder, which can be synthesized by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate using a known method such as a solid phase method, a sol-gel method, or a hydrothermal method.

[0075] Next, internal electrode patterns are formed on each of the multiple dielectric green sheets formed as described above. The internal electrode patterns can be formed, for example, by printing an internal electrode paste on the dielectric green sheets using a known printing method such as screen printing. When forming the internal electrode patterns by screen printing, the internal electrode paste can be produced by kneading metal powder, a binder resin, and a solvent using a three-roll mill. In other words, the internal electrode paste is obtained by dispersing metal powder in a binder resin. The metal powder contained in the internal electrode paste can be a mixed powder obtained by mixing Ni powder, which will become the main component of the first and second internal electrode layers 21 and 22, with Fe-containing powder containing Fe. The Fe-containing powder is, for example, Fe2O3 powder. The Fe-containing powder is weighed so that the Fe content is 0.02 to 4.0 at% relative to 100 at% of Ni, and the thus weighed Fe-containing powder is mixed with the Ni powder.

[0076] Cellulose resins such as ethyl cellulose and acrylic resins such as butyl methacrylate can be used as organic binders for the internal electrode paste. The internal electrode patterns formed on some dielectric green sheets serve as precursors for the first internal electrode layer 21, while the internal electrode patterns formed on other dielectric green sheets serve as precursors for the second internal electrode layer 22.

[0077] The method for forming the internal electrode pattern is not limited to the method specifically described in this specification. The internal electrode pattern can be formed using various well-known methods, such as sputtering, vacuum evaporation, PLD (pulsed laser evaporation), MO-CVD (metal organic chemical vapor deposition), MOD (metal organic decomposition), or CSD (chemical solution deposition).

[0078] By following the above procedures, a laminated unit is obtained, comprising a dielectric green sheet and an internal electrode pattern formed on the surface of the dielectric green sheet. A predetermined number of these laminated units are stacked and thermocompressed to form a laminate. Green sheets without internal electrode patterns may be stacked on the top and bottom layers of the laminate.

[0079] Next, the stack is separated into individual pieces to obtain a sheet-like stack that serves as a precursor to the main body 10. This sheet-like stack can be degreased. The degreasing process can be performed in an N2 atmosphere. Alternatively, the metal paste that will serve as the base electrode layers of the first and second external electrodes 31 and 32 can be applied to the degreased stack by dipping.

[0080] Next, in step S12, the sheet stack produced in step S11 is placed in a firing furnace to start firing the sheet stack. The firing furnace is maintained at an oxygen partial pressure of, for example, 10 -10 ~10 -9 Atm low oxygen atmosphere. In step S12, the temperature in the firing furnace is raised from room temperature to the sintering start temperature at a rate of 200-1000°C / h and maintained at the sintering start temperature for 10 minutes to 1 hour. In other words, in step S12, the sheet stack is heated at the sintering start temperature for approximately 10 minutes to 1 hour. The sintering start temperature is set to 850-1100°C, which is suitable for sintering Ni.

[0081] Next, in step S13, the oxygen partial pressure in the firing furnace is set to 10 -12 ~10 -10A reducing atmosphere of approximately 2000 atm is created. Furthermore, the temperature within the firing furnace is increased at a high rate from the sintering start temperature to the maximum firing temperature. The maximum firing temperature is, for example, 1150-1300°C. The heating rate is, for example, 3000-10000°C / h. An example heating rate is 3000°C / h. By maintaining a high heating rate of approximately 3000-10000°C / h, the diffusion of Fe from the internal electrode pattern into the dielectric green sheet can be suppressed. This prevents excessive Fe from being present in the first and second intermediate layers 41, 42 after firing.

[0082] Next, in step S14, the temperature inside the firing furnace is maintained at the maximum firing temperature for 10 to 30 minutes to further heat the sheet stack. Following the heating process in step S14, the firing furnace is cooled. The heating process in step S14 fires the sheet stack to form a fired body. During the heating process in step S14, the dielectric green sheets in the sheet stack are fired to form the dielectric layer 11, and the internal electrode patterns are fired to form the internal electrode layers (first internal electrode layer 21 and second internal electrode layer 22). Furthermore, during the heating process in steps S12 to S14, the Fe contained in the internal electrode patterns thermally diffuses toward the interface with the dielectric green sheets. Consequently, in the fired body, first and second intermediate layers 41 and 42, containing Fe at a higher concentration than that in the internal electrode layers, are formed between the dielectric layer 11 and the first and second internal electrode layers 21, respectively.

[0083] Next, in step S15, a Ni plating layer is formed on the surface of the base electrode layer of the sintered body. The Ni plating layer can be formed by electrolytic plating or electroless plating. In addition to the Ni plating layer, a Sn plating layer can also be formed on the surface of the base electrode layer.

[0084] Through the above-described steps, the multilayer ceramic capacitor 1 is obtained.

[0085] In order to manufacture the multilayer ceramic capacitor 1, it is also possible to Figure 6 For example, the fired body obtained in step S14 may be subjected to a reoxidation treatment at 600° C. to 1000° C. in an N 2 gas atmosphere or a low oxygen atmosphere.

[0086] 3 Examples The present invention will be described in more detail below based on examples. However, the present invention is not limited to the following examples.

[0087] 3-1 Preparation of samples according to Figure 6The multilayer ceramic capacitor of Sample 1 was produced as follows, using the manufacturing method described in [1]. First, polyvinyl butyral (PVB) resin, solvent, and plasticizer were added to barium titanate powder and wet-mixed to obtain a slurry. This slurry was then applied to a base film and dried to obtain a dielectric green sheet. Next, Fe2O3 powder was mixed with nickel powder with an average particle size of 200 nm to prepare a mixed powder. The Fe2O3 powder was weighed so that the Fe concentration in the internal electrodes of the fired multilayer ceramic capacitor would be 0.01 at% relative to 100 at% of Ni, taking into account the firing atmosphere and temperature distribution. The thus-weighed Fe2O3 powder was mixed with the nickel powder. Next, polyvinyl butyral (PVB) resin, solvent, and plasticizer were added to the mixed powder and wet-mixed to obtain an internal electrode slurry. The internal electrode slurry was then printed on a portion of the surface of the dielectric green sheet to form an internal electrode pattern on each dielectric green sheet, thereby forming a laminated unit. The laminated unit includes a dielectric green sheet and an internal electrode pattern formed on a surface of the dielectric green sheet.

[0088] Next, 500 stacked units were stacked to form a laminate, which was then separated into individual pieces to form a sheet laminate. The sheet laminate had a 1005 shape (length: 1.0 mm, width: 0.5 mm, height: 0.5 mm). The sheet laminate was then degreased in an N2 atmosphere. A metal paste was then applied to the degreased sheet laminate using a dipping method to form the base electrode layer, which served as the external electrode.

[0089] Next, the sheet stack obtained as described above is placed in a firing furnace and fired under predetermined firing conditions according to a predetermined temperature distribution. Specifically, the firing furnace is maintained at an oxygen partial pressure of 10 -10 The low oxygen atmosphere was heated from room temperature to 850°C at a heating rate of 300°C / h and maintained at 850°C for 30 minutes. -12 Atm reducing atmosphere, the temperature was raised from 850°C to 1250°C at a rate of 3000°C / h. After holding at 1250°C for 30 minutes, the furnace was cooled. A Ni plating layer was formed on the base electrode layer of the fired body obtained by firing in the above temperature profile by electrolytic plating. Sample 1 was produced by the above-described operation.

[0090] Samples 2 to 7 were prepared in the same manner as Sample 1, except for the amount of Fe2O3 powder mixed with Ni particles when generating the mixed powder as the raw material for the internal electrode pattern. The specific mixing ratios of Fe2O3 powder when preparing Samples 2 to 7 are as follows.

[0091] When preparing Sample 2, Fe 2 O 3 powder and Ni powder weighed so as to have a ratio of 0.03 at % relative to 100 at % of Ni were mixed to prepare a mixed powder.

[0092] When preparing Sample 3, Fe 2 O 3 powder and Ni powder weighed so as to have a ratio of 0.1 at % relative to 100 at % of Ni were mixed to prepare a mixed powder.

[0093] When preparing Sample 4, Fe 2 O 3 powder and Ni powder weighed so as to have a ratio of 0.3 at % relative to 100 at % of Ni were mixed to prepare a mixed powder.

[0094] When preparing Sample 5, Fe 2 O 3 powder and Ni powder weighed so as to have a ratio of 0.5 at % relative to 100 at % of Ni were mixed to prepare a mixed powder.

[0095] When preparing sample 6, Fe2O3 powder was not mixed.

[0096] When preparing Sample 7, Fe 2 O 3 powder and Ni powder weighed so as to have a ratio of 0.7 at % relative to 100 at % of Ni were mixed to prepare a mixed powder.

[0097] Samples 2 to 7 were prepared in the same manner as in Sample 1 using the internal electrode slurry containing the mixed powder obtained as described above.

[0098] 3-2 Confirmation of the middle layer Samples 1 to 7 were each thinned using a focused ion beam (FIB) apparatus with the LT surface as the observation surface. Samples 1 to 7 were each thinned to a thickness of 60 nm and prepared for analysis. Ar ion milling was used to remove any damage to the observation surface of each sample. Subsequently, each sample was placed in a TEM equipped with an EDS detector, and ten observation areas (equivalent to 15 nm squares) extending from the internal electrode layer to the dielectric layer were identified on the observation surface. Figure 3 Observation area A1), EDS analysis was performed on each of the 10 observation areas B1. Specifically, a concentration map expressing the concentration of quantitative elements (Ba, Ti, O, Ni, and Fe) in terms of atomic ratio (at%) was obtained in each observation area, and the concentration map was scanned along a scanning line (equivalent to the scanning line) set in each observation area so as to extend from the internal electrode layer along the T axis to the dielectric layer. Figure 3 The line distribution of each quantitative element in each observation area is obtained by reconstructing the scanning line SL of each observation area. Figure 5Similarly, the peak of Fe appears near the intersection of the distribution of Ba and the distribution of Ni. For sample 6, no Fe was detected except for system noise. From the results of this line analysis, it can be confirmed that an intermediate layer with Fe concentration (enrichment) is formed between the internal electrode layer and the dielectric layer for samples 1 to 5 and 7. As TEM, NEOARM manufactured by JEOL Corporation was used. EDS analysis used an energy dispersive X-ray spectrometer Octane Elite manufactured by AMETEK Corporation. In EDS, the acceleration voltage was set to 200 kV, the electron beam diameter was set to 1.0 nm, and the measurement time was set to 3 hours.

[0099] 3-3 Fe concentration analysis Next, for each sample except for sample 6 in which no Fe-containing powder was added to the raw material, the Fe concentration at the interface (intermediate layer) between the internal electrode layer and the dielectric layer, and the Fe concentration within the internal electrode layer were analyzed as follows. In the above-mentioned sample piece used to determine the presence or absence of the intermediate layer, the Fe concentration in the observation area extending from the internal electrode layer to the dielectric layer at 10 points (corresponding to Figure 3 The Fe concentration in the intermediate layer included in each of the ten observation areas A1 was calculated, and the average Fe concentration in these ten observation areas was calculated. The average Fe concentration in the ten observation areas set for the intermediate layer was recorded as the Fe concentration in the intermediate layer of each sample in the "Fe concentration in intermediate layer" column of Table 1 below.

[0100] Next, in the sample piece for quantifying the Fe concentration in the intermediate layer, 10 regions (corresponding to Figure 3 The Fe concentration was then measured in each of ten observation areas located near the center of the internal electrode layer in the stacking direction, and the average Fe concentration in these ten observation areas was calculated. The average Fe concentration in these ten observation areas was used as the Fe concentration in the internal electrode layer for each sample and is recorded in the "Fe concentration in internal electrode layer" column in Table 1 below. In Samples 1 to 5, and Sample 7, the first internal electrode layer 21 contained Fe at a first concentration of 0.01 at % or greater. This suppressed degradation of insulation reliability caused by hydrogen diffusion from the first internal electrode layer 21.

[0101] In addition, the ratio of the Fe concentration in the intermediate layer to the Fe concentration in the internal electrode layer was calculated and recorded in the "Fe Concentration Ratio" column in Table 1. The Fe concentration ratios of Samples 1 to 5 and Sample 7 were all greater than 3. In other words, in Samples 1 to 5 and Sample 7, the Fe concentration in the intermediate layer was at least three times the Fe concentration in the internal electrode layer. In Samples 1 to 5, the Fe concentration in the intermediate layer was at least three times the Fe concentration in the internal electrode layer. Therefore, the Schottky barrier formed between the dielectric layer 11 and the first internal electrode layer 21 was enhanced, thereby improving the insulation reliability of the multilayer ceramic capacitor 1.

[0102] 3-4 Capacitor Next, 100 samples were selected for each of Samples 1 to 7, and the capacitance of each selected sample was measured using an LCR meter under the conditions of 0.5V and 1kHz. The average value of the capacitance of the 100 samples measured, i.e., the capacitance average value, was calculated. It can be confirmed that the higher the Fe concentration in the intermediate layer, the lower the calculated capacitance average value. In addition, the capacitance average values ​​of Samples 1 to 5 and 7 calculated in this way were compared with the capacitance average value of Sample 6 to which no Fe-containing powder was added in the raw material. Compared with the capacitance average value of Sample 6, samples whose average capacitance value was reduced by less than 10% were judged to be qualified, and samples whose average capacitance value was reduced by more than 10% were judged to be unqualified. The judgment results are recorded in the "Capacitance Characteristics" column of Table 1 for each sample. It can be considered that in the samples judged to be qualified, the degradation of the capacitance caused by the diffusion of Fe into the dielectric layer is sufficiently suppressed.

[0103] 3-5 Reliability Test 100 samples were selected from each of Samples 1 to 7, and reliability tests were performed on each of these samples. In the reliability test, a voltage of 10V was applied to each sample at 150°C for 1000 hours, and then the sample was left at room temperature for 24 hours before the insulation resistance was measured. Samples in which at least one insulation resistance value was less than 10kΩ were judged as "failed," while samples in which no insulation resistance value was less than 10kΩ were judged as "passed." The results of this judgment are recorded for each sample in the "Insulation Reliability" column of Table 1.

[0104] [Table 1] In Table 1, samples not included in the present invention (ie, comparative examples) are given an asterisk (*) with respect to the sample number. Specifically, Samples 6 and 7 are comparative examples not included in the present invention.

[0105] According to the above verification, the higher the Fe concentration in the intermediate layer, the lower the capacitance. Therefore, by reducing the Fe concentration in the intermediate layer, high capacitance can be ensured. In one embodiment, by making the Fe concentration in the intermediate layer 2.0at% or less, excellent capacitance can be ensured. In addition, through the above verification, it was confirmed that by making the Fe concentration in the intermediate layer more than 3 times the Fe concentration in the internal electrode layer and containing more than 0.01at% of Fe in the internal electrode layer, excellent insulation reliability can be obtained. Therefore, it was confirmed that by making the Fe concentration in the internal electrode layer more than 0.01at% and making the Fe concentration in the intermediate layer more than 3 times the Fe concentration in the internal electrode layer and less than 2at%, excellent effective capacitance and excellent insulation reliability can be achieved.

[0106] 4 Comments The dimensions, materials, and configurations of the components described in the various embodiments are not limited to the dimensions, materials, and configurations explicitly described in the embodiments, and the components may be deformed to have any dimensions, materials, and configurations that are within the scope of the present invention.

[0107] Components that are not explicitly described in this specification may be added to the above-described embodiments, and some of the components described in the embodiments may be omitted.

[0108] The terms "first," "second," and "third" throughout this specification and other text are used to identify components and do not necessarily limit their quantity, order, or content. Furthermore, the numbers used to identify components are specific to each context; a number used in one context does not necessarily indicate the same component in another context. Furthermore, a component identified by one number does not preclude it from assuming the functionality of a component identified by a different number.

[0109] In this specification, when a component is “comprising”, it does not exclude other components as long as it does not conflict with the content of the present invention, and other components may be included.

[0110] 5 Notes The embodiments disclosed in this specification also include the following matters.

[0111] [Note 1] A laminated ceramic capacitor, comprising: a body comprising a first internal electrode layer containing Fe at a first concentration, a second internal electrode layer, a dielectric layer disposed between the first internal electrode layer and the second internal electrode layer in a first direction, and a first intermediate layer disposed between the first internal electrode layer and the dielectric layer and containing Fe at a second concentration; a first external electrode provided on the main body in electrical connection with the first internal electrode layer and comprising a Ni plating layer; and a second external electrode provided on the main body in electrical connection with the second internal electrode layer; The first concentration is 0.01 at % or more, The second concentration is 3 times or more of the first concentration and 2 at % or less.

[0112] [Note 2] The multilayer ceramic capacitor according to [Supplementary Note 1], characterized in that: The first internal electrode layer and the second internal electrode layer are mainly composed of Ni.

[0113] [Note 3] The multilayer ceramic capacitor according to [Supplementary Note 1] or [Supplementary Note 2], characterized in that: The dimension of the first internal electrode layer in the first direction is not less than 0.1 μm and not more than 2 μm.

[0114] [Note 4] The multilayer ceramic capacitor according to any one of [Supplementary Note 1] to [Supplementary Note 3], characterized in that: The second external electrode comprises a Ni plating layer, The second internal electrode layer contains Fe at a third concentration, The main body further includes a second intermediate layer provided between the second internal electrode layer and the dielectric layer in the first direction and containing Fe at a fourth concentration, The third concentration is 0.01 at % or more, The fourth concentration is 3 times or more of the third concentration and 2 at % or less.

[0115] [Note 5] A circuit component, characterized by comprising the multilayer ceramic capacitor described in any one of [Supplementary Note 1] to [Supplementary Note 4].

[0116] [Note 6] An electronic device, characterized in that it includes the circuit component described in [Supplementary Note 5].

[0117] [Note 7] A method for manufacturing a capacitor, comprising: a step of preparing a laminate including a dielectric green sheet and internal electrode patterns containing Ni and Fe provided on first and second surfaces of the dielectric green sheet; a first heating step of heating the laminate at a first temperature of 850° C. or higher; a heating step of heating the substrate from the first temperature to a second temperature of 1150° C. or higher at a heating rate of 3000° C. / h or higher; and The second heating step is to heat the laminated body at the second temperature.

[0118] Description of Reference Numerals 1 Capacitor, 10 Body, 11 Dielectric Layer, 21 First Internal Electrode Layer, 22 Second Internal Electrode Layer, 31 First External Electrode, 32 Second External Electrode, 41 First Intermediate Layer, 42 Second Intermediate Layer.

Claims

1. A multilayer ceramic capacitor, characterized in that: include: a body having a first internal electrode layer containing a main component metal and containing Fe at a first concentration, a second internal electrode layer, a dielectric layer arranged between the first internal electrode layer and the second internal electrode layer in a first direction, and a first intermediate layer provided between the first internal electrode layer and the dielectric layer and containing Fe at a second concentration; a first external electrode provided on the main body in electrical connection with the first internal electrode layer and comprising a Ni plating layer; and a second external electrode provided on the main body in electrical connection with the second internal electrode layer; The first concentration is 0.01 at % or more, The second concentration is 3 times or more of the first concentration and 2 at % or less.

2. The multilayer ceramic capacitor according to claim 1, wherein: The first internal electrode layer and the second internal electrode layer are mainly composed of Ni.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein: The dimension of the first internal electrode layer in the first direction is not less than 0.1 μm and not more than 2 μm.

4. The multilayer ceramic capacitor according to claim 1 or 2, wherein: The second external electrode comprises a Ni plating layer, The second internal electrode layer contains Fe at a third concentration, The main body further includes a second intermediate layer provided between the second internal electrode layer and the dielectric layer in the first direction and containing Fe at a fourth concentration, The third concentration is 0.01 at % or more, The fourth concentration is 3 times or more of the third concentration and 2 at % or less.

5. A circuit assembly, characterized in that: A multilayer ceramic capacitor according to claim 1 or 2 is included.

6. An electronic device, characterized in that: The circuit assembly according to claim 5 is included.

7. A method for manufacturing a capacitor, characterized in that: include: a step of preparing a laminate including a dielectric green sheet and internal electrode patterns containing Ni and Fe provided on first and second surfaces of the dielectric green sheet; a first heating step of heating the laminate at a first temperature of 850° C. or higher; a heating step of heating the substrate from the first temperature to a second temperature of 1150° C. or higher at a heating rate of 3000° C. / h or higher; and The second heating step is to heat the laminated body at the second temperature.

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