Bonding structure and forming method thereof

Abstract

The invention discloses a bonding structure and a forming method thereof, and the structure comprises a first wafer and a second wafer, and the first wafer and the second wafer are bonded at a first connection point; the first wafer comprises a substrate; the TSV penetrates through the substrate in the thickness direction; the interconnection structure is located between the substrate and the second wafer, the interconnection structure comprises top-layer metal and intermediate metal, the intermediate metal is located between the top-layer metal and the substrate, and the thickness of the top-layer metal is larger than that of the intermediate metal; the position of the intermediate metal corresponds to the position of the TSV, and the intermediate metal is connected with one end of the TSV; in a direction parallel to the surface of the substrate, the top metal extends from the position of the TSV to the position of the first connection point. The projection of the middle metal on the surface of the substrate is located in the projection range of the top metal on the surface of the substrate, the distance between the middle metal and the top metal in the direction parallel to the surface of the substrate is small, connection between the middle metal and the top metal can be achieved without arranging a long lead, and the middle metal transmits current only in the direction perpendicular to the surface of the substrate. When the current is transmitted in the direction perpendicular to the surface of the substrate, the overcurrent capacity of the intermediate metal is far larger than that of the intermediate metal when the current is transmitted in the direction parallel to the surface of the substrate, electromigration of the intermediate metal caused by large current from the TSV can be avoided, and the reliability of the three-dimensional integrated chip structure is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a bonding structure and a forming method thereof. Background Art

[0002] A conventional chip structure consists of multiple layers of intermediate metal and top metal. The intermediate metal, located below the top metal, is thin and has poor current resistance. The top metal, located above the intermediate metal, has larger critical dimensions and is thicker, capable of withstanding higher currents. The top metal is connected to an external circuit board. High-current signals from the external circuit board are first connected to the top metal, then shunted by the top metal and gradually transmitted to the intermediate metal connected to it. The top metal carries high currents, while the intermediate metal carries low currents. This driving method matches the device structure and has high reliability.

[0003] As circuit boards demand ever-higher levels of integration and functionality for various components, traditional two-dimensional integrated circuits are unable to meet these demands, prompting the emergence of three-dimensional integrated chips. Three-dimensional integrated chips utilize a bonding method that combines chips on top and bottom, or stacks multiple chips, to increase the integration of electronic devices.

[0004] However, the current three-dimensional integrated bonding structure needs to be optimized. Summary of the Invention

[0005] The problem solved by the present invention is how to optimize the bonding structure of a three-dimensional integrated chip to avoid severe electromigration of intermediate metals caused by large currents from external circuits, thereby affecting the reliability of the three-dimensional integrated chip structure.

[0006] To solve the above problems, the present invention provides a bonding structure, comprising: a first wafer and a second wafer, wherein the first wafer and the second wafer are bonded at a first connection point; the first wafer comprises: a substrate; a TSV, wherein the TSV penetrates the substrate along a thickness direction; an interconnection structure, wherein the interconnection structure is located between the substrate and the second wafer, and the interconnection structure comprises: a top metal and an intermediate metal, wherein the intermediate metal is located between the top metal and the substrate, and the thickness of the top metal is greater than the thickness of the intermediate metal; the position of the intermediate metal corresponds to the position of the TSV, and the intermediate metal is connected to one end of the TSV; in a direction parallel to the surface of the substrate, the top metal extends from the position of the TSV to the position of the first connection point.

[0007] Optionally, the first wafer has a plurality of interconnect structures, and the plurality of interconnect structures are connected to the plurality of TSVs in a one-to-one correspondence; and top metal layers of the plurality of interconnect structures are connected integrally.

[0008] Optionally, the top metal layer is connected to a plurality of first connection points.

[0009] Optionally, the other end of the TSV is connected with a pad.

[0010] Optionally, the other end of the TSV is connected with a redistribution layer.

[0011] Optionally, the bonding structure further comprises a third wafer, the third wafer is bonded with the first wafer at a second bonding point; and the redistribution layer extends from the position of the TSV to the position of the second bonding point in a direction parallel to the surface of the substrate.

[0012] Optionally, the first wafer has a plurality of TSVs, and the plurality of TSVs are connected with the same redistribution layer.

[0013] Optionally, the same redistribution layer is connected with a plurality of second bonding points.

[0014] Optionally, the adjacent intermediate metals are connected through a plug.

[0015] Optionally, the intermediate metal and the top layer metal are connected through a plug.

[0016] Optionally, the material of the top layer metal comprises copper.

[0017] Correspondingly, the application also provides a bonding structure forming method for forming the bonding structure.

[0018] Compared with the prior art, the technical scheme of the application has the following advantages:

[0019] In the bonding structure of the technical scheme, the top layer metal extends from the position of the TSV to the position of the first bonding point, and one end of the TSV is connected with the intermediate metal, so that the projection of the intermediate metal on the surface of the substrate is located in the projection range of the top layer metal on the surface of the substrate, the distance between the intermediate metal and the top layer metal in the direction parallel to the surface of the substrate is small, the connection between the intermediate metal and the top layer metal does not need to be provided with a long lead, the intermediate metal only transmits current in the direction perpendicular to the surface of the substrate, the cross-sectional area of the intermediate metal through which the current flows when the current is transmitted in the direction perpendicular to the surface of the substrate is much larger than the cross-sectional area of the intermediate metal through which the current flows when the current is transmitted in the direction parallel to the surface of the substrate, so that the current-carrying capacity of the intermediate metal when the current is transmitted in the direction perpendicular to the surface of the substrate is much larger than the current-carrying capacity of the intermediate metal when the current is transmitted in the direction parallel to the surface of the substrate, the large current from the TSV can be avoided to cause the electromigration of the intermediate metal and affect the reliability of the chip structure, the reliability of the three-dimensional integrated chip structure can be significantly improved without changing the chip architecture, and the application range is large. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1FIG. 1 is a schematic diagram of a cross-sectional structure of a bonding structure according to an embodiment of the present application;

[0021] Figure 2 FIG. 2 is a schematic diagram of a cross-sectional structure of an intermediate metal according to an embodiment of the present application;

[0022] Figure 3 FIG. 3 is a schematic diagram of a cross-sectional structure of a bonding structure according to an embodiment of the present application;

[0023] Figure 4 FIG. 4 is a schematic diagram of a cross-sectional structure of a bonding structure according to another embodiment of the present application. DETAILED DESCRIPTION

[0024] As known from the background, in the bonding structure in the prior art, a large current from an external circuit causes serious electromigration of the intermediate metal, resulting in reliability problems of the integrated chip structure. Now, a bonding structure is combined to analyze the causes of the reliability problems:

[0025] Figure 1 FIG. 1 is a schematic diagram of a cross-sectional structure of a bonding structure according to an embodiment of the present application; Figure 2 FIG. 2 is a schematic diagram of a cross-sectional structure of an intermediate metal according to an embodiment of the present application;

[0026] The bonding structure comprises a first wafer and a second wafer, the first wafer and the second wafer are bonded at a first connection point 100; the first wafer comprises a substrate 101, a TSV 102 penetrating through the substrate 101 in a thickness direction, and an interconnection structure between the substrate 101 and the second wafer, the interconnection structure comprises a top layer metal 103 and an intermediate metal 104, the intermediate metal 104 is between the top layer metal 103 and the substrate 101, the thickness of the top layer metal 103 is greater than the thickness of the intermediate metal 104; the intermediate metal 104 is connected with one end of the TSV 102.

[0027] The bonding structure further comprises a pad 105 connected with the other end of the TSV 102.

[0028] The bonding structure further comprises an external circuit board 106 connected with the pad 105.

[0029] In the three-dimensional integrated bonding structure, the TSV 102 penetrates the substrate 101, connecting the interconnection structure on the front surface of the substrate 101 with the external circuit board 106 on the back surface. The electrical signal from the external circuit board 106 on the back surface of the first wafer is directly connected to the middle metal 104 of the first wafer through the TSV 102, and is transmitted laterally along the long lead of the middle metal 104. The thickness of the middle metal 104 is small, and the thickness of the top metal 103 is large. A large current is loaded on the middle metal 104, and the current is transmitted to the top metal 103, which is contrary to the conventional chip architecture:

[0030] When the current flowing through the long lead of the middle metal 104 is parallel to the surface direction of the substrate 101, the cross-sectional area of the current is W*H, where W is the width of the long lead of the middle metal 104, and H is the thickness of the middle metal 104. When the current flowing through the long lead of the middle metal 104 is perpendicular to the surface direction of the substrate 101, the cross-sectional area of the current is W*L, where W is the width of the long lead of the middle metal 104, and L is the length of the middle metal 104, which is much larger than H. Therefore, when the current from the external circuit board 106 is transmitted in the direction perpendicular to the surface of the substrate 101, the current-carrying capacity of the long lead of the middle metal 104 is much larger than that when the current is transmitted in the direction parallel to the surface of the substrate 101.

[0031] In the current bonding structure, a large current is loaded on the middle metal 104, and the current is transmitted to the top metal 103, which seriously affects the reliability of the current 3D chip.

[0032] If the thickness of the middle metal 104 is increased to the thickness of the top metal 103, although the current transmission capacity of the middle metal 104 can be improved, the original chip architecture is changed, the workload is large, the process cost is increased, and the thickness of the middle metal 104 is increased, which changes the stress of the wafer, causing the characteristics of the devices connected to the middle metal 104 to change, and even causing the wafer to be broken.

[0033] If the size of the middle metal 104 in the direction parallel to the surface of the substrate 101 is increased, the current transmission capacity of the middle metal 104 can be improved, but due to the limitation of the process, the maximum line width of the middle metal cannot be greater than 4.5 μm.

[0034] To solve the technical problem, the application provides a bonding structure, comprising: a first wafer and a second wafer, the first wafer and the second wafer are bonded at a first connection point; the first wafer comprises: a substrate; a TSV, the TSV penetrates through the substrate in a thickness direction; an interconnection structure, the interconnection structure is located between the substrate and the second wafer, the interconnection structure comprises: a top layer metal and an intermediate metal, the intermediate metal is located between the top layer metal and the substrate, the thickness of the top layer metal is greater than the thickness of the intermediate metal; the position of the intermediate metal corresponds to the position of the TSV, and the intermediate metal is connected to one end of the TSV; in the direction parallel to the surface of the substrate, the top layer metal extends from the position of the TSV to the position of the first connection point.

[0035] In the bonding structure of the technical scheme of the application, the top layer metal extends from the position of the TSV to the position of the first connection point, and one end of the TSV is connected to the intermediate metal, so that the projection of the intermediate metal on the surface of the substrate is located in the projection range of the top layer metal on the surface of the substrate, the distance between the intermediate metal and the top layer metal in the direction parallel to the surface of the substrate is small, the connection between the intermediate metal and the top layer metal does not need to be provided with a long lead, the intermediate metal only transmits current in the direction perpendicular to the surface of the substrate, the cross-sectional area of the intermediate metal through which the current flows in the direction perpendicular to the surface of the substrate is much larger than the cross-sectional area of the intermediate metal through which the current flows in the direction parallel to the surface of the substrate, so that the current carrying capacity of the intermediate metal in the direction perpendicular to the surface of the substrate is much larger than the current carrying capacity of the intermediate metal in the direction parallel to the surface of the substrate, the large current from the TSV can be avoided to cause electromigration of the intermediate metal and affect the reliability of the chip structure, the reliability of the three-dimensional integrated chip structure can be significantly improved without changing the chip architecture, and the application range is large.

[0036] In order to make the above-mentioned purpose, features and advantages of the application more obvious and easy to understand, the specific embodiments of the application will be described in detail below with reference to the drawings.

[0037] Figure 3 is a cross-sectional structure schematic diagram of the bonding structure of an embodiment of the application.

[0038] Please refer to Figure 3 , the bonding structure comprises: a first wafer I and a second wafer II, the first wafer I and the second wafer II are bonded at a first connection point 200.

[0039] The bonding method of the first wafer I and the second wafer II includes fusion bonding and hybrid bonding. The hybrid bonding includes at least one of the hybrid bonding of metal and inorganic film.

[0040] The projection of the first connection point 200 on the surface of the substrate 201 is within the projection range of the top layer metal 203 on the surface of the substrate 201.

[0041] Please continue to refer to Figure 3 The first wafer I includes a substrate 201.

[0042] The substrate 201 provides support for the interconnection structure.

[0043] The material of the substrate 201 includes silicon, silicon carbide, silicon germanium, silicon-on-insulator (SOI), or germanium-on-insulator (GOI).

[0044] Please continue to refer to Figure 3 The first wafer I includes a TSV 202, which penetrates the substrate 201 in the thickness direction.

[0045] The TSV 202 penetrates the substrate 201 in the direction perpendicular to the surface of the substrate 201, and connects the front and back surfaces of the substrate 201. The TSV 202 connects the external circuit board 206 located on the back surface of the first wafer I to the interconnection structure located on the front surface of the first wafer I, realizing three-dimensional integration of multiple wafers.

[0046] The material of the TSV 202 includes metal.

[0047] Please continue to refer to Figure 3 The first wafer I includes an interconnection structure between the substrate 201 and the second wafer II. The interconnection structure includes a top layer metal 203 and an intermediate metal 204. The intermediate metal 204 is located between the top layer metal 203 and the substrate 201. The thickness of the top layer metal 203 is greater than the thickness of the intermediate metal 204. The position of the intermediate metal 204 corresponds to the position of the TSV 202. The intermediate metal 204 is connected to one end of the TSV 202. In the direction parallel to the surface of the substrate 201, the top layer metal 203 extends from the position of the TSV 202 to the position of the first connection point 200.

[0048] The top layer metal 203 extends from the position of the TSV 202 to the position of the first connection point 200, so that the projection of the middle layer metal 204 on the surface of the substrate 201 is within the projection range of the top layer metal 203 on the surface of the substrate 201, and the projection of the TSV 202 on the surface of the substrate 201 is within the projection range of the top layer metal 203 on the surface of the substrate 201. The position of the middle layer metal 204 corresponds to the position of the TSV 202, that is, the projection of the TSV 202 on the surface of the substrate 201 is within the projection range of the middle layer metal 204 on the surface of the substrate 201. The middle layer metal 204 is connected to one end of the TSV 202, and the connection between the middle layer metal 204 and the TSV 202 does not need to be provided with a long lead wire. The cross-sectional area of the current transmitted in the direction perpendicular to the surface of the substrate 201 is the thickness of the middle layer metal 204 multiplied by the width of the middle layer metal 204, and the cross-sectional area of the current transmitted in the direction parallel to the surface of the substrate 201 is the thickness of the middle layer metal 204 multiplied by the length of the middle layer metal 204. The length of the middle layer metal 204 is much larger than the width of the middle layer metal 204. The current carrying capacity of the middle layer metal in the direction perpendicular to the surface of the substrate 201 is much larger than the current carrying capacity of the middle layer metal in the direction parallel to the surface of the substrate 201. The middle layer metal 204 only transmits current in the direction perpendicular to the surface of the substrate 201, which can avoid the large current from the TSV 202 causing electromigration of the middle layer metal 204 and affecting the reliability of the chip structure, thereby improving the reliability of the three-dimensional integrated chip structure.

[0049] Specifically, in the embodiment, the interconnection structure has a plurality of middle layer metals 204, and adjacent middle layer metals 204 are connected in the direction perpendicular to the surface of the substrate 201 by a plug.

[0050] The middle layer metal 204 and the top layer metal 203 are connected by a plug. The material of the top layer metal 203 includes copper. The current from the TSV 202 flows through the middle layer metal 204, flows into the plug between the middle layer metal 204 and the top layer metal 203 in the direction perpendicular to the surface of the substrate 201, and then flows into the top layer metal 203.

[0051] Specifically, in the embodiment, the first wafer I has a plurality of interconnection structures, and the plurality of interconnection structures are connected one by one with the plurality of TSVs 202; and the top layer metals 203 of the plurality of interconnection structures are integrally connected.

[0052] The first wafer I has a plurality of interconnection structures and a plurality of TSVs 202 connected to the interconnection structures respectively, the intermediate metal 204 connected to the TSV 202 is separated from each other, and the top layer metal 203 of the plurality of interconnection structures is connected. The projection of the intermediate metal 204 connected to the TSV 202 on the surface of the substrate 201 is within the projection range of the top layer metal 203 on the surface of the substrate 201. When the TSV 202 receives current from the external circuit board 206, the intermediate metal 204 of each interconnection structure and the TSV 202 do not need to be provided with a long lead wire parallel to the surface direction of the substrate 201. The intermediate metal 204 corresponding to the TSV 202 vertically transmits current to the top layer metal 203 on the surface of the substrate 201, thereby improving the reliability of the three-dimensional integrated chip structure.

[0053] In other embodiments, the first wafer I can have one interconnection structure, and the interconnection structure is connected to one TSV. The projection of the intermediate metal of the interconnection structure in the direction parallel to the surface of the substrate is within the projection range of the top layer metal in the direction parallel to the surface of the substrate, and the projection of the TSV of the interconnection structure in the direction parallel to the surface of the substrate is within the projection range of the top layer metal in the direction parallel to the surface of the substrate.

[0054] Specifically, in the present embodiment, the top layer metal 203 is connected to a plurality of first connection points 200.

[0055] In other embodiments, the top layer metal 203 can be connected to one first connection point 200.

[0056] Specifically, in the present embodiment, the other end of the TSV 202 is connected to the pad 205.

[0057] In other embodiments, the other end of the TSV 202 can also be connected to a wire.

[0058] The bonding structure further comprises an external circuit board 206 connected to the TSV 202. Specifically, in the present embodiment, the external circuit board 206 is connected to the pad 205 through the solder ball.

[0059] Figure 4is a schematic diagram of a cross-sectional structure of a bonding structure according to another embodiment of the present application. The bonding structure comprises: a first wafer I and a second wafer II, the first wafer I and the second wafer II are bonded at a first connection point 300; the first wafer I comprises: a substrate 301; a TSV 302, the TSV 302 penetrates the substrate 301 along a thickness direction; an interconnection structure between the substrate 301 and the second wafer II, the interconnection structure comprises: a top metal layer 303 and an intermediate metal layer 304, the intermediate metal layer 304 is between the top metal layer 303 and the substrate 301, a thickness of the top metal layer 303 is greater than a thickness of the intermediate metal layer 304; a position of the intermediate metal layer 304 corresponds to a position of the TSV 302, the intermediate metal layer 304 is connected to one end of the TSV 302; in a direction parallel to a surface of the substrate 301, the top metal layer 303 extends from the position of the TSV 302 to a position of the first connection point 300.

[0060] Please refer to Figure 4 , the first wafer I and the second wafer II, the first wafer I and the second wafer II are bonded at a first connection point 300.

[0061] The bonding manner of the first wafer I and the second wafer II comprises: fusion bonding and hybrid bonding. The hybrid bonding includes at least one of the hybrid bonding of metal and inorganic film.

[0062] The projection of the first connection point 300 on the surface of the substrate 301 is within the projection range of the top metal layer 303 on the surface of the substrate 301.

[0063] Please refer to Figure 4 , the first wafer I comprises: a substrate 301.

[0064] The substrate 301 provides support for the interconnection structure.

[0065] The material of the substrate 301 comprises: silicon, silicon carbide, silicon germanium, silicon on insulator (SOI) or germanium on insulator (GOI).

[0066] Please refer to Figure 4 , the first wafer I comprises: a TSV 302, the TSV 302 penetrates the substrate 301 along a thickness direction.

[0067] Please refer to Figure 4 , the first wafer I comprises: the other end of the TSV 302 is connected with a redistribution layer 305.

[0068] One end of the TSV 302 is connected with the intermediate metal 304, and the other end of the TSV 302 is connected with the redistribution layer 305. The TSV 302 penetrates the substrate 301 along the direction of the surface of the vertical substrate 301, and connects the front surface and the back surface of the substrate 301, connects the redistribution layer 305 on the back surface of the first wafer I with the interconnection structure on the front surface of the first wafer I, and realizes the three-dimensional integration of multiple wafers.

[0069] The material of the TSV 302 includes metal.

[0070] Please refer to Figure 4 The first wafer I includes: an interconnection structure between the substrate 301 and the second wafer II, the interconnection structure includes: a top layer metal 303 and an intermediate metal 304, the intermediate metal 304 is between the top layer metal 303 and the substrate 301, the thickness of the top layer metal 303 is greater than the thickness of the intermediate metal 304; the position of the intermediate metal 304 corresponds to the position of the TSV 302, the intermediate metal 304 is connected with one end of the TSV 302; in the direction parallel to the surface of the substrate 301, the top layer metal 303 extends from the position of the TSV 302 to the position of the first connection point 300.

[0071] The top layer metal 303 extends from the position of the TSV 302 to the position of the first connection point 300 in the direction parallel to the surface of the substrate 301, so that the projection of the intermediate metal 304 on the surface of the substrate 301 is located within the projection range of the top layer metal 303 on the surface of the substrate 301, and the projection of the TSV 302 on the surface of the substrate 301 is located within the projection range of the top layer metal 303 on the surface of the substrate 301. The position of the intermediate metal 304 corresponds to the position of the TSV 302, that is, the projection of the TSV 302 on the surface of the substrate 301 is located within the projection range of the intermediate metal 304 on the surface of the substrate 301. The intermediate metal 304 is connected to one end of the TSV 302. The connection between the intermediate metal 304 and the TSV 302 does not require a long lead wire parallel to the surface of the substrate 301. The cross-sectional area of the current transmitted in the direction perpendicular to the surface of the substrate 301 is the thickness of the intermediate metal 304 multiplied by the width of the intermediate metal 304, while the cross-sectional area of the current transmitted in the direction parallel to the surface of the substrate 301 is the thickness of the intermediate metal 304 multiplied by the length of the intermediate metal 304. The length of the intermediate metal 304 is much larger than the width of the intermediate metal 304. The current carrying capacity of the intermediate metal 304 when the current is transmitted in the direction perpendicular to the surface of the substrate 301 is much larger than the current carrying capacity of the intermediate metal 304 when the current is transmitted in the direction parallel to the surface of the substrate 301. The intermediate metal 304 only transmits current in the direction perpendicular to the surface of the substrate 301, which can avoid the occurrence of electromigration in the intermediate metal 304 caused by large current and affect the reliability of the chip structure, thereby improving the reliability of the three-dimensional integrated chip structure.

[0072] Specifically, in the embodiment, the first wafer I has a plurality of interconnection structures, and each of the plurality of interconnection structures is connected to one of the plurality of TSVs 302. The top layer metals 303 of the plurality of interconnection structures are integrally connected.

[0073] In other embodiments, the first wafer I can have one interconnection structure, and the interconnection structure is connected to one TSV 302. The projection of the intermediate metal 304 of the interconnection structure in the direction parallel to the surface of the substrate 301 is located within the projection range of the top layer metal 303 in the direction parallel to the surface of the substrate 301, and the projection of the TSV 302 of the interconnection structure in the direction parallel to the surface of the substrate 301 is located within the projection range of the top layer metal 303 in the direction parallel to the surface of the substrate 301.

[0074] Specifically, in the embodiment, the intermediate metal 304 is a multi-layer structure, and adjacent intermediate metals 304 are connected in the direction perpendicular to the surface of the substrate 301 by a plug. The material of the plug is metal.

[0075] The intermediate metal 304 and the top metal 303 are connected by a plug. The material of the top metal 303 includes copper. The current from the top metal 303 flows into the intermediate metal 304 through the plug in the direction perpendicular to the surface of the substrate 301.

[0076] Please continue to refer to Figure 4 Specifically, in the embodiment, the first wafer I has a plurality of TSVs 302, and the plurality of TSVs 302 are connected to the same redistribution layer 305.

[0077] The first wafer I has a plurality of TSVs 302 and interconnection structures corresponding to the TSVs 302. The intermediate metals 304 corresponding to the TSVs 302 are mutually separated, and the projections of the intermediate metals 304 corresponding to the TSVs 302 on the surface of the substrate 301 are located within the projection range of the redistribution layer 305 on the surface of the substrate 301, and the projections of the TSVs 302 on the surface of the substrate 301 are located within the projection range of the intermediate metals 304 on the surface of the substrate 301.

[0078] Please refer to Figure 4 The bonding structure further includes: a third wafer III bonded to the first wafer I at a second connection point 306; and in the direction parallel to the surface of the substrate 301, the redistribution layer 305 extends from the position of the TSV 302 to the position of the second connection point 306.

[0079] Specifically, in the embodiment, the same redistribution layer 305 is connected to a plurality of second connection points 306.

[0080] In other embodiments, the redistribution layer 305 can be connected to one second connection point 306.

[0081] Correspondingly, the embodiment of the present application also provides a forming method for forming the above bonding structure, which will not be described here. Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various changes and modifications, therefore, the protection scope of the present application should be subject to the range defined by the claims.

Claims

1. A bonding structure, characterized in that Comprising: a first wafer and a second wafer, the first wafer and the second wafer are bonded at a first connection point; the first wafer comprises: a substrate; a TSV, the TSV penetrates the substrate along a thickness direction; an interconnection structure, the interconnection structure is between the substrate and the second wafer, the interconnection structure comprises: a top metal and an intermediate metal, the intermediate metal is between the top metal and the substrate, the thickness of the top metal is greater than the thickness of the intermediate metal; the position of the intermediate metal corresponds to the position of the TSV, the intermediate metal is connected to one end of the TSV; in the direction parallel to the surface of the substrate, the top metal extends from the position of the TSV to the position of the first connection point.

2. The bonded structure of Claim 1, wherein, The first wafer has a plurality of interconnection structures, and the plurality of interconnection structures are connected one by one with a plurality of TSVs; the top metals of the plurality of interconnection structures are integrally connected.

3. The bonded structure of Claim 1, wherein, The top metal is connected to a plurality of first connection points.

4. The bonded structure of Claim 1, wherein, The other end of the TSV is connected to a pad.

5. The bonding structure according to claim 1, wherein The other end of the TSV is connected to a redistribution layer.

6. The bonded structure of Claim 5, wherein, Further comprising: a third wafer, the third wafer is bonded with the first wafer at a second connection point; in the direction parallel to the surface of the substrate, the redistribution layer extends from the position of the TSV to the position of the second connection point.

7. The bonded structure of Claim 5, wherein, The first wafer has a plurality of TSVs, and the plurality of TSVs are connected to the same redistribution layer.

8. The bonded structure of claim 5, wherein, The same redistribution layer is connected to a plurality of second connection points.

9. The bonded structure of claim 1, wherein, The adjacent intermediate metals are connected by a plug.

10. The bonded structure of claim 1, wherein, The intermediate metal and the top metal are connected by a plug.

11. The bonded structure of claim 1, wherein, The material of the top metal comprises copper.

12. A method for forming a bonded structure, comprising: The forming method of the bonding structure forms the bonding structure as claimed in any one of claims 1 to 11.

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