Multi-phase power supply system with self-current balancing capability

Abstract

The invention relates to a multi-phase power supply system with self-current balancing capability. An apparatus includes a power converter controller. A power converter controller receives the first input. The amplitude of the first input is derived from a combined output current supplied to the load by the plurality of power converters. The power converter controller also receives a second input indicative of an amplitude of a first output current supplied from a first power converter of the plurality of power converters to the load. The combined output current includes a first output current supplied from the first power converter to the load. The power converter controller adjusts a leading edge and / or a trailing edge of the first pulse width modulation control signal based on a comparison of the second input and the first input. Additional examples to support signal edge control are discussed herein.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to power supply systems, and more particularly to multi-phase power supply systems with self-current balancing capability. BACKGROUND

[0002] One type of conventional power converter is a buck converter. Generally, to maintain an output voltage within a desired range, a controller associated with the buck converter compares a magnitude of the generated output voltage to a setpoint reference voltage. Based on a corresponding error voltage, the controller modifies a corresponding switching frequency and / or pulse width modulation associated with activating high-side and low-side switching circuitry in the buck converter to maintain the magnitude of the output voltage.

[0003] In certain instances, the controller controls operation of the buck converter and generation of the output voltage based on an amount of output current supplied by the generated output voltage to a load. For example, conventional techniques include receiving a so-called VID (voltage identification) from a load, such as a processor powered by the output voltage. The VID indicates a setpoint voltage in which the output voltage is produced to power the load. A magnitude of the VID setting, such as a setpoint reference voltage, can vary according to a magnitude of the output current. In a manner as previously described, a controller of the power supply can be configured to adjust a magnitude of the output voltage supplied to the load based on a target setpoint voltage derived from the received VID value.

[0004] Conventional power supply systems can include implementations of multiple buck converters in parallel to produce respective output voltages to power a load. Typically, the power supply system includes a single controller operable to generate control signals for each of the multiple power converter phases. If there are many phases controlled by the single controller, many circuit paths are needed to support communication of the control signals to each of the multiple power converter phases. Additionally, each power converter phase provides individual feedback to the single controller. Accordingly, additional circuit paths are needed to communicate the feedback from the multiple power converter phases to the single controller. SUMMARY

[0005] Implementing clean energy (or green technology) is very important to reduce the impact of human on the environment. Generally, clean energy includes any developed method and material to reduce the overall toxicity to the environment caused by energy consumption.

[0006] The present disclosure includes the observation that raw energy, such as received from green or non-green sources, often needs to be converted into an appropriate form (such as a desired AC voltage, DC voltage, etc.) before it can be used to power end devices (such as servers, computers, mobile communication devices, etc.). It is desirable to use the raw energy provided by such systems as efficiently as possible to reduce our impact on the environment, regardless of whether the energy is received from green or non-green sources. The present disclosure helps reduce our carbon footprint (and green energy) via more efficient energy conversion.

[0007] Additionally, the present disclosure includes the observation that it is desirable to reduce the number of circuit paths needed to support the communication of signals between a controller and a plurality of power converters controlled by the controller. Reducing the number of circuit paths advantageously reduces the complexity of implementing a power supply that includes a corresponding plurality of power converter phases.

[0008] More specifically, the controller discussed herein is operable to: receive a first input, an amplitude of the first input being derived from a combined output current supplied to a load from a plurality of power converters; receive a second input, the second input indicating an amplitude of a first output current supplied to the load from a first power converter of the plurality of power converters, the combined output current including the first output current; and adjust one or more edges (such as a leading edge and / or a trailing edge) of a first pulse width modulation control signal based on a comparison of the second input to the first input.

[0009] According to another example discussed herein, the first pulse width modulation control signal is operable to control an amplitude of the first output current supplied from the first power converter.

[0010] In one example, the adjusted leading edge and / or trailing edge of the first pulse width modulation control signal sets (controls) the amplitude of the first output current supplied from the first power converter to be substantially equal to the amplitude of the first input. The amplitude of the first input can be configured to indicate an average amplitude of current supplied to the load from the plurality of power converters.

[0011] According to another example, the first pulse width modulation control signal and the second pulse width modulation control signal are generated at the same frequency. Alternatively, the first pulse width modulation control signal and the second pulse width modulation control signal are generated at different frequencies.

[0012] Another example as discussed herein includes a first power converter controller operable to: receive a first control signal from a current controller, the first control signal generated by the current controller to control delivery of an output current from a plurality of power converters to a load; derive a second control signal from the received first control signal, the second control signal operable to control the first power converter; and wherein the second control signal includes a leading edge followed by a trailing edge, the leading edge of the second control signal adjusted by the first power converter controller over time to balance a magnitude of the output current from the plurality of converters. In one example, the leading edge of the second control signal is adjusted based on a difference between an average magnitude of the output current and a determined magnitude of a first output current output from the first power converter to the load.

[0013] Other examples discussed herein include an apparatus including a first power converter controller. The first power converter controller can be configured to: output a first output signal from the first power converter controller to a current controller over a shared signal path, the first output signal indicative of a magnitude of a first output current supplied by a first power converter phase to a load, the shared signal path operable to receive a second output signal from a second power converter controller, the second output signal indicative of a magnitude of a second output current supplied by a second power converter phase to the load; receive a first control signal from the current controller, the first control signal generated by the current controller based on the first output signal and the second output signal; and derive a second control signal from the received first control signal, a pulse width of the second control signal adjusted relative to a pulse width of the first control signal.

[0014] According to another embodiment discussed herein, the first power converter controller is further operable to derive the second control signal based on a first delay value and a second delay value. A leading edge of the first control signal is delayed by the first delay value to produce a leading edge of the second control signal; a trailing edge of the first control signal is delayed by the second delay value to produce a trailing edge of the second control signal.

[0015] In another example, the first power converter controller is further operable to: receive an input signal from the shared signal path, the received input signal indicative of an average magnitude value based on the first output current supplied by the first power converter phase to the load and the second output current supplied by the second power converter phase to the load; receive a first current monitor signal, the first current monitor signal indicative of a magnitude of the first output current; and generate the first delay value and the second delay value based on a comparison of: i) the received input signal indicative of the average magnitude value, and ii) the first current monitor signal indicative of the magnitude of the first output current.

[0016] Further, the first power converter controller can be configured to adjust the magnitude of the first delay value and the magnitude of the second delay value such that the magnitude of the second pulse width is greater than the magnitude of the first pulse width in response to detecting a condition that the magnitude of the first output current is less than the average magnitude value.

[0017] According to another embodiment, the first power converter controller can be configured to adjust the magnitude of the first delay value and the magnitude of the second delay value such that the magnitude of the second pulse width is less than the magnitude of the first pulse width in response to detecting a condition that the magnitude of the first output current is less than the average magnitude value.

[0018] In another embodiment, the first control signal is a first pulse width modulation control signal. The first power converter controller is operable to control the magnitude of the first output current based on the first pulse width modulation control signal received from the current controller. The second power converter controller is operable to control the magnitude of the second output current based on the first pulse width modulation control signal received from the current controller. The first control signal is a first pulse width modulation control signal. The first power converter controller is operable to control the magnitude of the first output current based on the first pulse width modulation control signal received from the current controller. The second power converter controller is operable to control the magnitude of the second output current based on a second pulse width modulation control signal received from the current controller.

[0019] In another example, the first power converter controller discussed herein is further operable to generate a first error signal based on a difference between a target value associated with producing the magnitude of the first output current and a measured magnitude of the first output current supplied to the load and generate a second error signal based on a difference between the target value associated with producing the magnitude of the first output current and the measured magnitude of the first output current supplied to the load. The first power converter controller adjusts the timing of a leading edge of the second control signal according to a magnitude and a polarity of the first error signal and adjusts the timing of a trailing edge of the second control signal according to a magnitude and a polarity of the second error signal. These operations can be performed in the same or different control cycles.

[0020] Further, the first power converter controller can be configured to control activation of a high-side switching circuit arrangement in the first power converter via the second control signal, the controlled activation of the high-side switching circuit arrangement using the second control signal, the second control signal being operable to substantially equalize the magnitudes of the first output current and the second output current over time.

[0021] In other examples, deriving the control signal from the received first control signal includes selecting a first delay signal from a first tapped delay line to control a respective timing of a leading edge of the second control signal and selecting a second delay signal from a second tapped delay line to control a respective timing of a trailing edge of the second control signal.

[0022] Further, the first power converter controller can be configured to implement a first current-starved inverter circuit to convert the first control signal to the second control signal, the first current-starved inverter circuit operable to control timing of a leading edge of the second control signal; and implement a second current-starved inverter circuit to convert the first control signal to the second control signal, the second current-starved inverter circuit operable to control timing of a trailing edge of the second control signal. A magnitude of the first delay provided by the first current-starved inverter circuit to control the timing of the leading edge of the second control signal can be based on a first error signal representing a difference between a target value controlling a magnitude of the first output current relative to a measured magnitude of the first output current; and a magnitude of the second delay provided by the second current-starved inverter circuit to control the timing of the trailing edge of the second control signal can be based on a second error signal representing a difference between the measured magnitude of the first output current relative to the target value controlling the magnitude of the first output current.

[0023] In another example, the first power converter controller can be configured to implement a first continuous delay element circuit to convert the first control signal to the second control signal, the first continuous delay element circuit operable to control timing of a leading edge of the second control signal; and implement a second continuous delay element circuit to convert the first control signal to the second control signal, the second continuous delay element circuit operable to control timing of a trailing edge of the second control signal. As before, the adjustments to the leading and trailing edges can occur in the same or different control cycles.

[0024] The techniques discussed herein are advantageous over conventional techniques. For example, the adjustment of the common pulse width modulation control signal by multiple power converter controllers to control their respective power converters provides a novel distributed control functionality that supports signal path reduction. This in turn supports efficient power conversion via less complex power converter circuitry.

[0025] These and other more specific examples are disclosed in greater detail below.

[0026] Note that although the examples discussed herein can apply to power converters, the concepts disclosed herein can be advantageously applied to any other suitable topology and general power supply control applications.

[0027] Note that any of the resources discussed herein can include one or more computerized devices, controllers, mobile communication devices, servers, base stations, wireless communication equipment, communication management systems, workstations, user devices, hand-held or laptop computers, etc., to perform and / or support any or all of the method operations disclosed herein. In other words, one or more computerized devices or processors can be programmed and / or configured to operate as explained herein to perform the different examples as described herein.

[0028] Other examples herein include software programs to perform the steps and operations summarized above and disclosed in detail below. One such example includes a computer program product which has a non-transitory computer readable storage medium (i.e., any computer readable hardware storage medium) encoded thereon with software instructions which, when executed in a computerized device having processor hardware, program and / or cause the processor hardware to perform the operations disclosed herein. Such arrangements are typically provided as software, code, instructions and / or other data (e.g., data structures) arranged or encoded on the non-transitory computer readable storage medium such as an optical medium (e.g., CD-ROM), floppy disk, hard disk, memory stick, memory device, etc., or other media such as firmware arranged on ROM, RAM, PROM, etc., or as an ASIC, etc. The software or firmware or other such configurations can be installed onto a computerized device to cause the computerized device to perform the techniques explained herein.

[0029] Accordingly, examples herein relate to methods, systems, computer program products, etc. that support the operations discussed herein.

[0030] One example herein includes a computer readable storage medium and / or system having instructions stored thereon. The instructions, when executed by computer processor hardware, cause the computer processor hardware (such as one or more co-located or remotely located processor devices) to: receive a first control signal from a current controller, the first control signal generated by the current controller to control delivery of output current from a plurality of power converters to a load; derive a second control signal from the received first control signal, the second control signal operable to control a first output current from a first power converter controlled by a first power converter controller; and wherein the second control signal includes a leading edge followed by a trailing edge, the leading edge of the second control signal adjusted over time by the first power converter controller to balance a magnitude of the output current from the plurality of converters.

[0031] Another example herein includes a computer-readable storage medium and / or system having instructions stored thereon. The instructions, when executed by computer processor hardware, cause the computer processor hardware, such as one or more co-located or separately located processor devices, to receive a first input, a magnitude of the first input being derived from a combined output current supplied to a load from a plurality of power converters; receive a second input, the second input indicating a magnitude of a first output current supplied to the load from a first power converter of the plurality of power converters, the combined output current including the first output current; and adjust a leading edge and a trailing edge of a first pulse width modulation control signal based on a comparison of the second input to the first input.

[0032] For clarity, the order of the above steps is added. Note that any of the processing operations discussed herein can be performed in any suitable order.

[0033] Other examples of the present disclosure include software programs and / or corresponding hardware to perform any of the method example steps and operations outlined above and disclosed in further detail below.

[0034] It should be understood that the systems, methods, apparatuses, instructions on computer-readable storage media, etc. as discussed herein can also be implemented strictly as software programs, firmware, hybrids of software, hardware, and / or firmware, or separate hardware such as within a processor (hardware or software) or within an operating system or within a software application.

[0035] As discussed herein, the technology herein is well suited for use in the field of implementing one or more power converters to deliver current to a load. However, it should be noted that the examples herein are not limited to use in such applications, and the technology discussed herein is well suited for other applications as well.

[0036] Additionally, it should be noted that while each of the different features, techniques, configurations, etc. herein can be discussed in

[0037] Further, it should be noted that this preliminary discussion of examples herein (SUMMARY) is not intended to intentionally limit or otherwise designate every example and / or incremental novel aspect of the present invention or claimed invention. Rather, this brief description merely presents general examples and corresponding points of novelty over conventional technology. For additional details and / or possible perspectives (arrangements) of the invention(s), the reader is directed to the Specific Embodiment portion of the disclosure (which is an overview of the examples) and corresponding drawings discussed further below. BRIEF DESCRIPTION OF DRAWINGS

[0038] Figure 1Ais an example diagram illustrating an implementation of a power converter including multiple power converter phases controlled by a multiphase controller as discussed herein.

[0039] Figure 1A is an example diagram illustrating a power converter and corresponding circuitry as discussed herein.

[0040] Figure 2A is an example diagram illustrating an implementation of a power converter including multiple power converter phases controlled by a multiphase controller as discussed herein.

[0041] Figure 2A is an example diagram illustrating a power converter and corresponding circuitry as discussed herein.

[0042] Figure 3 is an example timing diagram illustrating adjustment of a trailing edge of a pulse width modulation control signal to generate an output control signal as discussed herein.

[0043] Figure 4 is an example timing diagram illustrating adjustment of a leading edge of a pulse width modulation control signal to generate an output control signal as discussed herein.

[0044] Figure 5 is an example diagram illustrating a pulse width modulation signal generator operable to adjust a leading edge and / or a trailing edge of a respective received control signal as discussed herein.

[0045] Figure 6 is an example diagram illustrating a pulse width modulation signal generator operable to adjust a leading edge and / or a trailing edge of a respective received control signal as discussed herein.

[0046] Figure 7 is an example diagram illustrating a variable delay circuit operable to delay a clock signal as discussed herein.

[0047] Figure 8 is an example diagram illustrating delaying an input voltage associated with a variable delay circuit as discussed herein.

[0048] Figure 9 is an example diagram illustrating a hybrid pulse width modulation signal generator providing edge delay as discussed herein.

[0049] Figure 10 is an example diagram illustrating a hybrid pulse width modulation signal generator providing edge delay as discussed herein.

[0050] Figure 11 is an example diagram illustrating computer processor hardware and related software instructions operable to perform a method as discussed herein.

[0051] Figure 12is an example diagram illustrating methods and corresponding functionality associated with circuits as discussed herein.

[0052] Figure 13 is an example diagram illustrating methods and corresponding functionality associated with circuits as discussed herein.

[0053] Figure 14 is an example diagram illustrating methods and corresponding functionality associated with circuits as discussed herein.

[0054] The foregoing and other objects, features and advantages of the application will be apparent from the following more particular description of preferred examples, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the examples, principles, concepts, etc. DETAILED DESCRIPTION

[0055] Figure 1A is an example diagram illustrating implementation of a power converter including multiple power converter phases controlled by a multiphase controller as discussed herein.

[0056] As shown, Figure 1A The power supply 100 in includes a controller 140 (such as a multiphase controller, a current controller, controller hardware, etc.), a resistor R11, a resistor R21, a power converter phase 111, a power converter phase 112, a power converter phase 121, a power converter phase 122, an output capacitor C1, and a dynamic load 118.

[0057] Each power converter discussed herein can be configured to include a respective current balancer functionality (also referred to as a current balancer, a controller, hardware, circuitry, etc., such as based on digital circuitry, based on analog circuitry, or based on a combination of analog circuitry and digital circuitry).

[0058] For example, the power converter phase 111 includes a current balancer functionality DCB11, the power converter phase 112 includes a current balancer functionality DCB12, the power converter phase 121 includes a current balancer functionality DCB21, and the power converter phase 122 includes a current balancer functionality DCB22.

[0059] Accordingly, each current balancer functionality discussed herein can be considered a controller, a signal generator, etc.

[0060] Each power converter phase in the power supply 100 generates a respective feedback signal indicative of a magnitude of a corresponding current supplied by that power converter phase to the load 118.

[0061] For example, power converter phase 111 includes a corresponding current monitor operable to measure a magnitude of current i11supplied by power converter phase 111 through inductor L11 to a corresponding load 118. Current i11helps to maintain a magnitude of output voltage 123 at a desired setpoint reference voltage VREF1. Current balancing function DCB11 produces a corresponding output signal ISEN11 indicative of the magnitude of current i11. In one example, signal ISEN11 is a current proportional to the magnitude of current i11. Signal ISEN11 is output from corresponding current balancing function DCB11 to node N11 (circuit path), where the corresponding current from signal ISEN11 flows through resistor R11 to a ground reference voltage.

[0062] Power converter phase 112 includes a corresponding current monitor operable to measure a magnitude of current i12supplied by power converter phase 112 through inductor L12 to a corresponding load 118. Current i12helps to maintain a magnitude of output voltage 123 at a desired setpoint reference voltage VREF1. Current balancing function DCB12 produces a corresponding signal ISEN12 indicative of the magnitude of current i12. In one example, signal ISEN12 is an output current proportional to the magnitude of current i12. Signal ISEN12 is output from corresponding current balancing function DCB12 to node N11, where the corresponding current from signal ISEN12 flows through resistor R11 to a ground reference voltage.

[0063] In this case, voltage IAVG1 at node N11 is indicative of a magnitude of total current provided by power converter phase 111 and power converter phase 112 to load 118 (such as a magnitude of total current as a sum of current i11and current i12). Thus, communication of signal IAVG1 to controller 140 is indicative of a total current provided by the combination of power converter phase 111 and power converter phase 112 to load 118.

[0064] Power converter phase 121 includes a corresponding current monitor operable to measure a magnitude of current i21supplied by power converter phase 121 through inductor L21 to a corresponding load 118. Current i21helps to maintain a magnitude of output voltage 123 at a desired setpoint reference voltage VREF1. Current balancing function DCB21 produces a corresponding signal ISEN21 indicative of the magnitude of current i21. In one example, signal ISEN21 is a current proportional to the magnitude of current i21. Signal ISEN21 is output from corresponding current balancing function DCB21 to node N21 (such as a circuit path), where the corresponding current from signal ISEN21 flows through resistor R21 to a ground reference voltage.

[0065] The power converter phase 122 includes a corresponding current monitor operable to measure a magnitude of a current i22supplied by the power converter phase 122 through the inductor L22 to the corresponding load 118. The current i22helps to maintain a magnitude of the output voltage 123 at a desired setpoint reference voltage VREF1. A current balancing function DCB22 produces a corresponding signal ISEN22 indicative of the magnitude of the current i22. In one example, the signal ISEN22 is a current proportional to the magnitude of the current i22. The signal ISEN22 is output from the corresponding current balancing function DCB22 to the node N21, where the corresponding current from the signal ISEN22 flows through the resistor R21 to the ground reference voltage.

[0066] In this case, the voltage IAVG2 at the node N12 is indicative of a magnitude of a total current provided by the power converter phase 121 and the power converter phase 122 to the load 118 (such as the total current is a sum of the current i21and the current i22). Thus, communication of the signal IAVG2 to the controller 140 is indicative of a total current provided by the combination of the power converter phase 121 and the power converter phase 122 to the load 118.

[0067] As further shown in FIG. 1, the controller 140 can be configured to receive a feedback signal 131 indicative of a magnitude of the output voltage 123. It is also noted that the controller 140 also receives a setpoint reference voltage VREF1 indicative of a desired magnitude at which it is desired to control the magnitude of the output voltage 123.

[0068] The controller 140 generates a pulse width modulated control signal PWM1 to control a magnitude of a respective output current supplied by each of the power converter phase 111 and the power converter phase 112 to the load 118. The controller 140 generates a pulse width modulated control signal PWM2 to control a magnitude of a respective output current supplied by each of the power converter phase 121 and the power converter phase 122 to the load 118.

[0069] To further control (adjust) the magnitude of the output voltage 123, the controller 140 produces respective pulse width modulated control signals PWM1 and PWM2. A respective group of each power converter phase receives a respective pulse width modulated control signal indicative of a target magnitude of the respective output current to the load. Rather than simply using the received pulse width modulated control signal received from the controller 140, each power converter phase implements a respective current balancing function that supports balancing of the magnitude of the output current to the load 118 through the group (such as a first group including the power converter phase 111, the power converter phase 112, etc., or a second group including the power converter phase 121, the power converter phase 122, etc.).

[0070] More specifically, the controller 140 generates a corresponding pulse width modulation control signal PWM1 and supplies it to the power converter phase 111 and the power converter phase 112 through the node N12 (i.e., circuit path).

[0071] As discussed herein, the respective current balancing functionality of each power converter adjusts the received pulse width modulation control signal PWM1 to control its respective output current such that each power converter supplies an equal amount of current (e.g., i11 equals i12) to the load 118. Thus, the functionality of providing current balancing among multiple power converter phases, as discussed herein, is distributed to the power converter phases themselves as opposed to the controller 140 having the burden of generating and sending separate control signals to each power converter phase.

[0072] As further shown, the controller 140 generates a corresponding pulse width modulation control signal PWM2 and supplies it to the power converter phase 121 and the power converter phase 122 through the node N22 (i.e., circuit path). As discussed herein, the respective current balancing functionality of each power converter adjusts the received pulse width modulation control signal PWM2 such that each power converter supplies an equal amount of current (e.g., i21 equals i22) to the load 118. Thus, the functionality of providing current balancing among multiple power converter phases is distributed to the power converter phases themselves as opposed to the controller 140 having the burden of generating and sending separate control signals to each power converter phase.

[0073] It should also be noted that the controller 140 can be configured to control groups of power converter phases to provide different magnitudes of current to the respective load 118. For example, the controller 140 can be configured to generate the control signal PWM1 to supply a first magnitude of current (the sum of currents i11 and i12, such as 20 amps or other suitable amount) from the combination of the power converter phase 111 and the power converter phase 112 to the load. The controller 140 can be configured to generate the control signal PWM2 to supply a second magnitude of current (the sum of currents i21 and i22, such as 40 amps or other suitable amount) from the combination of the power converter phase 121 and the power converter phase 122 to the load 118.

[0074] Figure 1B is an example diagram illustrating a power converter and corresponding circuitry as discussed herein.

[0075] This example diagram illustrates the circuitry associated with each power converter phase as Figure 1A shown. As discussed below, the value of X can be 1 or 2. If desired, this can be extended to include any number of parallel power converter phases.

[0076] For example, each respective power converter phase (power converter phase 111, 112, etc.) includes a current balancing function DCBIX, a driver circuit arrangement 150-X, a high-side switch circuit arrangement S1X-H, a low-side switch circuit arrangement S1X-L, an inductor L1X, and a current monitor 21X.

[0077] As previously mentioned, the current balancing function DCBIX receives a pulse width modulated control signal PWM1 generated by the controller 140. The current balancing function DCBIX also receives a signal IPHASEIX indicative of the magnitude of the respective output current i1X supplied by that power converter phase to the load 118.

[0078] In addition, as previously mentioned, the current balancing function DCBIX receives a signal IAVG1. The current balancing function DCBIX also includes a comparator function 191-X (such as an error signal generator). As the name implies, the comparator function 191-X (differential function) is operable to compare the signal IAVG1 (setpoint or target value) to the signal (IPHASE1X) and generate a respective error signal ES1X. The error signal ES1X is indicative of the respective difference between the actual output current iX1 supplied to the load 118 relative to the desired setpoint output current value IAVG1. For example, the error signal ES1X can be set equal to the signal IAVG1 minus the signal IPHASE1X.

[0079] If the magnitude of the error signal ES1X is equal to 0, then the pulse width of the pulse width modulated control signal PWMXC output from the current balancing function DCBIX is substantially the same as the received pulse width modulated signal PWMX, with a small delay on each respective leading and trailing edge of the control signal PWMXC.

[0080] If the magnitude of the error signal ES1X is a negative value (first state of polarity) indicating that the magnitude of the output current iX1 indicated by the signal IPHASE1 is greater than the magnitude of the current indicated by the signal IAVG1, then the current balancing function DCBIX generates a respective pulse width modulated control signal PWMXC for the next control cycle having a shorter duty cycle (shorter pulse width) activating the respective high-side switch circuit arrangement S1X-H relative to the original duty cycle indicated by the pulse width modulated control signal PWMX.

[0081] If the magnitude of the error signal ES1X is positive (the polarity is the second state), indicating that the magnitude of the output current iX1 indicated by the signal IPHASE1 is less than the magnitude of the current indicated by the signal IAVG1, the current balancing function DCB1X generates a corresponding pulse width modulated control signal PWMXC for the next control period having a higher duty cycle (longer pulse width on time of the high side switching circuit device) activating the corresponding high side switching circuit device S1X-H relative to the original duty cycle indicated by the pulse width modulated control signal PWMX.

[0082] Thus, the controlled activation of the high side switching circuit device S1X-H in the first power converter phase via the control signal PWM1XC can be used to equalize the magnitudes of the first output current i11 and the second output current i12 over time (such that the magnitudes are within 2% or other appropriate value of each other).

[0083] As discussed herein, by adjusting one or more of the leading or trailing edges of the corresponding control signal PWMXC, the duty cycle or pulse width on time associated with the adjusted pulse width modulated control signal PWMXC can be increased or decreased. Thus, the leading or trailing edges of the control signal PWMXC can be adjusted based at least in part on a difference between the average magnitude of the output current (IAVG1) and the determined magnitude of the first output current (IPHASE1X) output from the corresponding power converter (111 or 112 depending on the case) to the load 118.

[0084] Thus, examples herein include a current balancing function DCB1X (i.e., a first power converter controller) operable to: receive an input signal (IAVG1) from the shared signal path (N11), the received input signal indicating an average magnitude value based on a first output current i11 supplied by a first power converter phase 111 to a load and a second output current i12 supplied by a second power converter phase 112 to the load; receive a first current monitor signal (IPHASE1X) indicating a magnitude of the first output current i11; and generate a first delay value and / or a second delay value based on a comparison of i) the received input signal indicating the average magnitude value, and ii) the first current monitor signal indicating the magnitude of the first output current. The first power converter controller is further operable to derive a second control signal PWMXC based on the first delay value and the second delay value, such as in the same or different control period; wherein a leading edge of the first control signal PWMX is delayed by the first delay value to generate a leading edge of the second control signal PWMXC; and wherein a trailing edge of the first control signal is delayed by the second delay value to generate a trailing edge of the second control signal.

[0085] As further discussed herein, the current balancing function DCB1X is further operable to, in response to detecting a condition that the magnitude of the first output current is less than the average magnitude, adjust the magnitude of the first delay value and the magnitude of the second delay value such that the magnitude of the second pulse width associated with the control signal PWMXC is greater than the magnitude of the first pulse width (associated with the high-side switch circuit device on-time indicated by PWM1).

[0086] As further discussed herein, the current balancing function DCB1X is further operable to, in response to detecting a condition that the magnitude of the first output current is less than the average magnitude, adjust the magnitude of the first delay value and the magnitude of the second delay value such that the magnitude of the second pulse width associated with the control signal PWMXC is greater than the magnitude of the first pulse width (associated with the high-side switch circuit device on-time indicated by PWM1).

[0087] Figure 2A is an example diagram illustrating an implementation of a power converter including multiple power converter phases controlled by a multiphase controller as discussed herein.

[0088] As shown, Figure 2A The power supply 100-2 includes a controller 140 (such as a multiphase controller, a current controller, controller hardware, etc.), a resistor R4, a power converter phase 101, a power converter phase 102, a power converter phase 103, a power converter phase 104, an output capacitor Cl, and a dynamic load 118.

[0089] Each power converter discussed herein can be configured to include a respective current balancer function (also referred to as a current balancer, a controller, hardware, circuitry, etc., such as based on digital circuitry, based on analog circuitry, or based on a combination of analog circuitry and digital circuitry). For example, the power converter phase 101 includes a current balancing function DCB1, the power converter phase 102 includes a current balancing function DCB2, the power converter phase 103 includes a current balancing function DCB3, and the power converter phase 104 includes a current balancing function DCB4.

[0090] Accordingly, each current balancing function discussed herein can be considered a controller, a signal generator, etc.

[0091] Each power converter phase in the power supply 100-1 generates a respective feedback signal that indicates a magnitude of a corresponding current supplied by that power converter phase to the load 118.

[0092] For example, power converter phase 101 includes a corresponding current monitor operable to measure a magnitude of current il supplied by power converter phase 101 through inductor LI to a corresponding load 118. Current il helps to maintain a magnitude of output voltage 123 at a desired setpoint reference voltage VREF1. Current balancing function DCB1 generates a corresponding signal ISEN1 indicative of the magnitude of current il. In one example, signal ISEN1 is a current proportional to the magnitude of current il. Signal ISEN1 is output from corresponding current balancing function DCB1 to node N31 (circuit path) where a corresponding current from signal ISEN1 flows through resistor R4 to a ground reference voltage.

[0093] Power converter phase 102 includes a corresponding current monitor operable to measure a magnitude of current i2supplied by power converter phase 102 through inductor L2 to a corresponding load 118. Current i2helps to maintain a magnitude of output voltage 123 at a desired setpoint reference voltage VREF1. Current balancing function DCB2 generates a corresponding signal ISEN2 indicative of the magnitude of current i2. In one example, signal ISEN2 is a current proportional to the magnitude of current i2. Signal ISEN2 is output from corresponding current balancing function DCB2 to node N31 where a corresponding current from signal ISEN2 flows through resistor R4 to a ground reference voltage.

[0094] Power converter phase 103 includes a corresponding current monitor operable to measure a magnitude of current i3supplied by power converter phase 103 through inductor L3 to a corresponding load 118. Current i3helps to maintain a magnitude of output voltage 123 at a desired setpoint reference voltage VREF1. Current balancing function DCB3 generates a corresponding signal ISEN3 indicative of the magnitude of current i3. In one example, signal ISEN3 is a current proportional to the magnitude of current i3. Signal ISEN3 is output from corresponding current balancing function DCB3 to node N31 where a corresponding current from signal ISEN3 flows through resistor R4 to a ground reference voltage.

[0095] The power converter phase 104 includes a corresponding current monitor operable to measure a magnitude of a current i4supplied by the power converter phase 104 through the inductor L4 to the corresponding load 118. The current i4helps to maintain a magnitude of the output voltage 123 at a desired setpoint reference voltage VREF1. The current balancing function DCB4 produces a corresponding signal ISEN4 indicative of the magnitude of the current i4. In one example, the signal ISEN4 is a current proportional to the magnitude of the current i4. The signal ISEN4 is output from the corresponding current balancing function DCB4 to the node N31, where the corresponding current from the signal ISEN4 flows through the resistor R4 to the ground reference voltage.

[0096] In this case, the voltage IAVG at the node N31 is indicative of a magnitude of a total current provided by the power converter phases 101, 102, 103, and 104 to the load 118 (such as the total current is a sum of the currents i1, i2, i3, and i4). Thus, communication of the signal IAVG to the controller 140 is indicative of the total current provided by the combination of the power converter phases to the load 118.

[0097] As Figure 2A As further shown, the controller 140 can be configured to receive a feedback signal 131 indicative of a magnitude of the output voltage 123. It is also noted that the controller 140 also receives a setpoint reference voltage VREF1 indicative of a desired magnitude to control the magnitude of the output voltage 123.

[0098] The controller 140 generates a pulse width modulated control signal PWM1 to control a magnitude of the corresponding output current i1supplied by the power converter phase 101 to the load 123.

[0099] The controller 140 generates a pulse width modulated control signal PWM2 to control a magnitude of the corresponding output current i2supplied by the power converter phase 102 to the load 123.

[0100] The controller 140 generates a pulse width modulated control signal PWM3 to control a magnitude of the corresponding output current i3supplied by the power converter phase 103 to the load 123.

[0101] The controller 140 generates a pulse width modulated control signal PWM4 to control a magnitude of the corresponding output current i4supplied by the power converter phase 104 to the load 123.

[0102] To further control the magnitude of the output voltage 123, the controller 140 produces the corresponding pulse width modulated control signals PWM1, PWM2, PWM3, and PWM4. Rather than simply using the received pulse width modulated control signals received from the controller 140, each power converter phase implements a corresponding current balancing function that supports equalizing the magnitude of the output current to the load 118.

[0103] More specifically, the controller 140 generates and supplies a respective pulse width modulated control signal PWM1 to the power converter 101. As discussed herein, a respective current balancing function DCB1 of the power converter 101 regulates the pulse width modulated control signal PWM1 to generate a pulse width modulated control signal PWM1C; a respective current balancing function DCB2 of the power converter 102 regulates the pulse width modulated control signal PWM2 to generate a pulse width modulated control signal PWM2C; a respective current balancing function DCB3 of the power converter 103 regulates the pulse width modulated control signal PWM3 to generate a pulse width modulated control signal PWM3C; a respective current balancing function DCB4 of the power converter 104 regulates the pulse width modulated control signal PWM4 to generate a pulse width modulated control signal PWM4C; and so on.

[0104] Thus, the functionality of providing current balancing among the plurality of power converter phases is distributed to the power converter phases themselves, as opposed to the controller 140 having the burden of generating and sending separate control signals to balance the current from each power converter phase.

[0105] Figure 2B is an example diagram illustrating a power converter and corresponding circuitry as discussed herein.

[0106] This example diagram illustrates circuitry associated with each power converter phase 10Y as Figure 2A shown. As discussed below, the value of Y can be 1, 2, 3, or 4. If desired, this can be extended to include any number of PWM signals.

[0107] For example, each respective power converter phase 10Y includes a current balancing function DCBY, a driver circuit 150-Y, a high-side switch circuit SY-H, a low-side switch circuit SY-L, an inductor LY, and a current monitor 2Y.

[0108] As previously mentioned, the current balancing function DCBY receives a pulse width modulated control signal PWMY generated by the controller 140. The current balancing function DCBY also receives a signal IPHASEY indicative of the magnitude of the respective output current iY supplied by the power converter phase 10Y to the load 118.

[0109] Additionally, as previously mentioned, the current balancing function DCBY receives the signal IAVG. The current balancing function DCBY also includes a comparator function 191-Y (e.g., error signal generator). As the name implies, the comparator function 191-Y (differencing function) is configured to compare the signal IAVG (setpoint value or target value) and the signal (IPHASEY) to produce a corresponding error signal ESY. The error signal ESY indicates a corresponding difference between the actual output current iY supplied to the load 118 relative to the desired setpoint output current value IAVG. For example, the error signal ESY can be set equal to the signal IAVG minus the signal IPHASEY.

[0110] If the magnitude of the error signal ESY is equal to 0, then the pulse width modulated control signal PWMYC output from the current balancing function DCBY is substantially identical to the received pulse width modulated signal PWMY with a small delay on each corresponding leading and trailing edge.

[0111] If the magnitude of the error signal ESY is a negative value (polarity is a first state) indicating that the magnitude of the output current iY indicated by the signal IPHASEY is greater than the magnitude of the current indicated by the signal IAVG, then the current balancing function DCBY generates a corresponding pulse width modulated control signal PWMYC for the next control cycle having a shorter duty cycle (shorter pulse width) activating the corresponding high side switching circuit device SY-H relative to the original duty cycle indicated by the pulse width modulated control signal PWMY.

[0112] If the magnitude of the error signal ESY is a positive value (polarity is a second state) indicating that the magnitude of the output current iY indicated by the signal IPHASEY is less than the magnitude of the current indicated by the signal IAVG, then the current balancing function DCBY generates a corresponding pulse width modulated control signal PWMYC for the next control cycle having a higher duty cycle (longer pulse width) activating the corresponding high side switching circuit device SY-H relative to the original duty cycle indicated by the pulse width modulated control signal PWMX.

[0113] Accordingly, the controlled activation of the high side switching circuit device SY-H in the first power converter phase via the control signal PWMYC can be used to ensure that the magnitude of the output current iY is substantially equal to the magnitude of the average current over time indicated by the signal IAVG.

[0114] As discussed herein, the duty cycle or pulse width associated with the adjusted pulse width modulation control signal PWMYC can be increased or decreased by adjusting one or more of the leading edge and / or the trailing edge of the corresponding control signal PWMYC. Thus, the leading edge or the trailing edge of the control signal PWMYC can be adjusted based on a difference between the average magnitude of the output current (IAVG) and the determined magnitude of the first output current (IPHASEY) output from the corresponding power converter 10Y to the load 118.

[0115] Figure 3 is an example timing diagram illustrating adjustment of the trailing edge of a pulse width modulation control signal as discussed herein.

[0116] In this example implementing a trailing edge timing adjustment based on Figure 1A the current balancing function DCB1X (where X equals 1 or 2) receives the control signal PWM1 as previously described and converts it to the corresponding control signal PWM1XC. In the event that the magnitude of the output current i1X as indicated by the signal IPHASE1X is less than the target average current value IAVG1, the corresponding current balancing function DCB1X delays the corresponding trailing edge of the control signal PWMXC, resulting in an increase in the time that the high side switching circuit arrangement S1X-H is activated during the corresponding control period. In other words, the delay of the trailing edge associated with the control signal PWMXC (from time T12 to time T13 or other suitable time such as indicated by the trailing edge delay 392) results in a longer conduction time of the corresponding high side switching circuit arrangement S1X-H during the corresponding control period, which increases the magnitude of the corresponding output current i1X as shown in Figure 3 supplied by the output current i1X-1 to the load 118. Figure 3 The signal i1X-2 in indicates a lower magnitude of the output current i1X using the original signal PWM1X without lengthening the conduction duration of the high side switching circuit arrangement S1X-H via the delay of the trailing edge.

[0117] Thus, the pulse width of the control signal PWM1X is between time T11 and time T13. The adjusted pulse width (longer pulse width) associated with the signal PWM1XC is between time T12 and time T14.

[0118] Figure 2AThe current balancing functions in FIG. 1 operate in a similar manner. More specifically, in this example where trailing edge timing adjustment is implemented, the current balancing function DCBY (where Y equals 1 through 4) receives the control signal PWMY and converts it to the control signal PWMYC in the manner discussed above. In the event that the magnitude of the output current iY indicated by the signal IPHASEY is less than the target average current value IAVG, the corresponding current balancing function DCB1Y delays the respective trailing edge of the control signal PWMYC, resulting in an increased time that the high-side switching circuit device S1Y-H is activated during the respective control period. The delay of the trailing edge associated with the control signal PWMYC (from time T12 to time T13 or other suitable time) results in an increased on-time of the respective high-side switching circuit device S1Y-H during the respective control period, which increases the magnitude of the output current iY-1 supplied to the load 118 by the output current iY as shown in FIG. 1. Figure 3 The signal iY-2 in FIG. 1 indicates a lower magnitude of the output current iY without lengthening the on-duration of the high-side switching circuit device S1Y-H. Figure 3

[0119] It should be noted that, as discussed herein, adjustment of the trailing edge of the respective control signal, such as via the delay ΔTON, changes the pulse width on-duration associated with the initially received pulse width modulation signal PWM1X or PWMY to generate the corresponding pulse width modulation control signal PWM1XC or PWMYC without changing the corresponding switching frequency. In other words, the switching frequency of the pulse width modulation control signal that is generated and output by the current balancing function is the same as the pulse width modulation control signal received by the current balancing function from the controller 140. As Figure 3 Further shown, the period associated with cycle #1 is the period associated with cycle #2.

[0120] Figure 4 is an example timing diagram illustrating adjustment of the leading edge of a pulse width modulation control signal as discussed herein.

[0121] In this example where leading edge timing adjustment is implemented, based on Figure 1A , the current balancing function DCB1X (where X equals 1 or 2) receives the control signal PWM1 and converts it to the control signal PWMXC. In the event that the magnitude of the output current i1X indicated by the signal IPHASE1X is greater than the target average current value IAVG1, the corresponding current balancing function DCB1X delays the respective leading edge of the control signal PWMXC, resulting in a decreased time that the high-side switching circuit device S1X-H is activated during the respective control period. The delay 491 (from approximately time T31 to time T32 or other suitable time) associated with the leading edge of the control signal PWMXC results in a shorter on-time of the respective high-side switching circuit device S1X-H during the respective control period, which decreases the magnitude of the output current i1X-1 supplied to the load 118 by the output current i1X as shown in FIG. 1.​Figure 4 the respective output current i1X supplied to the load 118 as shown. Figure 4 The signal i1X-2 in the signal i1X-2 indicates a higher magnitude of the output current i1X without reducing the on duration of the high-side switch circuit device S1X-H. Thus, the current balancer function discussed herein can be configured to delay the leading edge of the control signal PWM1XC by an amount of delay 491 and to delay the trailing edge of the control signal PWM1XC by an amount of delay 492 to produce the control signal PWM1XC1.

[0122] Figure 2A The current balancing functions in the power supply of FIG. 5 operate in a similar manner. More specifically, in this example where the leading edge timing adjustment is implemented, the current balancing function DCBY (where Y equals 1 to 4) receives the control signal PWMY and converts it to the control signal PWMYC. In the event that the magnitude of the output current iY as indicated by the signal IPHASEY is greater than the target average current value IAVG, the corresponding current balancing function DCB1Y delays the respective leading edge of the control signal PWMYC by an amount of delay such as the delay 491, resulting in a reduction in the time that the high-side switch circuit device S1Y-H is activated during the corresponding control cycle. The delay of the leading edge associated with the control signal PWMYC (from time T31 to time T32 or other suitable time such as the delay time 491) results in a shorter on time of the corresponding high-side switch circuit device SY-H during the corresponding control cycle, which reduces the magnitude of the output current iY supplied to the load 118 as shown. Figure 4 the respective output current iY supplied to the load 118 as shown. Figure 4 The signal iY-2 in the signal iY-2 indicates a higher magnitude of the output current iY without shortening the on duration of the high-side switch circuit device SY-H.

[0123] Figure 5 is an example diagram illustrating a pulse width modulated signal generator operable to adjust the leading and trailing edges of a respective received control signal as discussed herein.

[0124] In this example, the current balancing function DCBZ (such as any of the current balancing functions DCB11, DCB12, DCB21, DCB22, DCB1, DCB2, DCB3, DCB4, etc. discussed previously) includes Figure 5 the respective examples of circuit devices such as the amplifier A11, the amplifier A12, the integrator circuit 551, the integrator circuit 552, the trailing edge clock generator 511, the leading edge clock generator 512, the circuit device 541 providing discrete trailing edge duty correction, the circuit device 542 providing discrete leading edge duty correction, and the circuit device 599 providing dual edge duty correction.

[0125] As further shown, integrator circuit 551 includes resistor R51 and capacitor C51. Integrator circuit 552 includes resistor R52 and capacitor C52.

[0126] The trailing edge clock generator 511 includes a D flip-flop element 521. The leading edge clock generator 512 includes a D flip-flop element 531.

[0127] In this example, the signal PWMIN represents the corresponding signal PWM1, PWM2, PWM3, PWM4, PWM1X, PWMY, etc., as previously described. The trailing edge clock generator 511 includes a D flip-flop 521 that forwards the received PWMIN clock signal to a tapped delay line that includes a series connection of tapped delay line elements TL11, TL12, TL13, TL14. As their name implies, each tapped delay line element delays the corresponding input pulse width modulated PWMIN signal by the same or different amount of time.

[0128] The integrator circuit 551 includes an amplifier A11, a resistor R51, and a capacitor C51. The amplifier A11 produces a corresponding signal VCTRL_TRL that indicates or is based on a difference between an IPHASE signal (such as any of IPHASE11, IPHASE12, IPHASE21, IPHASE22, IPHASE1, IPHASE2, IPHASE3, IPHASE4) and an IAVG signal (such as any of IAVG1, IAVG2, IAVG, etc.), which depends on the instantiation of the current balancing function. A node N51 that connects the resistor R51 and the capacitor C51 stores a corresponding error signal VCTRL_TRL that is supplied to an analog-to-digital converter 561. The analog-to-digital converter 561 converts the received signal VCTRL_TRL to signals D1 and D0 that are supplied to a multiplexer 562. The multiplexer 562 uses the received signals D1 and D0 as address lines to select which delayed version of the PWM signal as a signal 563 output to the D flip-flop 522. Subsequent circuitry, such as D flip-flop 523, D flip-flop 524, logic 525, D flip-flop 528, uses the signal 591 as a basis for adjustment of the trailing edge of the control signal PWMC (such as signal PWM1XC or PWMYC), as indicated in the previous timing diagram.

[0129] via Figure 5 As previously discussed, when the magnitude of the current supplied by the corresponding power converter phase as indicated by the signal IPHASE is less than the current as specified by the signal IAVG, the trailing edge of the corresponding signal PWMC is delayed by the amount of change selected by the multiplexer 562, via the current balancing function (i.e., circuit) shown in FIG. 5B.

[0130] For example, the analog-to-digital converter 561 generates a select signal with C0 = 0 and C1 = 0 (to inputs of the multiplexer 562) in response to a condition that the amplitude of the current indicated by the signal IPHASE is less than or equal to the signal IAVG (based on the amplitude of the error signal VCTRL_TRL). In this case, the multiplexer 562 selects the signal Z0 (1 unit of time delay 392 for the trailing edge delay time 392 or minimum time delay) as the signal 563 to output.

[0131] The analog-to-digital converter 561 generates a select signal with C1 = 0 and C0 = 1 (to inputs of the multiplexer 562) in response to a condition that the amplitude of the current indicated by the signal IPHASE is 2 amperes or some other suitable value less than the number of amperes indicated by the signal IAVG (based on the amplitude of the error signal VCTRL_TRL). In this case, the multiplexer 562 selects the signal Z1 (2 unit time delay 392 for the trailing edge delay time 392) as the signal 563 to output. Via the trailing edge delay as shown in FIG. 4B, the delay of the trailing edge as indicated by the signal Z1 increases the amplitude of the on-time associated with the high-side switching circuit arrangement as previously described such that the actual current provided by the power converter phase is closer to the value as indicated by the signal IAVG. Figure 3

[0132] The analog-to-digital converter 561 generates a select signal with C1 = 1 and C0 = 0 (to inputs of the multiplexer 562) in response to a condition that the amplitude of the current indicated by the signal IPHASE is 4 amperes or some other suitable value less than the number of amperes indicated by the signal IAVG (based on the amplitude of the error signal VCTRL_TRL). In this case, the multiplexer 562 selects the signal Z2 (4 unit time delay 392 for the trailing edge delay time 392) as the signal 563 to output. Via the trailing edge delay as shown in FIG. 4C, the delay of the trailing edge as indicated by the signal Z2 increases the amplitude of the on-time associated with the high-side switching circuit arrangement as previously described such that the actual current provided by the power converter phase is closer to the value as indicated by the signal IAVG. Figure 3

[0133] The analog-to-digital converter 561 generates a select signal with C1 = 1 and C0 = 1 (to inputs of the multiplexer 562) in response to a condition that the amplitude of the current indicated by the signal IPHASE is 6 amperes or some other suitable value less than the number of amperes indicated by the signal IAVG (based on the amplitude of the error signal VCTRL_TRL). In this case, the multiplexer 562 selects the signal Z3 (6 unit time delay 392 for the trailing edge delay time 392) as the signal 563 to output. Via the trailing edge delay as shown in FIG. 4D, the delay of the trailing edge as indicated by the signal Z3 increases the amplitude of the on-time associated with the high-side switching circuit arrangement as previously described such that the actual current provided by the power converter phase is closer to the value as indicated by the signal IAVG. Figure 3 ​​The illustrated trailing edge delay, an increase in the magnitude of the turn-on time associated with the high-side switch circuit arrangement as previously described, as indicated by the trailing edge of signal Z3, causes the actual current provided by the power converter phase to be closer to the value as indicated by signal IAVG.

[0134] In this example, signal PWMIN represents the corresponding signals PWM1, PWM2, PWM3, PWM4, PWM1X, PWMY, etc. as previously described. The trailing edge clock generator 512 includes a D flip-flop 531 that forwards the PWMIN clock signal to a tapped delay line including tapped delay line elements TL21, TL22, TL23, TL24. As their name implies, each tapped delay line element delays the respective input pulse width modulated PWMIN signal.

[0135] The integrator circuit 552 includes an amplifier A12, a resistor R52, and a capacitor C52. The amplifier A12 produces a respective signal VCTRL_LED that is based on or indicative of the difference between the IPHASE signal (such as any of IPHASE11, IPHASE12, IPHASE21, IPHASE22, IPHASE1, IPHASE2, IPHASE3, IPHASE4) and the IAVG signal (such as any of IAVG1, IAVG2, IAVG, etc.). A node N52 connecting the resistor R52 and the capacitor C52 stores a respective error signal VCTRL_LED that is supplied to an analog-to-digital converter 571. The analog-to-digital converter 571 converts the received signal VCTRL_LED to signals D1 and D0 that are supplied to a multiplexer 572. The multiplexer 572 uses the received signals D1 and D0 to select which delayed version of the PWM signal to output as signal 573 to the D flip-flop 532. Subsequent circuitry such as D flip-flop 533, D flip-flop 534, logic 535, D flip-flop 528 uses the signal 592 as the basis for adjusting the leading edge of the signal PWMC (such as signal PWM1XC or PWMYC) as needed.

[0136] Via Figure 5 As previously discussed, the current balancing function (i.e. circuit) illustrated in FIG. 6, when the magnitude of the current supplied by the corresponding power converter phase as indicated by signal IPHASE is greater than the current as specified by signal IAVG, the leading edge of the respective signal PWMC is delayed by the amount of the change selected by the multiplexer 572.

[0137] For example, the analog-to-digital converter 571 generates a select signal with C0 = 0 and CI = 0 (to inputs of the multiplexer 572) in response to a condition that the amplitude of the current indicated by the signal IPHASE is greater than or equal to the signal IAVG (based on the amplitude of the error signal VCTRL LED). In this case, the multiplexer 572 selects the signal B0 (a 1 -unit time delay 491 of the leading edge in the signal B0) as the signal 573 to output. Figure 4

[0138] The analog-to-digital converter 571 generates a select signal with CI = 0 and C0 = 1 (to inputs of the multiplexer 572) in response to a condition that the amplitude of the current indicated by the signal IPHASE is 2 amperes or some other value greater than the amperage indicated by the signal IAVG (based on the amplitude of the error signal VCTRL LED). In this case, the multiplexer 572 selects the signal B1 (a 2-unit time delay 491 of the leading edge in the signal B1) as the signal 573 to output. The delay of the leading edge as indicated by the signal B1 reduces the amplitude of the on-time associated with the high-side switching circuit arrangement as previously discussed, such that the actual current provided by the power converter phase is closer to the value as indicated by the signal IAVG. Figure 4 Figure 4 The analog-to-digital converter 571 generates a select signal with CI = 1 and C0 = 0 (to inputs of the multiplexer 572) in response to a condition that the amplitude of the current indicated by the signal IPHASE is 4 amperes or some other appropriate value greater than the amperage indicated by the signal IAVG (based on the amplitude of the error signal VCTRL LED). In this case, the multiplexer 572 selects the signal B2 (a 4-unit time delay 491 of the leading edge in the signal B2) as the signal 573 to output. The delay of the leading edge as indicated by the signal B2 reduces the amplitude of the on-time associated with the high-side switching circuit arrangement as previously discussed, such that the actual current provided by the power converter phase is closer to the value as indicated by the signal IAVG.

[0139] The analog-to-digital converter 571 generates a select signal with CI = 1 and C0 = 1 (to inputs of the multiplexer 572) in response to a condition that the amplitude of the current indicated by the signal IPHASE is 6 amperes or some other appropriate value greater than the amperage indicated by the signal IAVG (based on the amplitude of the error signal VCTRL LED). In this case, the multiplexer 572 selects the signal B2 (a 6-unit time delay 491 of the leading edge in the signal B2) as the signal 573 to output. The delay of the leading edge as indicated by the signal B2 reduces the amplitude of the on-time associated with the high-side switching circuit arrangement as previously discussed, such that the actual current provided by the power converter phase is closer to the value as indicated by the signal IAVG. Figure 4 Figure 4

[0140] Figure 4 Figure 4 ​​​​​​The illustrated leading edge delay, as indicated by the delay of the leading edge of signal B3, reduces the magnitude of the on-time associated with the high-side switch circuit arrangement as previously discussed, such that the actual current provided by the power converter phase is closer to the value as indicated by signal IAVG.

[0141] Thus, as Figure 5 The illustrated current balancing circuit DCB provides leading edge or trailing edge adjustment to reduce the control signal PWMC in accordance with whether the output current from the phase is greater than, equal to, or less than the desired average current value as indicated by the corresponding signal IAVG for the power converter phase.

[0142] Thus, deriving the control signal PWMC from the received control signal PWMIN in accordance with whether the output current provided by the corresponding power converter phase is greater than or less than IAVG can include selecting a first delay signal from a first tapped delay line to control the respective timing of the leading edge of the control signal PWMC, and selecting a second delay signal from a second tapped delay line to control the respective timing of the trailing edge of the second control signal PWMC.

[0143] Figure 6 is an example diagram illustrating a pulse width modulation signal generator operable to adjust the leading edge and / or the trailing edge of a respective received control signal as discussed herein.

[0144] In this example, the power converter phase DCBZ includes a continuous trailing edge duty cycle correction circuit 641 as an alternative to the discrete trailing edge duty cycle correction circuit 541. Additionally, the power converter phase DCBZ includes a continuous leading edge duty cycle correction circuit 642 as an alternative to the discrete leading edge duty cycle correction circuit 542.

[0145] The continuous trailing edge duty cycle correction circuit 641 includes a variable delay circuit 625-1, a D flip-flop 621, a D flip-flop 522, and an amplifier circuit arrangement 651. The continuous leading edge duty cycle correction circuit 642 includes a variable delay circuit 625-2, a D flip-flop 622, a D flip-flop 532, and an amplifier circuit arrangement 652.

[0146] In a similar manner as previously described, the integrator circuit 551 generates a respective voltage at node N51 indicative of the magnitude of the error between the signal IPHASE and IAVG. The error signal is communicated to the amplifier circuit arrangement 651, which converts the voltage at node N51 to a respective signal VCTRL_TRL supplied to the variable delay circuit 625-1. The variable delay circuit 625-1 receives the original signal PWMIN, and as its name implies, varies the amount of delay applied to the trailing edge of the received control signal PWMIN (392) in accordance with the magnitude of the signal VCTL_TRL to generate the control signal PWMC. Figure 7Details of the variable delay circuit of 625-1 are shown.

[0147] via Figure 6 The illustrated current balancing function (i.e., circuit) is such that, as previously discussed, when the magnitude of the current supplied by the corresponding power converter phase, as indicated by signal IPHASE, is less than the current specified by signal IAVG, the trailing edge of the corresponding signal PWMC is delayed by a variable amount selected by variable delay circuit 625-X. For example, as the difference between signal IPHASE and signal IAVG increases (when IPHASE is less than IAVG), the magnitude of the delay (VCTRL), which controls the adjustment of the trailing edge delay 392 of the resulting control signal PWMC, also increases. Thus, as previously discussed, the magnitude of the pulse width associated with control signal PWMC increases over time as the magnitude of IPHASE becomes significantly less than the average current indicated by IAVG.

[0148] Figure 7 is an example diagram illustrating a variable delay circuit operable to delay a clock signal as discussed herein.

[0149] In this example, the variable delay circuit 625-X includes a plurality of field effect transistors Q1-Q9. The power supply 715 applies an input voltage Vcc to power the corresponding variable delay circuit 625-X. The variable delay circuit 625-X receives the clock signal CLK at a node N5X and outputs a delayed clock signal CLKd at a node N6X. Figure 8 The graph 810 in FIG. 8 illustrates the amount of delay between the clock CLK and the output clock CLKd according to the input control signal VCTRL (for the leading edge VCTRL_TRL or the trailing edge VCTRL_LED).

[0150] In one example, the variable delay circuit 625-X can be a current-starved inverter. In this case, a first power converter controller associated with the power converter phase (such as a current balancing function DCB) is configured to implement a first current-starved inverter circuit (such as the variable delay circuit 625-1) to convert the first control signal PWMIN (PWM1X) into the control signal PWM1XC, wherein the first current-starved inverter circuit is operable to control the timing of the trailing edge of the control signal PWMC as desired.

[0151] As previously discussed, the variable delay circuit 625-X can be a current starved inverter. In this case, the first power converter controller associated with the power converter phase, such as the current balancing function DCB, is configured to implement a second current starved inverter circuit, such as the variable delay circuit 625-2, to convert the first control signal PWMIN (PWM1X) to the control signal PWM1XC, where the second current starved inverter circuit is operable to control the timing of the leading edge of the control signal PWMC as needed.

[0152] Figure 8 is an example plot illustrating the delay as a function of the input voltage associated with a variable delay circuit as discussed herein.

[0153] In this example, the plot 800 includes a function 810 indicating the amount of time delay (in delay leading edge or delay trailing edge) provided by the variable delay circuit as previously discussed. Note that the function 810 can vary depending on the parameters associated with the corresponding variable delay circuit, such as temperature, etc.

[0154] Referring again to Figure 6 In a similar manner as previously discussed, the integrator circuit 552 generates a corresponding voltage at node N52 indicative of the magnitude of the error between the signals IPHASE and IAVG. The signal at node N52 is passed to the amplifier circuit arrangement 652, which converts the voltage at node N52 to a corresponding signal VCTRL LED that is supplied to the variable delay circuit 625-2. The variable delay circuit 625-2 receives the original signal PWMIN and, as its name implies, varies the amount of delay applied to the leading edge of the received control signal PWMIN (491) as a function of the magnitude of the signal VCTL LED to generate the control signal PWMC. Figure 7 Details for the variable delay circuit for 625-2 are shown.

[0155] Via Figure 6 The current balancing function (i.e., circuit) shown, as previously discussed, delays the leading edge of the corresponding signal PWMC by a varying amount selected by the variable delay circuit 625-2 when the magnitude of the current supplied by the corresponding power converter phase as indicated by the signal IPHASE is greater than the current as specified by the signal IAVG. For example, as the difference between the signal IPHASE and the signal IAVG increases (when IPHASE is greater than IAVG), the magnitude of the delay (VCTRL) that controls the adjustment of the leading edge of the final control signal PWMC also increases. Thus, as previously discussed, as the magnitude of IPHASE becomes much greater than the average current indicated by IAVG, the magnitude of the pulse width associated with the control signal PWMC decreases over time.

[0156] Accordingly, examples herein include controlling the magnitude of a first delay amount 491 provided by a first current-starved inverter circuit (625-2) to control the timing of the leading edge of the control signal PWMC based on a first error signal (signal VCTRL_LED) that captures a difference between a target value (IAVG) of the magnitude of the corresponding output current of the power converter phase relative to a measured magnitude of the output current (IPHASE1) provided by the power converter phase.

[0157] In the opposite case, examples herein include controlling the magnitude of a second delay amount 391 provided by a second current-starved inverter circuit (625-1) to control the timing of the trailing edge of the control signal PWMC based on a second error signal (signal VCTRL_TRL) that captures a difference between a target value (IAVG) of the magnitude of the corresponding output current of the power converter phase relative to a measured magnitude of the output current (IPHASE1) provided by the power converter phase.

[0158] Figure 9 is an example diagram illustrating a hybrid pulse width modulation signal generator as discussed herein.

[0159] In this example, the power converter phase DCBZ includes a hybrid trailing edge duty cycle correction circuit 941 that serves as a replacement for the discrete trailing edge duty cycle correction circuit 541 in Figure 6 Additionally, the power converter phase DCBZ includes a hybrid leading edge duty cycle correction circuit 942 that serves as a replacement for the discrete leading edge duty cycle correction circuit 542.

[0160] In this example, a circuit 991 (such as a combination of an amplifier A11, a resistor R91, a capacitor C91, a current source K1, etc.) produces a corresponding control signal VCTRL_TRL based on a difference between the signal IPHASE and IAVG. The hybrid trailing edge duty cycle correction circuit 941 includes multiple stages (such as the circuit 581 and the variable delay circuit 625-1 connected in series).

[0161] In a manner similar to the foregoing, a combination of an analog-to-digital converter 561 and a multiplexer 562 associated with the circuit 581 provides a first trailing edge delay amount.

[0162] The hybrid trailing edge duty cycle correction circuit 941 also includes a circuit 651 for producing a control signal VCTRL_TRL1 from VCTRL_TRL. The control signal VCTRL_TRL1 controls the variable delay circuit 625-1 in a manner as previously described. When the magnitude of IPHASE is less than IAVG, the variable delay circuit 625-1 also provides an additional delay associated with the trailing edge of the control signal PWMC. Accordingly, the combination of the discrete delay functions in the variable delay circuit will delay the corresponding trailing edge by any appropriate amount.

[0163] In this example, circuit 992 (such as a combination of amplifier A12, resistor R92, capacitor C92, current source K2, etc.) generates a corresponding control signal VCTRL LED based on the difference between signals IPHASE and IAVG. Hybrid trailing edge duty cycle correction circuit 942 includes multiple stages (such as series connected circuit 582 and variable delay circuit 625-2). In a manner similar to the foregoing, the combination of analog-to-digital converter 562 and multiplexer 562 associated with circuit 582 provide a first amount of trailing edge delay. Hybrid trailing edge duty cycle correction circuit 942 also includes circuit 652 operable to generate control signal VCTRL LED1 from VCTRL LED. Control signal VCTRL LED1 controls variable delay circuit 625-2 in a manner as previously described. Variable delay circuit 625-2 also provides an additional delay associated with the trailing edge of control signal PWMC when the amplitude of IPHASE is less than IAVG. Thus, the combination of discrete delay functions in variable delay circuit delays the corresponding trailing edge by any appropriate amount.

[0164] Figure 10 is an example diagram illustrating a hybrid pulse width modulation signal generator as discussed herein.

[0165] In this example, power converter phase DCBZ includes hybrid trailing edge duty cycle correction circuit 1041 as a replacement for discrete trailing edge duty cycle correction circuit 541. In addition, power converter phase DCBZ includes hybrid leading edge duty cycle correction circuit 1042 as a replacement for discrete leading edge duty cycle correction circuit 542.

[0166] As Figure 10 illustrated, hybrid trailing edge duty cycle correction circuit 1041 includes variable delay circuit 625-1 as well as discrete delay circuit 581. Hybrid trailing edge duty cycle correction circuit also includes circuit 651 for monitoring the amplitude of the error associated with the difference between signals IPHASE and IAVG.

[0167] If the amplitude of the error is above the threshold, then circuit 651 causes the multiplexer to use the output of variable delay circuit 625-1 to select channel SO for transmission to D flip-flop 522, in which case the trailing edge associated with signal PWMC is generated based on the output of variable delay circuit 625-1.

[0168] If the amplitude of the error is above the threshold, then circuit 651 causes the multiplexer to use the output of circuit 581 transmitted to D flip-flop 522 to select channel S1, in which case the trailing edge associated with signal PWMC is generated based on the output of circuit 581.

[0169] As Figure 10Further shown, the hybrid front porch duty cycle correction circuit 1042 includes a variable delay circuit 625-2 and a discrete delay circuit 582. The hybrid front porch duty cycle correction circuit also includes a circuit 652 for monitoring the magnitude of the error associated with the difference between the signals IPHASE and IAVG.

[0170] If the magnitude of the error is above a threshold, then the circuit 652 causes the multiplexer to use the output of the variable delay circuit 625-2 to select channel SO for transmission to the D flip-flop 532, in which case the leading edge associated with the signal PWMC is generated based on the output of the variable delay circuit 625-2.

[0171] If the magnitude of the error is above a threshold, then the circuit 652 causes the multiplexer to use the output of the circuit 582 to select channel SI for transmission to the D flip-flop 532, in which case the leading edge associated with the signal PWMC is generated based on the output of the circuit 582.

[0172] Figure 11 is an example block diagram of a computer device for implementing any of the operations as discussed herein according to the examples herein.

[0173] As shown, the computer system 1150 of the present example (such as implemented by any of the one or more resources such as the controller 140, the current balancing function DCB, etc.) includes an interconnect 1111, a processor 1113 (e.g., a computer processor hardware such as one or more processor devices), an I / O interface 1114 (e.g., for outputting control signals to power converter phases, monitoring currents, etc.), and a communication interface 1117, the interconnect 1111 coupling a computer readable storage medium 1112 such as a non-transitory type of medium (or hardware storage medium) that can store and retrieve digital information.

[0174] The I / O interface 1114 provides a connection to any appropriate circuitry such as power converter phases.

[0175] The computer readable storage medium 1112 can be any hardware storage resource or device such as a memory, optical storage, hard disk drive, floppy disk, etc. In one example, the computer readable storage medium 1112 stores instructions and / or data used by the controller application 140-1 (such as implemented by any of the controller 140, DCB, etc. to support front porch and / or back porch signal adjustment) to perform any of the operations described herein.

[0176] Further, in this example, the communication interface 1117 enables the computer system 1100 and processor 1113 to communicate through resources such as the network 190 to retrieve information from remote sources and communicate with other computers.

[0177] As shown, the computer-readable storage medium 1112 encodes a controller application 140-1 (e.g., software, firmware, etc.) that is executed by the processor 1113. The controller application 140-1 can be configured to include instructions that implement any of the operations discussed herein.

[0178] During operation of one example, the processor 1113 accesses computer- readable storage medium 1112, via the use of interconnect 1111, to retrieve or fetch instructions from controller application 140-1 stored thereon for execution.

[0179] Execution of the controller application 140-1 produces processing functionality, such as the controller process 140-1 in the processor 1113. In other words, the controller process 140-B associated with the processor 1113 represents one or more aspects of executing the controller application 140-A within or on the processor 1113 in the computer system 1100.

[0180] According to different examples, note that the computer system 1100 can be a microcontroller device, logic, a hardware processor, hybrid analog / digital circuitry, etc., that is configured to control power and perform any of the operations described herein.

[0181] The functionality supported by the different resources will now be discussed via the flowcharts in Figure 12

[0182] Figure 12 is an example diagram illustrating a method of controlling a power converter and corresponding edge control according to examples herein.

[0183] In processing operation 1210, the current balancing function DCB11 receives a first input, such as voltage IAVGl. The magnitude of the first input (voltage IAVGl, which is indicative of the average current supplied by the combination of current i11 and current i12) is derived from the combined output current (sum of i11 + i12) supplied to the load 118 from the plurality of power converters (111 and 112).

[0184] In processing operation 1220, the current balancing function DCB11 receives a second input, such as signal IPHASE11, which is indicative of the magnitude of the first output current i11 supplied to the load 118 from the first power converter 111. As previously mentioned, the combined output current 122 supplied to the load 118 includes the output current i11.

[0185] ​In process operation 1230, the current balancing function DCB11 adjusts a leading edge and / or a trailing edge of the first pulse width modulated control signal PWM1 based on a comparison of the second input (signal IPHASE11) and the first input (IAVG1) to generate a corresponding adjusted pulse width modulated control signal PWM1C to control operation of switches (high side switch circuitry S1X-H and low side switch circuitry S1X-L where X equals 1) in the power converter phase 111.

[0186] As previously mentioned, the current balancing function DCB12 and other current balancing functions operate in a similar manner as the current balancing function DCB11 described above.

[0187] Figure 13 is an example diagram illustrating controlling a power converter and implementing a corresponding edge control method in accordance with examples herein.

[0188] In process operation 1310, the current balancing function DCB11 receives a first control signal PWM1 from the current controller 140. The first control signal PWM1 is generated by the current controller 140 to control delivery of output currents (such as currents i11, i12, etc.) from the plurality of power converters 111, 112, etc. to the load 118.

[0189] In process operation 1320, the current balancing function DCB11 derives a second control signal PWM1C from the received first control signal PWM1, where the second control signal PWM1C is operable to control operation of the first power converter 111.

[0190] In process operation 1330, the second control signal PWM1C includes a leading edge followed by a trailing edge. In one example discussed herein, process operation 1330 includes the current balancing function DCB1 adjusting the leading edge and / or the trailing edge associated with the second control signal PWM1C over time to balance the magnitude of the output currents (i11, i12, etc.) from the plurality of converters to the load 118.

[0191] Figure 14 is an example diagram illustrating controlling a power converter and implementing a corresponding edge control method in accordance with examples herein.

[0192] In process operation 1410, current balancing function DCB 11, such as a first power converter controller associated with power converter 111, outputs a first output signal ISEN 11 to current controller 140 over a shared signal path (node N11). The output signal indicates a magnitude of a first output current i11 supplied by the first power converter phase 111 to load 118. The shared signal path, such as node N11, receives a second output signal ISEN 12 from a second current balancing function DCB 12, such as a second power converter controller associated with power converter 112. The second output signal ISEN 12 indicates a magnitude of a second output current i12 supplied by the second power converter 112 to load 118.

[0193] In process operation 1420, current balancing function DCB 11 receives a first control signal PWM1 from current controller 140. Current controller 140 generates the first control signal PWM1 based on a combination of the first output signal ISEN 11 and the second output signal ISEN 12. For example, currents ISEN 11 and ISEN 12 produce a respective voltage signal IAVG1 that indicates an average current supplied by the combination of i11 and i12.

[0194] In process operation 1430, current balancing function DCB 11 associated with power converter 111 derives a second control signal PWM1C from the received first control signal PWM1. Via implementation of a leading edge delay, a trailing edge delay, or a combination of both, current balancing function DCB 11 adjusts a pulse width duration of the second control signal PWM1C relative to a pulse width of the first control signal PWM1.

[0195] Again, note that the techniques herein work well for applications such as circuitry that implements power conversion. However, note that the examples herein are not limited to use in such applications, and the techniques discussed herein are well suited for other applications as well.

[0196] Based on the description set forth herein, numerous specific details have been set forth in order to provide a thorough understanding of the claimed subject matter. However, it will be understood by those skilled in the art that the claimed subject matter can be practiced without these specific details. In other instances, methods, apparatuses, systems, etc. have not been described in detail in order to avoid obscuring the claimed subject matter. Some portions of the detailed description have been presented in terms of algorithms or symbolic representations of operations on data bits or binary digital signals stored within a computing system memory, such as a computer memory. These algorithmic descriptions or representations are examples of techniques used by those of ordinary skill in the data processing arts to convey the substance of their work to others. An algorithm is here, and generally, is considered to be a self-consistent sequence of operations or similar processing leading to a desired result. In this context, operations or processing involve physical manipulation of physical quantities. Typically, although not necessarily, such quantities can take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to such signals as bits, data, values, elements, symbols, characters, terms, numbers, numerals, or the like. It should be understood, however, that all of these and similar terms are to be associated with appropriate physical quantities and are merely convenient labels. Unless specifically stated otherwise, as apparent from the following discussion, it is appreciated that throughout the description, discussions utilizing terms such as "processing," "computing," "calculating," "determining," or the like, refer to the action or processes of a computing platform, such as a computer or a similar electronic computing device, that manipulates or transforms a physical electronic or magnetic quantities within the computing platform's registers and memories and other information storage, transmission, or display devices into other data bits, values, elements, symbols, characters, terms, numbers, or the like.

[0197] While the application has been particularly shown and described with reference to particular embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the application as defined by the appended claims. Such changes are intended to fall within the scope of the application. Also, the above description is that of the best mode of the application and reflective of the inventors' best understanding of the principles of the application. However, the application is not limited to the details of this description but can be practiced with modifications within the scope of the appended claims.

Claims

1. An apparatus comprising: a power converter controller operable to: receive a first input, an amplitude of the first input being derived from a combined output current supplied from a plurality of power converters to a load; receive a second input, the second input indicating an amplitude of a first output current supplied from a first power converter of the plurality of power converters to the load, the combined output current including the first output current; and based on a comparison of the second input to the first input, adjust a leading edge and a trailing edge of a first pulse width modulation control signal.

2. The apparatus of claim 1, wherein the first pulse width modulation control signal is operable to control an amplitude of the first output current supplied from the first power converter.

3. The apparatus of claim 1, wherein the adjusted leading edge and the trailing edge of the first pulse width modulation control signal are operable to set the amplitude of the first output current supplied from the first power converter to be substantially equal to an amplitude of the first input.

4. The apparatus of claim 3, wherein the amplitude of the first input indicates an average amplitude of current supplied from the plurality of power converters to the load.

5. The apparatus of claim 1, wherein the power converter controller is further operable to: receive the first pulse width modulation control signal from a pulse width modulation signal generator that controls operation of the plurality of power converters; derive a second pulse width modulation control signal from the received first pulse width modulation control signal, the adjusted leading edge and the trailing edge being a trailing edge; and output the second pulse width modulation control signal to the first power converter.

6. The apparatus of claim 5, wherein the first pulse width modulation control signal and the second pulse width modulation control signal are generated at the same frequency.

7. An apparatus comprising: a first power converter controller operable to: receive a first control signal from a current controller, the first control signal being generated by the current controller to control delivery of an output current from a plurality of power converters to a load; derive a second control signal from the received first control signal, the second control signal being operable to control a first power converter; and wherein the second control signal includes a leading edge followed by a trailing edge, the leading edge of the second control signal being adjusted over time by the first power converter controller to balance an amplitude of the output current from the plurality of converters.

8. The apparatus of claim 7, wherein the leading edge of the second control signal is adjusted based on a difference between an average amplitude of the output current and a determined amplitude of the first output current output from the first power converter to the load.

9. An apparatus comprising: a first power converter controller operable to: ​ ​ outputting a first output signal from the first power converter controller to a current controller over a shared signal path, the first output signal indicative of a magnitude of a first output current supplied by a first power converter phase to a load, the shared signal path operable to receive a second output signal from a second power converter controller, the second output signal indicative of a magnitude of a second output current supplied by the second power converter to the load; receiving a first control signal from the current controller, the first control signal generated by the current controller based on the first output signal and the second output signal; and deriving a second control signal from the received first control signal, a pulse width of the second control signal adjusted relative to a pulse width of the first control signal.

10. The apparatus of claim 9, wherein the first power converter controller is further operable to derive the second control signal based on a first delay value and a second delay value; wherein a leading edge of the first control signal is delayed by the first delay value to produce a leading edge of the second control signal; and wherein a trailing edge of the first control signal is delayed by the second delay value to produce a trailing edge of the second control signal.

11. The apparatus of claim 10, wherein the first power converter controller is further operable to: receive an input signal from the shared signal path, the received input signal indicative of an average magnitude value based on the first output current supplied by the first power converter phase to the load and the second output current supplied by the second power converter phase to the load; receive a first current monitor signal indicative of a magnitude of the first output current; and generate the first delay value and the second delay value based on a comparison of i) the received input signal indicative of the average magnitude value and ii) the first current monitor signal indicative of the magnitude of the first output current.

12. The apparatus of claim 11, wherein the first power converter controller is further operable to: in response to detecting a condition that the magnitude of the first output current is less than the average magnitude value, adjust a magnitude of the first delay value and a magnitude of the second delay value such that the magnitude of the second pulse width is greater than the magnitude of the first pulse width.

13. The apparatus of claim 11, wherein the first power converter controller is further operable to: in response to detecting a condition that the magnitude of the first output current is less than the average magnitude value, adjust a magnitude of the first delay value and a magnitude of the second delay value such that the magnitude of the second pulse width is less than the magnitude of the first pulse width.

14. The apparatus of claim 11, wherein the first control signal is a first pulse width modulation control signal; wherein the first power converter controller is operable to control the magnitude of the first output current based on the received first pulse width modulation control signal from the current controller; and wherein the second control signal is a second pulse width modulation control signal. wherein the second power converter controller is operable to control the magnitude of the second output current based on the first pulse width modulation control signal received from the current controller.

15. The apparatus of claim 9, wherein the first control signal is a first pulse width modulation control signal; wherein the first power converter controller is operable to control the magnitude of the first output current based on the first pulse width modulation control signal received from the current controller; and wherein the second power converter controller is operable to control the magnitude of the second output current based on a second pulse width modulation control signal received from the current controller.

16. The apparatus of claim 9, wherein the first power converter controller is further operable to: generate a first error signal based on a difference between a target value associated with producing the magnitude of the first output current and a measured magnitude of the first output current supplied to the load; and generate a second error signal based on a difference between the target value associated with producing the magnitude of the first output current and the measured magnitude of the first output current supplied to the load.

17. The apparatus of claim 16, wherein the first power converter controller is further operable to: adjust a timing of a leading edge of the second control signal according to a magnitude and a polarity of the first error signal; and adjust a timing of a trailing edge of the second control signal according to a magnitude and a polarity of the second error signal.

18. The apparatus of claim 17, wherein the first power converter controller is further operable to: control activation of a high-side switching circuit device in the first power converter via the second control signal, the controlled activation of the high-side switching circuit device using the second control signal, the second control signal operable to substantially equalize the magnitudes of the first output current and the second output current over time.

19. The apparatus of claim 9, wherein deriving the control signal from the received first control signal comprises: selecting a first delay signal from a first tapped delay line to control a respective timing of a leading edge of the second control signal; and selecting a second delay signal from a second tapped delay line to control a respective timing of a trailing edge of the second control signal.

20. The apparatus of claim 9, wherein the first power converter controller is operable to: implement a first current-starved inverter circuit to convert the first control signal to the second control signal, the first current-starved inverter circuit operable to control a timing of a leading edge of the second control signal; and implement a second current-starved inverter circuit to convert the first control signal to the second control signal, the second current-starved inverter circuit operable to control a timing of a trailing edge of the second control signal.

21. The apparatus of claim 20, wherein a magnitude of a first amount of delay provided by the first current-starved inverter circuit to control the timing of the leading edge of the second control signal is based on a first error signal representing a difference between a target value for controlling the magnitude of the first output current relative to a measured magnitude of the first output current; and wherein a magnitude of a second amount of delay provided by the second current-starved inverter circuit to control the timing of the trailing edge of the second control signal is based on a second error signal representing a difference between the measured magnitude of the first output current relative to the target value for controlling the magnitude of the first output current.

22. The apparatus of claim 9, wherein the first power converter controller is operable to: implement a first continuous delay element circuit to convert the first control signal to the second control signal, the first continuous delay element circuit operable to control a timing of a leading edge of the second control signal; and implement a second continuous delay element circuit to convert the first control signal to the second control signal, the second continuous delay element circuit operable to control a timing of a trailing edge of the second control signal.

Images