Clock data recovery method and apparatus based on injection locking

Abstract

This invention provides a clock data recovery method and apparatus based on injection-locked oscillator. The method includes sampling an analog clock signal to obtain an initial sampled signal; detecting a clock error in the initial sampled signal to obtain a clock error signal; performing a first digital filtering process on the clock error signal to obtain a first clock control signal; acquiring a clock jitter estimate output from a digital filter within an injection-locked oscillator; injecting the clock jitter estimate into the clock error signal and performing a second digital filtering process; calculating a second clock control signal based on the clock signal after the second digital filtering process; and adjusting the phase of the sampled clock signal based on the first and second clock control signals. This invention also provides an apparatus for implementing the above method. The clock data recovery method of this invention has strong clock jitter tracking capability and low noise, and can be applied to next-generation communication technologies.

Description

Technical Field

[0001] This invention relates to the field of clock data processing technology, specifically to a clock data recovery method based on injection locking and an apparatus for implementing this method. Background Technology

[0002] With the development of mobile internet, cloud computing, big data, artificial intelligence, and other technologies, related industries have seen a significant increase in demand for high-speed data center communication bandwidth, power consumption, and connection density. To meet this increased demand for bandwidth, the single-channel rate of high-speed serial communication is continuously improving. Currently, single-channel 100Gbps systems are mature and widely used, and the relevant standards for the next-generation single-channel 200Gbps system are largely complete. Compared to single-channel 100Gbps systems, single-channel 200Gbps systems double the symbol rate, placing more stringent demands on system clock jitter. In high-speed serial communication systems, Clock Data Recovery (CDR) technology is a crucial means of tracking and eliminating clock jitter. Therefore, to ensure signal quality in single-channel 200Gbps systems, a more efficient clock data recovery method is needed to eliminate clock jitter.

[0003] Currently, high-speed serial communication systems widely use digital signal processors (DSPs) based on analog-to-digital converters (ADCs) to recover clock data at the receiver. To reduce the complexity and latency of the DSP, a 1x oversampling scheme is typically used, where the ADC's sampling rate is the same as the symbol rate. In this scheme, the receiver's numerically controlled oscillator (CNC) provides the ADC's sampling clock. Clock data recovery is then performed by controlling the CNC based on feedback from the signal acquired by the ADC, ensuring that the ADC completes signal acquisition at the optimal sampling time.

[0004] In the above process, the digital signal processor uses a clock data recovery algorithm to calculate the deviation between the actual sampling time and the optimal sampling time of the signal from the analog-to-digital converter (ADC), and uses a digital filter to filter the deviation. The filtered result is then used to fine-tune the frequency or phase of the numerically controlled oscillator (CNC) in a digital manner. The technique for calculating the deviation between the acquired signal and the optimal sampling time is called clock error detection or phase error detection. In this technique, the digital filter is typically designed as a first-order or second-order digital low-pass filter, and the output of the digital low-pass filter is used to control the clock phase of the CNC oscillator output.

[0005] However, as symbol rates increase, signals become more sensitive to clock jitter, thus requiring greater clock data recovery bandwidth. Traditional methods can only increase the clock data recovery bandwidth by adjusting the coefficients of the PI controller, which increases noise in the clock data recovery loop and may even cause the loop to become unstable. Therefore, traditional clock data recovery methods cannot provide sufficient bandwidth, which is detrimental to high-quality transmission of signals at speeds of 200Gbps or even higher.

[0006] An existing clock and data recovery circuit uses an injection-locked oscillator (ILO). However, the ILO is based on analog circuitry and requires a large number of complex circuits to process the analog signal. Furthermore, the generated clock requires additional phase adjustment, making the clock data recovery calculation quite complex. Moreover, simply using an ILO for clock data recovery calculations cannot meet the signal transmission quality requirements of 200Gbps or even higher speeds. Summary of the Invention

[0007] The primary objective of this invention is to provide a clock data recovery method based on injection locking that has strong tracking capability for clock jitter and low noise.

[0008] A second objective of the present invention is to provide an injection-lock-based clock data recovery apparatus that implements the above-described injection-lock-based clock data recovery method.

[0009] To achieve the first objective of this invention, the clock data recovery method based on injection-locked oscillator provided by this invention includes sampling an analog clock signal to obtain an initial sampling signal; performing clock error detection on the initial sampling signal to obtain a clock error signal; performing a first digital filtering process on the clock error signal to obtain a first clock control signal; obtaining a clock jitter estimate output from the digital filter in the injection-locked oscillator; injecting the clock jitter estimate into the clock error signal and performing a second digital filtering process; calculating a second clock control signal based on the clock signal after the second digital filtering process; and adjusting the phase of the sampling clock signal based on the first clock control signal and the second clock control signal.

[0010] As can be seen from the above scheme, after calculating the clock error signal, the present invention processes the clock error signal in two paths. One path involves performing a first digital filtering process using a first digital filter, and the other path involves injecting the estimated clock jitter value into the clock error signal using an injection-locked oscillator (ILO) and then performing a second digital filtering process. Finally, the phase of the sampled clock signal is adjusted based on the first and second clock control signals obtained from the two processing paths, respectively. Since the estimated clock jitter value generated by the ILO only contains the frequency components of the actual clock jitter, it has high clock jitter tracking accuracy and a wide jitter frequency tracking range, resulting in a more accurate phase of the generated sampled clock signal and more effectively eliminating clock jitter.

[0011] In addition, the injection-locked oscillator can be a fully digital injection-locked oscillator based entirely on digital signal calculations, without the design of analog signal processing. This approach can avoid the circuit complexity problems caused by sampling analog circuits and also improve the accuracy of phase calculation of the sampling clock signal.

[0012] A preferred approach is to perform a second digital filtering process on the clock error signal containing the injected clock jitter estimate, followed by gain adjustment, and then calculate the second clock control signal based on the gain-adjusted clock jitter estimate.

[0013] Therefore, by adjusting the gain of the clock jitter estimate after the second digital filtering process, the amplitude of the second clock control signal can be better matched with the amplitude of the first clock control signal, making the final calculated sampled clock signal more accurate.

[0014] A preferred approach is to adaptively adjust the tap coefficients of the digital filter based on the clock jitter estimate; and / or to adaptively adjust the gain coefficients based on the clock jitter estimate.

[0015] Therefore, by adaptively adjusting the tap coefficients and gain coefficients of the digital filter, the tap coefficients and gain coefficients of the digital filter can be made more reasonable, thus avoiding interference with clock data recovery calculations.

[0016] A further approach is to adaptively adjust the tap coefficients of the digital filter based on the estimated clock jitter value, including: determining whether the estimated clock jitter value is greater than a first threshold; if so, reducing the tap coefficients; otherwise, updating the tap coefficients based on the clock error signal.

[0017] Therefore, by adaptively adjusting the tap coefficients of the digital filter, the filtering effect can be adjusted to suit the frequency characteristics of the actual clock jitter. This ensures both the bandwidth of the clock digital recovery loop and improves the signal-to-noise ratio of the clock jitter estimate. For example, if the actual clock jitter frequency is within 1MHz, ideally, the digital filter will adaptively adjust to a low-pass filter with a bandwidth slightly higher than 1MHz. This ensures tracking of the 1MHz clock jitter while filtering out noise components above 1MHz in the clock error signal.

[0018] A further approach is to adaptively adjust the gain coefficient based on the estimated clock jitter value, including: determining whether the estimated clock jitter value is greater than a second threshold; if so, increasing the gain coefficient; otherwise, decreasing the gain coefficient.

[0019] Therefore, adaptive adjustment of the gain coefficient can control the amplitude of the output clock control signal, preventing the amplitude of the control signal from exceeding the circuit's tolerance range. Furthermore, when the actual clock jitter amplitude is very small, or when the injection lock condition is not met, the gain coefficient will automatically decrease to 0, preventing the injection lock oscillator's output from interfering with clock data recovery.

[0020] A further approach is to adjust the phase of the sampling clock signal based on the first clock control signal and the second clock control signal, including: if the clock signal generation module that generates the sampling clock signal is a frequency-controlled clock signal generation module, then the instantaneous frequency of the sampling clock signal is calculated based on the weighted value of the frequency of the first clock control signal, the frequency of the second clock control signal, and the reference frequency, and the target phase of the sampling clock signal is calculated based on the instantaneous frequency and the initial phase.

[0021] Therefore, for the frequency-controlled clock signal generation module, the present invention first calculates the instantaneous frequency of the sampling clock signal, and then calculates the target phase of the sampling clock signal based on the instantaneous frequency and the initial phase, thereby accurately calculating the target phase of the sampling clock signal.

[0022] An alternative approach is to adjust the phase of the sampling clock signal based on the first clock control signal and the second clock control signal, including: if the clock signal generation module that generates the sampling clock signal is a phase-controlled clock signal generation module, then the target phase of the sampling clock signal is calculated based on the weighted value of the phase of the first clock control signal, the phase of the second clock control signal, and the initial phase.

[0023] Therefore, for the phase-controlled clock signal generation module, the target phase of the sampled clock signal is directly calculated in a weighted manner, and the initial phase of the sampled clock signal is also considered when calculating the target phase, so as to accurately calculate the target phase of the sampled clock signal.

[0024] A further approach is to perform equalization processing on the initial sampled signal before clock error detection.

[0025] Therefore, by equalizing the initial sampled signal, the signal quality input to the clock error detection module can be improved, thereby enhancing the quality of the final calculated sampled clock signal.

[0026] To achieve the second objective mentioned above, the clock data recovery device based on injection lock provided by the present invention includes a sampling module for sampling an analog clock signal; a clock error detection module for detecting clock errors in the initial sampled signal to obtain a clock error signal; a first digital filter for performing a first digital filtering process on the clock error signal to obtain a first clock control signal; an injection lock oscillator for obtaining a clock jitter estimate, injecting the clock jitter estimate into the clock error signal, performing a second digital filtering process using a second digital filter, and calculating a second clock control signal based on the clock signal after the second digital filtering process; and a clock signal generation module for adjusting the phase of the sampled clock signal based on the first clock control signal and the second clock control signal.

[0027] As can be seen from the above scheme, the present invention sets up an injection-locked oscillator, injects the estimated clock jitter value into the clock error signal and performs a second digital filtering process. The obtained second clock control signal and the first clock error signal obtained by performing a first digital filtering process on the clock error signal are both used as the basis for calculating the phase of the sampled clock signal. The phase of the sampled clock signal calculated in this way is more accurate, the tracking ability of clock jitter is stronger, and clock jitter can be effectively eliminated.

[0028] In a preferred embodiment, the injection-locked oscillator is further provided with an adaptive adjustment module for adaptively adjusting the tap coefficients of the second digital filter and / or the gain coefficients of the clock jitter estimate processed by the second digital filter based on the clock jitter estimate.

[0029] Therefore, by adaptively adjusting the tap coefficients and gain coefficients of the second digital filter injected into the lock-in oscillator, it is possible to ensure the bandwidth of the clock digital recovery loop, improve the signal-to-noise ratio of the clock jitter estimate, and prevent the amplitude of the control signal from exceeding the range that the circuit can tolerate. Attached Figure Description

[0030] Figure 1 This is a structural block diagram of an embodiment of the clock data recovery device based on injection locking according to the present invention.

[0031] Figure 2This is a structural block diagram of the injection-locked oscillator in an embodiment of the clock data recovery device based on injection locking according to the present invention.

[0032] Figure 3 This is a flowchart of an embodiment of the clock data recovery method based on injection locking according to the present invention.

[0033] The present invention will be further described below with reference to the accompanying drawings and embodiments. Detailed Implementation

[0034] The clock data recovery device based on injection locking of the present invention is used to adjust the phase of the sampled clock signal, thereby eliminating clock jitter. The present invention improves the tracking accuracy of clock jitter and the tracking range of jitter frequency, making the phase of the generated sampled clock signal more accurate.

[0035] See Figure 1 The clock data recovery device based on injection locking in this embodiment includes a sampling module 11, an equalization module 12, a clock error detection module 13, a first digital filter 14, an injection-locked oscillator 20, and a clock signal generation module 15.

[0036] The sampling module 11 is used to acquire analog clock signals. The sampling module 11 needs to receive the sampled clock signal output by the clock signal generation module 15 and sample the analog clock signal based on this sampled clock signal. In this embodiment, the clock signal generation module 15 is mainly used to adjust the phase of the sampled clock signal. Therefore, the sampling module 11 mainly dynamically adjusts the sampling phase according to the sampled clock signal output by the clock signal generation module 15 to obtain discrete sampled signals. The initial sampled signal obtained by the sampling module 11 is denoted as S0.

[0037] The equalization module 12 is used to equalize the initial sampled signal S0 obtained by the sampling module 11. For example, it sets a sliding window of a certain width and performs equalization processing on the discrete data based on this sliding window. By equalizing the initial sampled signal, the influence of inter-symbol crosstalk can be suppressed, thereby improving the quality of the initial sampled signal S0, which is beneficial to subsequent calculations and improves the phase accuracy of the calculated sampled clock signal. After being processed by the equalization module 12, the initial sampled signal S0 forms an equalized signal S1, which is output to the clock error detection module 13.

[0038] The clock error detection module 13 is used to calculate the deviation between the actual sampling time and the ideal sampling time of the clock signal. The clock error detection module 13 can be implemented based on a 1x oversampling algorithm, such as the Mueller-Muller algorithm or the minimum mean square error algorithm. The clock error signal TE output by the clock error detection module 13 is split into two paths: one path is output to the first digital filter 14, and the second path is output to the injection-locked oscillator 20. The clock error signals TE output to the first digital filter 14 and the injection-locked oscillator 20 are identical, i.e., they have the same frequency and phase.

[0039] The first digital filter 14 can be a first-order or second-order digital filter, or a filter of other orders, used to perform digital filtering on the clock error signal TE and obtain the first clock control signal C1. The first clock control signal C1 is output to the clock signal generation module 15.

[0040] See Figure 2 The injection-locked oscillator 20 is equipped with a second digital filter 22, a gain module 23, a calculation module 24, and an adaptive adjustment module 25. After the clock error signal TE is input to the injection-locked oscillator 20, it is injected with an estimated clock jitter value J. Preferably, in the initial state, the estimated clock jitter value J can be set to an initial value. The second digital filter 22 performs a second digital filtering process on the clock error signal TE with the injected estimated clock jitter value J. Preferably, the second digital filter 22 is a first-order filter, a second-order filter, or a filter of other orders. The second digital filter 22 outputs an updated estimated clock jitter value J and feeds it back to the input of the injection-locked oscillator 20. In this way, the injection-locked oscillator 20 continuously injects the updated estimated clock jitter value J into the clock error signal TE.

[0041] Gain module 23 performs gain adjustment processing on the clock jitter estimate J output by the second digital filter 22, for example, increasing the amplitude of the clock jitter estimate J. The clock jitter estimate after gain adjustment is output to calculation module 24. Calculation module 24 calculates and obtains the second clock control signal C2 based on the clock jitter estimate after gain adjustment. The second clock control signal C2 is also output to clock signal generation module 15.

[0042] The adaptive adjustment module 25 is used to dynamically adjust the tap coefficient of the second digital filter 22 and the gain coefficient of the gain module 23 according to the clock jitter estimate J output by the second digital filter 22, thereby flexibly controlling the amplitude of the second clock control signal output by the injection-locked oscillator 20, and avoiding interference from the output of the injection-locked oscillator 20 to the clock digital recovery operation.

[0043] The clock signal generation module 15 adjusts the phase of the sampled clock signal based on the first clock control signal C1 and the second clock control signal C2, and outputs the phase-adjusted signal to the sampling module 11. The sampling module 11 samples the analog signal based on the updated clock sampling signal.

[0044] In this embodiment, the equalization module 12, the clock error detection module 13, the first digital filter 14, and the injection-locked oscillator 20 are all implemented on a digital signal processor (DSP). Therefore, the injection-locked oscillator 20 is a fully digital injection-locked oscillator, meaning that the clock error signal TE received by the injection-locked oscillator 20 is a digital signal, and the clock jitter estimate J output by processing this digital signal is also a digital signal. Therefore, the injection-locked oscillator 20 processes the received digital signal in a fully digital signal processing manner.

[0045] The following is combined with Figure 3 The working method of the clock data recovery device based on injection locking according to the present invention is introduced. First, step S11 is executed, in which the sampling module 11 samples the analog clock signal. Since the sampling module 11 receives the sampling clock signal output by the clock signal generation module 15, the sampling module 11 samples the analog signal based on the sampling clock signal to obtain multiple discrete digital signals, which form the initial sampling signal S0.

[0046] Next, step S12 is executed. The equalization module 12 performs equalization processing on the initial sampled signal S0 obtained by the sampling module 11 to suppress the influence of inter-symbol crosstalk and improve the quality of the initial sampled signal S0. After equalization processing, the equalized signal S1 is obtained and the equalized signal S1 is output to the clock error detection module 13.

[0047] Then, step S13 is executed. The clock error detection module 13 acquires the equalization signal S1 and performs error detection on the equalization signal S1, that is, calculates the degree of deviation between the actual sampling time and the ideal sampling time of the clock signal, obtains the clock error signal TE, and outputs the clock error signal TE to the first digital filter 14 and the injection-locked oscillator 20 respectively.

[0048] Next, step S14 is executed, where the clock error signal TE is subjected to first digital filtering processing by the first digital filter 14 to obtain the first clock control signal C1. The first digital filter 14 can be a first-order digital filter or a second-order digital filter; this embodiment does not limit the type of digital filter.

[0049] Simultaneously, step S15 is executed, and the clock error signal TE is also input to the injection-locked oscillator 20, which calculates the second clock control signal C2. Specifically, the clock error signal TE is first added to the clock jitter estimate J output by the second digital filter 22 inside the injection-locked oscillator 20, thus achieving injection-locking between the clock jitter estimate J and the clock error signal TE. Then, the clock error signal TE with the injected clock jitter estimate J is output to the second digital filter 22, which performs a second digital filtering process on the received clock signal to obtain a new clock jitter estimate J. Furthermore, the new clock jitter estimate J is also fed back to the input of the injection-locked oscillator 20 for injection-locking with the value of the subsequent clock error signal TE.

[0050] Next, the clock jitter estimate J output by the second digital filter 22 is input to the gain module 23, which performs gain adjustment processing on the clock jitter estimate J, such as increasing or decreasing the amplitude of the clock jitter estimate J.

[0051] To more flexibly adjust the amplitude of the second clock control signal C2 output by the injection-locked oscillator 20, this embodiment dynamically adjusts the tap coefficients of the second digital filter 22 and the gain coefficients of the gain module 23 through the adaptive adjustment module 25. Specifically, when adaptively adjusting the tap coefficients of the second digital filter 22, the estimated clock jitter value J of the current output of the second digital filter 22 is first obtained, and it is determined whether the estimated clock jitter value J is greater than the first threshold T1. If it is greater than the first threshold T1, the tap coefficients of the second digital filter 22 are reduced; otherwise, the tap coefficients are updated according to the clock error signal TE. For example, the corresponding tap coefficient h(n) is updated according to the nth clock error signal TE(n). The update of the tap coefficient h(n) can be expressed by the following formula: , where i represents the i-th tap coefficient, μ1 is a pre-set coefficient, and L is the total number of tap coefficients.

[0052] In addition, the adaptive adjustment module 25 also dynamically adjusts the gain coefficient of the gain module 23. Specifically, it determines whether the estimated clock jitter value J is greater than the second threshold T2. If it is greater than the second threshold T2, the gain coefficient G is increased. For example, the gain coefficient G is updated to G + μ2. If it is not greater than the second threshold T2, the gain coefficient G is decreased. The gain coefficient G is updated to G – μ3. Here, μ2 and μ3 are preset values ​​and are both positive numbers. μ2 and μ3 can be equal or unequal.

[0053] Finally, the calculation module 24 needs to calculate the second clock control signal C2 based on the clock jitter estimate J after gain adjustment processing. The calculation of the second clock control signal C2 can be implemented in two ways. The first way is for a frequency-controlled clock signal generation module 15. In this case, when calculating the second clock control signal C2, the instantaneous frequency fclk of the sampled clock signal is directly controlled. Therefore, the second clock control signal C2 can be directly calculated using the difference between the nth clock jitter estimate J(n) and the previous clock jitter estimate J(n-1), i.e., C2(n) = J(n) – J(n-1). The second way is for a phase-controlled clock signal generation module 15. In this case, when calculating the second clock control signal C2, the phase of the sampled clock signal is directly controlled. Therefore, the second clock control signal directly uses the nth clock jitter estimate J(n), i.e., C2(n) = J(n).

[0054] This embodiment adaptively adjusts the gain coefficient of the gain module 23. On the one hand, it can control the amplitude of the output second clock control signal C2, preventing the amplitude of the second clock control signal C2 from exceeding the range that the circuit can tolerate. On the other hand, if the amplitude of the actual clock jitter is very small, or if the conditions for injection lock are not met, the gain coefficient G will automatically shrink to 0. At this time, the output of the injection lock oscillator 20 is also 0, which can prevent the output of the injection lock oscillator 20 from interfering with the normal operation of the clock data recovery operation.

[0055] Furthermore, this embodiment also adaptively adjusts the tap coefficients of the second digital filter 22, enabling it to adaptively adjust the filtering effect according to the frequency characteristics of the actual clock jitter. This ensures both the bandwidth of the clock digital recovery loop and improves the signal-to-noise ratio of the clock jitter estimate J. For example, if the actual clock jitter frequency is within 1MHz, ideally, the second digital filter 22 will adaptively adjust to a low-pass filter with a bandwidth slightly higher than 1MHz. This ensures tracking of the 1MHz clock jitter while filtering out noise components above 1MHz in the clock error signal.

[0056] After calculating and obtaining the first clock control signal C1 and the second clock control signal C2, step S16 is finally executed. The clock signal generation module 15 adjusts the phase of the sampled clock signal based on the first clock control signal C1 and the second clock control signal C2. Specifically, if the clock signal generation module 15 is a frequency-controlled clock signal generation module, the instantaneous frequency fclk of the sampled clock signal is calculated based on the first clock control signal C1 and the second clock control signal C2. For example, the frequency of the first clock control signal C1, the frequency of the second clock control signal C2, and the reference frequency f0 of the sampled clock signal are used for weighted calculation. That is, the instantaneous frequency fclk(t) of the sampled clock signal is calculated based on the weighted value of the frequency of the first clock control signal C1, the frequency of the second clock control signal C2, and the reference frequency f0. The specific calculation formula is as follows: fclk(t) = k1(C1(t)+C2(t))+f0, where t is time, and k1 is a preset proportional coefficient, which is related to the circuit design of the clock generation module. After calculating the instantaneous frequency fclk of the sampling clock signal, the final target phase pclk of the sampling clock signal is also calculated based on the initial phase p0 of the sampling clock signal. The specific calculation formula is as follows: , where t is time.

[0057] If the clock signal generation module 15 is a phase-controlled clock signal generation module, then the target phase pclk of the sampled clock signal is directly calculated based on the first clock control signal C1 and the second clock control signal C2. The specific calculation formula is as follows: Where t is time, k2 is a preset scaling factor, and p0 is the initial phase of the sampling clock signal. Therefore, in this case, the target phase pclk of the sampling clock signal is calculated based on the weighted value of the phase of the first clock control signal C1, the phase of the second clock control signal C2, and the initial phase p0 of the sampling clock signal.

[0058] After calculating and obtaining the target phase pclk and instantaneous frequency fclk of the sampling clock signal, the waveform of the sampling clock signal can be determined, which means the data output by the sampling clock signal is determined. Finally, the sampling clock signal is fed back to the sampling module 11. The sampling module 11 samples the analog signal based on the updated sampling clock signal and starts the processing of the clock signal for the next cycle.

[0059] In the above embodiments, the first digital filter 14 and the injection-locked oscillator 20 operate independently and do not affect each other. Furthermore, the injection-locked oscillator 20 can be turned off individually. For example, by setting the gain coefficient of the gain module 23 of the injection-locked oscillator 20 to 0, the second clock control signal C2 output by the injection-locked oscillator 20 will also be 0, which is equivalent to turning off the injection-locked oscillator 20.

[0060] This invention does not limit the type and implementation of the first digital filter 14 and the second digital filter 22, as long as they can filter the clock error signal TE. Furthermore, the injection-locked oscillator 20 may not require the adaptive adjustment module 25. The tap coefficients of the second digital filter 22 and the gain coefficients of the gain module 23 of the injection-locked oscillator 20 can be manually set, and this method does not affect the calculation of the second clock control signal C2.

[0061] Furthermore, in other embodiments, an equalization module may not be required. After obtaining the initial sampling signal, the sampling module can directly output it to the clock error detection module. Alternatively, the analog clock signal can be equalized before sampling. In this way, the initial sampling signal obtained by the sampling module is already an equalized clock signal, and no further equalization is needed after sampling.

[0062] The clock data recovery process of this invention employs an injection-locking method, which injects the estimated clock jitter value into the clock error signal. Since the estimated clock jitter value generated by the injection-locked oscillator only contains the frequency component of the actual clock jitter, the method of this invention has high clock jitter tracking accuracy and a wide jitter frequency tracking range, and can be applied to next-generation high-speed serial communication systems.

[0063] Furthermore, both the injection-locked oscillator and the first digital filter proposed in this invention are implemented based on a digital signal processor. Therefore, they operate independently and can both be turned off individually to save power without significantly increasing latency. Additionally, since the tap coefficients of the second digital filter and the gain coefficients of the gain module in the injection-locked oscillator can be adjusted, either adaptively or manually, the adaptive adjustment method can automatically adjust to the optimal configuration parameters based on the current clock data recovery state. This improves the phase accuracy of the generated sampling clock signal and effectively avoids clock jitter.

[0064] Finally, it should be emphasized that the above are merely preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A clock data recovery method based on injection locking, characterized in that, include: The initial sampled signal is obtained by sampling the analog clock signal; Clock error detection is performed on the initial sampled signal to obtain a clock error signal; The clock error signal is subjected to a first digital filtering process to obtain a first clock control signal; The clock jitter estimate is obtained from the output of the digital filter in the injection-locked oscillator. The clock jitter estimate is injected into the clock error signal and then subjected to a second digital filtering process to obtain a new clock jitter estimate, which is fed back to the input of the injection-locked oscillator. A second clock control signal is calculated based on the clock signal after the second digital filtering process. The phase of the sampling clock signal is adjusted based on the first clock control signal and the second clock control signal.

2. The clock data recovery method based on injection locking according to claim 1, characterized in that: After performing a second digital filtering process on the clock error signal into which the clock jitter estimate is injected to obtain a new clock jitter estimate, a gain adjustment is also performed, and the second clock control signal is calculated based on the clock jitter estimate after gain adjustment.

3. The clock data recovery method based on injection locking according to claim 2, characterized in that, Also includes: The tap coefficients of the digital filter are adaptively adjusted based on the estimated clock jitter value. and / or The gain coefficient is adaptively adjusted based on the estimated clock jitter value.

4. The clock data recovery method based on injection locking according to claim 3, characterized in that: Adaptive adjustment of the tap coefficients of the digital filter based on the estimated clock jitter includes: Determine whether the estimated clock jitter value is greater than a first threshold. If so, decrease the tap coefficient; otherwise, update the tap coefficient based on the clock error signal.

5. The clock data recovery method based on injection locking according to claim 3, characterized in that: Adaptive adjustment of the gain coefficient based on the clock jitter estimate includes: Determine whether the estimated clock jitter value is greater than the second threshold. If so, increase the gain coefficient; otherwise, decrease the gain coefficient.

6. The clock data recovery method based on injection locking according to any one of claims 1 to 5, characterized in that: Adjusting the phase of the sampling clock signal based on the first clock control signal and the second clock control signal includes: If the clock signal generation module that generates the sampling clock signal is a frequency-controlled clock signal generation module, then the instantaneous frequency of the sampling clock signal is calculated based on the weighted value of the frequency of the first clock control signal, the frequency of the second clock control signal, and the reference frequency, and the target phase of the sampling clock signal is calculated based on the instantaneous frequency and the initial phase.

7. The clock data recovery method based on injection locking according to any one of claims 1 to 5, characterized in that: Adjusting the phase of the sampling clock signal based on the first clock control signal and the second clock control signal includes: If the clock signal generation module that generates the sampling clock signal is a phase-controlled clock signal generation module, then the target phase of the sampling clock signal is calculated based on the weighted value of the phase of the first clock control signal, the phase of the second clock control signal, and the initial phase.

8. The clock data recovery method based on injection locking according to any one of claims 1 to 5, characterized in that: Before performing clock error detection on the initial sampled signal obtained from sampling, the initial sampled signal is also subjected to equalization processing.

9. A clock data recovery device based on injection locking, characterized in that, include: The sampling module is used to sample the analog clock signal; The clock error detection module is used to detect clock errors in the initial sampled signal obtained by sampling, and to obtain a clock error signal. A first digital filter is used to perform a first digital filtering process on the clock error signal to obtain a first clock control signal; An injection-locked oscillator is used to obtain a clock jitter estimate. After the clock jitter estimate is injected into the clock error signal, a second digital filter is used for second digital filtering to obtain a new clock jitter estimate, which is fed back to the input of the injection-locked oscillator. A second clock control signal is calculated based on the clock signal after the second digital filtering. A clock signal generation module is used to adjust the phase of the sampled clock signal based on the first clock control signal and the second clock control signal.

10. The clock data recovery device based on injection locking according to claim 9, characterized in that: The injection-locked oscillator is further provided with an adaptive adjustment module, which is used to adaptively adjust the tap coefficients of the second digital filter and / or the gain coefficients of the clock jitter estimate processed by the second digital filter based on the clock jitter estimate.

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