Impact recovery

Abstract

The invention relates to impact recovery. Disclosed is an impact recovery circuit, the circuit including a phase locked loop (PLL) monitoring circuit configured to receive at least one of a PLL input clock and a PLL feedback clock, and to generate a PLL state signal based on the at least one of the PLL input clock and the PLL feedback clock, the PLL state signal indicating whether an impact event has occurred; the acceleration monitoring circuit is configured to receive acceleration data and generate an acceleration state signal based on the acceleration data, the acceleration state signal indicating whether an impact event has occurred; the controller is configured to receive a PLL state signal and an acceleration state signal, generate an enable signal indicating whether a mechanical oscillation sensor generating a PLL input clock is to operate, and generate a multiplexer signal indicating whether a system clock is to be generated based on a PLL feedback clock.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to clock generation circuits, and methods for recovery from mechanical shock. BACKGROUND

[0002] Some electronic systems benefit from clock generation circuits that generate a system clock. The system clock of a system can be used by many components to perform their respective data operations and computational functions. Some system clock generation circuits use oscillation of mechanical components to generate the system clock. Such system clock generation circuits are susceptible to system clock failure due to mechanical shock. SUMMARY

[0003] One embodiment is a shock recovery circuit that includes a phase-locked loop (PLL) monitor circuit, an acceleration monitor circuit, and a controller. The PLL monitor circuit is configured to receive at least one of a PLL input clock and a PLL feedback clock, and generate a PLL status signal based on the at least one of the PLL input clock and the PLL feedback clock, the PLL status signal indicating whether a shock event has occurred. The acceleration monitor circuit is configured to receive acceleration data, and generate an acceleration status signal based on the acceleration data, the acceleration status signal indicating whether a shock event has occurred. The controller is configured to receive the PLL status signal and the acceleration status signal, generate an enable signal indicating whether a mechanical oscillation sensor generating the PLL input clock is to be operated, and generate a multiplexer signal indicating whether a system clock is to be generated based on the PLL feedback clock.

[0004] Another embodiment is a clock generation system comprising an oscillator circuit configured to electronically generate an oscillator clock; a mechanical oscillation sensor comprising a mechanical oscillator and configured to generate a PLL input clock; a phase-locked loop (PLL) configured to receive the PLL input clock and generate a PLL clock and a PLL feedback signal based on the PLL input clock; a clock multiplexer configured to conditionally connect the PLL clock and the oscillator clock to an output of a system clock; an acceleration sensor configured to sense acceleration in each of one, two, or three orthogonal spatial dimensions and generate an acceleration measurement for each of the sensed spatial dimensions; and a shock recovery circuit configured to receive one or more of the PLL input clock, the PLL feedback signal, and the acceleration measurements and generate a multiplexer control signal configured to cause the clock multiplexer to connect a particular one of the PLL clock and the oscillator clock to the output based on one or more of the PLL input clock, the PLL feedback signal, and the acceleration measurements, wherein the multiplexer control signal causes the clock multiplexer to connect the oscillator clock to the output in response to one or more of the received PLL input clock, the received PLL feedback signal, and the received acceleration measurement indicating a shock event.

[0005] Another embodiment is a method of using a clock generation system, the method comprising generating an oscillator clock; generating a PLL input clock; generating a PLL clock based on the PLL input clock; generating a system clock based on the PLL clock; monitoring the PLL clock; generating a PLL status signal based on the monitored PLL clock; monitoring acceleration of the clock generation system and generating an acceleration status signal based on the monitored acceleration; generating the system clock based on the oscillator clock in response to one or more of the PLL status signal and the acceleration status signal indicating a shock event; and after a delay, generating the system clock based on the PLL clock, wherein the delay starts from generating the system clock based on the oscillator clock. BRIEF DESCRIPTION OF DRAWINGS

[0006] For a more complete understanding of the present disclosure, one or more embodiments thereof, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings in which:

[0007] Figure 1 A schematic circuit diagram of a clock generation system is shown in accordance with some embodiments;

[0008] Figure 2 A block diagram of a phase-locked loop (PLL) circuit is shown in accordance with some embodiments;

[0009] Figure 3 a schematic circuit diagram of a mechanical shock recovery circuit according to some embodiments is shown;

[0010] Figure 4 a schematic circuit diagram of a PLL monitor circuit according to some embodiments is shown;

[0011] Figure 5 a schematic circuit diagram of a high acceleration monitoring circuit according to some embodiments is shown;

[0012] Figure 6 a flowchart of a method of using a clock generation system according to some embodiments is shown; and

[0013] Figure 7 a flowchart of a method of using a clock generation system according to some embodiments is shown.

[0014] Unless otherwise indicated, corresponding numbers and symbols in different figures generally refer to corresponding parts. The figures are drawn to illustrate relevant aspects of the embodiments and are not necessarily drawn to scale. The edges of features drawn in the figures do not necessarily represent terminations of the extent of the features. DETAILED DESCRIPTION

[0015] Illustrative embodiments of the systems and methods of the present disclosure are described below. In some instances, all or aspects of the description in this specification can not describe the practices in a manner that is necessary to practice the embodiments in conformance with its principles. Of course, it is understood that numerous implementation-specific decisions can be made to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which can vary from one implementation to another. Moreover, it is understood that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.

[0016] As shown in the drawings, reference can be made to spatial relationships between various components and to the spatial orientation of various aspects of components as the drawings are viewed in the direction of the viewing. As will be realized by those of ordinary skill in the art having the benefit of the present disclosure, the devices, components, apparatuses, etc. described herein can be positioned in any desired orientation after a full appreciation of the present disclosure. As such, the use of terms such as "above", "below", "upper", "lower", or other like terms to describe a spatial relationship between various components or to describe the spatial orientation of aspects of such components should be understood to be describing a relative relationship between components or a spatial orientation of aspects of such components, respectively, as the devices described herein can be oriented in any desired direction.

[0017] The making and using of various embodiments are discussed in detail below. It should be appreciated, however, that the various embodiments described herein are applicable in a variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the various embodiments, and should not be construed as being limited in scope.

[0018] The embodiments discussed herein illustrate various aspects of clock generation circuit technology that uses mechanical elements to generate a system clock, and that provide for effective recovery from mechanical shock events that disturb the generated system clock.

[0019] Systems in which there is a mechanical oscillation sensor, such as a gyroscope, use the oscillation of the oscillation sensor as a time base reference, and a PLL generates a system clock for use by other components of the system. In some embodiments, when the mechanical oscillation sensor is on, the timing of the operation of other sensors, such as accelerometers and shock sensors, is synchronized to the timing of the mechanical oscillation sensor.

[0020] In some embodiments, for example, a local (electronic) oscillator can be included in the system, so that this oscillator is used when, for example, the mechanical oscillation sensor is off or in its start-up phase.

[0021] Events such as shock events (impulsive acceleration, e.g. short and high amplitude) can disturb the mechanical oscillation sensor drive loop, and stop or temporarily distort the mechanical oscillation. As a result, the system clock can be disturbed, and cause the system to freeze or cause the system to go out of specification. These results are preferably avoided if other components or sensors are to continue to function normally.

[0022] In some embodiments, the shock recovery controller can monitor signals from the PLL (e.g. input frequency, duty cycle, and phase shift between input and feedback) to detect precursor signals of distorted oscillation. The shock recovery controller can additionally or alternatively monitor shock data from a high-g accelerometer to detect precursor signals of distorted oscillation. The shock recovery controller can cause the system clock generation circuit to enter a safe mode before the effects of the problem shock event affect the system. In some embodiments, when in the safe mode, the clock source of the system clock is switched from the PLL to an internal oscillator. In some embodiments, a force or enable signal to the mechanical oscillation sensor is terminated and / or a mass braking signal is generated to keep the mechanical oscillation sensor in a safe state.

[0023] In some embodiments, the advantageous aspects are implemented as digital circuitry that can be implemented in an inexpensive way (e.g. using 0.6k type gates), and that can be kept on at all times, as its power consumption is negligible relative to the total power required by the mechanical oscillation sensor.

[0024] In some embodiments, the system clock generator avoids system freeze and data discontinuity in the accelerometer. In some embodiments, a plurality of parameters are continuously monitored to predict an impending system shock event impact. Thus, the impact of a shock event on a sensor in a MEMS device embedded with a mechanical oscillation sensor can be predicted, and a switch is made to a local electrical oscillator source to put the system in a safe state and continue apple, for example, when the mechanical oscillation sensor clock generation system recovers from an anticipated shock event.

[0025] Figure 1 A schematic circuit diagram of a clock generation system 100 is shown in accordance with some embodiments. The clock generation system 100 includes an oscillator circuit 110, a phase-locked loop (PLL) 120, a clock multiplexer 130, a mechanical oscillation sensor 140, an AND gate 150, a mechanical oscillation sensor start controller 160, a shock recovery circuit 170, an accelerometer sensor 180, and a high frequency oscillator circuit 190. The clock generation system 100 is a particular example of a circuit that implements various aspects of the present specification. Other examples can be considered.

[0026] The oscillator circuit 110 can be any electronic oscillator circuit configured to generate an oscillator clock suitable for use as a system clock. For example, the oscillator circuit 110 can include any of a number of clock generation circuits, such as a ring oscillator, a PLL, a delay line, etc.

[0027] The PLL 120 can be any phase-locked loop circuit or delay-locked loop circuit configured to generate an output clock suitable for use as a system clock, where the output clock is generated based on a difference between an input clock reference and a feedback clock generated based on the output clock. As shown, in this embodiment, the PLL 120 receives an oscillation signal CKPLLIN from the mechanical oscillation sensor 140 as the input clock reference. Further, the PLL 120 is configured to generate a PLL clock CKPLL as its output clock. The PLL 120 also generates a feedback clock CKPLLFB that is used internally to synchronize the PLL clock CKPLL with the oscillation signal CKPLLIN.

[0028] Clock multiplexer 130 can be any multiplexing circuit configured to generate or transmit an output clock based on a first input clock and a second input clock according to a selection control signal. As shown, in this embodiment, clock multiplexer 130 receives an oscillator clock CKOSC from oscillator circuit 110 as the first input clock and a PLL clock CKPLL from PLL 120 as the second input clock. Further, clock multiplexer 130 receives a selection control signal CTRL from AND gate 150 and, according to the state of selection control signal CTRL, generates or transmits a system clock CKSYS based on one of oscillator clock CKOSC and PLL clock CKPLL or generates or transmits a system clock CKSYS that is similar or identical to one of oscillator clock CKOSC and PLL clock CKPLL.

[0029] Mechanical oscillation sensor 140 is configured to receive an enable signal EN from shock recovery circuit 170. Further, mechanical oscillation sensor 140 has a drive circuit configured to conditionally cause mechanical oscillation sensor 140 to generate an oscillation output signal according to the state of enable signal EN.

[0030] In response to enable signal EN indicating that mechanical oscillation sensor 140 is to operate, the drive circuit causes mechanical oscillation sensor 140 to generate an oscillation signal CKPLLIN received by PLL 120. In some embodiments, oscillation signal CKPLLIN is generated based on an oscillating mechanical mass and the electronic sensor generates oscillation signal CKPLLIN based on one or more sensing locations of the oscillating mechanical mass.

[0031] In response to enable signal EN indicating that mechanical oscillation sensor 140 is not to operate, the drive circuit causes mechanical oscillation sensor to not generate oscillation signal CKPLLIN. For example, the output of mechanical oscillation sensor 140 can be fixed, e.g., at a high or low state. In some embodiments, in response to enable signal EN indicating that mechanical oscillation sensor 140 is not to operate, the mechanical mass of mechanical oscillation sensor 140 is fixed to prevent or substantially prevent movement of the mechanical mass.

[0032] Shock recovery circuit 170 receives oscillation signal CKPLLIN, feedback clock CKPLLFB, an acceleration data value from accelerometer sensor 180, and a high frequency clock from high frequency oscillator circuit 190 and generates enable signal EN based at least in part on oscillation signal CKPLLIN, feedback clock CKPLLFB, acceleration data value, and high frequency clock.

[0033] In some embodiments, if the acceleration data values from the accelerometer sensor 180 indicate that the clock generation system 100 has experienced a shock event or acceleration greater than a threshold value, the shock recovery circuit 170 generates the enable signal EN to cause the mechanical oscillation sensor 140 to not operate, as described in more detail below.

[0034] In some embodiments, if the oscillation signal CKPLLIN and the feedback clock CKPLLFB collectively indicate or imply that the mechanical oscillation sensor 140 has experienced a shock event or acceleration that disturbed the oscillation signal CKPLLIN, the shock recovery circuit 170 generates the enable signal EN to cause the mechanical oscillation sensor 140 to not operate, as described in more detail below.

[0035] In some embodiments, if no acceleration data values indicate that the clock generation system 100 experienced a shock event or acceleration, and no abnormalities in the oscillation signal CKPLLIN and the feedback clock signal CKPLLFB collectively indicate or imply that the mechanical oscillation sensor 140 has experienced a shock event or acceleration that disturbed the oscillation signal CKPLLIN, the shock recovery circuit 170 generates the enable signal EN to cause the mechanical oscillation sensor 140 to operate.

[0036] In the illustrated embodiment, the shock recovery circuit 170 also generates a first multiplexer control signal for the AND gate 150 that indicates that the system clock CKSYS can be generated based on the PLL clock CKPLL instead of the oscillator clock CKOSC. In some embodiments, the shock recovery circuit 170 generates the first multiplexer control signal in response to a predetermined delay from the enable signal EN changing to a state that indicates that the mechanical oscillation sensor 140 is to operate.

[0037] The mechanical oscillation sensor start controller 160 generates a second multiplexer control signal for the AND gate 150 that indicates that the system clock CKSYS can be generated based on the PLL clock CKPLL instead of the oscillator clock CKOSC. In some embodiments, the mechanical oscillation sensor start controller 160 generates the second multiplexer control signal after a predetermined delay from the start of the mechanical oscillation sensor 140, for example, in some implementations one or more starts of the mechanical oscillation sensor 140 can be initiated by other signals, such as a system start signal or a power-on signal.

[0038] In some embodiments, if neither of the first multiplexer control signal and the second multiplexer control signal indicates that the system clock CKSYS can be generated based on the PLL clock CKPLL, then the AND gate 150 generates the selection control signal CTRL having a state indicating that the system clock CKSYS will be generated based on the oscillator clock CKOSC. In some embodiments, if both of the first multiplexer control signal and the second multiplexer control signal indicate that the system clock CKSYS can be generated based on the PLL clock CKPLL, then the AND gate 150 generates the selection control signal CTRL having a state indicating that the system clock CKSYS will be generated based on the PLL clock CKPLL.

[0039] The accelerometer sensor 180 senses acceleration of the clock generation system 100. For example, the accelerometer sensor 180 can be any accelerometer configured to generate a series of acceleration measurements in each of 1, 2, or 3 spatial dimensions. In some embodiments, the accelerometer sensor 180 senses and generates acceleration measurements in spatial dimensions corresponding to those of the mechanical mass of the mechanical oscillation sensor 140. For example, in some embodiments, the accelerometer sensor 180 generates acceleration measurements in spatial dimensions in which sufficient acceleration can interfere with the oscillation operation of the mass of the mechanical oscillation sensor 140.

[0040] The high frequency oscillator circuit 190 generates a clock signal for the shock recovery circuit 170 having characteristics, such as frequency and / or phase performance, that allow the shock recovery circuit 170 to properly generate the enable signal EN, as discussed in further detail below. In some embodiments, the high frequency oscillator circuit 190 is incorporated in the oscillator circuit 110.

[0041] Figure 2 A block diagram of a phase-locked loop (PLL) circuit 200 is shown in accordance with some embodiments. The PLL circuit 200 includes a phase frequency detector 210, a filter 220, a voltage controlled oscillator (VCO) 230, and a frequency divider 240. For example, the PLL circuit 200 can be used as the PLL 120 of the clock generation system 100. In some embodiments, the PLL 120 of the clock generation system 100 uses a different PLL circuit.

[0042] The phase frequency detector 210 receives an input clock and a feedback clock, and generates one or more signals for the filter 220 based on, for example, a phase difference between the input clock and the feedback clock.

[0043] The filter 220 receives the signal from the phase frequency detector 210 and generates a voltage output for the VCO 230. In some embodiments, the phase frequency detector 210 and filter 220 are configured such that a clock edge of the input clock that precedes a corresponding clock edge of the feedback clock causes the voltage output of the VCO 230 generated by the filter 220 to increase the frequency of the output clock generated by the VCO 230. Similarly, in some embodiments, the phase frequency detector 210 and filter 220 are configured such that a clock edge of the feedback clock that precedes a corresponding clock edge of the input clock causes the voltage output of the VCO generated by the filter 220 to decrease the frequency of the output clock generated by the VCO 230.

[0044] The frequency divider 240 receives the output clock generated by the VCO 230 and generates a feedback clock for the phase frequency detector 210. In some embodiments, the frequency of the feedback clock is a particular fraction of the frequency of the output clock, e.g., such that the frequency of the input clock is a particular fraction of the frequency of the output clock.

[0045] When used in a clock generation system such as the clock generation system 100, the feedback clock is provided as an output of the PLL circuit 200. When used in the clock generation system 100, the feedback clock can be used as the feedback clock CKPLLFB. In embodiments of the clock generation system 100 that use a different PLL circuit for the PLL 120, another suitable feedback clock can be used as the feedback clock CKPLLFB.

[0046] Figure 3 A schematic circuit diagram of a shock recovery circuit 300 is shown in accordance with some embodiments. The shock recovery circuit 300 includes a PLL monitor circuit 310, an acceleration monitor 320, and a controller 330. The shock recovery circuit 300 can be used as the shock recovery circuit 170 of the clock generation system 100. In some embodiments, the clock generation system 100 uses other shock recovery circuits, e.g., a shock recovery circuit having aspects similar to or the same as aspects of the shock recovery circuit 300.

[0047] The PLL monitor circuit 310 receives a first input clock and a second input clock. For example, in some embodiments, the PLL monitor circuit 310 receives a PLL input clock PLL IN, a PLL feedback clock PLL FB. The PLL monitor circuit 310 can also receive a high frequency clock input CK. Based on the PLL input clock PLL IN and the PLL feedback clock PLL FB, the PLL monitor circuit 310 generates a PLL status signal PLLSTAT for the controller 330 that indicates one or more state conditions of the PLL input clock PLL IN, e.g., as discussed below with reference to Figure 4 discussed in more detail.

[0048] In some embodiments, if the PLL status signal PLLSTAT indicates or implies that the mechanical oscillation sensor has experienced a shock event or acceleration that interferes with the PLL input clock PLL IN, the controller 330 generates the enable signal EN to cause the mechanical oscillation sensor to not operate, e.g., as described in more detail below.

[0049] In some embodiments, if the PLL status signal PLLSTAT does not indicate or imply that the mechanical oscillation sensor has experienced a shock event or acceleration that interferes with the PLL input clock PLL IN, the controller 330 generates the enable signal EN to cause or allow the mechanical oscillation sensor to operate.

[0050] The acceleration monitor 320 receives the acceleration data value DATA. In some embodiments, the acceleration monitor 320 also receives a clock signal (not shown). Based on the acceleration data value DATA, and optionally based on the clock signal, the acceleration monitor 320 generates an acceleration status signal ACCSTAT for the controller 330 that indicates one or more status conditions of the acceleration of the mechanical oscillation sensor used to generate the PLL input clock PLL IN, e.g., as discussed in more detail below with reference to Figure 5

[0051] In some embodiments, if the acceleration status signal ACCSTAT indicates or implies that the mechanical oscillation sensor has experienced a shock event or acceleration that interferes with the PLL input clock PLL IN, the controller 330 generates the enable signal EN to cause the mechanical oscillation sensor to not operate, e.g., as described in more detail below.

[0052] In some embodiments, if the acceleration status signal ACCSTAT does not indicate or imply that the mechanical oscillation sensor has experienced a shock event or acceleration that interferes with the PLL input clock PLL IN, the controller 330 generates the enable signal EN to cause or allow the mechanical oscillation sensor to operate.

[0053] In some embodiments, the controller 330 generates a multiplexer control signal CKMUX, e.g., for controlling a selection multiplexer, where the multiplexer control signal CKMUX indicates that the system clock can be generated based on the PLL clock input PLL IN instead of the oscillator clock. In some embodiments, the controller 330 generates the multiplexer control signal CKMUX in response to a predetermined delay from the enable signal EN changing to a state indicating that the mechanical oscillation sensor is to operate.

[0054] Figure 4 ​A schematic circuit diagram of a PLL monitor circuit 410 is shown, in accordance with some embodiments. The PLL monitor circuit 410 can be used as the PLL monitor circuit 310 in the strike recovery circuit 300. In some embodiments, the strike recovery circuit 300 uses another PLL monitor circuit, e.g., a PLL monitor circuit having similar or identical characteristics as the characteristics of the PLL monitor circuit 400.

[0055] In some embodiments, the PLL monitor circuit 410 receives at least one of the first clock and the second clock. For example, the PLL monitor circuit 410 can receive the PLL IN clock as the first input clock. In some embodiments, the PLL monitor circuit 410 can receive the PLL FB clock as the second input clock. In some embodiments, the PLL monitor circuit 410 can also receive the high frequency clock input CK. In some implementations, based on at least one of the PLL input clock PLL IN and the PLL feedback clock PLL FB, the PLL monitor signal 410 generates a PLL status signal PLLSTAT that indicates one or more state conditions of the PLL input clock PLL IN. The PLLSTAT signal can be generated based on one or more of a set of detected characteristics or parameters.

[0056] In some embodiments, the PLLSTAT signal can be generated based at least in part on a duty cycle of the PLL IN clock. For example, when the circuit is operating without a strike event, the PLL IN clock has a particular expected duty cycle. For example, the expected duty cycle can be 50%, where the high time of the PLL IN clock is 50% of the period of the PLL IN clock. In some embodiments, the expected duty cycle is different than 50%. The PLL monitor circuit 410 can include a duty cycle monitor circuit configured to monitor the duty cycle of the PLL IN clock based on the received PLL IN clock and the received high frequency clock input CK, and if the monitored duty cycle differs from the expected duty cycle by more than a threshold, the duty cycle monitor circuit can generate a duty cycle alert signal indicating that a strike event has occurred in response to the monitored duty cycle differing from the expected duty cycle by more than the threshold. The threshold can be one of approximately 0.5%, 0.6%, 0.7%, 0.8%, 0.9%, 1.0%, 1.1%, 1.2%, 1.3%, 1.4%, 1.5%, or another percentage. In some embodiments, the threshold is configurable, e.g., during a test operation or during a calibration operation. In some embodiments, the threshold used to generate the duty cycle alert signal when the monitored duty cycle is greater than the expected duty cycle is different than the threshold used to generate the duty cycle alert signal when the monitored duty cycle is less than the expected duty cycle.

[0057] In some embodiments, the PLLSTAT signal can be generated based at least in part on a rate of change of a duty cycle of the PLL IN clock. For example, when the circuit is operating without a shock event, the duty cycle of the PLL IN clock has a particular expected rate of change, such as an average rate of change. For example, the expected rate of change of the duty cycle can be 1% / us. In some embodiments, the expected rate of change of the duty cycle is different than 1% / us, the PLL monitoring circuit 410 can include a duty cycle rate of change monitoring circuit configured to monitor a rate of change of the duty cycle of the PLL IN clock based on the received PLL IN clock and the received high frequency clock input CK, and if the monitored rate of change of the duty cycle is more than a threshold above the expected rate of change of the duty cycle, the duty cycle rate of change monitoring circuit can generate a duty cycle rate of change alert signal indicating that a shock event has occurred in response to the monitored rate of change of the duty cycle differing from the expected rate of change of the duty cycle by more than the threshold. The threshold can be one of approximately 0.5%, 0.6%, 0.7%, 0.8%, 0.9%, 1.0%, 1.1%, 1.2%, 1.3%, 1.4%, 1.5%, or another percentage. In some embodiments, the threshold is configurable, for example, during a test operation or during a calibration operation.

[0058] In some embodiments, the PLLSTAT signal can be generated based at least in part on a period of the PLL IN clock. For example, when the circuit is operating without a shock event, the PLL IN clock has a particular expected period. For example, the expected period can be 40us. In some embodiments, the expected period is different than 40us. The PLL monitoring circuit 410 can include a period monitoring circuit configured to monitor a period of the PLL IN clock based on the received PLL IN clock and the received high frequency clock input CK, and if the monitored period differs from the expected period by more than a threshold, the period monitoring circuit can generate a period alert signal indicating that a shock event has occurred in response to the monitored period differing from the expected period by more than the threshold. The threshold can be one of approximately 1.0%, 1.3%, 1.6%, 1.9%, 2.2%, 2.5%, 2.8%, 3.1%, 3.4%, 3.7%, 4%, or another percentage of the expected period. In some embodiments, the threshold is configurable, for example, during a test operation or during a calibration operation. In some embodiments, the threshold used to generate the period alert signal when the monitored period is greater than the expected period is different than the threshold used to generate the period alert signal when the monitored period is less than the expected period.

[0059] In some embodiments, the PLL STAT signal can be generated based at least in part on a rate of change of a period of the PLL IN clock. For example, when the circuit is operating without a shock event, the PLL IN clock has a particular expected rate of change of period. For example, the expected period can be 5% / period. In some embodiments, the expected rate of change of period is different than 5% / period. The PLL monitoring circuit 410 can include a rate of change of period monitoring circuit configured to monitor a rate of change of period of the PLL IN clock based on the received PLL IN clock and the received high frequency clock input CK, and if the monitored rate of change of period is more than a threshold above the expected rate of change of period, the rate of change of period monitoring circuit can generate a rate of change of period alert signal indicating that a shock event has occurred in response to the monitored rate of change of period being more than the threshold above the expected period. The threshold can be one of approximately 1.0%, 1.3%, 1.6%, 1.9%, 2.2%, 2.5%, 2.8%, 3.1%, 3.4%, 3.7%, 4%, or another percentage of the expected rate of change of period. In some embodiments, the threshold is configurable, for example, during a test operation or during a calibration operation.

[0060] In some embodiments, the PLL STAT signal can be generated based at least in part on a phase difference between the PLL IN clock and the PLL FB clock. For example, when the circuit is operating without a shock event, the phase difference between the PLL IN clock and the PLL FB clock has a particular expected value. For example, the phase difference between the PLL IN clock and the PLL FB clock can be 0 ns. In some embodiments, the expected phase difference between the PLL IN clock and the PLL FB clock is different than 0 ns. The PLL monitoring circuit 410 can include a phase difference monitoring circuit configured to monitor a phase difference between the PLL IN clock and the PLL FB clock based on the received PLL IN clock, the received PLL FB clock, and the received high frequency clock input CK, and if the monitored phase difference is more than a threshold from the expected phase difference, the phase difference monitoring circuit can generate a phase difference alert signal indicating that a shock event has occurred. The threshold can be a particular number of clock periods. For example, the threshold can be 1, 2, 3, 4, 5, 10, 20, or another number of clock periods. In some embodiments, the threshold can be one of approximately 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns, 7 ns, 8 ns, 9 ns, 10 ns, 11 ns, 12 ns, 13 ns, 14 ns, 15 ns, or another time. In some embodiments, the threshold for generating the phase difference alert signal when the monitored phase difference is greater than the expected phase difference is different than the threshold for generating the phase difference alert signal when the monitored phase difference is less than the expected phase difference.

[0061] In some embodiments, other characteristics or parameters of the PLL IN clock are monitored, and a corresponding alert signal is generated that indicates that a shock event has occurred. For example, the PLL monitoring circuit 410 can include circuitry to monitor any one or more of the following: jitter of the PLL IN clock, amplitude of the PLL IN clock, rise time of one or more edges of the PLL input clock, fall time of one or more edges of the PLL input clock, and another characteristic or parameter of the PLL IN clock. In some embodiments, the PLL monitor circuit 410 additionally or alternatively receives a lock signal from the PLL circuit that generates the PLL IN clock and the PLL FB clock, and generates a lock alert signal indicating that a shock event has occurred in response to the PLL circuit indicating that the PLL circuit is no longer locked.

[0062] In some embodiments, the PLL monitoring circuit 410 generates the PLL STAT signal indicating that a shock event has occurred in response to any particular one of the alert signals indicating that a shock event has occurred. In some embodiments, the PLL monitoring circuit 410 generates the PLL STAT signal indicating that a shock event has occurred in response to a particular first alert signal and any one of the other alert signals that additionally indicate that a shock event has occurred. In some embodiments, the PLL monitoring circuit 410 generates the PLL STAT signal indicating that a shock event has occurred in response to any two or more of the alert signals indicating that a shock event has occurred.

[0063] Figure 5 A schematic circuit diagram of an acceleration monitor circuit 500 is shown in accordance with some embodiments. The acceleration monitor circuit 500 can be used as the acceleration monitor 320 in the shock recovery circuit 300. In some embodiments, the shock recovery circuit 300 uses another acceleration monitor circuit, e.g., an acceleration monitor circuit having similar or identical characteristics as the acceleration monitor circuit 500. The acceleration monitor circuit 500 includes a processor circuit 540 and a comparator circuit 550.

[0064] The processor circuit 540 receives acceleration signals from an accelerometer sensor, such as the accelerometer sensor 180. The processor circuit 540 is configured to calculate a mathematical square of each acceleration signal, and generate a total acceleration signal based on a sum of the calculated mathematical squares.

[0065] The comparator circuit 550 is configured to receive the total acceleration signal from the processor circuit 540. Further, the comparator circuit receives a reference value corresponding to an acceleration threshold. In some embodiments, the acceleration threshold is configurable, e.g., during a test operation or during a calibration operation. The comparator circuit 550 is configured to compare the total acceleration signal to the reference value. In response to the total acceleration signal being greater than the reference value, the comparator circuit 550 generates an acceleration status signal ACCSTAT indicating that a shock event has occurred. In response to the total acceleration signal being less than the reference value, the comparator circuit 550 generates an acceleration status signal ACCSTAT not indicating that a shock event has occurred.

[0066] In some embodiments, the acceleration monitoring circuit 500 is configured for use with a mechanical shock sensor that is sensitive to shock events in only two spatial dimensions. In such embodiments, the acceleration monitoring circuit 500 comprises the accelerometers 510 and 520, the processor circuit 540, and the comparator circuit 550, wherein the accelerometers 510 and 520 are sensitive to acceleration in the two spatial dimensions to which the mechanical shock sensor is sensitive.

[0067] Further, in such embodiments, the processor circuit 540 receives acceleration signals from the accelerometers 510 and 520. The processor circuit 540 is configured to calculate a mathematical square of each received acceleration signal and to generate the total acceleration signal based on the sum of the calculated mathematical squares.

[0068] Further, the comparator circuit 550 is configured to function similarly or identically to the function described above with reference to embodiments using three accelerometers 510, 520, and 530.

[0069] In some embodiments, the acceleration monitoring circuit 500 is configured for use with a mechanical shock sensor that is sensitive to shock events in only one spatial dimension. In such embodiments, the acceleration monitoring circuit 500 comprises the accelerometer 510, the processor circuit 540, and the comparator circuit 550, wherein the accelerometer 510 is sensitive to acceleration in the one spatial dimension to which the mechanical shock sensor is sensitive.

[0070] Further, in these embodiments, the processor circuit 540 receives an acceleration signal from the accelerometer 510. The processor circuit 540 is configured to calculate a mathematical square of the received acceleration signal and to generate the total acceleration signal based on the calculated mathematical square.

[0071] Further, the comparator circuit 550 is configured to function similarly or identically to the function described above with reference to embodiments using three accelerometers 510, 520, and 530.

[0072] Figure 6A flowchart showing a method 600 of using a clock generation system is shown, in accordance with some embodiments. The method 600 can be performed, for example, by a system such as the clock generation system 100. In some embodiments, the clock generation system 100 is configured to perform another method having various aspects similar or identical to various aspects of the method 600.

[0073] At block 610, an oscillator clock is generated. For example, an oscillator circuit such as the oscillator circuit 110 can generate an oscillator clock such as CKOSC. The clock generated at block 610 can be generated, for example, with an electronic oscillator such as any of a variety of ring oscillator circuit architectures or another electronic oscillator circuit.

[0074] At block 620, a PLL clock is generated. For example, a PLL such as the PLL 120 can generate a PLL clock such as the PLL clock CKPLL. The clock generated at block 620 can be generated, for example, by a PLL receiving an input clock generated by a mechanical oscillation sensor such as the mechanical oscillation sensor 140. Thus, the PLL clock is generated based in part on the mechanical oscillation structure.

[0075] At block 630, a system clock is generated based on the PLL clock generated at block 620. For example, the PLL clock or a derivative thereof can be provided to a plurality of circuits forming an electronic circuit or system. In some embodiments, the system is or includes an automotive instrument, a wearable device, a phone, a camera, an augmented reality or virtual reality device, or another system.

[0076] At block 640, one or more characteristics or parameters of the PLL clock are monitored. In some but not necessarily all embodiments, at block 640, one or more acceleration signals indicative of acceleration experienced by the mechanical oscillation structure are additionally monitored. Further, based on the monitored characteristics or parameters of the PLL clock and / or the acceleration signals, a shock signal is generated.

[0077] At block 650, if the shock signal indicates that the mechanical oscillation structure can not have experienced a shock event, at block 640, the monitoring of the characteristics or parameters of the PLL clock and / or the acceleration signals is continued. Further, if the shock signal indicates that the mechanical oscillation structure can have experienced a shock event, at block 660, the system clock is generated based on the oscillator clock generated at 610 rather than the PLL clock generated at block 620. For example, the oscillator clock or a derivative thereof can be provided to a circuit forming an electronic circuit or system.

[0078] Figure 7A flowchart showing a method 700 of using a clock generation system is shown, in accordance with some embodiments. The method 700 can be performed, for example, by a system such as the clock generation system 100. In some embodiments, the clock generation system 100 is configured to perform another method having aspects similar or identical to aspects of the method 700.

[0079] At block 710, an oscillator clock is generated. For example, an oscillator circuit such as the oscillator circuit 110 can generate an oscillator clock such as CKOSC. The clock generated at block 710 can be generated, for example, with an electronic oscillator such as any of a variety of ring oscillator circuit architectures or another electronic oscillator circuit.

[0080] At block 720, a system clock is generated based on the oscillator clock generated at block 710. For example, the oscillator clock or a derivative thereof can be provided to a plurality of circuits forming an electronic circuit or system. In some embodiments, the system is or includes an automotive instrument, a wearable device, a phone, a camera, an augmented reality or virtual reality device, or another system.

[0081] At block 730, a PLL clock is generated. For example, a PLL such as the PLL 120 can generate a PLL clock such as the PLL clock CKPLL. The clock generated at block 730 can be generated, for example, by a PLL receiving an input clock generated by a mechanical oscillation sensor such as the mechanical oscillation sensor 140. Thus, the PLL clock is generated based in part on the mechanical oscillation structure.

[0082] In some embodiments, the PLL clock generated at block 730 is generated after an impact signal indicates that the mechanical oscillation structure is disturbed due to an impact event experienced by the mechanical oscillation structure. For example, the PLL clock generated at block 730 can be generated based on the input clock from the mechanical oscillation sensor, where the PLL is adjusted to the input clock after the impact signal.

[0083] At block 740, a system clock is generated based on the PLL clock generated at block 730. For example, the PLL clock or a derivative thereof can be provided to a circuit forming an electronic circuit or system.

[0084] In some embodiments, the system clock generated at block 740 is generated after the shock signal indicates that the mechanical oscillation structure can have been disturbed due to a shock event experienced by the mechanical oscillation structure. For example, the system clock generated at block 740 can be generated based on the PLL clock a fixed duration or time period after the shock signal indicating that the mechanical oscillation structure can have been disturbed ceases. For example, in some embodiments, the system clock is generated at block 740 10 ms after the shock signal indicating that the mechanical oscillation structure can have been disturbed ceases. Other fixed time periods can be used. The time period should be of sufficient duration for the PLL and the input clock to the PLL to sufficiently recover from the shock event. In some embodiments, the system clock is generated at block 640 immediately after the shock signal indicating that the mechanical oscillation structure can have been disturbed ceases. In such embodiments, the shock signal indicating that the mechanical oscillation structure can have been disturbed ceases provides an indication that the PLL and the input clock to the PLL have sufficiently recovered from the shock event.

[0085] Examples of the application are summarized here. Other examples can also be understood from the entirety of the specification and claims.

[0086] Example 1. Another embodiment is a shock recovery circuit, the shock recovery circuit comprising:

[0087] a phase-locked loop (PLL) monitoring circuit configured to receive at least one of a PLL input clock and a PLL feedback clock, and generate a PLL status signal based on at least one of the PLL input clock and the PLL feedback clock, the PLL status signal indicating whether a shock event has occurred;

[0088] an acceleration monitoring circuit configured to receive acceleration data, and generate an acceleration status signal based on the acceleration data, the acceleration status signal indicating whether the shock event has occurred; and

[0089] a controller configured to

[0090] receive the PLL status signal and the acceleration status signal,

[0091] generate an enable signal, the enable signal indicating whether a mechanical oscillation sensor generating the PLL input clock is to operate, and

[0092] generate a multiplexer signal, the multiplexer signal indicating whether a system clock is to be generated based on the PLL feedback clock.

[0093] Example 2. The shock recovery circuit of example 1, wherein the PLL monitoring circuit is configured to monitor a duty cycle of the PLL input clock and generate a duty cycle alert signal indicative of the shock event in response to at least one of the monitored duty cycle differing from an expected duty cycle by more than a threshold or a rate of change of the monitored duty cycle differing from an expected rate of change of duty cycle by more than a threshold.

[0094] Example 3. The shock recovery circuit of example 1, wherein the PLL monitoring circuit is configured to monitor a period of the PLL input clock and generate a period alert signal indicative of the shock event in response to at least one of the monitored period differing from an expected period by more than a threshold or a rate of change of the monitored period differing from an expected rate of change of period by more than a threshold.

[0095] Example 4. The shock recovery circuit of example 1, wherein the PLL monitoring circuit is configured to monitor a phase difference between the PLL input clock and the PLL feedback clock and generate a phase difference alert signal indicative of the shock event in response to the monitored phase difference differing from an expected phase difference by more than a threshold.

[0096] Example 5. The shock recovery circuit of example 1, wherein the acceleration monitoring circuit comprises:

[0097] a processor circuit configured to receive first, second, and third acceleration signals each indicative of an acceleration in one of three orthogonal spatial dimensions, compute a mathematical square of each of the acceleration signals, and generate a total acceleration signal based on a sum of the computed mathematical squares; and

[0098] a comparator circuit configured to receive the total acceleration signal from the processor circuit and receive a reference value corresponding to an acceleration threshold, and further configured to compare the total acceleration signal to the reference value and generate the acceleration status signal indicative of the shock event in response to the total acceleration signal being greater than the reference value.

[0099] Example 6. The shock recovery circuit of example 1, wherein the controller is configured to generate the enable signal indicative of the mechanical oscillation sensor not operating in response to the PLL status signal being indicative of the shock event.

[0100] Example 7. The shock recovery circuit of example 1, wherein the controller is configured to generate the enable signal indicative of the mechanical oscillation sensor not operating in response to the acceleration status signal being indicative of the shock event.

[0101] Example 8. Another embodiment is a clock generation system comprising:

[0102] an oscillator circuit configured to electronically generate an oscillator clock;

[0103] a mechanical oscillation sensor comprising a mechanical oscillator and configured to generate a PLL input clock;

[0104] a phase-locked loop (PLL) configured to receive the PLL input clock and generate a PLL clock and a PLL feedback signal based on the PLL input clock;

[0105] a clock multiplexer configured to conditionally connect the PLL clock and the oscillator clock to an output of a system clock;

[0106] an acceleration sensor configured to sense an acceleration in each of one, two, or three orthogonal spatial dimensions and generate an acceleration measurement for each of the sensed spatial dimensions; and

[0107] a shock recovery circuit configured to receive one or more of the PLL input clock, the PLL feedback signal, and the acceleration measurement and generate a multiplexer control signal configured to cause the clock multiplexer to connect a particular one of the PLL clock and the oscillator clock to the output based on one or more of the PLL input clock, the PLL feedback signal, and the acceleration measurement, wherein the multiplexer control signal causes the clock multiplexer to connect the oscillator clock to the output in response to one or more of a received PLL input clock, a received PLL feedback signal, and a received acceleration measurement indicating a shock event.

[0108] Example 9. The clock generation system of example 8, wherein the shock recovery circuit comprises a duty cycle monitoring circuit configured to monitor a duty cycle of the PLL input clock and generate a duty cycle alert signal indicating the shock event in response to at least one of the monitored duty cycle differing from an expected duty cycle by more than a threshold or a monitored rate of change of the duty cycle differing from an expected rate of change of the duty cycle by more than a threshold.

[0109] Example 10. The clock generation system of example 8, wherein the shock recovery circuit is configured to monitor a period of the PLL input clock and generate a period alert signal indicating a shock event in response to at least one of the monitored period differing from an expected period by more than a threshold or a monitored rate of change of the period differing from an expected rate of change of the period by more than a threshold.

[0110] Example 11. The clock generation system of example 8, wherein the shock recovery circuit is configured to monitor a phase difference between the PLL input clock and the PLL feedback signal, and in response to the monitored phase difference differing from an expected phase difference by more than a threshold, generate a phase difference alert signal indicating the shock event.

[0111] Example 12. The clock generation system of example 8, wherein the acceleration sensor comprises a first accelerometer, a second accelerometer, and a third accelerometer, each accelerometer configured to monitor acceleration in one of three orthogonal spatial directions, and each accelerometer configured to generate a corresponding acceleration measurement indicative of the monitored acceleration.

[0112] Example 13. The clock generation system of example 12, wherein the shock recovery circuit comprises:

[0113] a processor circuit configured to receive the acceleration measurements from the first, second, and third accelerometers, compute a mathematical square of each of the acceleration measurements, and generate a total acceleration signal based on a sum of the computed mathematical squares; and

[0114] a comparator circuit configured to receive the total acceleration signal from the processor circuit, and receive a reference value corresponding to an acceleration threshold, and further configured to compare the total acceleration signal to the reference value, and in response to the total acceleration signal being greater than the reference value, generate an acceleration state signal indicating the shock event.

[0115] Example 14. The clock generation system of example 8, wherein the shock recovery circuit is configured to generate an enable signal indicating the mechanical oscillation sensor is not operational in response to one or more of the received PLL input clock, PLL feedback signal, and acceleration measurements indicating the shock event.

[0116] Example 15. The clock generation system of example 8, wherein the shock recovery circuit is configured to generate an enable signal indicating the mechanical oscillation sensor is not operational in response to the acceleration measurements indicating the shock event has occurred.

[0117] Example 16. Another embodiment is a method of using a clock generation system, the method comprising:

[0118] generating an oscillator clock;

[0119] generating a PLL input clock;

[0120] generating a PLL clock based on the PLL input clock;

[0121] generating a system clock based on the PLL clock;

[0122] monitoring the PLL clock;

[0123] generating a PLL status signal based on the monitored PLL clock;

[0124] monitoring acceleration of the clock generation system and generating an acceleration status signal based on the monitored acceleration;

[0125] in response to one or more of the PLL status signal and the acceleration status signal indicating a shock event, generating the system clock based on the oscillator clock; and

[0126] generating the system clock based on the PLL clock after a delay, wherein the delay is from generating the system clock based on the oscillator clock.

[0127] Example 17. The method of example 16, further comprising:

[0128] generating a PLL feedback clock; and

[0129] receiving one or more of the PLL input clock and the PLL feedback clock, wherein the PLL status signal is based on one or more of the PLL input clock and the PLL feedback clock.

[0130] Example 18. The method of example 17, wherein the PLL status signal is based on a duty cycle of the PLL input clock.

[0131] Example 19. The method of example 17, wherein the PLL status signal is based on a period of the PLL input clock.

[0132] Example 20. The method of example 17, wherein the PLL status signal is based on a phase difference between the PLL input clock and the PLL feedback clock.

Claims

1. A shock recovery circuit, comprising: a phase-locked loop (PLL) monitor circuit configured to receive at least one of a PLL input clock and a PLL feedback clock, and generate a PLL status signal based on at least one of the PLL input clock and the PLL feedback clock, the PLL status signal indicating whether a shock event has occurred; an acceleration monitor circuit configured to receive acceleration data, and generate an acceleration status signal based on the acceleration data, the acceleration status signal indicating whether the shock event has occurred; and a controller configured to receive the PLL status signal and the acceleration status signal, generate an enable signal indicating whether a mechanical oscillation sensor generating the PLL input clock is to operate, and generate a multiplexer signal indicating whether a system clock is to be generated based on the PLL feedback clock.

2. The shock recovery circuit of claim 1, wherein the PLL monitor circuit is configured to monitor a duty cycle of the PLL input clock, and generate a duty cycle alert signal indicating the shock event in response to at least one of the monitored duty cycle differing from an expected duty cycle by more than a threshold, or a monitored duty cycle rate of change differing from an expected duty cycle rate of change by more than a threshold.

3. The shock recovery circuit of claim 1, wherein the PLL monitor circuit is configured to monitor a period of the PLL input clock, and generate a period alert signal indicating a shock event in response to at least one of the monitored period differing from an expected period by more than a threshold, or a monitored period rate of change differing from an expected period rate of change by more than a threshold.

4. The shock recovery circuit of claim 1, wherein the PLL monitor circuit is configured to monitor a phase difference between the PLL input clock and the PLL feedback clock, and generate a phase difference alert signal indicating the shock event in response to the monitored phase difference differing from an expected phase difference by more than a threshold.

5. The shock recovery circuit of claim 1, wherein the acceleration monitor circuit comprises: a processor circuit configured to receive first, second, and third acceleration signals each indicating an acceleration in one of three orthogonal spatial dimensions, compute a mathematical square of each of the acceleration signals, and generate a total acceleration signal based on a sum of the computed mathematical squares; and a comparator circuit configured to receive the total acceleration signal from the processor circuit, and receive a reference value corresponding to an acceleration threshold, and further configured to compare the total acceleration signal to the reference value, and generate the acceleration status signal indicating the shock event in response to the total acceleration signal being greater than the reference value. ​ ​ 6. The shock recovery circuit of claim 1, wherein the controller is configured to generate the enable signal indicating that the mechanical shock sensor is not operational in response to the PLL status signal indicating the shock event.

7. The shock recovery circuit of claim 1, wherein the controller is configured to generate the enable signal indicating that the mechanical shock sensor is not operational in response to the acceleration status signal indicating the shock event.

8. A clock generation system comprising: an oscillator circuit configured to electronically generate an oscillator clock; a mechanical shock sensor comprising a mechanical shocker and configured to generate a PLL input clock; a phase-locked loop (PLL) configured to receive the PLL input clock and generate a PLL clock and a PLL feedback signal based on the PLL input clock; a clock multiplexer configured to conditionally connect the PLL clock and the oscillator clock to an output of a system clock; an acceleration sensor configured to sense acceleration in each of one, two, or three orthogonal spatial dimensions and generate an acceleration measurement for each of the sensed spatial dimensions; and a shock recovery circuit configured to receive one or more of the PLL input clock, the PLL feedback signal, and the acceleration measurements and generate a multiplexer control signal configured to cause the clock multiplexer to connect a particular one of the PLL clock and the oscillator clock to the output based on one or more of the PLL input clock, the PLL feedback signal, and the acceleration measurements, wherein the multiplexer control signal causes the clock multiplexer to connect the oscillator clock to the output in response to one or more of a received PLL input clock, a received PLL feedback signal, and a received acceleration measurement indicating a shock event.

9. The clock generation system of claim 8, wherein the shock recovery circuit comprises a duty cycle monitoring circuit configured to monitor a duty cycle of the PLL input clock and generate a duty cycle alert signal indicating the shock event in response to at least one of the monitored duty cycle differing from an expected duty cycle by more than a threshold or a monitored duty cycle rate of change differing from an expected duty cycle rate of change by more than a threshold.

10. The clock generation system of claim 8, wherein the shock recovery circuit is configured to monitor a period of the PLL input clock and generate a period alert signal indicating a shock event in response to at least one of the monitored period differing from an expected period by more than a threshold or a monitored period rate of change differing from an expected period rate of change by more than a threshold.

11. The clock generation system of claim 8, wherein the shock recovery circuit is configured to monitor a phase difference between the PLL input clock and the PLL feedback signal, and in response to the monitored phase difference differing from an expected phase difference by more than a threshold, generate a phase difference alert signal indicating the shock event.

12. The clock generation system of claim 8, wherein the acceleration sensor comprises a first accelerometer, a second accelerometer, and a third accelerometer, each configured to monitor acceleration in one of three orthogonal spatial directions, and each configured to generate a corresponding acceleration measurement indicative of the monitored acceleration.

13. The clock generation system of claim 12, wherein the shock recovery circuit comprises: a processor circuit configured to receive the acceleration measurements from the first, second, and third accelerometers, compute a mathematical square of each of the acceleration measurements, and generate a total acceleration signal based on a sum of the computed mathematical squares; and a comparator circuit configured to receive the total acceleration signal from the processor circuit, and receive a reference value corresponding to an acceleration threshold, and further configured to compare the total acceleration signal to the reference value, and in response to the total acceleration signal being greater than the reference value, generate an acceleration state signal indicating the shock event.

14. The clock generation system of claim 8, wherein the shock recovery circuit is configured to generate an enable signal indicating that the mechanical oscillation sensor is not operational in response to one or more of the received PLL input clock, the PLL feedback signal, and the acceleration measurements indicating the shock event.

15. The clock generation system of claim 8, wherein the shock recovery circuit is configured to generate an enable signal indicating that the mechanical oscillation sensor is not operational in response to the acceleration measurements indicating that the shock event has occurred.

16. A method of using a clock generation system, the method comprising: generating an oscillator clock; generating a PLL input clock; generating a PLL clock based on the PLL input clock; generating a system clock based on the PLL clock; monitoring the PLL clock; generating a PLL state signal based on the monitored PLL clock; monitoring acceleration of the clock generation system, and generating an acceleration state signal based on the monitored acceleration; in response to one or more of the PLL state signal and the acceleration state signal indicating a shock event, generating the system clock based on the oscillator clock; and after a delay, generating the system clock based on the PLL clock, wherein the delay begins from generating the system clock based on the oscillator clock.

17. The method of claim 16, further comprising: generating a PLL feedback clock; and receiving one or more of the PLL input clock and the PLL feedback clock, wherein the PLL status signal is based on one or more of the PLL input clock and the PLL feedback clock.

18. The method of claim 17, wherein the PLL status signal is based on a duty cycle of the PLL input clock.

19. The method of claim 17, wherein the PLL status signal is based on a period of the PLL input clock.

20. The method of claim 17, wherein the PLL status signal is based on a phase difference between the PLL input clock and the PLL feedback clock.

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