Electronic device, communication chip and transmitting terminal energy buffer processing control thereof
By introducing digital baseband circuits and control signals into the RF transmission circuit, the gradual rise and fall of RF energy are adjusted, solving the problem of insufficient flexibility in the energy processing at the transmitter in the existing technology, and achieving more efficient RF energy control.
Patent Information
- Application Number
- CN202410471103.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-18
- Publication Date
- 2025-10-24
AI Technical Summary
Existing RF transmission circuits lack flexibility in energy buffering at the transmitting end, resulting in electronic devices failing to meet RF energy requirements.
By employing a combination of digital baseband circuits, reference signal generation circuits, power amplifier drivers, and power amplifiers, the rise and fall of radio frequency energy are adjusted through control signals and control codes, thereby enhancing the flexibility of energy processing at the transmitter.
It improves the flexibility of energy handling at the transmitter, enabling electronic devices to better comply with various radio frequency energy regulations, and saves circuit area and cost.
Smart Images
Figure CN120834827A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to an electronic device, and in particular to an electronic device for implementing transmitter energy buffering control and a communication chip thereof. Background Art
[0002] A radio frequency (RF) transmitter circuit must handle the ramp-up and ramp-down of RF energy when it turns on (begins transmitting a signal) and turns off (ends transmitting a signal), respectively (collectively referred to as transmitter power ramping).
[0003] The RF transmitter circuit generally includes a power amplifier (PA) and a power amplifier driver (PAD). Figure 1 The circuit used for transmitting end energy buffering in the power amplifier driver is shown. Figure 1 The circuit mainly includes a current source 110, a transistor M1 and a low-pass filter 120. The low-pass filter 120 includes a resistor R1 and a capacitor C1. The voltage PA_bias is used to bias the power amplifier. Figure 1 The disadvantage of this circuit is that there are too few adjustable parameters, which makes the transmitter energy buffering lack flexibility, resulting in the RF energy of the electronic device failing to meet regulations in some cases. Summary of the Invention
[0004] In view of the deficiencies of the prior art, an object of the present invention is to provide an electronic device and a communication chip thereof to improve the deficiencies of the prior art.
[0005] An embodiment of the present invention provides a communications chip comprising: a digital baseband circuit, a reference signal generating circuit, a power amplifier driver, a power amplifier, and a digital-to-analog converter. The digital baseband circuit is configured to generate a control signal and a control code. The reference signal generating circuit is coupled to the digital baseband circuit and configured to generate a reference signal and change the frequency of the reference signal in accordance with the control signal. The power amplifier driver is coupled to the reference signal generating circuit. The power amplifier is coupled to the power amplifier driver. The digital-to-analog converter is coupled to the digital baseband circuit and configured to control the output power of at least one of the power amplifier driver and the power amplifier in accordance with the control code. The power amplifier driver and the power amplifier amplify the reference signal, and the control signal is not equal to the control code.
[0006] Another embodiment of the present application provides an electronic device for transmitting a radio frequency output signal or receiving a radio frequency input signal, comprising an antenna and a communication chip. The communication chip comprises a digital baseband circuit, a reference signal generating circuit, a power amplifier driver, a power amplifier, and a digital-to-analog converter. The digital baseband circuit is configured to generate a control signal and a control code. The reference signal generating circuit is coupled to the digital baseband circuit and configured to generate a reference signal and change a frequency of the reference signal according to the control signal. The power amplifier driver is coupled to the reference signal generating circuit. The power amplifier is coupled to the power amplifier driver. The digital-to-analog converter is coupled to the digital baseband circuit and configured to control an output power of at least one of the power amplifier driver and the power amplifier according to the control code. The power amplifier driver and the power amplifier amplify the reference signal, and the control signal is not equal to the control code.
[0007] The technical means embodied in the embodiments of the present application can improve at least one of the disadvantages of the prior art, so that the present application can improve the flexibility of the transmit end energy buffer processing compared with the prior art.
[0008] The features, practices, and effects of the present application will be described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS
[0009] Figure 1 An embodiment of the circuit for performing the transmit end energy buffer processing in the power amplifier driver is shown;
[0010] Figure 2 is a functional block diagram of an embodiment of the electronic device of the present application;
[0011] Figure 3 is a detailed functional block diagram of an embodiment of the communication chip of the present application;
[0012] Figure 4 An embodiment of the connection relationship of the impedance matching circuit, the power amplifier driver, and the power amplifier of Figure 3
[0013] Figure 5 is a functional block diagram of an embodiment of the transmit end energy buffer processing of the communication chip of the present application in the two-point modulation mode;
[0014] Figure 6 is a circuit diagram of an embodiment of the power amplifier driver and the power amplifier of the present application;
[0015] Figure 7 is a schematic diagram of an embodiment of the control code for the slow rise control of the radio frequency energy of the present application;
[0016] Figure 8 is a schematic diagram of an embodiment of the control code for the slow fall control of the radio frequency energy of the present application. DETAILED DESCRIPTION
[0017] The technical terms used in the following descriptions refer to the customary terms in this technical field. If this specification provides explanations or definitions for some terms, the interpretation of these terms shall be based on the explanations or definitions in this specification.
[0018] The disclosure of the present invention includes an electronic device and a communication chip thereof. Since some components of the electronic device and the communication chip thereof may be individually known components, the following description will omit details of the known components without affecting the full disclosure and feasibility of the device invention.
[0019] See also Figure 2 , Figure 2 2 is a functional block diagram of an embodiment of an electronic device of the present invention. Electronic device 200 includes a communication chip 201 and an antenna 205. Communication chip 201 includes pin 203, a digital baseband circuit 212, a reference signal generating circuit 214, an impedance matching circuit 216, a receiving circuit 220, and a transmitting circuit 230. Receiver circuit 220 includes a receiving front-end circuit 222, a filtering circuit 224, and an analog-to-digital converter (ADC) 226. Transmitter circuit 230 includes a transmitting front-end circuit 232, a filtering circuit 234, and a digital-to-analog converter (DAC) 236. Impedance matching circuit 216 is used to achieve impedance matching of the transmission line. Filter circuits 224 and 234 can be complex filters or low-pass filters (LPFs). Communication chip 201 is coupled to antenna 205 via pin 203.
[0020] The digital baseband circuit 212 is coupled or electrically connected to the reference signal generation circuit 214, the receive-end circuit 220, and the transmit-end circuit 230. For the transmit-end circuit 230 (more specifically, the transmit front-end circuit 232), the reference signal generation circuit 214 generates a reference signal Rf_tx1 in an in-phase quadrature modulation (IQM) mode (hereinafter referred to as the IQM mode) and a reference signal Rf_tx2 in a two-point modulation (TPM) mode (hereinafter referred to as the TPM mode). For the receive-end circuit 220 (more specifically, the receive front-end circuit 222), the reference signal generation circuit 214 generates a reference signal Rf_rx in both the IQM mode and the TPM mode, and the frequency of the reference signal Rf_rx in the IQM mode can or can not be equal to the frequency of the reference signal Rf_rx in the TPM mode.
[0021] The digital baseband circuit 212 generates a control signal Ctrl and a control code D_ramp. The digital baseband circuit 212 controls the reference signal generation circuit 214 to set or adjust (change) the frequency of the reference signal Rf_tx1 and / or the frequency of the reference signal Rf_tx2 by means of the control signal Ctrl. In the IQM mode, the frequency of the reference signal Rf_tx1 is constant (i.e., the reference signal Rf_tx1 is a single tone signal). In the TPM mode, the digital baseband circuit 212 frequency modulates (FM) the reference signal Rf_tx2 (equivalent to frequency modulating the radio frequency output signal STx) by means of the control signal Ctrl.
[0022] In the IQM mode, the transmit-end circuit 230 converts the digital output signal Dout generated by the digital baseband circuit 212 into a radio frequency output signal STx, which is coupled to the antenna 205 via the impedance matching circuit 216 and the pin 203. More specifically, the digital-to-analog converter 236 converts the digital output signal Dout into an analog output signal Sout. The filter circuit 234 filters the analog output signal Sout to generate a filtered analog output signal Sout'. The transmit front-end circuit 232 up-converts and amplifies the filtered analog output signal Sout' according to the reference signal Rf_tx1 to generate the radio frequency output signal STx.
[0023] In the TPM mode, the filter circuit 234 and the digital-to-analog converter 236 are inactive, and the transmit front-end circuit 232 amplifies the reference signal Rf_tx2 to generate the radio frequency output signal STx. The radio frequency output signal STx is coupled to the antenna 205 via the impedance matching circuit 216 and the pin 203.
[0024] The receive front-end circuit 222 down-converts the radio frequency input signal SRx according to the reference signal Rf_rx to generate an analog input signal Sin. The filter circuit 224 filters the analog input signal Sin to generate a filtered analog input signal Sin'. The analog-to-digital converter 226 converts the filtered analog input signal Sin' to the digital input signal Din.
[0025] Since the receive front-end circuit 220 and the transmit front-end circuit 230 share the impedance matching circuit 216, the communication chip 201 can transmit the radio frequency output signal STx or receive the radio frequency input signal SRx through the same pin (i.e., the pin 203). Moreover, because the receive front-end circuit 220 and the transmit front-end circuit 230 share the pin 203, the antenna 205 does not need to switch between two pins. That is, the pin 203 and the antenna 205 can be electrically connected to each other.
[0026] Please refer to Figure 3 , Figure 3 is a detailed function block diagram of an embodiment of the communication chip 201 of the present application. The reference signal generation circuit 214 includes a synthesizer 214_1, a frequency division circuit 214_3, and a buffer circuit 214_5. The receive front-end circuit 222 includes an in-phase / quadrature (IQ) generator 222_1, a mixing circuit 222_3, and a low noise amplifier (LNA) 222_5. The analog-to-digital converter 226 includes an analog-to-digital converter 226_1 and an analog-to-digital converter 226_3. The transmit front-end circuit 232 includes an IQ generator 232_1, a mixing circuit 232_3, a power amplifier driver (PAD) 232_5, and a power amplifier 232_7. The digital-to-analog converter 236 includes a digital-to-analog converter 236_1 and a digital-to-analog converter 236_3. The following is described with respect to the IQM mode and the TPM mode, respectively.
[0027] Mode (one): IQM mode.
[0028] The synthesizer 214_1 generates a frequency-fixed reference signal Rf_tx1 (i.e., the reference signal Rf_tx1 is a single tone), and the frequency divider circuit 214_3 and the buffer circuit 214_5 are inactive or disabled (in other words, the reference signal Rf_tx2 does not exist in the IQM mode). More specifically, the digital baseband circuit 212 sets the frequency of the reference signal Rf_tx1 with the control signal Ctrl, and then the synthesizer 214_1 operates at the frequency; or the synthesizer 214_1 operates at a default frequency (i.e., the frequency of the reference signal Rf_tx1) without being controlled by the control signal Ctrl.
[0029] In some embodiments, the control signal Ctrl is a digital signal, and the synthesizer 214_1 is a digitally controlled synthesizer (e.g., including a digital controlled oscillator (DCO)).
[0030] When the communication chip 201 transmits a signal, the in-phase / quadrature generation circuit 232_1 generates in-phase and quadrature signals according to the reference signal Rf_tx1, and the mixing circuit 232_3 up-converts the filtered analog output signal Sout' to generate a radio frequency signal S_RF. The radio frequency signal S_RF is amplified by the power amplifier driver 232_5 and the power amplifier 232_7 to generate a radio frequency output signal STx.
[0031] When the communication chip 201 receives a signal, the synthesizer 214_1 generates a reference signal Rf_rx, the in-phase / quadrature generation circuit 222_1 generates in-phase and quadrature signals according to the reference signal Rf_rx, and the mixing circuit 222_3 down-converts the output signal of the low noise amplifier 222_5 to generate an analog input signal Sin.
[0032] Mode (two): TPM mode.
[0033] When communication chip 201 transmits a signal, digital baseband circuit 212 uses control signal Ctrl to control synthesizer 214_1, varying the frequencies of reference signals Rf_tx1 and Rf_tx2 to frequency modulate the RF output signal STx. Reference signal Rf_tx2 is the result of processing reference signal Rf_tx1 through frequency divider circuit 214_3 and buffer circuit 214_5. Power amplifier driver 232_5 and power amplifier 232_7 amplify reference signal Rf_tx2 to generate RF output signal STx. Frequency divider circuit 214_3 ensures that the frequency of RF output signal STx is not equal to that of reference signal Rf_tx1. This prevents the high energy of RF output signal STx from affecting the operation of synthesizer 214_1 when the frequency of RF output signal STx and reference signal Rf_tx1 are the same. Buffer circuit 214_5 boosts signal energy to counteract signal attenuation on the transmission line.
[0034] In some embodiments, if the energy of the RF output signal STx is relatively small or the synthesizer 214_1 is relatively ideal, the frequency dividing circuit 214_3 may be omitted.
[0035] In some embodiments, if the signal attenuation on the transmission line is relatively small, the buffer circuit 214_5 may be omitted.
[0036] The operation of the receive front-end circuit 222 in TPM mode is identical to that in IQM mode, and therefore will not be further described. It should be noted that when the communication chip 201 receives signals, whether in IQM or TPM mode, the reference signal Rf_rx is a single-tone signal. In other words, the digital baseband circuit 212 does not frequency modulate the reference signal Rf_rx.
[0037] As can be seen from the above, in the TPM mode, the digital baseband circuit 212 modulates the frequency of the reference signal Rf_tx1 (equivalent to modulating the frequencies of the reference signal Rf_tx2 and the RF output signal STx) via the control signal Ctrl.
[0038] In some embodiments, since the in-phase and quadrature generation circuit 232_1 , the mixing circuit 232_3 , the filtering circuit 234 , and the digital-to-analog converter 236 are inactive in the TPM mode, the digital baseband circuit 212 may shut down or disable these components to save power.
[0039] See also Figure 4 , Figure 4 Show Figure 3 The embodiment of the connection relationship between the impedance matching circuit 216, the power amplifier driver 232_5 and the power amplifier 232_7. Figure 4In an embodiment, impedance matching circuit 216 is a transformer, and transmit front-end circuit 232 includes a transformer 430 in addition to power amplifier driver 232_5 and power amplifier 232_7. Power amplifier driver 232_5 includes sub-power amplifier driver 410 and sub-power amplifier driver 420 for processing (e.g., amplifying) reference signal Rf_tx2 and radio frequency signal S_RF, respectively. Primary side of transformer 430 is coupled or electrically connected to sub-power amplifier driver 410 and sub-power amplifier driver 420, and secondary side is coupled or electrically connected to power amplifier 232_7, where voltage PA_Vg is the gate bias voltage of the main transistor of power amplifier 232_7. Primary side of impedance matching circuit 216 is coupled or electrically connected to power amplifier 232_7, and secondary side is coupled or electrically connected to antenna 205, where voltage VDD is the power supply voltage of power amplifier 232_7.
[0040] Referring to Figure 5 , Figure 5 is a functional block diagram of an embodiment of transmit energy ramping processing of communication chip 201 in TPM mode. As discussed previously, because in TPM mode, filter circuit 234, in-phase quadrature generation circuit 232_1, and mixing circuit 232_3 are not active and / or disabled, these elements are omitted. In TPM mode, digital-to-analog converter 236 is used for transmit energy ramping processing. More specifically, digital baseband circuit 212 generates control code D_ramp for performing transmit energy ramping processing, and digital-to-analog converter 236 converts control code D_ramp into control signal Ctrl_ramp to control at least one of power amplifier driver 232_5 and power amplifier 232_7 (e.g., to control at least one output power of the at least one). Note that control code D_ramp is not equal to control signal Ctrl. Figure 5
[0041] Referring to Figure 6 , Figure 6 is a circuit diagram of an embodiment of the power amplifier driver and power amplifier of the present invention. The sub-power amplifier driver 410 is similar to the power amplifier 232_7. The sub-power amplifier driver 410 (power amplifier 232_7) includes a transistor M3a (M3b), a transistor M4a (M4b), a capacitor C2a (C2b), a resistor R2a (R2b), a resistor R3a (R3b), a current source I1a (I1b), a transistor M5a (M5b), a transistor M6a (M6b), and an inductor L1a (L1b). The transistor M5a (M5b) is the main transistor of the sub-power amplifier driver 410 (power amplifier 232_7) that dominates the gain of the sub-power amplifier driver 410 (power amplifier 232_7).
[0042] The gate of the transistor M3a (M3b) is coupled or electrically connected to the gate of the transistor M2. The source of the transistor M3a (M3b) is coupled or electrically connected to the voltage VDD. The drain of the transistor M3a (M3b) is coupled or electrically connected to the drain of the transistor M4a (M4b).
[0043] The gate of the transistor M4a (M4b) is coupled or electrically connected to the drain of the transistor M4a (M4b). The source of the transistor M4a (M4b) is coupled or electrically connected to the ground voltage GND.
[0044] The source of the transistor M5a (M5b) is coupled or electrically connected to the ground voltage GND. The gate of the transistor M5a (M5b) is coupled to the gate of the transistor M4a (M4b) through the resistor R2a (R2b). The drain of the transistor M5a (M5b) is coupled to the inductor L1a (L1b) through the transistor M6a (M6b).
[0045] One end of the capacitor C2a is coupled or electrically connected to the gate of the transistor M5a; the other end of the capacitor C2a receives the input signal PAD_in (e.g., the reference signal Rf_tx2). Similarly, one end of the capacitor C2b is coupled or electrically connected to the gate of the transistor M5b; the other end of the capacitor C2b receives the input signal PA_in (i.e., the output signal PAD_out of the sub-power amplifier driver 410).
[0046] The source of the transistor M6a (M6b) is coupled or electrically connected to the drain of the transistor M5a (M5b). The drain of the transistor M6a (M6b) is coupled or electrically connected to the inductor L1a (L1b).
[0047] The first end of the inductor L1a (L1b) is coupled or electrically connected to the drain of the transistor M6a (M6b); the second end of the inductor L1a (L1b) is coupled or electrically connected to the voltage VDD.
[0048] One end of the current source I1a (I1b) is coupled to or electrically connected to the voltage VDD; the other end of the current source I1a (I1b) is coupled to or electrically connected to the gate of the transistor M6a (M6b).
[0049] One end of the resistor R3 a ( R3 b ) is coupled to or electrically connected to the ground voltage GND; the other end of the resistor R3 a ( R3 b ) is coupled to or electrically connected to the gate of the transistor M6 a ( M6 b ).
[0050] Transistor M2 and current source 610 are connected in series between a reference voltage (e.g., voltage VDD) and another reference voltage (e.g., ground voltage GND). Current source 610 is a current digital-to-analog converter (IDAC). The current of current source 610 (i.e., the current Idac flowing through transistor M2) is controlled by a control code D_ramp.
[0051] Please also see Figure 5 and Figure 6 In some embodiments, the current source 610 may be one of the digital-to-analog converter 236_1 and the digital-to-analog converter 236_3, and the current Idac may correspond to Figure 5 The regulation signal Ctrl_ramp.
[0052] See also Figure 6 Because transistors M3a (M3b) and M2 form a current mirror, the current flowing through transistors M4a (M4b) is also controlled by the control code D_ramp, resulting in a voltage TPM_PAD_Vg (PA_Vg) proportional to the current Idac. In other words, the gate bias of the main transistor M5a (M5b) varies with the control code D_ramp, and the variation trend is similar to or substantially the same as the variation trend of the current Idac. Because the gain of transistors M5a (M5b) is related to their gate bias, the digital baseband circuit 212 can control the output power of the sub-power amplifier driver 410 (power amplifier 232_7) via the control code D_ramp.
[0053] The transistor M6a (M6b) is coupled to the transistor M5a (M5b) to boost the overall gain of the sub-power amplifier driver 410 (the power amplifier 232_7). The current source I1a (I1b) and the resistor R3a (R3b) are used to bias the transistor M6a (M6b). The drain of the transistor M6a (M6b) is coupled to the voltage VDD through the inductor L1a (L1b). The drain of the transistor M6a and the drain of the transistor M6b are the output of the sub-power amplifier driver 410 and the power amplifier 232_7, respectively. The inductor L1a and the inductor L1b are the load of the sub-power amplifier driver 410 and the power amplifier 232_7, respectively. The power amplifier 232_7 outputs the output signal PA_out (corresponding to the radio frequency output signal STx) through the drain of the transistor M6b. Figure 5
[0054] In summary, since the digital baseband circuit 212 can generate the accurate control code D_ramp, the digital baseband circuit 212 can accurately perform the transmit end energy ramping process and improve the flexibility of the transmit end energy ramping process.
[0055] In some embodiments, the transistor M6a, the current source I1a, the resistor R3a, the transistor M6b, the current source I1b and the resistor R3b can be omitted. In this case, the first end of the inductor L1a (L1b) is coupled or electrically connected to the drain of the transistor M5a (M5b), and the drain of the transistor M5a (M5b) becomes the output of the sub-power amplifier driver 410 (the power amplifier 232_7).
[0056] Please refer to Figure 7 and Figure 8 , Figure 7 and Figure 8 are schematic diagrams of embodiments of the control code D_ramp of the present application. Figure 7 corresponding to the ramp-up control of the radio frequency energy, and Figure 8 corresponding to the ramp-down control of the radio frequency energy. In Figure 7 and Figure 8 , the control code D_ramp is 8 bits. As shown in Figure 7 , the digital baseband circuit 212 controls the control code D_ramp to gradually increase from the minimum value (0) to the maximum value (255) within a specified time to achieve the ramp-up control curve of the radio frequency energy of Figure 7 . As shown in Figure 8 , the digital baseband circuit 212 controls the control code D_ramp to gradually decrease from the maximum value to the minimum value within a specified time to achieve the ramp-up control curve of the radio frequency energy of Figure 8 .
[0057] Note that the variations of the current Idac, the voltage TPM_PAD_Vg, and the voltage PA_Vg with respect to time are approximately or substantially equal to Figure 7 or Figure 8 a curve.
[0058] In summary, the communication chip 201 of the present application can support both the IQM mode and the TPM mode, and in the TPM mode, the transmit-side energy buffering is implemented using the digital-to-analog converter 236 of the IQM mode. In other words, the IQM mode and the TPM mode also share the digital-to-analog converter 236. Therefore, the communication chip 201 of the present application can not only save circuit area and cost, but also perform the transmit-side energy buffering more flexibly in the TPM mode, making the communication chip 201 and the electronic device 200 more likely to comply with various regulations on radio frequency energy.
[0059] Note that performing the transmit-side energy buffering on at least one of the sub-power amplifier driver 410 and the power amplifier 232_7 can achieve the purpose of improving the flexibility of the transmit-side energy buffering.
[0060] Although the foregoing embodiments are exemplified by the two-point modulation and the in-phase quadrature modulation, this is not a limitation of the present application, and those skilled in the art can appropriately apply the present application to other types of modulation mechanisms according to the disclosure of the present application.
[0061] Note that in the foregoing diagrams, the shapes, sizes, and proportions of the elements are only for the purpose of understanding the present application by those skilled in the art, and are not intended to limit the present application.
[0062] Although the embodiments of the present application are described above, these embodiments are not intended to limit the present application, and those skilled in the art can make changes to the technical features of the present application according to the explicit or implicit content of the present application, and any such changes can be within the scope of the patent protection sought by the present application. In other words, the scope of the patent protection of the present application shall be determined by the scope of the patent application defined in the specification.
[0063]
Symbol Description
[0064] 110, 610, I1a, I1b: current source
[0065] 120: low-pass filter
[0066] C1, C2a, C2b: capacitor
[0067] M1, M2, M3a, M3b, M4a, M4b, M5a, M5b, M6a, M6b: transistor
[0068] PA_bias, PA_Vg, VDD, TPM_PAD_Vg: voltage
[0069] R1, R2a, R2b, R3a, R3b: resistor
[0070] 200: electronic device
[0071] 201: communication chip
[0072] 203: pin
[0073] 205: antenna
[0074] 212: digital baseband circuit
[0075] 214: reference signal generation circuit
[0076] 216: impedance matching circuit
[0077] 220: receive-end circuit
[0078] 222: receive-front-end circuit
[0079] 224, 234: filter circuit
[0080] 226, 226_1, 226_3: analog-to-digital converter
[0081] 230: transmit-end circuit
[0082] 232: transmit-front-end circuit
[0083] 236, 236_1, 236_3: digital-to-analog converter
[0084] Ctrl: control signal
[0085] Din: digital input signal
[0086] Dout: digital output signal
[0087] Rf_rx, Rf_tx1, Rf_tx2: reference signal
[0088] Sin: analog input signal
[0089] Sin': filtered analog input signal
[0090] Sout: analog output signal
[0091] Sout': filtered analog output signal
[0092] SRx: radio frequency input signal
[0093] STx: radio frequency output signal
[0094] 214_1: synthesizer
[0095] 214_3: frequency elimination circuit
[0096] 214_5: buffer circuit
[0097] 222_1, 232_1: in-phase quadrature generation circuit
[0098] 222_3, 232_3: mixing circuit
[0099] 222_5: low-noise amplifier
[0100] 232_5: power amplifier driver
[0101] 232_7: power amplifier
[0102] S_RF: radio frequency signal
[0103] 410, 420: sub-power amplifier driver
[0104] 430: transformer
[0105] Ctrl_ramp: adjustment signal
[0106] D_ramp: control code
[0107] GND: ground voltage
[0108] Idac: current
[0109] L1a, L1b: inductor
[0110] PA_in, PAD_in: input signal
[0111] PA_out, PAD_out: output signal
Claims
1. A communication chip, comprising: a digital baseband circuit to generate a control signal and a control code; a reference signal generation circuit coupled to the digital baseband circuit to generate a reference signal and to vary a frequency of the reference signal according to the control signal; a power amplifier driver coupled to the reference signal generation circuit; a power amplifier coupled to the power amplifier driver; a digital-to-analog converter coupled to the digital baseband circuit to control at least one output power of at least one of the power amplifier driver and the power amplifier according to the control code; wherein the power amplifier driver and the power amplifier amplify the reference signal, and the control signal is not equal to the control code.
2. The communication chip of claim 1, wherein, The digital baseband circuit further generates a digital output signal, the digital-to-analog converter is to convert the digital output signal into an analog output signal, the communication chip transmits a radio frequency output signal, the communication chip further comprises: a filter circuit coupled to the digital-to-analog converter to filter the analog output signal to generate a filtered analog output signal; and a transmit front-end circuit coupled to the filter circuit to up-convert and amplify the filtered analog output signal according to the reference signal to generate the radio frequency output signal; wherein the power amplifier driver and the power amplifier are part of the transmit front-end circuit.
3. The communication chip of claim 2, further comprising: an impedance matching circuit coupled to the transmit front-end circuit; a pin coupled to the impedance matching circuit; a receive circuit coupled to the impedance matching circuit to receive a radio frequency input signal through the pin and the impedance matching circuit; wherein the transmit front-end circuit transmits the radio frequency output signal through the impedance matching circuit and the pin.
4. The communication chip of claim 1, wherein, The communication chip further comprises a first transistor coupled to the digital-to-analog converter, the power amplifier driver or the power amplifier comprises: a load; a resistor; a second transistor coupled to the first transistor and forming a current mirror with the first transistor; a third transistor coupled to the second transistor and having a first gate, a first source and a first drain, wherein the first drain is coupled to the second transistor, the first source is coupled to a first reference voltage; a fourth transistor having a second gate, a second source and a second drain, wherein the second source is coupled to the first reference voltage, the second drain is coupled to a second reference voltage through the load, and the second gate is coupled to the first gate through the resistor; and a capacitor having a first terminal and a second terminal, wherein the first terminal is coupled to the second gate, and the second terminal receives a signal.
5. The communication chip of claim 4, wherein, The resistor is a first resistor, the power amplifier driver or the power amplifier comprises: a fifth transistor having a third gate, a third source and a third drain, wherein the third source is coupled to the second drain, and the third drain is coupled to the load; a current source coupled between the second reference voltage and the third gate; and a second resistor coupled between the first reference voltage and the third gate.
6. The communication chip of claim 4, wherein, The first gate is electrically connected to the first drain.
7. An electronic device to transmit a radio frequency output signal or receive a radio frequency input signal, comprising: an antenna; and a communication chip, comprising: a digital baseband circuit to generate a control signal and a control code; a reference signal generation circuit coupled to the digital baseband circuit to generate a reference signal and to vary a frequency of the reference signal according to the control signal; a power amplifier driver coupled to the reference signal generation circuit; a power amplifier coupled to the power amplifier driver; and a digital-to-analog converter coupled to the digital baseband circuit to control at least one output power of at least one of the power amplifier driver and the power amplifier according to the control code; wherein the power amplifier driver and the power amplifier amplify the reference signal, and the control signal is not equal to the control code. 8.The electronic device of claim 7, wherein, The communication chip further includes: a pin coupled to the antenna; and an impedance matching circuit coupled to the pin; wherein the communication chip transmits the radio frequency output signal through the pin and the impedance matching circuit, or receives the radio frequency input signal through the pin and the impedance matching circuit. 9.The electronic device of claim 7, wherein, The digital baseband circuit further generates a digital output signal, the digital-to-analog converter is to convert the digital output signal into an analog output signal, and the communication chip further includes: a filter circuit coupled to the digital-to-analog converter to filter the analog output signal to generate a filtered analog output signal; and a transmit front-end circuit coupled to the filter circuit to up-convert and amplify the filtered analog output signal according to the reference signal to generate the radio frequency output signal; wherein the power amplifier driver and the power amplifier are part of the transmit front-end circuit. 10.The electronic device of claim 7, wherein, The communication chip further includes a first transistor coupled to the digital-to-analog converter, and the power amplifier driver or the power amplifier includes: a load; a resistor; a second transistor coupled to the first transistor and forming a current mirror with the first transistor; a third transistor coupled to the second transistor and having a first gate, a first source, and a first drain, wherein the first drain is coupled to the second transistor, the first source is coupled to a first reference voltage; a fourth transistor having a second gate, a second source, and a second drain, wherein the second source is coupled to the first reference voltage, the second drain is coupled to a second reference voltage through the load, and the second gate is coupled to the first gate through the resistor; and a capacitor having a first end and a second end, wherein the first end is coupled to the second gate, and the second end receives a signal.