MIPI receiving device and calibration method for MIPI receiving device
By performing multiple phase delays on the clock and data signals in the MIPI receiving device and determining the optimal phase delay value, the problem of skew between the clock and data signals at the MIPI receiving end is solved, more extensive and effective calibration is achieved, and data sampling accuracy is improved.
Patent Information
- Application Number
- CN202410471404.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-18
- Publication Date
- 2025-10-24
AI Technical Summary
There is a skew between the clock signal and data signal at the MIPI receiver, which leads to data sampling errors. Existing technologies are difficult to calibrate effectively.
By performing multiple phase delays on the clock channel and data channel in the MIPI receiving device, sampling data calibration is performed using a set step size, and the optimal phase delay values of the data signal and clock signal are determined to achieve bidirectional adjustment calibration.
The calibration range is increased, the unidirectional adjustment failure of the existing method is avoided, the internal and external skew of the MIPI receiver can be effectively calibrated, and the data sampling accuracy is improved.
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Figure CN120834873A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the MIPI technical field, and in particular to a MIPI receiving device and a calibration method for the MIPI receiving device. BACKGROUND
[0002] The MIPI (Mobile Industry Processor Interface) protocol is a protocol proposed for the standardization of high-speed communication of mobile devices, including a logical layer protocol and a physical layer protocol. The logical layer protocol of MIPI is a special data transmission protocol for different purposes such as storage, camera, display screen, vehicle communication, etc. The physical layer protocol includes D-PHY, M-PHY and C-PHY. D-PHY is part of the MIPI protocol, which describes a synchronous, high-speed, low-power physical layer. D-PHY includes, for example, the definition of DSI (Display Serial Interface) and CSI (Camera Serial Interface) on the physical layer.
[0003] According to the MIPI D-PHY protocol, the MIPI transmitting end and the receiving end each include a plurality of data lanes and a clock lane, the plurality of data lanes are independent of each other, and share one clock lane. Due to transmission channel delay and interference of external environment (such as temperature, electromagnetic noise), there is often a different delay between the clock signal and the data signal transmitted from the MIPI transmitting end to the MIPI receiving end through the data lane and the clock lane, resulting in misalignment of the clock signal and the data signal, that is, the clock signal and the data signal have skew. The larger the skew, the greater the probability of data sampling error. For the MIPI receiving end, the skew size between the input clock signal and the data signal is unknown. If the clock signal is directly used to sample the data signal to obtain data, it may cause serious data errors. SUMMARY
[0004] Therefore, the present application provides a MIPI receiving device and a calibration method for the MIPI receiving device, which takes the actual input data as the basis for judgment and adjusts the phase difference between the clock signal and the data in both directions.
[0005] According to an embodiment of the present disclosure, a calibration method for a MIPI receiving device is provided, the MIPI receiving device including a clock lane and a data lane, and the calibration method includes:
[0006] The clock signal of the clock lane is phase delayed multiple times according to a set step size;
[0007] sampling the data signal of the data channel using the clock signal after each phase delay, and determining a first calibration result corresponding to the clock signal after each phase delay according to the sampled data;
[0008] phase delaying the data signal of the data channel multiple times according to the set step;
[0009] sampling the data signal after each phase delay using the clock signal of the clock channel, and determining a second calibration result corresponding to the data signal after each phase delay according to the sampled data;
[0010] determining a preferred phase delay value of the data signal and a preferred phase delay value of the clock signal from the phase delay values of the clock signals and the phase delay values of the data signals according to the multiple first calibration results and the multiple second calibration results.
[0011] In some embodiments, the determining the preferred phase delay value of the data signal and the preferred phase delay value of the clock signal comprises:
[0012] concatenating the multiple second calibration results arranged in descending order of the delay steps and the multiple first calibration results arranged in ascending order of the delay steps into a row; and
[0013] determining a middle value of a maximum number of continuous data sequences representing successful calibration in the row, and determining the preferred phase delay value of the data signal and the preferred phase delay value of the clock signal according to the delay steps of the data signal and the delay steps of the clock signal corresponding to the middle value.
[0014] In some embodiments, the MIPI receiving end comprises multiple data channels generating multiple independent data signals, and the calibration method further comprises: phase delaying the clock signal according to the preferred phase delay value of the clock signal to obtain a calibrated clock signal; and using the calibrated clock signal to calibrate the remaining data signals.
[0015] In some embodiments, the maximum number of continuous data sequences representing successful calibration is greater than a set threshold.
[0016] In some embodiments, the method further comprises: phase delaying the clock signal of the clock channel according to the preferred phase delay value of the clock signal; and phase delaying the data signal of the data channel according to the preferred phase delay value of the data signal.
[0017] In some embodiments, the method further comprises: selecting a signal with a smaller preferred phase delay value for phase delay, and setting the phase delay value of the selected signal equal to the preferred phase delay value; and selecting a signal with a larger preferred phase delay value not for phase delay, and setting the phase delay value of the selected signal equal to zero.
[0018] In some embodiments, the MIPI receiving device performs the calibration method when connected with an external MIPI transmitting device.
[0019] According to another embodiment of the present disclosure, a MIPI receiving device is provided, comprising a clock channel and a data channel, comprising:
[0020] a first parallel-to-serial conversion circuit, configured to convert a clock differential signal received by the clock channel into a clock signal;
[0021] a second parallel-to-serial conversion circuit, configured to convert a data differential signal received by the data channel into a data signal;
[0022] a first phase shift module, configured to perform phase delay on the clock signal according to a first delay value;
[0023] a second phase shift module, configured to perform phase delay on the data signal according to a second delay value;
[0024] a calibration module, configured to calculate a plurality of the first delay values and a plurality of the second delay values according to a set step, receive a plurality of first calibration results and a plurality of second calibration results, and determine a preferred phase delay value of the data signal and a preferred phase delay value of the clock signal from the plurality of the first delay values and the plurality of the second delay values respectively according to the plurality of the first calibration results and the plurality of the second calibration results;
[0025] a sampling module, configured to sample the data signal of the data channel using the clock signal after each phase delay, and sample the data signal after each phase delay using the clock signal of the clock channel;
[0026] a state machine, configured to determine the first calibration result corresponding to each phase delay of the clock signal and the second calibration result corresponding to each phase delay of the data signal according to the sampling data.
[0027] In some embodiments, the first phase shift module further comprises performing phase delay according to the preferred phase delay value of the clock signal; and the second phase shift module further comprises performing phase delay according to the preferred phase delay value of the data signal.
[0028] In some embodiments, when the preferred phase delay value of the clock signal is greater than the preferred phase delay value of the data signal, only the second phase shift module performs phase delay according to the preferred phase delay value of the data signal; and when the preferred phase delay value of the clock signal is less than or equal to the preferred phase delay value of the data signal, only the first phase shift module performs phase delay according to the preferred phase delay value of the clock signal.
[0029] In some embodiments, the calibration module is further configured to:
[0030] splicing the plurality of second calibration results arranged in descending order of the delay steps and the plurality of first calibration results arranged in ascending order of the delay steps into a row; and
[0031] In the row, selecting a maximum number of continuous middle values of the data sequences representing successful calibration, and determining the phase delay preferred value of the data signal and the phase delay preferred value of the clock signal according to the delay step of the data signal and the delay step of the clock signal corresponding to the middle values.
[0032] In some embodiments, the maximum number of continuous data sequences representing successful calibration is greater than a set threshold.
[0033] In summary, the MIPI receiving device and the calibration method provided by the embodiments of the present disclosure have the following advantages:
[0034] 1. The calibration range is increased, and the situation that the existing dynamic calibration method depends on a specific dynamic calibration sequence and can only adjust the phase of the clock signal in one direction for calibration, thereby failing to calibrate, is effectively avoided.
[0035] 2. Although the existing static calibration method supports adjusting the phase of the clock signal in both directions for calibration, it can only adjust the internal skew of the MIPI receiving end. However, the embodiments of the present disclosure can achieve adjustment and calibration of the internal and external skew of the MIPI receiving end by respectively increasing the delay of the clock signal and the data signal. BRIEF DESCRIPTION OF DRAWINGS
[0036] The above and other objects, features and advantages of the present application will become more apparent from the following description when taken in conjunction with the accompanying drawings, in which:
[0037] Figure 1 is an example of a communication applying MIPI;
[0038] Figure 2 is a structural schematic diagram of the MIPI receiving device provided by the embodiments of the present disclosure;
[0039] Figure 3 is a flowchart of the calibration method applied to the MIPI receiving device provided by an embodiment of the present disclosure;
[0040] Figure 4is a flowchart of a calibration method applied to a MIPI receiving device provided by another embodiment of the present disclosure.
[0041] Figure 5 is Figure 4 An example of the first calibration result and the second calibration result mentioned by the embodiment being spliced into a row. DETAILED DESCRIPTION
[0042] The present application is described below based on embodiments, but the present application is not limited to only these embodiments. In the following detailed description of the present application, some specific details are described in detail. The present application can also be fully understood without the description of these details. In order to avoid confusion of the essence of the present application, the well-known methods, processes, and flows are not described in detail. In addition, the drawings are not necessarily drawn to scale.
[0043] The flowcharts and block diagrams in the drawings illustrate the possible system, method, and device of the embodiments of the present application, the blocks on the flowcharts and block diagrams can represent a module, a program segment, or only a piece of code, which are executable instructions for implementing the specified logic function. It should also be noted that the executable instructions for implementing the specified logic function can be recombined to generate new modules and program segments. Therefore, the blocks of the drawings and the block sequence are only used to better illustrate the processes and steps of the embodiments, and should not be regarded as a limitation on the present application itself.
[0044] Figure 1 is an example of a communication applied to MIPI. As shown in the figure, the visible light sensor 101 transmits the captured image data to the CSI device controller 102. The CSI device controller 102 packs the image data according to the CSI protocol, and then provides the packed image data to the D-PHY module 103. After the D-PHY 103 performs digital-to-analog conversion, the generated image analog signal is provided to the D-PHY module 201. The D-PHY module 103 and the D-PHY module 201 perform serial signal transmission based on the interface circuit defined by the D-PHY. After the D-PHY module 201 performs analog-to-digital conversion on the received signal, the signal is provided to the CSI controller 202. The CSI controller 202 unpacks the image data in reverse order according to the CSI protocol, and the subsequent application is performed by the image processing program 203 running on the processor 203.
[0045] According to the D-PHY protocol, the D-PHY module 103 and the D-PHY module 201 can support 5 transmission channels (lanes), including one clock transmission channel (CLK Lane) and four data transmission channels (Data Lane). The four data transmission channels (Data Lane) are independent of each other, that is, the four data signals are independent of each other and share one clock signal.
[0046] Figure 2 is a structural schematic diagram of the MIPI receiving apparatus 300 provided by the embodiments of the present disclosure. For the convenience of description, only the components and functional units related to the embodiments of the present disclosure are shown in Figure 2
[0047] In Figure 2 , the MIPI receiving apparatus 300 is a data receiving apparatus according to the MIPI protocol, which can be constructed by software and hardware. For example, the MIPI receiving apparatus includes hardware supporting D-PHY, M-PHY or C-PHY protocol, and the MIPI receiving apparatus also includes software programs (referred to as MIPI logic part) for supporting protocols such as camera, display screen, vehicle-mounted communication, etc., and a processor for processing the software programs, so as to Figure 1 refer to the MIPI receiving apparatus 300, which includes a D-PHY module 201 and a CSI controller 202 for identifying and connecting a camera.
[0048] In Figure 2 , the MIPI receiving apparatus 300 includes a parallel-serial conversion circuit 301, a phase shift module 302, a calibration module 303, a sampling module 304, a state machine 305, a parallel-serial conversion circuit 306 and a phase shift module 307.
[0049] Figure 2 In , the parallel-serial conversion circuit 301 and the parallel-serial conversion circuit 306 respectively convert the clock differential signals (CLKp and CLKn) input through the clock channel and the data differential signals (DATAp and DATAn) input through the data channel into clock signals CLK' and data signals DATA', which are single-ended signals. The phase shift module 302 and the phase shift module 307 are responsible for performing phase delay of the clock signals CLK' and the data signals DATA', and respectively convert the clock signals CLK' and the data signals DATA' into clock signals CLK" and data signals DATA". The sampling module 304 is responsible for sampling the delayed data signals DATA" using the clock signals CLK" to obtain sampling data DATA. The state machine 305 is used to determine whether the data receiving is correct according to the sampling data. The calibration module 303 is responsible for calculating the delay values of the phase shift module 302 and the phase shift module 307, and providing the delay values to the phase shift module 302 and the phase shift module 307 to drive the phase shift module 302 and the phase shift module 307 to perform corresponding phase delay respectively. The state machine 305 also includes timing control logic, which drives the calibration module, the state machine, the phase shift module and the sampling module to work cooperatively according to the timing control logic.
[0050] In this embodiment, the calibration module, the state machine, the phase shifting module and the sampling module jointly constitute the executor of the calibration method of the disclosed embodiment. The calibration module gives a delay value, the phase shifting module performs phase delay according to the delay value, and the sampling module and the state machine jointly determine whether the current delay value is valid. In theory, the delay value is infinite and continuous. In order to ensure the efficiency of the calibration method, the method disclosed in the embodiment samples discrete delay values. Specifically, the frequency of the clock signal CLK' is used to determine the set step, the calibration module selects an integer multiple of the set step to the phase shifting module, and the phase shifting module performs phase delay, thereby adjusting the phase difference between the clock signal and the data signal.
[0051] In some embodiments, a microcontroller (MCU) is added in Figure 2 The timing control logic in the state machine of the embodiment is encoded into the microcontroller. Since the microcontroller is externally coded, this design is relatively easy to implement.
[0052] Figure 3 is applied to Figure 2 The flowchart of the calibration method of the MIPI receiving device is shown in FIG. 3. Specifically, the method comprises the following steps.
[0053] In step S302, the clock signal generated from the clock channel is phase delayed multiple times according to the set step.
[0054] In step S303, the data signal generated from the data channel is sampled using the clock signal after each phase delay, and the first calibration result corresponding to the clock signal after each phase delay is determined according to the sampled data.
[0055] In step S304, the data signal received from the data channel is phase delayed multiple times according to the set step.
[0056] In step S305, the data signal after each phase shift is sampled using the clock signal generated from the clock channel, and the second calibration result corresponding to the data signal after each phase delay is determined according to the sampled data.
[0057] In step S306, the phase delay preferred value of the data signal and the phase delay preferred value of the clock signal are determined according to the combination of the multiple first calibration results and the multiple second calibration results.
[0058] The above flow is explained and described as follows.
[0059] In the above process, the clock signal generated by the clock channel refers to a single-ended signal obtained by processing (e.g., analog-to-digital conversion, parallel-to-serial conversion) a differential clock analog signal received from the clock channel, and by analogy, the data signal generated by the data channel refers to a single-ended signal obtained by processing (e.g., analog-to-digital conversion, parallel-to-serial conversion) a differential data analog signal received from the data channel. The set step is a step defined by the system in advance according to the frequency of the clock signal CLK'.
[0060] In the above process, steps S302 and S303 refer to performing multiple phase delays on the clock signal of the clock channel while keeping the phase of the data signal of the data channel unchanged, and the delay values are the products of the set step and (0, …, n-1) in turn, where n is a positive integer. After each clock signal delay and before the next clock delay, the current data signal is sampled using the current clock signal to obtain sampled data, and whether the data is correctly received is determined according to whether the sampled data is correct. If yes, the calibration result corresponding to the current clock signal delay is successful, otherwise it is failed. In this way, n verification results can be obtained.
[0061] In the above process, steps S304 and S305 refer to performing multiple phase delays on the data signal of the data channel while keeping the phase of the clock signal of the clock channel unchanged, and the delay values are the products of the set step and (0, …, m-1) in turn, where m is a positive integer. After each data signal delay and before the next data delay, the current data signal is sampled using the current clock signal to obtain sampled data, and whether the data is correctly received is determined according to whether the sampled data is correct. If yes, the calibration result corresponding to the current data signal delay is successful, otherwise it is failed. In this way, m verification results can be obtained.
[0062] Note that in the above process, steps S302 to S305 are steps executed in turn (steps S304 and S305 can also be executed before steps S302 and S303), and when the data signal is phase-shifted, the current clock signal keeps the phase unchanged, and the current clock signal is used to sample the data signal after each delay. When the clock signal is phase-shifted, the current data signal keeps the phase unchanged, and the clock signal after each delay is used to sample the data signal.
[0063] In the above process, the phase delay preferred value of the data signal and the phase delay preferred value of the clock signal are determined according to the combination of the plurality of first calibration results and the plurality of second calibration results.
[0064] In some embodiments, with reference to Figure 2As shown, the phase shift module 302 sets and keeps the phase delay of the clock signal to the phase delay preferred value, and the phase shift module 307 sets and keeps the phase delay of the data signal to the phase delay preferred value, to perform the corresponding phase delay; in another embodiment, the signal with the smaller phase delay preferred value is selected as the delay phase, and the phase delay value thereof is equal to the phase delay preferred value; the signal with the larger phase delay preferred value is not phase delayed, and the phase delay value thereof is equal to zero.
[0065] In some embodiments, the MIPI receiving device applying the above calibration method includes two working modes: a connection mode and a working mode. When the MIPI receiving device is connected with an external MIPI transmitting device, the connection mode is entered, in which the calibration method is performed to obtain the phase delay preferred value of the data signal and the phase delay preferred value of the clock signal, and then the working mode is switched to, in which the phase delay is performed according to the phase delay preferred value of the data signal and the phase delay preferred value of the clock signal.
[0066] Figure 4 is a flowchart of a calibration method applied to a MIPI receiving device provided by another embodiment of the present disclosure. The method includes the following steps.
[0067] In step S401, NdataM=16 and NclockM=32 are set.
[0068] In step S402, an array Rdata[NdataM] is established to save the calibration result of the delayed data signal.
[0069] In step S403, an array Rclock[NclockM] is established to save the calibration result of the delayed clock signal.
[0070] In step S404, a current data phase delay step variable NdataC=0 and a current clock phase delay step variable NclockC=0 are set.
[0071] In step S405, it is determined whether NclockC
[0072] In step S406, the clock signal is phase delayed by (NclockC*step length).
[0073] In step S407, the data source sends data, and the received data signal is sampled. If the sampled data is correct, Rclock[NclockC]=0; if the sampled data is incorrect, Rclock[NclockC]=1.
[0074] In step S408, NclockC++.
[0075] In step S409, set the sequence variables NdataC = 0 and NclockC = 0.
[0076] In step S410, determine if NdataC < NdataM. If so, execute step S411; if not, execute step S414.
[0077] In step S411, perform a phase delay on the data signal with a delay value of (NdataC * step size).
[0078] In step S412, the data source sends data and samples the received data signal. If the sampled data is correct, Rdata[NdataC] = 0; if incorrect, Rdata[NdataC] = 1.
[0079] In step S413, NdataC++.
[0080] In step S414, create an array R
[47] and set N = 0.
[0081] In step S415, put Rdata[15,0] into R[0,15].
[0082] In step S416, put Rclock[1,31] into R[16,46].
[0083] In step S417, starting from R
[15] , expand to the left and right, and calculate the maximum number of consecutive 0s in R and the index median value.
[0084] In Figure 4 The flowchart details the calibration method for the phase delay value of the data signal and the phase delay value of the clock signal on a single channel: by traversing the delay steps of the data and clock signals respectively to record the calibration results, then merging the calibration results of the data and clock signals to form a two-way calibration result, and then taking the median value of the maximum continuous range of successful calibrations as the final delay value, which is also the preferred value, for subsequent phase delay based on the final signal phase delay value and the clock signal phase delay value. In addition, for the calibration of the data signals of other data channels, the clock signal can be phase-delayed first based on the preferred value of the phase delay of the clock signal, and then calibrated using this clock signal. Multiple channels can traverse the delay steps simultaneously for calibration to improve the calibration efficiency.
[0085] Next, taking Figure 5 as a reference, the calibration results of the spliced data and clock signals and the selection of the preferred value from them will be described in detail.
[0086] In Figure 5In the table, data_phase represents the calibration result of the delayed data signal, and the data is stored in Rdata[0:15], and clk_phase represents the calibration result of the delayed clock signal, and the data is stored in Rclk[0:15]. When splicing, Rdata[15:0] and Rclk[0:15] are spliced into a row from left to right, and Rdata[0] and Rclk[0] are combined into a value through an "or" operation, and the value is 0 when both are 0 and is placed in R
[15] , otherwise the value of R
[15] is 1.
[0087] In Figure 5 The five rows of data in the table represent five cases respectively.
[0088] The first row of data takes the middle value of the value sequence marked in yellow (this is the sequence of the largest number of 0s in the combination), and the delay step number of the data signal is 0 and the delay step number of the clock signal is 0. That is, the preferred value of the delay of the data signal and the preferred value of the delay of the clock signal are both 0 (delay step number*step length). Corresponding to Figure 2 When the system is working normally, the delay values of the phase shift module 302 and the phase shift module 307 are both set and kept as 0.
[0089] The second row of data takes the middle value of the value sequence marked in yellow, and the delay step number of the clock signal is 2 and the delay step number of the data signal is 0. That is, the preferred value of the delay of the data signal is (0*step length) and the preferred value of the delay of the clock signal is (2*step length). Corresponding to Figure 2 When the system is working normally, the delay value of the phase shift module 302 is set as (2*step length) and is phase shifted by (2*step length), and the delay value of the phase shift module 307 is set as 0 (0*step length), that is, no phase shift.
[0090] The third row of data takes the middle value of the value sequence marked in yellow, and the delay step number of the clock signal is 0 and the delay step number of the data signal is 2. That is, the preferred value of the delay of the data signal is (2*step length) and the preferred value of the delay of the clock signal is (0*step length). Corresponding to Figure 2 When the system is working normally, the delay value of the phase shift module 302 is set as 0 (0*step length), that is, no phase shift, and the delay value of the phase shift module 307 is set as (2*step length) and is phase shifted by (2*step length).
[0091] The fourth row of data has two yellow marks and both are 10 0s, the former 0 sequence corresponds to the delay step number of the data signal being 6 and the delay step number of the clock signal being 0, and the latter 0 sequence corresponds to the delay step number of the data signal being 0 and the delay step number of the clock signal being 7, so the former is preferred. That is, the preferred value of the delay of the data signal is (6*step length) and the preferred value of the delay of the clock signal is (0*step length). Corresponding to Figure 2When the system is working normally, the delay value of the phase shifting module 302 is set to (0*step) and the delay value of the phase shifting module 307 is set to (6*step) and the phase is shifted by (6*step).
[0092] In the fifth row of data, there are two yellow marks and both are 10 zeros, the former 0 sequence corresponds to the delay step number of the data signal being 8 and the delay step number of the clock signal being 0, and the latter 0 sequence corresponds to the delay step number of the data signal being 0 and the delay step number of the clock signal being 5, and thus the latter is preferred. That is, the preferred delay value of the data signal is (0*step) and the preferred delay value of the clock signal is (5*step). Corresponding to Figure 2 When the system is working normally, the delay value of the phase shifting module 302 is set to (0*step) and the delay value of the phase shifting module 307 is set to (6*step) and the phase is shifted by (6*step).
[0093] It should be noted that in the calibration result of the spliced data and clock in the embodiments of the present disclosure, the number of the sequence (for example Figure 5 the sequence composed of 0 in each row) selected to represent the successful calibration needs to be greater than a set threshold (in Figure 5 the set threshold is 6), because the clock and data signals input from outside will have jitter, and in order for the delay value to safely cover the influence of the jitter, the set threshold is provided, that is, when the sequence representing the successful calibration is less than the set threshold, it can be determined that the calibration result is risky, or even the calibration fails. Thus, by splicing the data and clock calibration results, the calibration range is expanded, and more successful possibilities are provided for the calibration of the clock and data. By setting the threshold, the calibration result of the spliced data and clock covers at least one signal period, thereby completely covering the jitter of the internal and external clock signals and data signals, and thus the adjustment and calibration of the internal and external skew are realized.
[0094] In summary, the MIPI receiving device and the calibration method provided by the embodiments of the present disclosure can simultaneously calibrate multiple channels, can simultaneously calibrate the phase errors caused by the internal and external data access, is convenient, fast, and saves time cost, can directly use the source data for calibration without the aid of additional calibration sequences, and can realize the bidirectional calibration of the clock or data signal, thereby increasing the calibration range.
[0095] The term "module" used herein can refer to, be part of, or include an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and / or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and / or other suitable components that provide the described functionality.
[0096] Those skilled in the art can understand that the various modules or units of the data processing system according to the present application can be implemented by hardware, firmware or software. The software includes, for example, coded programs formed by using various programming languages such as JAVA, C / C++ / C#, SQL, etc. Although the steps and the order of the steps of the embodiments of the present application are given in the method and the method flowchart, the executable instructions implementing the specified logical functions of the steps can be recombined to generate new steps. The order of the steps should not be limited to the order of the steps in the method and the method flowchart, and can be adjusted at any time according to the needs of the functions. For example, some of the steps can be executed in parallel or in reverse order.
[0097] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. The present application can have various modifications and changes for those skilled in the art. Any modification, equivalent replacement, improvement, etc. within the spirit and principles of the present application should be included in the protection scope of the present application.
Claims
1. A method for calibrating a MIPI receiving device, the MIPI receiving device comprising a clock lane and a data lane, the method comprising: performing multiple phase delays on a clock signal of the clock lane according to a set step size; sampling a data signal of the data lane using the clock signal after each phase delay, and determining a first calibration result corresponding to the clock signal after each phase delay according to the sampled data; performing multiple phase delays on the data signal of the data lane according to the set step size; sampling the data signal after each phase delay using the clock signal of the clock lane, and determining a second calibration result corresponding to the data signal after each phase delay according to the sampled data; and determining a preferred phase delay value of the data signal and a preferred phase delay value of the clock signal from the multiple phase delay values of the clock signal and the multiple phase delay values of the data signal according to the multiple first calibration results and the multiple second calibration results. The determining of the preferred phase delay value of the data signal and the preferred phase delay value of the clock signal comprises: concatenating the multiple second calibration results arranged in descending order of delay step size and the multiple first calibration results arranged in ascending order of delay step size into a row; and determining a middle value of a maximum number of continuous data sequences representing successful calibration in the row, and determining the preferred phase delay value of the data signal and the preferred phase delay value of the clock signal according to the delay step size of the data signal and the delay step size of the clock signal corresponding to the middle value. The MIPI receiving device comprises multiple data lanes generating multiple independent data signals, and the method further comprises: performing phase delay on the clock signal based on the preferred phase delay value of the clock signal to obtain a calibrated clock signal; and calibrating the remaining data signals using the calibrated clock signal. The maximum number of continuous data sequences representing successful calibration is greater than a set threshold. The clock signal of the clock lane is phase delayed according to the preferred phase delay value of the clock signal; and the data signal of the data lane is phase delayed according to the preferred phase delay value of the data signal. Further comprising: selecting a signal with a smaller preferred phase delay value for phase delay, and setting the phase delay value of the selected signal equal to the preferred phase delay value; and selecting a signal with a larger preferred phase delay value without phase delay, and setting the phase delay value of the selected signal equal to zero.
2. The calibration method of claim 1, wherein, The MIPI receiving device performs the calibration method when connected with an external MIPI transmitting device. 8.A MIPI receiving device comprising a clock lane and a data lane, the MIPI receiving device further comprising: a first parallel-to-serial conversion circuit configured to convert a clock differential signal received by the clock lane into a clock signal; a second parallel-to-serial conversion circuit configured to convert a data differential signal received by the data lane into a data signal; a first phase shift module configured to perform phase delay on the clock signal according to a first delay value; and a second phase shift module configured to perform phase delay on the data signal according to a second delay value. 3. The calibration method of claim 1, wherein, 4. The calibration method of claim 2, wherein, 5. The calibration method of claim 1 or 2, further comprising: 6. The calibration method of claim 1 or 2, wherein, 7. The calibration method of claim 1, wherein, a calibration module, configured to calculate a plurality of first delay values and a plurality of second delay values according to a set step, receive a plurality of first calibration results and a plurality of second calibration results, and determine preferred phase delay values of the data signal and the clock signal from the plurality of first delay values and the plurality of second delay values according to the plurality of first calibration results and the plurality of second calibration results, respectively; a sampling module, configured to sample the data signal of the data channel using the clock signal after each phase delay, and sample the data signal after each phase delay using the clock signal of the clock channel; a state machine, configured to determine the first calibration result corresponding to each phase delay of the clock signal and the second calibration result corresponding to each phase delay of the data signal according to the sampled data.
9. The MIPI receiving apparatus of claim 8, the first phase shifting module further comprising: perform phase delay according to the preferred phase delay value of the clock signal; the second phase shift module further comprises: performing phase delay according to the preferred phase delay value of the data signal.
10. The MIPI calibration apparatus of claim 8, wherein, when the preferred phase delay value of the clock signal is greater than the preferred phase delay value of the data signal, only the second phase shift module performs phase delay according to the preferred phase delay value of the data signal, and when the preferred phase delay value of the clock signal is less than or equal to the preferred phase delay value of the data signal, only the first phase shift module performs phase delay according to the preferred phase delay value of the clock signal.
11. The MIPI receiving apparatus according to claim 8, wherein the calibration module is further configured to: splice the plurality of second calibration results arranged in descending order of delay step number and the plurality of first calibration results arranged in ascending order of delay step number into a row; and in the row, select the middle value of the maximum number of continuous data sequences representing successful calibration, and determine the preferred phase delay values of the data signal and the clock signal according to the delay step number of the data signal and the delay step number of the clock signal corresponding to the middle value.
12. The MIPI receiving apparatus according to claim 8, wherein the maximum number of continuous data sequences representing successful calibration is greater than a set threshold.