A low power feed forward equalizer circuit

Abstract

The application provides a low-power feedforward equalizer circuit, comprising a group processing module, tap values of the feedforward equalizer circuit are divided into multiple groups, each group contains multiple tap values, and tap combination values processed by each lookup table module are calculated; a lookup table module is used for storing the tap combination values calculated in advance, and performing lookup operation according to input data bit combination to generate intermediate results; a clock gate trigger module is used for enabling signal tap_update_en=1 when the tap values are updated, and the tap values output by the register DFF are updated; when the tap values remain unchanged, tap_update_en=0, and the input clock of the DFF is closed; a shift accumulation module is used for accumulating the intermediate results output by the lookup table module after weight shift operation to generate processing results of multiple tap values; and a result output module is used for outputting the final equalization signal of the feedforward equalizer circuit. The application realizes the conversion of the multiplier into the LUT table and the adder, thereby greatly reducing the power consumption of the FFE circuit while ensuring the signal processing performance.

Description

Technical Field

[0001] This invention relates to the field of signal processing technology in high-speed communication systems, specifically to a low-power feedforward equalizer circuit, which can be widely used in high-speed communication scenarios such as 5G communication and fiber optic communication where there are strict requirements for signal quality and power consumption. Background Technology

[0002] With the rapid development of communication technology, the bandwidth of communication data is constantly increasing, and the requirements for signal processing are also becoming more and more demanding. In high-speed communication systems, inter-symbol interference (ISI) in the channel can seriously affect the transmission quality of signals, leading to an increase in the bit error rate.

[0003] Feed-Forward Equalizer (FFE) is a signal processing technique widely used in high-speed communication systems, primarily to overcome inter-symbol interference (ISI) in the channel. Its core idea is to use FIR (Finite Impulse Response) filters to preprocess the received signal to cancel channel distortion. As the bandwidth of communication data continues to increase, FFE needs to support wider bandwidth and lower power consumption.

[0004] An FFE is essentially an FIR digital filter, and existing technical solutions mainly use D-flip-flops, multipliers, and adders to implement it, such as... Figure 1 As shown:

[0005] The FFE output signal can be represented as:

[0006]

[0007] As can be seen from the above formulas, the area and power consumption of the FFE circuit mainly depend on the number of multipliers and the bit width of the multiplied data.

[0008] Existing technologies suffer from significant power consumption issues, especially in high-bandwidth, high-speed communication applications. Due to the large number of tap coefficients in the FFE (Freeform Factor Expansion) circuit, numerous multipliers and adders are required. However, in practical applications, the tap coefficient value of the FFE is a slowly varying value; aside from changing during the adaptive phase, it can be considered a constant value after normal operation. This necessitates considering the large number of multipliers in the circuit. tap(k)×x(n - k) , tap(k) Treat it as a constant. x(n - k) Since the input data is a variable, the gate circuits that make up the multiplier will generate a lot of dynamic power consumption. At the same time, the adder, as a calculation unit, will also generate a certain amount of dynamic power consumption. Moreover, for multipliers and adders with the same data bit width, the number of gate circuits in the multiplier is usually several times to more than ten times that of the adder. Therefore, the power consumption of the entire FFE circuit is mainly determined by the number of multipliers. Summary of the Invention

[0009] To address the various shortcomings of existing technologies, this invention provides a low-power feedforward equalizer circuit, aiming to solve the problem of high power consumption in existing technologies. This is achieved by transforming multipliers into lookup tables and adders, which greatly reduces the power consumption of the feedforward equalizer circuit while ensuring its signal processing performance.

[0010] The present invention achieves the above objectives through the following technical solutions:

[0011] A low-power feedforward equalizer circuit includes:

[0012] The grouping processing module divides the tap coefficients of the feedforward equalizer circuit into multiple groups, each containing multiple tap values, and calculates the combined tap values ​​that each lookup table module needs to process. Specifically, it performs an equivalent transformation on the input data corresponding to each group of taps, extracts common factors to generate addresses suitable for lookup table queries, and combines the grouped tap values ​​into the combined values ​​of the corresponding lookup table.

[0013] The lookup table module is used to store pre-calculated tap combination values ​​and perform lookup operations based on the input data bit combinations to generate intermediate results. The lookup table module is configured to convert multiplier calculations into lookup table calculations, and reduce dynamic power consumption by storing static tap combination values ​​instead of real-time multiplication operations.

[0014] The clock-gated trigger module, integrated within the lookup table module, is a trigger circuit with clock gating function. When the tap value is updated, the enable signal tap_update_en=1, and the tap value output by the register DFF is updated. When the tap value remains unchanged, tap_update_en=0, and the input clock of the register DFF is turned off to save power. At this time, the tap value output by the register DFF remains stable.

[0015] The shift-accumulation module performs a weight shift operation on the intermediate results output by the lookup table module and then accumulates them to generate multiple sets of tap values.

[0016] The result output module adds multiple processing results through an adder tree structure and outputs the final equalized signal of the feedforward equalizer circuit for inter-symbol interference compensation in high-speed communication systems.

[0017] According to a low-power feedforward equalizer circuit provided by the present invention, the tap_update_en enable signal of the clock-gated trigger module remains invalid during the normal operation phase of the feedforward equalizer circuit, i.e., tap_update_en=0, and is only activated during the adaptive phase or when the tap value needs to be updated, i.e., tap_update_en=1, thereby reducing the dynamic power consumption caused by the flip-flop clock.

[0018] According to the present invention, a low-power feedforward equalizer circuit includes a clock-gated trigger module comprising:

[0019] The latch circuit is used to temporarily store the tap_update_en enable signal to ensure signal stability.

[0020] An AND gate circuit that receives the system clock and tap_update_en enable signal, allowing the clock signal to pass only when tap_update_en enable signal = 1;

[0021] The DFF register updates the LUT contents when the clock is active, otherwise it remains static to reduce power consumption.

[0022] When the feed-in equalizer circuit is in normal operation, and the tap_update_en enable signal is 0, the AND gate outputs the clock off, the clock input of register DFF is 0, register DFF has no signal toggling, and the dynamic power consumption is approximately zero.

[0023] According to a low-power feedforward equalizer circuit provided by the present invention, the group processing module performs the following operations:

[0024] Define input signal x ( n ), where the value of the input signal at relative time nk is x(nk), and the coefficient sequence is defined. tap ( k The number of coefficients is N one, and this N The coefficients are divided into M Groups, each group contains L Each coefficient value, i.e. N = M × L ;

[0025] Output signal y ( n It is obtained by summing the product of the input signal sequence and the coefficient sequence. The calculation formula is:

[0026]

[0027] After grouping the coefficient sequence using a grouping operation strategy, the output signal is... y ( n This can be represented as the sum of the results of each group operation, i.e.:

[0028]

[0029] in, i Indicates the group number. j Indicates the sequence number within the group;

[0030] Since the circuit structure of each group is the same after grouping, the output signal of one group is equivalently transformed and expressed as the following formula:

[0031]

[0032] The packet processing module includes an input interface for receiving input signal sequences. x(nk) And tap value; calculation unit, used to perform group calculations and calculations after equivalent transformations; output interface, used to output the result signal after group processing and calculation.

[0033] According to the present invention, a low-power feedforward equalizer circuit is provided to convert the input signal... x ( n Converting to binary form, it can be represented by the following formula:

[0034]

[0035] in, W For data bit width, x ( n ) b represent x ( n ) b One bit;

[0036] With N Each coefficient is divided into M Groups, each group L coefficients ( N = M × L Taking the input signal converted from binary form as an example, the operation on one set of output signals can be expressed by the following formula:

[0037]

[0038] in, i For group number ( i =0,1,..., M -1), j This is the group number.

[0039] According to the low-power feedforward equalizer circuit provided by the present invention, the operation after extracting the common factor is combined with binary bit operations, based on the binary representation of the input signal: input signal x ( n It is decomposed into individual binary bits. x ( n ) b With corresponding weight 2 bThe sum of products, in the expression after factoring out the common factor, is further integrated into a weighted summation of the results of operations on different binary bits:

[0040]

[0041] in, for The output value is used to calculate all of them. sum b Combine and get these calculations Combined values ​​are stored in the lookup table module;

[0042] in, .

[0043] According to a low-power feedforward equalizer circuit provided by the present invention, the lookup table module performs the following operations:

[0044] The set of tap combination values ​​is stored in static random access memory or register array according to the index order of the input bit combination to form a lookup table. The lookup table adopts a block storage structure, which divides the input data into multiple sub-tables according to the high-order bits. Each sub-table has the same content.

[0045] Receive the input data bit stream, parse the bit height of the data stream bits, and form a lookup table address for the same bit height within the group;

[0046] Through a multi-port parallel access mechanism, multiple tap combination values ​​that match the bit combination are read simultaneously from the corresponding sub-table;

[0047] A weighted shift operation is performed on the tap combination values ​​output from the lookup table for different high bits to generate a candidate set of intermediate results;

[0048] A table lookup operation is performed using a multiplexer (MUX) to access addresses based on the same high-order bit combination.

[0049] According to the low-power feedforward equalizer circuit provided by the present invention, when the input signal is B bits, the lookup table module is a parallel lookup table array composed of B fully parallel lookup tables. Each lookup table is configured with 4 input ports and stores pre-calculated weight data matching the bit width of the tap value. Four groups of B-bit-width data are input and split into ⌈B⌉ groups through a grouping strategy. Each group of 4 bits is input in parallel to the corresponding lookup table to realize the synchronous output of B weight values ​​within a single cycle.

[0050] According to a low-power feedforward equalizer circuit provided by the present invention, the shift-accumulation module includes a configurable shift register array, where each register unit corresponds one-to-one with the output of a lookup table. The module performs a dynamic right shift operation on the weight values ​​output by the lookup table according to a preset shift control word. The number of shift bits is determined by the bit height of the current lookup table address data, expressed by the following formula:

[0051]

[0052] in, S k The shift number is set to the number of bits for the output data of the k-th lookup table to ensure that the lower-order weight values ​​are aligned before accumulation.

[0053] According to a low-power feedforward equalizer circuit provided by the present invention, the result output module performs the following operations:

[0054] The input data is adjusted in bit width and aligned so that the processing results of each group arrive at the adder tree structure synchronously in time.

[0055] The addition operation is performed according to the preset structure through the adder tree structure. Each adder layer adds the input data under the drive of the clock signal and passes the result to the next adder layer. For a large number of groups, a multi-layer adder cascade method is adopted, and the number of adders in each layer is optimized according to the number of results in the previous layer.

[0056] The operation process and results of the adder tree structure are monitored in real time. Once an error is detected, the final equalization signal is immediately corrected according to the compensation algorithm.

[0057] After correction, the final equalized signal is amplified, level-converted, and buffered by the output driver unit before being output to the high-speed communication system for inter-symbol interference compensation.

[0058] Therefore, compared with the prior art, the low-power feedforward equalizer circuit proposed in this invention has the following beneficial effects:

[0059] 1. This invention transforms the multiplier into a lookup table (LUT) and an adder. The LUT value is composed of a combination of tap values, which serves as a static variable and remains stable during circuit operation. Based on this characteristic, the cell in this part of the circuit does not flip every clock cycle, and its dynamic power consumption is approximately zero.

[0060] 2. The LUT and adder combination implementation adopted in this invention avoids frequent cell flipping in the multiplier circuit, reducing interference caused by power consumption fluctuations. The static LUT value combination makes the circuit's operational state more stable at different times, reducing thermal noise and electromagnetic interference caused by dynamic power consumption, thereby improving the stability and reliability of the entire feedforward equalizer circuit (FFE circuit). Under long-term operation or complex environments, the circuit proposed in this invention can perform signal processing tasks more stably, reduce signal distortion and errors, and ensure the normal operation of the communication system.

[0061] 3. This invention simplifies the circuit structure by converting the multiplier into a LUT and an adder. As a programmable logic unit, the LUT offers high flexibility and integration, enabling complex logic functions to be implemented within a small chip area. Furthermore, the adder has a relatively simple structure and occupies a small area. Therefore, the low-power feedforward equalizer circuit proposed in this invention effectively reduces the circuit area and design complexity while maintaining performance, making it easier to integrate into integrated circuits and improving the chip's integration density and performance-price ratio.

[0062] 4. The circuit structure proposed in this invention has better system adaptability and scalability. Since the LUT value can be flexibly configured according to different tap value combinations, when the feedforward equalizer circuit needs to adapt to different communication scenarios or adjust signal processing parameters, only the values ​​in the LUT need to be modified, without large-scale changes to the circuit's hardware structure. This allows the circuit to easily handle various communication requirements, such as signal processing with different bandwidths and bit rates. Simultaneously, it also facilitates subsequent functional expansion and performance improvement of the feedforward equalizer circuit. Developers can further improve the circuit's performance based on the existing circuit by optimizing the LUT configuration and the adder's operation method, meeting the ever-evolving needs of communication technologies.

[0063] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. Attached Figure Description

[0064] Figure 1 This is a schematic diagram of a feedforward equalizer (FFE) circuit in the prior art.

[0065] Figure 2 This is a schematic diagram of an embodiment of a low-power feedforward equalizer circuit according to the present invention.

[0066] Figure 3 This is a circuit diagram of the lookup table module in an embodiment of a low-power feedforward equalizer circuit of the present invention.

[0067] Figure 4This is a circuit diagram of the clock-gated trigger module in an embodiment of a low-power feedforward equalizer circuit of the present invention. Detailed Implementation

[0068] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0069] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0070] See Figures 2 to 4 This embodiment provides a low-power feedforward equalizer circuit, including:

[0071] The grouping processing module divides the tap coefficients of the feedforward equalizer circuit into multiple groups, each containing multiple tap values, and calculates the combined tap values ​​that each lookup table module needs to process. Specifically, it performs an equivalent transformation on the input data corresponding to each tap group, extracts common factors to generate addresses suitable for lookup table queries, and combines the grouped tap values ​​into the corresponding lookup table values. For example, each group corresponds to 7 parallel LUTs (corresponding to 7-bit data width), and each LUT selects a pre-stored combination of tap values ​​based on one bit of the input data for output.

[0072] The lookup table module is used to store pre-calculated tap combination values ​​and perform lookup operations based on the input data bit combinations to generate intermediate results. The lookup table module is configured to convert multiplier calculations into lookup table calculations, and reduce dynamic power consumption by storing static tap combination values ​​instead of real-time multiplication operations.

[0073] The clock-gated trigger module, integrated within the lookup table module, is a trigger circuit with clock gating functionality. When the tap value is updated, the enable signal tap_update_en=1, and the tap value output by the register DFF is updated. When the tap value remains unchanged, tap_update_en=0, and the input clock of the register DFF is turned off to save power. At this time, the tap value output by the register DFF remains stable.

[0074] The shift-accumulation module performs a weight shift operation on the intermediate results output by the lookup table module and then accumulates them to generate multiple sets of tap values.

[0075] The result output module adds multiple processing results through an adder tree structure and outputs the final equalized signal of the feedforward equalizer circuit for inter-symbol interference compensation in high-speed communication systems.

[0076] In particular, the tap_update_en enable signal of the clock-gated trigger module remains invalid during the normal operation of the feedforward equalizer circuit, i.e., tap_update_en=0, and is only activated during the adaptive phase or when the tap value needs to be updated, i.e., tap_update_en=1, thereby reducing the dynamic power consumption caused by the flip-flop clock.

[0077] In this embodiment, as Figure 4 As shown, the clock-gated trigger module includes:

[0078] The latch circuit is used to temporarily store the tap_update_en enable signal to ensure signal stability.

[0079] An AND gate circuit that receives the system clock and tap_update_en enable signal, allowing the clock signal to pass only when tap_update_en enable signal = 1;

[0080] The DFF register updates the LUT contents when the clock is active, otherwise it remains static to reduce power consumption.

[0081] When the feed-through equalizer circuit is in normal operation, and the tap_update_en enable signal is 0, the AND gate output turns off the clock, the clock input of register DFF is 0, register DFF has no signal toggling, and the dynamic power consumption is approximately zero.

[0082] Specifically, `tap_update_en` is the enable signal for updating tap values. Most of the time, `tap_update_en` = 0, so the 16 entries in the LUT table (there are 16 combinations of 4 tap values) are not updated, and the clock input to the DFF flip-flop is 0. During this time, the dynamic power consumption of the DFF is very small and can be ignored. When `tap_update_en` = 1, the 16 entries in the LUT table are updated, and the clock input to the DFF divider is the clock signal. During this time, the DFF has dynamic power consumption.

[0083] As can be seen, this embodiment uses a clock gating mechanism to turn off the flip-flop clock for more than 95% of the working time and activate it only when necessary, which significantly reduces the overall dynamic power consumption when the multiplier and flip-flop work together, making it suitable for high-bandwidth and high-speed communication scenarios.

[0084] Specifically, in this embodiment, the 16 FFE tap coefficients (tap values) are evenly divided into 4 groups, each group containing 4 tap values; an equivalent transformation operation is performed on the input data corresponding to each group of taps, the common factors are extracted, and the address of the corresponding lookup table (LUT) module is generated to adapt to the subsequent calculation logic based on the lookup table.

[0085] A lookup table (LUT) module is used to store pre-calculated values ​​related to the combination of FFE tap coefficients (tap values). Based on the bit combination of the input data and the input instructions generated in the grouping processing steps, a lookup operation is performed to generate intermediate results. Specifically, by converting traditional multiplier calculations to lookup table calculations, the stored static tap value combinations are used to replace real-time multiplication operations, thereby reducing dynamic power consumption. Furthermore, when the tap value update enable signal (tap_update_en) is invalid, the clock input is turned off by the clock gating trigger module integrated within the LUT module, keeping the relevant triggers static and further reducing dynamic power consumption. The clock input is activated only when tap_update_en is valid, allowing the LUT content to be updated.

[0086] The intermediate results output by the lookup table (LUT) module are subjected to binary weight shift operations, followed by accumulation operations to generate the processing results of each tap value. The specific shift operation is determined according to the bit weight of the input data. For example, the output result of the b-th LUT is shifted left by b bits before being added, thereby achieving a weighted sum calculation equivalent to the original multiplier.

[0087] The results of the four group processing modules obtained after the shift and accumulation steps are added together through the adder tree structure, and the final equalization signal of the 16-tap feedforward equalizer (FFE) is output to compensate for inter-symbol interference (ISI) in high-speed communication systems.

[0088] In this embodiment, the group processing module performs the following operations:

[0089] Define input signal x ( n The input signal has a value of x(nk) at a relative time nk. The signal has a specific data bit width. In actual application scenarios, the data bit width can be set according to the requirements, such as 7 bits in this embodiment. Its most significant bit (MSB) and least significant bit (LSB) are determined according to the specific data range.

[0090] Define coefficient sequence tap ( k The number of coefficients is N one, and this N The coefficients are divided into M Groups, each group contains L Each coefficient value, i.e. N = M × L For example, in this patent, they are divided into 4 groups, with 4 items in each group. tap value

[0091] Output signal y ( n It is obtained by summing the product of the input signal sequence and the coefficient sequence. The calculation formula is:

[0092]

[0093] To improve computational efficiency or adapt to hardware implementation requirements, a grouping operation strategy is adopted to group the coefficient sequence before outputting the signal. y ( n This can be represented as the sum of the results of each group operation, i.e.:

[0094]

[0095] in, i Indicates the group number. j Indicates the sequence number within the group;

[0096] Taking the grouping method in this embodiment as an example, the following calculation form can be obtained:

[0097]

[0098] Since the circuit structure of each group is the same after grouping, the output signal of one group is equivalently transformed and expressed as the following formula:

[0099]

[0100] It is evident that this equivalent transformation reduces redundant parts in the calculation and further optimizes the calculation process.

[0101] The packet processing module includes an input interface for receiving input signal sequences. x(nk) And tap value; calculation unit, used to perform group calculations and calculations after equivalent transformations; output interface, used to output the result signal after group processing and calculation.

[0102] Furthermore, the input signal x ( n Converting to binary form, it can be represented by the following formula:

[0103]

[0104] in, W For data bit width, x ( n ) b represent x ( n ) b One bit;

[0105] With N Each coefficient is divided into M Groups, each group L coefficients ( N = M × L Taking the input signal converted from binary form as an example, the operation on one set of output signals can be expressed by the following formula:

[0106]

[0107] in, i For group number ( i =0,1,..., M -1), j This is the group number.

[0108] Combining the binary representation of the input signal, the operation after extracting the common factor is combined with binary bit operations: Input signal x ( n It is decomposed into individual binary bits. x ( n ) b With corresponding weight 2 b The sum of products, in the expression after factoring out the common factor, is further integrated into a weighted summation of the results of operations on different binary bits:

[0109]

[0110] in, for The output value is used to calculate all of them. sum b Combine and get these calculations Combined values ​​are stored in the lookup table module;

[0111] in, .

[0112] In this embodiment, the lookup table module performs the following operations:

[0113] The set of tap combination values ​​is stored in static random access memory or register array according to the index order of the input bit combination to form a lookup table. The lookup table adopts a block storage structure, which divides the input data into multiple sub-tables according to the high-order bits. Each sub-table has the same content.

[0114] Receive the input data bit stream, parse the bit height of the data stream bits, and form a lookup table address for the same bit height within the group;

[0115] Through a multi-port parallel access mechanism, multiple tap combination values ​​that match the bit combination are read simultaneously from the corresponding sub-table;

[0116] A weighted shift operation is performed on the tap combination values ​​output from the lookup table for different high bits to generate a candidate set of intermediate results;

[0117] A table lookup operation is performed using a multiplexer (MUX) to access addresses based on the same high-order bit combination.

[0118] Among them, lookup table access clock gating: the lookup table clock signal is enabled only when the input data is valid, reducing power consumption of invalid access; dynamic data bit width truncation: based on the sparsity of multiplier coefficients, the storage and access of tap combination values ​​corresponding to all-zero coefficients are shielded; differential coding compression: the tap combination values ​​of adjacent input bit combinations are stored differentially, reducing the frequency of memory cell flipping.

[0119] Preferably, when the input signal is B bits, the lookup table module is a parallel lookup table array consisting of B fully parallel lookup tables. Each lookup table is configured with 4 input ports to store pre-calculated weight data that matches the bit width of the tap value. Four groups of B-bit-width data are input and split into ⌈B⌉ groups through a grouping strategy. Each group of 4 bits is input in parallel to the corresponding lookup table to achieve synchronous output of B weight values ​​within a single cycle.

[0120] In this embodiment, the shift-accumulate module includes a configurable shift register array, where each register unit corresponds one-to-one with the output of the lookup table. It performs a dynamic right shift operation on the weight values ​​output by the lookup table according to a preset shift control word. The number of shift bits is determined by the bit height of the current lookup table address data, expressed by the following formula:

[0121]

[0122] in, S k The shift number is set to the number of bits for the output data of the k-th lookup table to ensure that the lower-order weight values ​​are aligned before accumulation.

[0123] In this embodiment, a state machine controller module is also included. The state machine controller precisely divides the work cycle into six stages, T0-T5. In stage T0, the parallel loading of lookup table input data is implemented. Input signals are simultaneously transmitted to the lookup table module through multiple data channels, ensuring that the data loading operation is completed quickly and accurately, providing initial data support for subsequent calculations. In stages T1-T4, the pipeline adder tree is driven to perform step-by-step operations. Each adder completes its corresponding addition operation within its corresponding stage. Data is sequentially passed and calculated in the pipeline structure, achieving an efficient accumulation operation process. In stage T5, sign bit detection and subtraction compensation operations are performed. The sign bit of the result obtained from the previous operations is analyzed, and subtraction compensation is performed according to preset rules to ensure the accuracy and sign correctness of the final output result.

[0124] To address potential data hazard issues during high-order tap processing, the state machine controller employs a two-clock-cycle hold state. During these two hold cycles, data transmission and computation are paused, awaiting the availability of relevant data. This ensures stable and correct computation on the critical path, while guaranteeing that the critical path delay does not exceed 80% of the system clock cycle, thus maintaining the circuit's efficient and stable operation.

[0125] In this embodiment, a dynamic reconfiguration interface module is also included, providing an 8-bit configuration register set as the core control unit for dynamic reconfiguration. This register set has flexible configuration capabilities, allowing parameter settings and function adjustments to be made according to different application requirements.

[0126] Lookup table data update: Users can modify the pre-calculated weight data stored in the lookup table at any time according to actual needs, so that the circuit can adapt to different calculation scenarios and data characteristics, improving the flexibility and adaptability of the circuit.

[0127] Shift control word overloading: Enables real-time modification of shift control word parameters. S k By adjusting S k The value of can change the number of shift bits of the weight value, thereby adapting to the processing requirements of different order taps and supporting different FIR filter structures.

[0128] Adder tree depth configuration: The adder tree depth can be adjusted within the range of 3-5 levels. Users can flexibly configure the adder tree depth to optimize circuit performance based on different computational accuracy and speed requirements, enabling it to adapt to various data bit widths (8 / 12 / 16 bits) and different orders (4≤N≤256) of FIR filters.

[0129] This control circuit, through the precise timing control of the state machine controller and the flexible configuration of the dynamic reconfiguration interface, achieves efficient management of shift-accumulation operations and adaptability to various application scenarios. While ensuring operational accuracy and stability, it significantly improves the circuit's versatility and scalability, reduces switching costs and development difficulty in different application scenarios, and is suitable for scenarios requiring FIR filters in multiple fields such as communication and signal processing.

[0130] In this embodiment, the result output module performs the following operations:

[0131] The input data is adjusted in bit width and aligned so that the processing results of each group arrive at the adder tree structure synchronously in time.

[0132] The addition operation is performed according to the preset structure through the adder tree structure. Each adder layer adds the input data under the drive of the clock signal and passes the result to the next adder layer. For a large number of groups, a multi-layer adder cascade method is adopted, and the number of adders in each layer is optimized according to the number of results in the previous layer.

[0133] The operation process and results of the adder tree structure are monitored in real time. Once an error is detected, the final equalization signal is immediately corrected according to the compensation algorithm.

[0134] After correction, the final equalized signal is amplified, level-converted, and buffered by the output driver unit before being output to the high-speed communication system for inter-symbol interference compensation.

[0135] In practical applications, this applies to input signal sequences with a data width of 7 bits, i.e., the most significant bit (MSB) is 6 and the least significant bit (LSB) is 0. , and a set of 16 taps divided into 4 groups, each containing 4 tap values;

[0136] The input signal is processed according to the formula for finite font effect (FFE):

[0137]

[0138] Since the circuit structures of each group are the same after grouping, an equivalent transformation is performed on one of the groups, which is expressed as the following formula:

[0139]

[0140] Furthermore, it can be Written in binary form:

[0141]

[0142] in, for From the b-th bit, we can obtain:

[0143]

[0144] Will By extracting the common factor, we can obtain:

[0145]

[0146]

[0147]

[0148]

[0149]

[0150]

[0151]

[0152]

[0153]

[0154] in .here , , , It can take the value 0 or 1. Therefore The values ​​of satisfy the following lookup table 1:

[0155] Table 1: Combined lookup table

[0156]

[0157] Therefore, as long as the above table is calculated in advance... All combinations are stored in a lookup table (LUT), and then... , , , By performing a lookup table operation on the address, the result can be calculated. The value, and then for different ( )of After shifting, the results are accumulated to finally calculate the result of the feedforward equalizer circuit.

[0158] like Figure 3The diagram shows a circuit diagram of a single grouped lookup table (LUT) module. Each group has 7 such LUTs (corresponding to 7-bit wide data), and the content of each LUT table is the same, except that the input data is selected. , , , There will be differences. This lookup table is actually a case selection circuit that selects different combinations of tap values ​​for output based on different input values.

[0159] For example, for input data in group 1 , , , = {1010001 ,0101101, 1100101, 0011001}, then the input and output data for the 7 LUTs are shown in Table 2:

[0160] Table 2: Input and Output Data of LUT

[0161]

[0162] From the above formula, it can be derived that for one of the group circuits in the FFE function, as shown in the figure... Figure 2 As shown. Because the FFEtap value is a slowly changing parameter, the FFE tap value update enable signal tap_update_en is used as the clock gating circuit. In most actual operations, the FFE tap value does not need to be updated; the tap_update_en signal keeps the DFF clock off. Therefore, the DFF circuit signal does not toggle, and the overall dynamic power consumption of the FFE circuit is concentrated in the back-end adder, thus reducing overall power consumption.

[0163] The result derived from the above formula is:

[0164]

[0165] Figure 2 The circuit in the diagram is the specific implementation of this formula, where... for The output value, corresponding to the left shift operation. .

[0166] The final result of the FFE function is the sum of the results of the four groups, expressed as follows:

[0167]

[0168] The technical solution of this invention can achieve significant power consumption reduction benefits, as shown in Table 3 below:

[0169] Table 3: Comparison of the effects of the present invention with traditional solutions

[0170]

[0171] In summary, traditional FFE circuits heavily rely on multipliers for signal processing. Since the number of multiplier gates is typically several to ten times that of adders, and in practical applications, the tap coefficients of the FFE are mostly constant except during the adaptive phase, while the input data is constantly changing, causing the cell clock of the multiplier circuit to flip every clock cycle, resulting in significant dynamic power consumption. This invention transforms the multiplier into a lookup table (LUT) and adders. The LUT value is composed of a combination of tap values, which acts as a static variable, remaining stable during circuit operation. Based on this characteristic, the cell clock of this part of the circuit does not flip every clock cycle, and its dynamic power consumption is approximately zero. Through actual testing and comparison, with 16 FFE taps and 7-bit widths for both the FFE tap data and the input data, the traditional solution consumes 59.6 mW, while the solution of this invention consumes only 38.9 mW, a reduction of 34.74%, significantly reducing circuit energy consumption and improving energy efficiency.

[0172] Due to the extensive use of multipliers and their dynamic power consumption characteristics in traditional FFE circuits, the circuits are susceptible to power fluctuations during operation, which can lead to signal processing instability and even circuit failure. The LUT and adder combination implementation used in this invention avoids frequent cell toggling in the multiplier circuit, reducing interference caused by power consumption fluctuations. The static LUT value combination makes the circuit's operational state more stable at different times, reducing thermal noise and electromagnetic interference caused by dynamic power consumption, thereby improving the stability and reliability of the entire FFE circuit. Under long-term operation or complex environments, the circuit proposed in this invention can more stably perform signal processing tasks, reduce signal distortion and errors, and ensure the normal operation of the communication system.

[0173] The extensive use of multipliers in traditional FFE circuits results in a large circuit area, high design complexity, and hinders circuit integration and optimization. The complex structure of multipliers occupies significant chip area, increasing manufacturing costs and power consumption. This invention simplifies the circuit structure by converting multipliers into LUTs and adders. LUTs, as programmable logic units, offer high flexibility and integration, enabling complex logic functions within a smaller chip area. Adders have a relatively simple structure and occupy less space. Therefore, the low-power feedforward equalizer circuit proposed in this invention effectively reduces circuit area and design complexity while maintaining performance, making it easier to integrate into integrated circuits and improving chip integration density and performance-price ratio.

[0174] The circuit structure proposed in this invention offers superior system adaptability and scalability. Since the LUT value can be flexibly configured based on different tap value combinations, when the feedforward equalizer circuit needs to adapt to different communication scenarios or adjust signal processing parameters, only the LUT values ​​need to be modified, without requiring large-scale changes to the circuit's hardware structure. This allows the circuit to easily handle various communication requirements, such as signal processing with different bandwidths and bit rates. Simultaneously, it facilitates subsequent functional expansion and performance enhancement of the feedforward equalizer circuit. Developers can further improve the circuit's performance by optimizing the LUT configuration and the adder's operation method, based on the existing circuit, to meet the evolving needs of communication technologies.

[0175] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0176] The above embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of protection of the present invention. Any non-substantial changes and substitutions made by those skilled in the art based on the present invention shall fall within the scope of protection claimed by the present invention.

Claims

1. A low-power feedforward equalizer circuit, characterized in that, include: The group processing module divides the tap coefficients of the feedforward equalizer circuit into multiple groups, each containing multiple tap values, and calculates the combination of tap values ​​that each lookup table module needs to process. The lookup table module is used to store the pre-calculated tap combination values ​​and perform lookup operations based on the input data bit combinations to generate intermediate results; The clock-gated trigger module, integrated within the lookup table module, is a trigger circuit with clock gating function. When the tap value is updated, the enable signal tap_update_en=1, and the tap value output by the register DFF is updated. When the tap value remains unchanged, tap_update_en=0, and the input clock of the register DFF is turned off. The shift-accumulation module performs a weight shift operation on the intermediate results output by the lookup table module and then accumulates them to generate multiple sets of processing results for the tap values. The result output module adds multiple sets of processing results through an adder tree structure and outputs the final equalization signal of the feedforward equalizer circuit for inter-symbol interference compensation in high-speed communication systems.

2. The circuit according to claim 1, characterized in that: The tap_update_en enable signal of the clock-gated trigger module remains invalid during the normal operation of the feedforward equalizer circuit, i.e., tap_update_en=0. It is only activated during the adaptive phase or when the tap value needs to be updated, i.e., tap_update_en=1, thereby reducing the dynamic power consumption caused by the trigger clock flip.

3. The circuit according to claim 2, characterized in that, The clock-gated trigger module includes: The Latch circuit is used to temporarily store the tap_update_en enable signal; An AND gate circuit that receives the system clock and tap_update_en enable signal, allowing the clock signal to pass only when tap_update_en enable signal = 1; The DFF register updates the LUT contents when the clock is active, otherwise it remains static to reduce power consumption. When the feed-in equalizer circuit is in normal operation, and the tap_update_en enable signal is 0, the AND gate outputs the clock off, the clock input of register DFF is 0, register DFF has no signal toggling, and the dynamic power consumption is approximately zero.

4. The circuit according to claim 1, characterized in that, The packet processing module performs the following operations: Define input signal x ( n ), where the value of the input signal at relative time nk is x(nk), and the coefficient sequence is defined. tap ( k The number of coefficients is N one, and this N The coefficients are divided into M Groups, each group contains L Each coefficient value, i.e. N = M × L ; Output signal y ( n It is obtained by summing the product of the input signal sequence and the coefficient sequence. The calculation formula is: After grouping the coefficient sequence using a grouping operation strategy, the output signal is... y ( n This can be represented as the sum of the results of each group operation, i.e.: in, i Indicates the group number. j Indicates the sequence number within the group; Since the circuit structure of each group is the same after grouping, the output signal of one group is equivalently transformed and expressed as the following formula: The packet processing module includes an input interface for receiving input signal sequences. x(nk) And tap value; calculation unit, used to perform group calculations and calculations after equivalent transformations; output interface, used to output the result signal after group processing and calculation.

5. The circuit according to claim 4, characterized in that: Input signal x ( n Converting to binary form, it can be represented by the following formula: in, W For data bit width, x ( n ) b represent x ( n ) b One bit; With N Each coefficient is divided into M Groups, each group L Taking one coefficient as an example, combined with the input signal after conversion from binary form, the operation on one set of output signals is expressed by the following formula: in, i For group number, j This is the group number.

6. The circuit according to claim 5, characterized in that: Combining the binary representation of the input signal, the operation after extracting the common factor is combined with binary bit operations: Input signal x ( n It is decomposed into individual binary bits. x ( n ) b With corresponding weight 2 b The sum of products, in the expression after factoring out the common factor, is further integrated into a weighted summation of the results of operations on different binary bits: in, for The output value is used to calculate all of them. sum b Combine and get these calculations Combined values ​​are stored in the lookup table module; in, .

7. The circuit according to claim 1, characterized in that, The lookup table module performs the following operations: The set of tap combination values ​​is stored in static random access memory or register array according to the index order of the input bit combination to form a lookup table. The lookup table adopts a block storage structure, which divides the input data into multiple sub-tables according to the high-order bits. Each sub-table has the same content. Receive the input data bit stream, parse the bit height of the data stream bits, and form a lookup table address for the same bit height within the group; Through a multi-port parallel access mechanism, multiple tap combination values ​​that match the bit combination are read simultaneously from the corresponding sub-table; A weighted shift operation is performed on the tap combination values ​​output from the lookup table for different high bits to generate a candidate set of intermediate results; A table lookup operation is performed using a multiplexer (MUX) to access addresses based on the same high-order bit combination.

8. The circuit according to claim 1, characterized in that: When the input signal is B bits, the lookup table module is a parallel lookup table array consisting of B fully parallel lookup tables. Each lookup table is configured with 4 input ports and stores pre-calculated weight data that matches the bit width of the tap value. Input four sets of data with a width of B bits, which are then split into ⌈B⌉ groups using a grouping strategy. Each group of four bits is input in parallel into the corresponding lookup table, thereby achieving synchronous output of B weight values ​​within a single period.

9. The circuit according to claim 7 or 8, characterized in that: The shift-accumulate module includes a configurable shift register array, where each register unit corresponds one-to-one with the output of the lookup table. It performs a dynamic right shift operation on the weight values ​​output by the lookup table according to a preset shift control word. The number of shift bits is determined by the bit height of the current lookup table address data, expressed by the following formula: in, S k The shift number is set to the number of bits for the output data of the k-th lookup table to ensure that the lower-order weight values ​​are aligned before accumulation.

10. The circuit according to any one of claims 1 to 8, characterized in that, The result output module performs the following operations: The input data is adjusted in bit width and aligned so that the processing results of each group arrive at the adder tree structure synchronously in time. The addition operation is performed according to the preset structure through the adder tree structure. Each adder layer adds the input data under the drive of the clock signal and passes the result to the next adder layer. For a large number of groups, a multi-layer adder cascade method is adopted, and the number of adders in each layer is optimized according to the number of results in the previous layer. The operation process and results of the adder tree structure are monitored in real time. Once an error is detected, the final equalization signal is immediately corrected according to the compensation algorithm. After correction, the final equalized signal is amplified, level-converted, and buffered by the output driver unit before being output to the high-speed communication system for inter-symbol interference compensation.

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