Pixel circuit supply noise cancellation

Abstract

Systems and methods for pixel circuit supply noise cancellation are described herein. In one embodiment, a pixel circuit of an imaging sensor includes a front-end circuit having a photodiode configured to generate charge accumulated at a floating diffusion FD0 as a photodiode voltage. The pixel circuit also includes a signal storage circuit coupled to the front-end circuit, the signal storage circuit including a common floating diffusion (FDC) configured to store a common floating diffusion voltage corresponding to the photodiode voltage. A unity gain circuit is coupled to the signal storage circuit. The unity gain circuit includes an operational amplifier that generates a control voltage VCTRL as an output voltage. The control voltage VCTRL includes a voltage noise component of the supply voltage PIXVDD. An output circuit is configured for outputting a signal voltage VS corresponding to the floating diffusion voltage.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to the design of image sensors, and in particular to image sensors with reduced supply voltage noise. BACKGROUND

[0002] Image sensors have become ubiquitous. The image sensors are widely used in digital still cameras, cellular phones, security cameras, and in medical, automotive, and other applications. The technology for manufacturing image sensors continues to rapidly evolve. For example, the demand for higher image sensor resolution and lower power consumption has prompted image sensors to be further miniaturized and integrated into digital devices.

[0003] An image sensor operates in response to image light from an external scene that is incident on the image sensor. The image sensor includes an array of pixels having light-sensitive elements (e.g., photodiodes) that absorb a portion of the incident image light, and in response, the light-sensitive elements generate corresponding charges. The charges of individual pixels can be measured as an output voltage for each light-sensitive element. Generally, the output voltage varies as a function of the intensity and duration of the incident light. The output voltage of individual light-sensitive elements is used to generate a digital image (i.e., image data) that represents the external scene.

[0004] Generally, the resulting output voltage of the light-sensitive elements is read out by electronic circuitry to generate an image frame. However, the output voltage can be sensitive to electrical noise in the electronic circuitry. Therefore, there is a need for systems and methods for reducing electrical noise of image sensors and improving their readout accuracy. SUMMARY

[0005] In one aspect, the disclosure provides a pixel circuit of an imaging sensor, the pixel circuit comprising: a front-end circuit comprising a photodiode configured to generate a charge accumulated at a floating diffusion FD0 as a photodiode voltage, wherein the front-end circuit is configured to receive a supply voltage PIXVDD; a signal storage circuit coupled to the front-end circuit, the signal storage circuit comprising: a common floating diffusion FDC configured to store a common floating diffusion voltage corresponding to the photodiode voltage, wherein the common floating diffusion voltage includes a voltage noise component of the supply voltage PIXVDD; a unit gain circuit coupled to the signal storage circuit, the unit gain circuit comprising an operational amplifier configured to: couple the supply voltage PIXVDD and a reference voltage VREF as input voltages to the operational amplifier; and generate a control voltage VCTRL as an output voltage, wherein the control voltage VCTRL includes the voltage noise component of the supply voltage PIXVDD; and an output circuit coupled to the signal storage circuit, wherein the output circuit is configured for outputting a signal voltage VS corresponding to the floating diffusion voltage.

[0006] In another aspect, the disclosure provides a method for operating a pixel circuit of an imaging sensor, the method comprising: generating, by a photodiode, a charge at a floating diffusion FD0 of a front-end circuit as a photodiode voltage, wherein the front-end circuit is coupled to a supply voltage PIXVDD, and wherein the supply voltage PIXVDD includes a voltage noise component; transferring the photodiode voltage to a common floating diffusion FDC of a signal storage circuit coupled to the front-end circuit, wherein the photodiode voltage is transferred as a common floating diffusion voltage of the signal storage circuit, and wherein the common floating diffusion voltage includes the voltage noise component of the supply voltage PIXVDD; generating, by a unit gain circuit, a control voltage VCTRL as an output voltage of the unit gain circuit, wherein the control voltage VCTRL includes the voltage noise component of the supply voltage PIXVDD, and wherein the unit gain circuit is coupled to the signal storage circuit; storing, by the signal storage circuit, a reference voltage VR, wherein the reference voltage VR includes the voltage noise component of the supply voltage PIXVDD; storing, by the signal storage circuit, a signal voltage VS, wherein the signal voltage VS includes the voltage noise component of the supply voltage PIXVDD, and wherein the signal voltage VS corresponds to the common floating diffusion voltage; and outputting, by an output circuit coupled to the signal storage circuit, the signal voltage VS. BRIEF DESCRIPTION OF DRAWINGS

[0007] Non-limiting and non-exhaustive embodiments of the present disclosure are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

[0008] Figure 1 FIG. illustrates an imaging system in accordance with embodiments of the present disclosure.

[0009] Figure 2 is a schematic diagram illustrating a pixel circuit in accordance with embodiments of the present disclosure.

[0010] Figure 3 is a schematic diagram illustrating Figure 2 a pixel circuit shown in

[0011] Figure 4 is a schematic diagram illustrating a pixel circuit in accordance with embodiments of the present disclosure.

[0012] Figure 5 is a schematic diagram illustrating Figure 4 a pixel circuit shown in

[0013] Corresponding reference characters indicate corresponding parts throughout the several views of the drawings. It will be understood that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in each of the figures can be exaggerated relative to other elements to help improve the DETAILED DESCRIPTION

[0014] Image sensors are disclosed, and in particular, image sensors that include a color router. In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments. One skilled in the relevant art will recognize, however, that the technology herein described can be practiced without one or more of the specific details, or

[0015] Reference throughout this specification to "one example" or "an example" means that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present invention. Thus, the appearances of the phrases "in one example" or "in one embodiment" in various places throughout this specification are not necessarily all referring to the same example. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more examples.

[0016] For purposes of the description hereinafter, spatial

[0017] In light of the forgoing, it should be appreciated that the specific embodiments of the technology described herein are illustrative only and not limiting of the technology as claimed. While the technology has been described in terms of particular embodiments, it is not intended that the technology be limited to the specific embodiments described. For example, although the technology has been described in the context of particular embodiments, it is not intended that the technology be limited to the specific embodiments described. Like numbers refer to like elements throughout. In addition, although the technology has been described in language specific to structural features, it is to be understood that the technology is not necessarily limited to these specific features. Rather, the specific features of the technology are shown by way of example in the drawings and described in detail below. It is to be understood that the technology is not limited in this regard. Rather, the technology is applicable in any embodiment that employs structural features equivalent to those described herein.

[0018] Throughout this specification, several terms will be used. These terms will take on their ordinary meaning in the art to which the specification belongs unless specifically defined otherwise or the context will otherwise clearly indicate. It should be noted that throughout this document, element names and symbols can be used interchangeably (e.g., Si and silicon); however, both have the same meaning.

[0019] In short, embodiments of the present technology are directed to image sensors with reduced electrical noise and improved accuracy in photodiode voltage readout. In some embodiments, the photodiode voltage corresponding to the accumulated charge is ultimately read out as a differential voltage relative to a control (reference) voltage. However, the photodiode voltage can be affected by voltage noise in the supply voltage of the readout circuitry, which can negatively impact the accuracy of determining the photodiode voltage. Therefore, in some embodiments of the present application, the control voltage is intentionally affected by the same voltage noise of the supply voltage through suitable passive components (e.g., capacitors) and active components (e.g., an operational amplifier operating in unity gain). Because the photodiode voltage is ultimately acquired as the differential voltage between the control voltage and the photodiode voltage, and because both the control voltage and the photodiode voltage are affected by voltage noise in the same manner, the noise content of the control voltage and the photodiode voltage tends to cancel each other. As a result, by eliminating or at least reducing the effect of supply noise on the voltage difference between the control voltage and the photodiode voltage, a more accurate readout of the photodiode voltage can be achieved.

[0020] Figure 1 An exemplary imaging system 100 according to an embodiment of the present disclosure is illustrated. Imaging system 100 includes a pixel array 102, control circuitry 104, readout circuitry 106 (also referred to as pixel circuitry), and function logic 110. In one example, pixel array 102 is a two-dimensional (2D) array of photodiodes or image sensor pixels 112 (e.g., pixels P1, P2, ..., Pn). As illustrated, the photodiodes are arranged in rows (e.g., rows R1 to Ry) and columns (e.g., columns C1 to Cx). In operation, the photodiodes acquire image data of an external scene, which can then be used to render a 2D image of a person, place, object, etc. However, in other embodiments, the photodiodes may be arranged in configurations other than rows and columns.

[0021] In one embodiment, after each pixel 112 in the pixel array 102 has acquired its image charge, the image data is read out by the readout circuitry 106 via the bit lines 118 and then transferred to the functional logic 110. In various embodiments, the readout circuitry 106 can include signal amplifiers, analog-to-digital (ADC) conversion circuitry, and data transfer circuitry. The functional logic 110 can store the image data, or even manipulate the image data by applying post-image effects (e.g., cropping, rotation, red-eye removal, brightness adjustment, contrast adjustment, etc.). In some embodiments, the control circuitry 104 and the functional logic 110 can be combined into a single functional block to control the capture of an image by the pixels 112 and the readout of the image data from the readout circuitry 106. For example, the functional logic 110 can be a digital processor. In one embodiment, the readout circuitry 106 can read one row of image data at a time along the readout column lines (bit lines 118), or can use a variety of other techniques to read the image data, such as serial readout or simultaneous full parallel readout of all pixels (not illustrated).

[0022] In one embodiment, the control circuitry 104 is coupled to the pixel array 102 to control the operation of the plurality of photodiodes in the pixel array 102. For example, the control circuitry 104 can generate a shutter signal for controlling image acquisition. In one embodiment, the shutter signal is a global shutter signal for enabling all of the pixels within the pixel array 102 to capture their respective image data simultaneously during a single data acquisition window. In another embodiment, the shutter signal is a rolling shutter signal such that each row, each column, or each group of pixels is sequentially enabled during successive acquisition windows. In another embodiment, the image acquisition is synchronized with an illumination effect such as a flash.

[0023] In one embodiment, the readout circuitry 106 includes an analog-to-digital converter (ADC) that converts the analog image data received from the pixel array 102 into a digital representation. The digital representation of the image data can be provided to the functional logic 110. In some embodiments, the data transfer circuitry 108 can receive the digital representation of the image data from the ADC in parallel, and can provide the image data to the functional logic 110 serially.

[0024] In different embodiments, imaging system 100 can be included in a digital camera, a cell phone, a laptop, etc. Additionally, imaging system 100 can be coupled to other pieces of hardware, such as a processor (general purpose or otherwise), memory elements, an output (USB port, wireless transmitter, HDMI port, etc.), an illumination device / flash, an electrical input (keyboard, touch display, touchpad, mouse, microphone, etc.), and / or a display. The other pieces of hardware can deliver instructions to imaging system 100, extract image data from imaging system 100, or manipulate image data supplied by imaging system 100.

[0025] Figure 2 is a schematic diagram illustrating a pixel circuit according to embodiments of the present disclosure. Figure 2 Pixel circuit 10 is illustrated as including front-end circuit 120, signal storage circuit 140, and output circuit 160. Signal storage circuit 140 is coupled to front-end circuit 120, and output circuit 160 is coupled to signal storage circuit 140. When exposed to light, photodiode PD generates charge that accumulates at floating diffusion FD0, which in some embodiments is connected to floating diffusion capacitor Cfd. Those skilled in the art will appreciate that the illustrated capacitor Cfd is not necessarily implemented as a conductive plate capacitor, but can be implemented within a doped semiconductor layer. Indeed, the combination of floating diffusion FD0 and capacitor Cfd is often referred to collectively as a “floating diffusion.”

[0026] The flow of charge generated by photodiode PD toward floating diffusion FD0 is controlled by transistor Ml based on a control signal TX coupled to the gate terminal of transistor Ml (also referred to as the “first transistor” or “transfer gate”). When the TX signal sets transistor Ml to an “on” state, accumulated charge from photodiode PD is transferred to floating diffusion FD0. The voltage readout of floating diffusion FD0 is timed, among other things, by the operation of transistor M2 (also referred to as the “reset gate” or “second transistor”), which can be coupled to a supply voltage PIXVDD and can receive a reset control signal RST on its gate terminal.

[0027] The gate, drain, and source terminals of the transistor M3 (also referred to as the "third transistor") are coupled to the floating diffusion FD0, the supply voltage PIXVDD, and the drain of the transistor M4, respectively. The transistor M4 (also referred to as the "fourth transistor") is coupled between the source terminal of the transistor M3 and the drain terminal of the transistor M5 (also referred to as the "fifth transistor"). The gate terminal of the transistor M4 is coupled to the control signal GR (e.g., a ground voltage or another voltage). The gate terminal of the transistor M5 is coupled to the control signal VP. The voltage at the floating diffusion FD0 controls the "on / off" state of the gate of the transistor M3, and the control signal GR controls the "on / off" state of the gate of the transistor M4. When the gates of the transistors M3 and M4 are set to the "on" state, the charge accumulated at the floating diffusion FD0 is transferred through the output terminal VO1 as the common floating diffusion FDC, provided, of course, that the control signal VP sets the gate of the transistor M5 to the "off" state. Those skilled in the art will appreciate that the voltages at FD0 and FDC are related generally as FDC = FD0 - VGS, where VGS is the voltage drop between the gate and source of the transistor M3, since the voltage drop through the transistor M4 is relatively small, i.e., significantly less than the voltage VGS of the transistor M3, in most practical cases.

[0028] Notably, the reference signal FDC stored in the signal storage circuit 140 is pulled up from the original voltage level FD0 to a higher voltage level according to the voltage increment AV applied to the control voltage VCTRL. Those skilled in the art will appreciate that, without this voltage pull-up, the available output voltage range can be reduced due to the voltage drops introduced by the transistors M3 and M8, respectively. More particularly, the voltage increment AV should be greater than the threshold voltage (i.e., the turn-on voltage) of the transistor M8 (or the transistor M3) to ensure that the transistor M8 can be "turned on." For example, the voltage increment AV can be equal to or greater than the voltage difference between the gate terminal and the source terminal of the transistor M3 in order to compensate for the voltage drop introduced by the transistor M3. Thus, the voltage increment AV can be equal to or greater than the voltage difference between the gate terminal and the source terminal of the transistor M8 in order to compensate for the voltage drop introduced by the transistor M8. The operation of the signal storage circuit 140 is described below.

[0029] In some embodiments, the signal storage circuit 140 includes a plurality of transistors, such as transistors M6 (also referred to as "sixth transistor") and M7 (also referred to as "seventh transistor"), and a plurality of capacitors, such as capacitors C R (also referred to as "reference voltage capacitor") and C S (also referred to as "signal voltage capacitor"). The transistor M6 is coupled between the common floating diffusion FDC and the capacitor C R, while the transistor M7 is coupled between the common floating diffusion FDC and the capacitor C S. The gate of the transistor M6 is controlled by the signal GRST, and the gate of the transistor M7 is controlled by the signal GTX. The capacitors C R and C S are coupled at one end to the control voltage V CTRL, and at the other end to the transistors M6 and M7. VR represents the reference voltage value at the node between the source terminal of the transistor M6 and the capacitor C R, and VS represents the signal voltage value at the node between the source terminal of the transistor M7 and the capacitor C S. In operation, the voltages VR and VS can store the reference voltage and the signal voltage, respectively. The voltage VS represents the common floating diffusion FDC, that is, the voltage VS represents the accumulation of the charge generated in response to the irradiation of a particular photodiode PD.

[0030] The output circuit 160 can include a plurality of transistors, such as transistors M8 (also referred to as "eighth transistor") and M9 (also referred to as "ninth transistor"). The gate terminal of the transistor M8 is coupled to and controlled by the voltage of the common floating diffusion FDC. The gate terminal of the transistor M9 is controlled by the row selection signal SEL. The drain terminal of the transistor M8 is connected to the supply voltage PIXVDD, and the source terminal of the transistor M8 is connected to the drain terminal of the transistor M9. The operation of the row selection signal SEL on the gate terminal of the transistor M9 enables the readout of a particular photodiode PD in the photodiodes of a given row.

[0031] Figure 3 is illustrated in FIG. 10. Figure 2The timing diagram of the signal and control voltages of the pixel circuit shown in the figure. In particular, the RST signal initiates the readout of the voltage VS, which corresponds to the charge accumulated by illuminating the photodiode PD, as explained above. The accumulated charge is transferred to the floating diffusion FDO by the transfer transistor Ml, and further transferred to the common floating diffusion FDC by the operation of transistors M3 and M4. The control signal GRST applied to the gate of transistor M6 sets the reference voltage VR for the readout, and the control signal GTX applied to the gate of transistor M7 sets the signal voltage VS for the readout. However, in many practical cases, the supply voltage PIXVDD contains an amount of noise, as illustrated in the graph. This noise in the supply voltage PIXVDD, also referred to as "supply noise", can couple to the voltage of the floating diffusion FD0, as follows: AFDO = supply noise x Cgd_m3 / (Cfd + Cgd_m3), where Cgd_m3 is the gate-drain capacitance of transistor M3, and Cfd is the capacitance of the floating diffusion. As a result, the voltage of the floating diffusion FD0 also contains the supply noise, as shown in the graph of FD0. Furthermore, the voltage of the floating diffusion FD0 is transferred to the voltage of the common floating diffusion FDC, as follows: FDC = FD0 - VGS_m3. Therefore, the noise in the supply voltage PIXVDD also propagates to the voltage of the common floating diffusion FDC.

[0032] As Figure 2 shown in the schematic diagram of FIG. 1, the capacitors C_R and C_S are charged and discharged based on the control voltage VCTRL, which is a DC voltage in at least some embodiments. Therefore, when the signal GRST sets transistor M6 to the "on" state, the reference voltage VR is also affected by the noise in the supply voltage PIXVDD. Similarly, when the signal GTX sets transistor M7 to the "on" state, the signal voltage VS is also affected by the noise in the supply voltage PIXVDD. Furthermore, when the signal GTX sets transistor M7 to the "on" state, transistor M6 has been set to the "off' state for some time, thus disconnecting the reference voltage VR from the supply noise, and over time, a process of dissipating the noise from the reference voltage begins. The overall result is that the voltage values of FDC, VR, and VS are affected by the noise in the supply voltage PIXVDD to different degrees, thus distorting the final readout of the VR and VS voltage values after transistors M6 and M7 are set to the "off' state by the control signals GRST and GTX, respectively, at different times.

[0033] Figure 4 is a schematic diagram illustrating a pixel circuit 20 according to an embodiment of the present disclosure. Figure 4 The pixel circuit 20 of FIG. 2 is similar to the pixel circuit 20 of Figure 3pixel circuit 10, in addition to pixel circuit 20, includes a unity gain circuit VCTRL buffer based on an operational amplifier OP AMP. Those skilled in the art will appreciate that the illustrated VCTRL buffer circuit generates VCTRL with a Hi or Lo output based on a voltage comparison between the positive input of the operational amplifier (V0) and a preset threshold of the operational amplifier. The operation of the VCTRL buffer is described below.

[0034] In some embodiments, the sampling voltage is first set to an appropriate value to set the gate of transistor M10 (also referred to as "tenth transistor") to an "on" state. In this case, the V0 node is set to the VREF voltage (also referred to as "bias voltage"), which is the bias voltage that initiates the VCTRL buffer input transfer. Next, the sampling voltage is set to place transistor M10 in an "off state, thus making the V0 node a floating node following ΔPIXVDD (i.e., a change in PIXVDD, which can also be interpreted as the nominal value of PIXVD plus noise). Thus, the output voltage VCTRL of the OP AMP includes the noise component of PIXVDD. The corresponding signal graphs are explained below with reference to Figure 5

[0035] Figure 5 is a timing diagram illustrating the signal voltages and control voltages of the pixel circuit shown in Figure 4 Figure 3 ​​In contrast to the signal graphs shown in the middle, the supply noise at the FDC node no longer charges / discharges the capacitors C_R and C_S, because as long as the circuit values guarantee: C1 / (C1+C2) = Cgd_m3 / (Cfd+Cgd_m3), the VCTRL at the output of the OPAMP follows the phase and amplitude of the supply noise of the PIX VDD. In other words, the noise content of VCTRL becomes: AVCTRL = supply noise x C1 / (C1+C2). As a result, the supply noise does not affect the differential voltage readout because the noise content now exists in each of the common floating diffusion FDC, the reference voltage VR, the signal voltage VS, and the control voltage VCTRL. Thus, in response to the signals GRST and GTX being set high, VR and VS are likewise (or at least proportionally) affected by the noise / signal sampling. In other words, after the control signal GTX is set high and set back low, the voltage difference Δ(VR - VS) = 0. As a result, the photodiode readout signal is not distorted (or at least the distortion is reduced) by the supply noise, and the noise performance of the image sensor is improved. The capacitors C1 and C2 can be referred to as a first capacitor and a second capacitor, respectively.

[0036] Further embodiments can be derived from the above detailed description. The terms used in the following claims should not be construed to limit the application to the specific embodiments disclosed in the specification and the claims. Rather, the scope of the application is to be determined entirely by the following claims, which are to be construed in accordance with the established doctrines of claim interpretation. Accordingly, the specification and drawings are to be regarded as illustrative and not restrictive.

Claims

1. A pixel circuit of an imaging sensor, the pixel circuit comprising: a front-end circuit including a photodiode configured to generate charge accumulated at a floating diffusion FD0 as a photodiode voltage, wherein the front-end circuit is configured to receive a supply voltage PIXVDD; a signal storage circuit coupled to the front-end circuit, the signal storage circuit including: a common floating diffusion FDC configured to store a common floating diffusion voltage corresponding to the photodiode voltage, wherein the common floating diffusion voltage includes a voltage noise component of the supply voltage PIXVDD; a unity gain circuit coupled to the signal storage circuit, the unity gain circuit including an operational amplifier configured to: couple the supply voltage PIXVDD and a reference voltage VREF as input voltages to the operational amplifier; and generate a control voltage VCTRL as an output voltage, wherein the control voltage VCTRL includes the voltage noise component of the supply voltage PIXVDD; and an output circuit coupled to the signal storage circuit, wherein the output circuit is configured for outputting a signal voltage VS corresponding to the floating diffusion voltage.

2. The pixel circuit of claim 1, wherein the signal storage circuit includes: a reference voltage capacitor coupled to the control voltage VCTRL, wherein the reference voltage capacitor is configured to store the reference voltage VR; and a signal voltage capacitor coupled to the control voltage VCTRL, wherein the signal voltage capacitor is configured to store the signal voltage VS.

3. The pixel circuit of claim 2, wherein the reference voltage VR includes the voltage noise component of the supply voltage PIXVDD.

4. The pixel circuit of claim 3, wherein the signal voltage VS includes the voltage noise component of the supply voltage PIXVDD. The voltage noise components of the reference voltage VR and the signal voltage VS are the same when the signal voltage VS is read out.

6. The pixel circuit of claim 2, wherein the unity gain circuit further includes:

5. The pixel circuit of claim 4, wherein, a first capacitor coupled to the supply voltage PIXVDD; and a second capacitor coupled to the first capacitor and to an input of the operational amplifier; wherein the operational amplifier is configured to output the control voltage VCTRL.

7. The pixel circuit of claim 6, wherein the unity gain circuit further includes a tenth transistor having a drain coupled to a bias voltage VREF and a source coupled to the first capacitor and the second capacitor.

8. The pixel circuit of claim 6, wherein the front-end circuit further includes a third transistor configured for transferring the common floating diffusion voltage to a readout circuit, and wherein: C1 / (C1+C2) = Cgd_m3 / (Cfd+Cgd_m3) wherein: C1 is a capacitance of the first capacitor, C2 is a capacitance of the second capacitor, Cgd_m3 is a capacitance of a gate-drain capacitance of the third transistor, and Cfd is a capacitance of a floating diffusion of the third transistor. C2 is a capacitance of the second capacitor, Cfd is a capacitance of a floating diffusion capacitor, and Cgd_m3 is a gate-drain capacitance of the third transistor.

9. The pixel circuit of claim 8, wherein the photodiode voltage at the floating diffusion FD0 is transferred to the common floating diffusion voltage of the common floating diffusion FDC as follows: FDC = FD0 - Vgs_m3 where: Vgs_m3 is a gate-source voltage of the third transistor.

10. The pixel circuit of claim 9, wherein the photodiode voltage at the floating diffusion FD0 includes a noise component: AFDO = (PIXVDD supply noise) x Cgd_m3 / (Cfd + Cgd_m3), where: AFDO represents the noise component photodiode voltage at the floating diffusion FD0, Cgd_m3 is the gate-drain capacitance of the third transistor, and Cfd is the capacitance of the floating diffusion capacitor Cfd.

11. A method for operating a pixel circuit of an imaging sensor, the method comprising: generating, by a photodiode, a charge at a floating diffusion FD0 of a front-end circuit as a photodiode voltage, wherein the front-end circuit is coupled to a supply voltage PIXVDD, and wherein the supply voltage PIXVDD includes a voltage noise component; transferring the photodiode voltage to a common floating diffusion FDC of a signal storage circuit coupled to the front-end circuit, wherein the photodiode voltage is transferred as a common floating diffusion voltage of the signal storage circuit, and wherein the common floating diffusion voltage includes the voltage noise component of the supply voltage PIXVDD; generating, by a unity gain circuit, a control voltage VCTRL as an output voltage of the unity gain circuit, wherein the control voltage VCTRL includes the voltage noise component of the supply voltage PIXVDD, and wherein the unity gain circuit is coupled to the signal storage circuit; storing, by the signal storage circuit, a reference voltage VR, wherein the reference voltage VR includes the voltage noise component of the supply voltage PIXVDD; storing, by the signal storage circuit, a signal voltage VS, wherein the signal voltage VS includes the voltage noise component of the supply voltage PIXVDD, and wherein the signal voltage VS corresponds to the common floating diffusion voltage; and outputting, by an output circuit coupled to the signal storage circuit, the signal voltage VS.

12. The method of claim 11, further comprising: storing, by a reference voltage capacitor coupled to the control voltage VCTRL, the reference voltage VR; and storing, by a signal voltage capacitor coupled to the control voltage VCTRL, the signal voltage VS.

13. The method of claim 12, wherein the signal voltage VS includes the voltage noise component of the supply voltage PIXVDD, and wherein the signal voltage VS includes the voltage noise component of the supply voltage PIXVDD. ​ ​ ​ ​ ​ ​ ​ ​ ​ 14. The method of claim 13, wherein, The voltage noise components of the reference voltage VR and the signal voltage VS are different after a reset RST signal.

15. The method of claim 14, wherein, The voltage noise components of the reference voltage VR and the signal voltage VS are the same when reading out the signal voltage VS.

16. The method of claim 12, wherein the unity gain circuit further comprises: a first capacitor coupled to the supply voltage PIXVDD; and a second capacitor coupled to the first capacitor and to an input of an operational amplifier.

17. The method of claim 16, wherein the front-end circuit further comprises a third transistor configured for transferring the common floating diffusion voltage to a readout circuit, and wherein: C1 / (C1+C2) = Cgd_m3 / (Cfd+Cgd_m3) wherein: C1 is a capacitance of the first capacitor, C2 is a capacitance of the second capacitor, Cfd is a capacitance of a floating diffusion capacitor, and Cgd_m3 is a gate-drain capacitance of the third transistor.

18. The method of claim 17, wherein the photodiode voltage at the floating diffusion FD0 is transferred to the common floating diffusion voltage of the common floating diffusion FDC as follows: FDC = FD0 - Vgs_m3 wherein: Vgs_m3 is a gate-source voltage of the third transistor.

19. The method of claim 18, wherein the photodiode voltage at the floating diffusion FD0 includes a noise component: AFD0 = (PIXVDD supply noise) x Cgd_m3 / (Cfd+Cgd_m3), wherein: AFD0 represents the noise component photodiode voltage at the floating diffusion FD0, Cgd_m3 is the gate-drain capacitance of the third transistor, and Cfd is the capacitance of the floating diffusion capacitor.

20. The method of claim 16, wherein the unity gain circuit further comprises a tenth transistor having a drain coupled to a bias voltage VREF and a source coupled to the first capacitor and the second capacitor.

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