Tripolar transistor and preparation method thereof

Abstract

The invention relates to the technical field of triode transistors, and discloses a triode transistor and a preparation method thereof.The triode transistor comprises a semiconductor substrate which comprises a collector region and a plurality of shallow trench isolation structures arranged at intervals, and the collector region is located below the shallow trench isolation structures; grooves are formed in the sides, close to each other, of every two adjacent shallow trench isolation structures, and the grooves are filled with conductive materials. The intrinsic base region is arranged on the surface of one side, close to the shallow trench isolation structure, of the semiconductor substrate; the extrinsic base regions are arranged on the surface of one side, close to the shallow trench isolation structure, of the semiconductor substrate, are positioned on two sides of the intrinsic base region, and are in contact with the conductive material; and the emitter region is arranged on the surface of one side, far away from the semiconductor substrate, of the intrinsic base region. According to the invention, the base resistance of the triode transistor can be effectively reduced under the condition that the process complexity and the cost are not greatly increased.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of triode, in particular to a triode and a preparation method thereof. BACKGROUND

[0002] A triode such as a bipolar junction transistor (BJT) and a heterojunction bipolar transistor (HBT) is composed of an emitter, a base and a collector, and can amplify a weak electrical signal to a required amplitude by using the control effect of the base current on the collector current, so the triode is a core element of various amplifiers and is widely used in analog and radio frequency circuit fields.

[0003] In order to realize a large amplification factor, the thickness of the base must be thin enough. If the interconnection between the base and the external circuit is realized by using a thin base thickness, the external base resistance (extrinsic base resistance) R Bx of the triode will be larger, which limits the improvement of the highest working frequency.

[0004] In order to effectively reduce the extrinsic base resistance while realizing a thin intrinsic base thickness, one solution is to open the emitter window after extrinsic base poly deposition (Extrinsic Base Poly Dep), and then selectively epitaxially grow the intrinsic base. However, this solution has a complex process, high cost, and the problem of virtual connection between the intrinsic base epitaxy and the extrinsic base. Another solution is to deposit (Dep) a thin layer of extrinsic polysilicon before non-selective base epitaxy, then photo-etch the intrinsic base region, and then epitaxially grow the intrinsic base. This solution has a simple process and low cost, but has the problem of surface unevenness after the entire base deposition is completed, which affects the photoetching process precision of the subsequent emitter formation, and seriously limits the size shrinkage of the device.

[0005] Therefore, there is an urgent need to solve the problem of high process complexity and cost in effectively reducing the base resistance of the triode. SUMMARY

[0006] Therefore, the present application provides a triode and a preparation method thereof, which can effectively reduce the base resistance of the triode or the heterojunction triode without greatly increasing the process complexity and cost.

[0007] In a first aspect, the present application provides a triode, comprising: a semiconductor substrate, comprising a collector region and a plurality of spaced shallow trench isolation structures, the collector region being located below the shallow trench isolation structures, and each of two adjacent shallow trench isolation structures being provided with a groove on a side close to each other, and the groove being filled with a conductive material; an intrinsic base region, being provided on a side surface of the semiconductor substrate close to the shallow trench isolation structures, and the intrinsic base region being located between the two adjacent shallow trench isolation structures; a non-intrinsic base region, being provided on a side surface of the semiconductor substrate close to the shallow trench isolation structures, and the non-intrinsic base region being located on two sides opposite to the intrinsic base region, and the two non-intrinsic base regions being in contact with the intrinsic base region respectively, and the non-intrinsic base region being in contact with the conductive material respectively; and an emitter region, being provided on a side surface of the intrinsic base region away from the semiconductor substrate.

[0008] The triode provided by the embodiment can replace the insulating material such as silicon dioxide with the conductive material at the edge of the shallow trench isolation structure, so as to increase the conductive area of the base region, thereby effectively reducing the base resistance of the triode without greatly increasing the process complexity and cost, and because the non-intrinsic base region extends downward to the shallow trench isolation structure, the surface flatness problem after the complete base epitaxy is not generated, and the subsequent photolithography process is not affected, and the size of the device can be continuously miniaturized.

[0009] In an optional embodiment, the width of the groove is 1 / 4 of the width of the shallow trench isolation structure to 3 / 4 of the width of the shallow trench isolation structure.

[0010] In the embodiment, the width of the groove is limited to 1 / 4 of the width of the shallow trench isolation structure to 3 / 4 of the width of the shallow trench isolation structure, so that the structure after the conductive material is filled can achieve a better balance between mechanical properties and electrical properties, and the reliability and stability of the triode structure are improved.

[0011] In an optional embodiment, the shallow trench isolation structure comprises a liner layer and an insulating layer, the liner layer is provided on the side wall and the bottom of the shallow trench, the insulating layer fills the shallow trench after the liner layer is formed, and the groove is formed by recessing inward from the surface of the insulating layer away from the collector region, and the liner layer is composed of oxides and nitrides stacked in sequence, or the liner layer is composed of oxides, nitrides and oxides stacked in sequence.

[0012] In the embodiment, the liner layer in the shallow trench isolation structure adopts the stacked structure of oxides and nitrides or the stacked structure of oxides, nitrides and oxides, so that the nitrides and oxides in the liner layer can be retained when the groove is etched in the shallow trench isolation structure, and the electrical isolation between the non-intrinsic base region and the collector region is achieved.

[0013] In an optional embodiment, the thickness of the liner layer is to

[0014] In the embodiment, the thickness of the pad layer is limited to to The parasitic capacitance and leakage current can be reduced while ensuring the isolation effect, and the electrical performance and stability of the transistor can be improved.

[0015] In an alternative embodiment, the conductive material includes at least one of amorphous silicon, polysilicon, and metal.

[0016] In a second aspect, the present application provides a method for manufacturing a bipolar transistor, the method comprising: providing a semiconductor substrate, the semiconductor substrate comprising a collector region and a plurality of spaced shallow trench isolation structures, the collector region being located below the shallow trench isolation structures; forming a recess on a side of the semiconductor substrate close to the shallow trench isolation structures, and filling the recess with a conductive material; forming an intrinsic base region and extrinsic base regions on a surface of the semiconductor substrate close to the shallow trench isolation structures, the intrinsic base region being located between two adjacent shallow trench isolation structures, the extrinsic base regions being located on two sides opposite to the intrinsic base region, the two extrinsic base regions being in contact with the intrinsic base region respectively, and the extrinsic base regions being in contact with the conductive material respectively; and forming an emitter region on a surface of the intrinsic base region away from the semiconductor substrate, to obtain the bipolar transistor according to the first aspect or the corresponding embodiments thereof.

[0017] In an alternative embodiment, the forming of the recess on the side of the semiconductor substrate close to the shallow trench isolation structures and the filling of the recess with the conductive material comprise: coating a photoresist on a surface of the semiconductor substrate close to the shallow trench isolation structures to form a first photoresist layer; performing a first etching treatment on the semiconductor substrate based on the first photoresist layer, so that the recess is formed on the side of the two adjacent shallow trench isolation structures close to each other; removing the first photoresist layer; depositing the conductive material on the surface of the semiconductor substrate close to the shallow trench isolation structures; and performing a polishing treatment on the deposited conductive material until the deposited conductive material is flush with the surface of the semiconductor substrate close to the shallow trench isolation structures, so as to fill the recess with the conductive material.

[0018] In an alternative embodiment, the conductive material is polysilicon, and before the polishing treatment on the deposited conductive material, the method further comprises: performing an in-situ doping treatment on the deposited polysilicon, or performing an ion implantation treatment and a heating annealing treatment on the deposited polysilicon.

[0019] In an alternative embodiment, forming the intrinsic base region and the extrinsic base region on the side surface of the semiconductor substrate close to the shallow trench isolation structure comprises: growing an epitaxial layer on the side surface of the semiconductor substrate close to the shallow trench isolation structure; coating photoresist on the side surface of the epitaxial layer away from the semiconductor substrate to form a second photoresist layer; performing exposure and development treatment on the second photoresist layer; after the exposure and development treatment, performing boron ion implantation treatment and rapid thermal annealing treatment on the epitaxial layer with the remaining second photoresist layer as a mask to form an initial intrinsic base region and an initial extrinsic base region; and performing second etching treatment on the initial intrinsic base region and the initial extrinsic base region to form the intrinsic base region and the extrinsic base region.

[0020] In an alternative embodiment, forming the emitter region on the side surface of the intrinsic base region away from the semiconductor substrate comprises: sequentially depositing oxide and nitride on the side surface of the initial intrinsic base region and the initial extrinsic base region away from the semiconductor substrate; coating photoresist on the side surface of the nitride away from the oxide to form a third photoresist layer, the third photoresist layer having an opening exposing a position corresponding to the initial intrinsic base region of the nitride; performing third etching treatment on the nitride and the oxide based on the third photoresist layer to form an emitter window exposing the initial intrinsic base region; removing the third photoresist layer; depositing polysilicon on the side surface of the nitride away from the oxide to form a polysilicon layer; and performing fourth etching treatment on the polysilicon layer to form the emitter region. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the specific embodiments or the related art, the following will briefly introduce the drawings needed to be used in the specific embodiments or the related art description. Obviously, the drawings described below are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0022] Figure 1 is a structural schematic diagram of a triode according to an embodiment of the present application;

[0023] Figure 2 is an equivalent circuit schematic diagram of a triode according to an embodiment of the present application;

[0024] Figure 3 is a structural schematic diagram of another triode according to an embodiment of the present application;

[0025] Figure 4 is a scanning electron microscope (SEM) diagram of an extrinsic base epitaxial layer according to an embodiment of the present application;

[0026] Figure 5 is a SEM image of an intrinsic base epitaxy according to an embodiment of the present invention;

[0027] Figure 6 is a structural diagram of another triode transistor according to an embodiment of the present invention;

[0028] Figure 7 is a schematic diagram of a shallow trench isolation structure according to an embodiment of the present invention;

[0029] Figures 8 to 21 It is a schematic diagram of the structure involved in preparing a triode transistor according to the method for preparing a triode transistor in an embodiment of the present invention.

[0030] Reference numerals: 100, triode transistor; 101, semiconductor substrate; 1011, collector region; 1012, shallow trench isolation structure; 10121, liner layer; 10122, insulating layer; 1012a, recess; 1013, deep trench isolation structure; 102, intrinsic base region; 103, extrinsic base region; 104, emitter region; 105, conductive material; 106, base conductive layer; 107, collector conductive layer Electrical layer; 108, emitter conductive layer; 109, base electrode; 110, collector electrode; 111, emitter electrode; 112, first photoresist layer; 113, second photoresist layer; 114, oxide; 115, nitride; 116, third photoresist layer; 1161, opening; 117, emitter window; 118, polysilicon layer; 119, fourth photoresist layer; 120, epitaxial layer; 121, sidewall structure. DETAILED DESCRIPTION

[0031] The present invention will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are intended only to illustrate the present invention and are not intended to limit the present invention. It should also be noted that, for ease of description, the accompanying drawings only illustrate portions relevant to the present invention, not all structures.

[0032] In the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion about the concepts of the present invention. The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present invention. These figures are not drawn to scale; certain details are exaggerated and may be omitted for clarity. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions based on actual needs. In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intervening layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, it may be "below" the other layer / element when the orientation is reversed.

[0033] The structure diagram of the triode transistor can be shown as Figure 1 As shown, the equivalent circuit diagram of the triode transistor can be shown as Figure 2 As shown, in Figure 2 In, R Bx Represents the base resistance of the extrinsic part, R Bi The base resistance represents the intrinsic part, and the extrinsic part comes from the connection area where the intrinsic base contacts. BCx represents the base-collector capacitance of the extrinsic part, C BCi represents the base-collector capacitance of the intrinsic part, R C Represents the collector resistance, C BE Represents the base-emitter depletion layer capacitance and oxide layer capacitance, C diff Indicates that the forward working mode is less

[0034] Diffusion capacitance related to carrier storage, β f represents the forward DC current gain, g m represents transconductance, V BE represents the intrinsic base-emitter voltage, R Ea represents the output resistance associated with the Early effect, R E represents the emitter resistance.

[0035] In order to improve the amplification factor of the bipolar junction transistor or heterojunction bipolar transistor, the thickness of the base needs to be set thinner, and a thinner base thickness may cause R Bx According to the maximum operating frequency formula of the triode transistor shown in formula (1), a higher base resistance will limit the increase in the maximum operating frequency, thereby affecting the performance of the triode transistor in high-frequency scenarios.

[0036]

[0037] In formula (1), f MAX represents the highest oscillation frequency of the triode, which is the highest frequency at which the triode can work normally and realize power amplification, f T represents the characteristic frequency, which refers to the signal frequency corresponding to the drop of the common emitter current amplification factor β of the triode to 1, C Bi represents the base capacitance of the intrinsic part, which is the capacitance generated by the internal structure of the base, C Bx represents the base capacitance of the extrinsic part, which is the capacitance related to the connection between the base and the external circuit.

[0038] To effectively reduce the extrinsic base resistance when the intrinsic base thickness is relatively thin, as shown in Figure 3 , a method of depositing polycrystalline silicon of the extrinsic base, then opening the emitter window, and then selectively epitaxially growing the intrinsic base can be used to solve the problem. However, this solution is complicated in process and high in cost, and there is a problem of virtual connection between the epitaxial intrinsic base and the extrinsic base.

[0039] Another solution is to deposit a thin layer of extrinsic polycrystalline silicon before non-selective epitaxial growth of the base, as shown in Figure 4 , etching the intrinsic base region by lithography, and then epitaxially growing the intrinsic base. This solution is simple in process and low in cost, but as shown in Figure 5 , there is a problem of uneven surface after the entire base deposition is completed, thereby affecting the lithography process precision of the subsequently formed emitter, and the device size is severely limited in micro-shrinking.

[0040] Therefore, the present application provides a triode, in which an insulating material is replaced by a conductive material in the edge part of a shallow trench isolation (STI) structure, so as to increase the conductive area of the base part, thereby effectively reducing the base resistance of the triode without greatly increasing the process complexity and cost. At the same time, because the extrinsic base extends downward to the shallow trench isolation structure, there is basically no problem of surface flatness after the complete epitaxy of the base, and the subsequent lithography process is not affected, and the device size can be continuously micro-shrunk.

[0041] First, the structure of the triode provided by the present application will be described in detail in combination with the drawings.

[0042] As shown in Figure 6 , the triode 100 includes a semiconductor substrate 101, an intrinsic base region 102, an extrinsic base region 103, and an emitter region 104.

[0043] As shown in Figure 6As shown, the semiconductor substrate 101 includes a collector region 1011 and a plurality of shallow trench isolation structures 1012 arranged at intervals. The collector region 1011 is located below the shallow trench isolation structure 1012. Two adjacent shallow trench isolation structures 1012 are each provided with a groove 1012a on a side close to each other, and the groove 1012a is filled with a conductive material 105.

[0044] The intrinsic base region 102 is disposed on a surface of the semiconductor substrate 101 adjacent to the shallow trench isolation structure 1012. The intrinsic base region 102 is located between two adjacent shallow trench isolation structures 1012. The extrinsic base region 103 is disposed on a surface of the semiconductor substrate 101 adjacent to the shallow trench isolation structure 1012. The extrinsic base region 103 is located on opposite sides of the intrinsic base region 102 and covers the conductive material 105 within the grooves 1012a of the two adjacent shallow trench isolation structures 1012. The emitter region 104 is disposed on a surface of the intrinsic base region 102 away from the semiconductor substrate 101.

[0045] The two extrinsic base regions 103 are in contact with the intrinsic base region 102 respectively, and the extrinsic base regions 103 are also in contact with the conductive material respectively. Figure 6 As shown, the adjacent side surfaces of the two extrinsic base regions 103 respectively contact the opposite sides of the intrinsic base region 102, and the surface of the extrinsic base region 103 adjacent to the semiconductor substrate 101 contacts the conductive material. When the triode transistor 100 is operating, the extrinsic base regions 103 contact the intrinsic base region 102 to form an electrical path, electrically connecting the external circuit to the base of the triode transistor 100. The extrinsic base regions 103 also form an electrical path with the corresponding conductive material, increasing the connection area between the extrinsic base regions 103 and the intrinsic base region.

[0046] Specifically, the shallow trench isolation structures 1012 are used to achieve electrical isolation between different regions, preventing current leakage and mutual interference between adjacent regions. In the present application, after forming multiple shallow trench isolation structures 1012 on the semiconductor substrate 101, grooves 1012a are formed on the sides of two adjacent shallow trench isolation structures 1012 that are close to each other, and the grooves 1012a are filled with a conductive material 105. The conductive material 105 can include at least one of amorphous silicon, polycrystalline silicon, and metal.

[0047] Among them, Figure 6 For example, the sides of two adjacent shallow trench isolation structures 1012 close to each other specifically refer to the right side of the left shallow trench isolation structure 1012 and the left side of the right shallow trench isolation structure 1012 .

[0048] The edge of the shallow trench isolation structure 1012 is etched to form a recess, and the original insulating material (e.g., silicon dioxide) of the shallow trench isolation structure 1012 is replaced with a conductive material to increase the conductive area of the base portion and reduce the resistance of the base.

[0049] The semiconductor substrate 101 provides physical support for the other regions and provides a path for current flow. The semiconductor substrate 101 can be silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), or the like. The intrinsic base region 102 is located above the collector region 1011 and between two adjacent shallow trench isolation structures 1012. The intrinsic base region 102 controls the current flow from the emitter to the collector and is a key region for carrier transport and control. The extrinsic base region 103 is located above the collector region 1011 and on both sides of the intrinsic base region 102 and covers the conductive material in the recess 1012a. The extrinsic base region 103 is typically connected to an external circuit and serves as an input port for the base signal. The emitter region 104 is located above the intrinsic base region 102 and serves as a source of carriers for the base. The collector region 1011 is formed in the semiconductor substrate 101 and collects carriers that are transported from the emitter through the base. The collector region 1011 forms a collector current and is the main source of output current for the transistor.

[0050] The transistor can be configured as an NPN type, and the collector region 1011 and the emitter region 104 include N-type semiconductor material. The intrinsic base region 102 and the extrinsic base region 103 can include P-type semiconductor material. In other embodiments, the transistor can be configured as a PNP type, and the collector region 1011 and the emitter region 104 include P-type semiconductor material. The intrinsic base region 102 and the extrinsic base region 103 can include N-type semiconductor material.

[0051] For embodiments in which the collector region 1011 includes N-type semiconductor material, the collector region 1011 can be doped with one or more of the following materials: phosphorus (P), arsenic (As), antimony (Sb), lithium (Li), or other suitable dopants. For embodiments in which the collector region 1011 includes P-type semiconductor material, the collector region 1011 can be doped with one or more of the following materials: carbon (C), boron (B), oxygen (O), or indium (In), or other suitable dopants.

[0052] The triode transistor provided in this embodiment uses conductive materials instead of insulating materials such as silicon dioxide at the edge of the shallow trench isolation structure 1012, which can increase the conductive area of ​​the base region, thereby effectively reducing the base resistance of the triode transistor without significantly increasing the process complexity and cost. At the same time, because the non-intrinsic base region 103 extends downward toward the shallow trench isolation structure, there is basically no surface flatness problem after the complete base epitaxy, which will not affect the subsequent photolithography process, and the size of the device can be continuously miniaturized.

[0053] Exemplarily, the width of the groove is 1 / 4 to 3 / 4 of the width of the shallow trench isolation structure 1012. For example, the width of the groove can be 1 / 4, 1 / 2, or 3 / 4 of the width of the shallow trench isolation structure 1012.

[0054] Specifically, if the groove width is too narrow, the increased conductive area is limited, making it difficult to effectively reduce the base resistance. If the groove width is too wide, the mechanical properties of the shallow trench isolation structure 1012 may be degraded, making it easy for the structure to be damaged or deformed during subsequent processing. In this embodiment, the groove width is limited to 1 / 4 to 3 / 4 of the width of the shallow trench isolation structure 1012. This allows the structure filled with conductive material to achieve a good balance between mechanical and electrical properties, thereby improving the reliability and stability of the triode transistor structure.

[0055] In some embodiments, as Figure 7 As shown, the shallow trench isolation structure 1012 includes a liner layer 10121 and an insulating layer 10122. The liner layer 10121 is disposed on the sidewalls and bottom of the shallow trench. The insulating layer 10122 fills the shallow trench formed after the liner layer 10121 is formed. The recess 1012a is formed inwardly from the surface of the insulating layer 10122 away from the collector region 1011. Specifically, the upper surface of the insulating layer 10122 can be flush with the upper surface of the semiconductor substrate 101, and the recess 1012a extends downward from the upper surface of the insulating layer 10122.

[0056] The liner layer is composed of an oxide and a nitride (SiN) stacked in sequence, or an oxide, a nitride, and an oxide stacked in sequence. That is, the liner layer adopts an ON structure or an ONO structure. The insulating layer can be made of silicon dioxide (SiO2).

[0057] Specifically, the shallow trench isolation structure 1012 is generally formed by etching a shallow trench on a semiconductor substrate. The sidewalls and bottom of the etched shallow trench are then thermally oxidized to grow a thin silicon dioxide layer, improving the trench interface properties and reducing surface states and leakage current. A thin liner layer is then deposited within the shallow trench to further protect the sidewalls and bottom of the shallow trench and prevent subsequent filler material from interacting with the semiconductor substrate. Finally, the shallow trench is filled with an insulating material (such as silicon dioxide) using methods such as chemical vapor deposition (CVD). The filling process ensures that the shallow trench is completely filled and the surface is smooth, forming an insulating layer.

[0058] In this embodiment, the liner layer in the shallow trench isolation structure 1012 adopts an ON structure or an ONO structure, so that when the groove is etched in the shallow trench isolation structure 1012, the two layers (SiN / Oxide) inside the liner layer can be retained to achieve electrical isolation between the non-intrinsic base region 103 and the collector region 1011.

[0059] For example, the thickness of the liner layer is to For example, the thickness of the liner layer may be or wait.

[0060] Specifically, if the liner layer is too thin (less than ), may not provide sufficient insulation performance, resulting in poor isolation between the extrinsic base region 103 and the collector region 1011, leakage, and affecting the switching characteristics and amplification of the transistor. On the contrary, if the liner layer is too thick (greater than ), will increase parasitic capacitance and affect the high-frequency response speed and signal transmission efficiency of the transistor.

[0061] In this embodiment, the thickness of the liner layer is limited to to It can reduce parasitic capacitance and leakage current while ensuring isolation effect, and improve the electrical performance and stability of transistors.

[0062] In some embodiments, as Figure 6 As shown, the semiconductor substrate 101 also includes multiple deep trench isolation (DTI) structures 1013. Two adjacent deep trench isolation structures 1013 are respectively located on the side away from each other of two adjacent shallow trench isolation structures 1012. The deep trench isolation structure 1013 is used for effective electrical isolation to prevent current leakage and signal crosstalk.

[0063] like Figure 6As shown, the triode 100 further comprises a base conductive layer 106, a collector conductive layer 107, an emitter conductive layer 108, a base electrode 109, a collector electrode 110 and an emitter electrode 111.

[0064] The base conductive layer 106 is disposed on the side surface of the extrinsic base region away from the semiconductor substrate, and the base electrode 109 is disposed on the base conductive layer 106, for connecting the base region of the triode to an external circuit. The collector conductive layer 107 is disposed on the side surface of the semiconductor substrate close to the shallow trench isolation structure, and the collector conductive layer 107 is located between the adjacent shallow trench isolation structure 1012 and the deep trench isolation structure 1013, and the collector conductive layer 107 is electrically connected to the collector region. The collector electrode 110 is disposed on the collector conductive layer 107, for connecting the collector region of the triode to an external circuit. The emitter conductive layer 108 is disposed on the side surface of the emitter region away from the semiconductor substrate, and the emitter electrode 111 is disposed on the emitter conductive layer 108, for connecting the emitter region of the triode to an external circuit.

[0065] In the present embodiment, a preparation method of the triode is also provided, and the preparation process of the triode provided by the present application will be described in detail below in combination with the drawings.

[0066] As shown in the drawings, Figures 8 to 21 The preparation method of the triode comprises but is not limited to the following steps S11 to S14:

[0067] Step S11, providing a semiconductor substrate.

[0068] Specifically, the semiconductor substrate is the basic structure for constructing the triode, and the semiconductor substrate can comprise a collector region and a plurality of spaced shallow trench isolation structures, and the collector region is located below the shallow trench isolation structures.

[0069] For example, the semiconductor substrate can be as shown in the drawings, Figure 8 Figure 8 The semiconductor substrate as shown can further comprise a deep trench isolation structure 1013.

[0070] Step S12, forming a groove on the side close to each other of the two adjacent shallow trench isolation structures, and filling the groove with a conductive material.

[0071] In some optional embodiments, step S12 comprises but is not limited to steps S121 to S125:

[0072] Step S121, coating photoresist on the side surface of the semiconductor substrate close to the shallow trench isolation structure to form a first photoresist layer.

[0073] ​Specifically, after obtaining the semiconductor substrate, the semiconductor substrate can be placed on a coating machine, and a certain thickness of photoresist is formed on the surface of one side of the semiconductor substrate close to the shallow trench isolation structure by rotating the coating machine. Then, a soft baking treatment is performed to solidify the photoresist to form a first photoresist layer.

[0074] Step S122 , performing a first etching process on the semiconductor substrate based on the first photoresist layer, so that grooves are formed on the sides of two adjacent shallow trench isolation structures that are close to each other.

[0075] After forming the first photoresist layer 112, the first photoresist layer 112 is exposed and developed based on the formation position of the groove 1012a, and the pattern of the groove 1012a to be processed is transferred to the first photoresist layer 112, so as to obtain the following: Figure 9 The semiconductor structure shown.

[0076] In getting Figure 9 After the structure shown in FIG. 1 is formed, the semiconductor substrate is subjected to a first etching process based on a mask formed by the first photoresist layer, so that two adjacent shallow trench isolation structures 1012 form grooves 1012a on the sides close to each other, and the structure shown in FIG. Figure 10 The semiconductor structure shown.

[0077] Exemplarily, the first etching process can be dry etching or wet etching, etc. Dry etching uses plasma to react physically or chemically with the material to remove unnecessary parts on the semiconductor substrate. Wet etching immerses the semiconductor substrate in a solution containing a chemical corrosive liquid, and uses the corrosive liquid to react chemically with the substrate material to remove the part that needs to be etched.

[0078] Step S123 , removing the first photoresist layer.

[0079] Specifically, in getting Figure 10 After the semiconductor structure shown, the Figure 10 The semiconductor structure is placed in a stripping solution, and the stripping solution reacts chemically with the photoresist to dissolve and remove the photoresist.

[0080] Step S124 , depositing a conductive material on a surface of the semiconductor substrate close to the shallow trench isolation structure.

[0081] Specifically, after removing the first photoresist layer 112, a conductive material 105 is deposited on the upper surface of the semiconductor substrate by using a method such as physical vapor deposition (PVD) or chemical vapor deposition to obtain a conductive material 105. Figure 11 The semiconductor structure shown in FIG.

[0082] Exemplarily, before the deposition of the conductive material 105, a thermal oxidation process can also be performed on the semiconductor substrate to form a thin oxide layer (e.g., a silicon dioxide layer) on the upper surface of the semiconductor substrate, so as to improve the interface properties between the substrate and the conductive material, and improve the adhesion and electrical properties.

[0083] In step S125, the deposited conductive material is polished until the deposited conductive material and the semiconductor substrate are flush with each other on the side surface close to the shallow trench isolation structure, so as to fill the recess with the conductive material.

[0084] Specifically, after obtaining the semiconductor structure as shown in FIG. 1C, the semiconductor substrate with the deposited conductive material is placed on a polishing pad of a chemical mechanical polishing (CMP) device, and the deposited conductive material on the upper surface of the semiconductor substrate is removed by chemical mechanical polishing until the deposited conductive material and the semiconductor substrate are flush with each other on the side surface close to the shallow trench isolation structure, so as to obtain the semiconductor structure as shown in FIG. 1D. Figure 11 Figure 12 Specifically, after obtaining the semiconductor structure as shown in FIG. 1C, the semiconductor substrate with the deposited conductive material is placed on a polishing pad of a chemical mechanical polishing (CMP) device, and the deposited conductive material on the upper surface of the semiconductor substrate is removed by chemical mechanical polishing until the deposited conductive material and the semiconductor substrate are flush with each other on the side surface close to the shallow trench isolation structure, so as to obtain the semiconductor structure as shown in FIG. 1D.

[0085] Exemplarily, the conductive material can be polysilicon, and before the polishing of the deposited conductive material, the preparation method further includes: in-situ doping of the deposited polysilicon, or ion implantation and heating annealing of the deposited polysilicon.

[0086] Specifically, the in-situ doping is to introduce impurity atoms (e.g., phosphorus, boron, etc.) into the polysilicon during the deposition of the polysilicon. These impurity atoms will replace the silicon atoms in the crystal lattice and become the source of carriers (electrons or holes) in the polysilicon. When there is an electric current, these additional carriers can participate in conduction, thereby reducing the resistivity of the polysilicon, making the polysilicon more easily conduct current and improving its conductive performance.

[0087] After obtaining the semiconductor structure as shown in FIG. 1D, high-energy impurity ions (e.g., phosphorus ions, boron ions) can be accelerated and implanted into the polysilicon by an ion implantation device. After the implantation of the ions, the polysilicon crystal lattice structure will be damaged and have defects due to the impact of the high-energy ions. Through heating annealing, the atoms in the polysilicon can obtain enough energy to move and rearrange at a certain temperature, repair the lattice damage, and make the implanted impurity atoms better integrate into the crystal lattice, thereby activating the impurities and making them effectively provide carriers, thereby reducing the resistivity of the polysilicon. Figure 11 In step S13, an intrinsic base region and a non-intrinsic base region are formed on the side surface of the semiconductor substrate close to the shallow trench isolation structure.

[0088]

[0089] ​​The intrinsic base region is located between two adjacent shallow trench isolation structures, and the extrinsic base regions are located on both sides of the intrinsic base region and cover the conductive material in the grooves of the two adjacent shallow trench isolation structures. The two extrinsic base regions are in contact with the intrinsic base region respectively, and the extrinsic base regions are also in contact with the conductive material respectively. When the triode works, the extrinsic base regions and the intrinsic base region form an electrical path, so that the external circuit is electrically connected with the base of the triode, and the extrinsic base regions also form an electrical path with the corresponding conductive material, thereby increasing the communication area between the extrinsic base regions and the intrinsic base region.

[0090] In some optional embodiments, the step S13 includes but is not limited to steps S131-S135:

[0091] Step S131: growing an epitaxial layer on the side surface of the semiconductor substrate close to the shallow trench isolation structure.

[0092] Specifically, after obtaining the semiconductor structure as shown in Figure 12 , an epitaxial layer 120 can be grown on the base region to obtain the semiconductor structure as shown in Figure 13 , and the material of the epitaxial layer can be single crystal silicon, polycrystalline silicon and / or amorphous silicon.

[0093] For example, the epitaxial layer as shown in Figure 13 can be formed on the upper surface of the semiconductor substrate 101 by a vapor phase epitaxy (VPE) process or a molecular beam epitaxy (MBE) process.

[0094] It should be understood that, during epitaxy, if the base material is silicon, the epitaxial growth is also silicon; if the base material is not silicon, the epitaxial growth is polycrystalline silicon or amorphous silicon. The upper surface of the semiconductor substrate 101 can be divided into a center region and two side regions, the center region refers to the region between the two adjacent shallow trench isolation structures on the upper surface, that is, the defined intrinsic base region, and the material of the center region is the material of the semiconductor substrate, such as silicon, etc., and the epitaxial layer on the center region is usually single crystal silicon; the two side regions are the regions on the upper surface except the center region, and the material of the two side regions is a conductive material, silicon dioxide and silicon nitride, and the epitaxial layer on the two side regions is usually polycrystalline silicon or amorphous silicon. When the epitaxial layer 120 is epitaxially grown on the upper surface of the semiconductor substrate 101, due to the difference in materials between the center region and the two side regions on the upper surface, the growth rate of silicon and polycrystalline silicon (or amorphous silicon) is different, which will cause the epitaxial layer to have a structure of thin in the middle and thick on the sides.

[0095] It should be noted that a semiconductor substrate typically integrates more than just a single triode transistor. For example, the same semiconductor substrate can integrate a bipolar junction transistor and a complementary metal-oxide-semiconductor (CMOS) to form an operational amplifier or power integrated circuit. During the triode transistor formation process, to prevent interference with the formation of other semiconductor devices, a silicon nitride protective layer is formed on the silicon region, excluding the central region, before epitaxial growth.

[0096] The structure that is thin in the middle and thick on both sides does not affect the subsequent processing technology, so the subsequent process steps can be carried out directly after the epitaxial layer is formed.

[0097] In step S132 , photoresist is coated on a surface of the epitaxial layer away from the semiconductor substrate to form a second photoresist layer.

[0098] Step S133 , performing exposure and development processing on the second photoresist layer.

[0099] Specifically, in getting Figure 13 After the semiconductor structure shown in the figure is formed, it can be placed on a spreader, and a certain thickness of photoresist is formed on the surface of the epitaxial layer away from the semiconductor substrate by rotating the spreader. Then, a soft baking treatment is performed to solidify the photoresist to form a second photoresist layer. Then, the second photoresist layer is exposed and developed, and only the second photoresist layer corresponding to the intrinsic base region is retained.

[0100] Step S134 , after the exposure and development processes, the epitaxial layer is subjected to boron ion implantation and rapid thermal annealing using the remaining second photoresist layer as a mask to form an initial intrinsic base region and an initial extrinsic base region.

[0101] Specifically, if Figure 14 As shown, after forming the second photoresist layer 113 only at the position corresponding to the intrinsic base region, the epitaxial layer is subjected to boron ion implantation and rapid thermal annealing based on the mask formed by the remaining second photoresist layer 113 to form an initial intrinsic base region and an initial extrinsic base region.

[0102] Step S135 , performing a second etching process on the initial intrinsic base region and the initial extrinsic base region to form an intrinsic base region and an extrinsic base region.

[0103] Specifically, after forming the initial intrinsic base region and the initial extrinsic base region, the remaining second photoresist layer 113 is removed, and then the initial intrinsic base region and the initial extrinsic base region are subjected to a second etching process to form the intrinsic base region and the extrinsic base region. The second etching process and the first etching process may be the same or different.

[0104] Step S14, forming an emitter region on the side surface of the intrinsic base region away from the semiconductor substrate to obtain a triode.

[0105] In some optional embodiments, step S14 includes but is not limited to steps S141 to S146:

[0106] Step S141, sequentially depositing an oxide and a nitride on the side surface of the initial intrinsic base region and the initial extrinsic base region away from the semiconductor substrate.

[0107] Specifically, after forming the initial intrinsic base region and the initial extrinsic base region, an oxide 114 can be deposited on the side surface of the initial intrinsic base region and the initial extrinsic base region away from the semiconductor substrate by a chemical vapor deposition method, and then a nitride 115 can be deposited on the side surface of the oxide away from the semiconductor substrate again by a chemical vapor deposition method, to obtain a semiconductor structure as shown in Figure 15 .

[0108] Wherein, step S141 can be performed before step S135.

[0109] Step S142, coating a photoresist on the side surface of the nitride away from the oxide to form a third photoresist layer.

[0110] Wherein, the third photoresist layer has an opening, and the opening exposes the position corresponding to the initial intrinsic base region of the nitride.

[0111] Specifically, after obtaining a semiconductor structure as shown in Figure 15 , a photoresist with a certain thickness can be formed on the side surface of the nitride 115 away from the oxide by a photoresist coater, and then baking treatment is performed to obtain a third photoresist layer 116. Then, exposure treatment and development treatment are performed to form an opening 1161 in the third photoresist layer 116, to obtain a semiconductor structure as shown in Figure 16 .

[0112] Step S143, performing a third etching treatment on the nitride and the oxide based on the third photoresist layer to form an emitter window.

[0113] Wherein, the emitter window exposes the initial intrinsic base region.

[0114] Specifically, after obtaining a semiconductor structure as shown in Figure 16 , a third etching treatment is performed on the nitride and the oxide based on the mask formed by the third photoresist layer to form an emitter window 117. Wherein, the third etching treatment can be the same as the first etching treatment, or can be different.

[0115] Step S144, removing the third photoresist layer.

[0116] Specifically, after forming the emitter window 117, it can be placed in a stripping solution which chemically reacts with the photoresist and dissolves and removes the photoresist, obtaining a semiconductor structure as shown in FIG. 11B. Figure 17

[0117] Step S145, polycrystalline silicon is deposited on the side surface of the nitride away from the oxide to form a polycrystalline silicon layer.

[0118] Specifically, after obtaining a semiconductor structure as shown in FIG. 11B, a chemical vapor deposition method can be used to deposit polycrystalline silicon on the side surface of the nitride away from the oxide to form a polycrystalline silicon layer 118, which can be as shown in FIG. 11C. Figure 17 Figure 18

[0119] Step S146, the polycrystalline silicon layer is subjected to a fourth etching treatment to form an emitter region.

[0120] Specifically, after obtaining a semiconductor structure as shown in FIG. 11C, a fourth photoresist layer 119 is formed on the side surface of the polycrystalline silicon layer away from the nitride, and then the fourth photoresist layer is subjected to an exposure treatment and a development treatment, only the fourth photoresist layer at the position corresponding to the emitter region is reserved, obtaining a semiconductor structure as shown in FIG. 11D. Figure 18 Figure 19

[0121] After obtaining a semiconductor structure as shown in FIG. 11D, the polycrystalline silicon layer, the nitride and the oxide are subjected to a wet etching or a dry etching with the remaining fourth photoresist layer 119 as a mask to form an emitter region, and a side wall structure 121 is formed on both sides of the emitter region, obtaining a semiconductor structure as shown in FIG. 11E. Figure 19 Figure 20

[0122] For example, step S134 is after step S146, specifically, after obtaining a semiconductor structure as shown in FIG. 11E, a fifth photoresist layer can be formed again, and the fifth photoresist layer is subjected to an exposure treatment and a development treatment, and then the remaining fifth photoresist layer is used as a mask to etch the initial intrinsic base region and the initial extrinsic base region to form an intrinsic base region and an extrinsic base region, obtaining a triode transistor as shown in FIG. 11F. Figure 20 Figure 21

[0123] Specifically, after obtaining a semiconductor structure as shown in FIG. 11F, the base conductive layer 106, the collector conductive layer 107, the emitter conductive layer 108, the base electrode 109, the collector electrode 110 and the emitter electrode 111 are continuously formed, obtaining a triode transistor as shown in FIG. 11G. Figure 21 Figure 6

[0124] ​​​​​​​​​​​In the description of the specification, the description of the terms "the embodiment", "one embodiment", "some embodiments", "example", "specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Also, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, the person skilled in the art can combine and combine the different embodiments or examples described in the specification and the features of the different embodiments or examples without contradiction.

[0125] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is at least two, for example, two, three, etc., unless otherwise explicitly specified.

[0126] In the above description, the technical details such as the arrangement of each layer, etching, etc. are not described in detail. However, those skilled in the art should understand that the layers, regions, etc. of the required shape can be formed by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the methods described above in order to form the same structure. In addition, although each embodiment is described above, this does not mean that the measures in each embodiment cannot be effectively combined.

[0127] The above is only the preferred embodiment of the present application and the technical principle applied. Those skilled in the art will understand that the present application is not limited to the specific embodiments described above, and those skilled in the art can make various obvious changes, re-adjustments, mutual combinations and replacements without departing from the scope of the present application.

[0128] Therefore, although the present application is described in more detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application.

Claims

1. A triode transistor, characterized by The triode transistor comprises: a semiconductor substrate comprising a collector region and a plurality of spaced shallow trench isolation structures, the collector region being located below the shallow trench isolation structures, two adjacent shallow trench isolation structures each being provided with a groove on a side close to each other, and the groove being filled with conductive material; an intrinsic base region provided on a side surface of the semiconductor substrate close to the shallow trench isolation structures, the intrinsic base region being located between two adjacent shallow trench isolation structures; extrinsic base regions provided on a side surface of the semiconductor substrate close to the shallow trench isolation structures, the extrinsic base regions being located on two sides opposite to the intrinsic base region, two extrinsic base regions respectively contacting the intrinsic base region, and the extrinsic base regions respectively contacting the conductive material; an emitter region provided on a side surface of the intrinsic base region away from the semiconductor substrate.

2. The triode transistor of claim 1, wherein The width of the groove is 1 / 4 of the width of the shallow trench isolation structure to 3 / 4 of the width of the shallow trench isolation structure.

3. The triode transistor of claim 1, wherein The shallow trench isolation structure comprises a liner layer and an insulating layer, the liner layer being provided on the sidewall and bottom of the shallow trench, the insulating layer filling the shallow trench after the liner layer is formed, the groove being formed by recessing inward from the surface of the insulating layer away from the collector region, and the liner layer being sequentially stacked by oxide and nitride or sequentially stacked by oxide, nitride and oxide.

4. The triode transistor of claim 3, wherein The thickness of the spacer layer is to 5. The triode transistor according to any one of claims 1 to 4, characterized in that The conductive material comprises at least one of amorphous silicon, polysilicon and metal.

6. A method of fabricating a triode transistor, characterized by, The method comprises: providing a semiconductor substrate comprising a collector region and a plurality of spaced shallow trench isolation structures, the collector region being located below the shallow trench isolation structures; forming a groove on a side of two adjacent shallow trench isolation structures close to each other and filling the groove with conductive material; forming an intrinsic base region and extrinsic base regions on a side surface of the semiconductor substrate close to the shallow trench isolation structures, the intrinsic base region being located between two adjacent shallow trench isolation structures, the extrinsic base regions being located on two sides opposite to the intrinsic base region, two extrinsic base regions respectively contacting the intrinsic base region, and the extrinsic base regions respectively contacting the conductive material; forming an emitter region on a side surface of the intrinsic base region away from the semiconductor substrate to obtain the triode transistor according to any one of claims 1 to 5.

7. The method of claim 6, wherein, forming a groove on a side of two adjacent shallow trench isolation structures close to each other and filling the groove with conductive material, comprising: coating photoresist on a side surface of the semiconductor substrate close to the shallow trench isolation structures to form a first photoresist layer; performing first etching treatment on the semiconductor substrate based on the first photoresist layer to form a groove on a side of two adjacent shallow trench isolation structures close to each other; removing the first photoresist layer; depositing conductive material on a side surface of the semiconductor substrate close to the shallow trench isolation structures; polishing the deposited conductive material until the deposited conductive material and the semiconductor substrate are flush with each other on a side surface of the semiconductor substrate close to the shallow trench isolation structure to fill the recess with the conductive material.

8. The method of claim 7, wherein, The conductive material is polysilicon, and before the polishing of the deposited conductive material, the method further comprises: in-situ doping the deposited polysilicon, or ion implantation and heat annealing the deposited polysilicon.

9. The method according to any one of claims 6 to 8, characterized in that, forming an intrinsic base region and a non-intrinsic base region on a side surface of the semiconductor substrate close to the shallow trench isolation structure, comprising: growing an epitaxial layer on a side surface of the semiconductor substrate close to the shallow trench isolation structure; coating a photoresist on a side surface of the epitaxial layer away from the semiconductor substrate to form a second photoresist layer; exposing and developing the second photoresist layer; after the exposing and developing, implanting boron ions into the epitaxial layer with the remaining second photoresist layer as a mask and performing heat annealing to form an initial intrinsic base region and an initial non-intrinsic base region; performing a second etching on the initial intrinsic base region and the initial non-intrinsic base region to form the intrinsic base region and the non-intrinsic base region.

10. The method of claim 9, wherein, forming an emitter region on a side surface of the intrinsic base region away from the semiconductor substrate, comprising: depositing oxide and nitride on a side surface of the initial intrinsic base region and the initial non-intrinsic base region away from the semiconductor substrate in sequence; coating a photoresist on a side surface of the nitride away from the oxide to form a third photoresist layer, the third photoresist layer having an opening exposing a position corresponding to the initial intrinsic base region and the nitride; performing a third etching on the nitride and the oxide based on the third photoresist layer to form an emitter window exposing the initial intrinsic base region; removing the third photoresist layer; depositing polysilicon on a side surface of the nitride away from the oxide to form a polysilicon layer; performing a fourth etching on the polysilicon layer to form an emitter region.

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