Power semiconductor device and preparation method of power semiconductor device

Abstract

The invention provides a power semiconductor device and a preparation method of the power semiconductor device. The power semiconductor device includes: a substrate; the epitaxial layer is located on one side of the substrate, the epitaxial layer comprises first doped regions and epitaxial regions which are alternately arranged in the first direction, the adjacent first doped regions and epitaxial regions form a super junction structure, and the first direction is perpendicular to the thickness direction of the substrate; in a second direction, the second doped region is located at one side, far away from the substrate, of the super junction structure, and the second direction is the thickness direction of the substrate; in the second direction, the third doped region is located on the partial surface, away from the super junction structure, of the second doped region, and the doping type of the first doped region, the doping type of the second doped region and the doping type of the third doped region are the same; the first metal layer is located on the side, away from the epitaxial layer, of the substrate; the second metal layer is located on the side, away from the substrate, of the epitaxial layer. The problem that the injection efficiency of the power semiconductor device is not ideal is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, in particular, to a power semiconductor device and a preparation method of the power semiconductor device. BACKGROUND

[0002] In the current field of power semiconductor devices, there is a clear contradiction between the performance stability under high reverse bias and the efficiency under large current conditions in the traditional technology. Under the condition of large current, the injection efficiency of the power semiconductor is low, and after exiting the bipolar conduction mode, the turn-off speed is slow and the tail current is large, which reduces the switching efficiency and the reliability of the device.

[0003] Therefore, there is an urgent need for a new technical solution to overcome the above problems.

[0004] The above information disclosed in the background section is only used to enhance the understanding of the background of the technology described herein, therefore, the background may contain some information which is not considered as prior art by those skilled in the art in the country. SUMMARY

[0005] The main purpose of the present application is to provide a power semiconductor device and a preparation method of the power semiconductor device, to solve the problem of unsatisfactory injection efficiency of the power semiconductor device in the prior art.

[0006] In order to achieve the above purpose, according to one aspect of the present application, a power semiconductor device is provided, comprising: a substrate; an epitaxial layer located on one side of the substrate, the epitaxial layer comprising first doped regions and epitaxial regions arranged alternately along a first direction, adjacent first doped regions and epitaxial regions forming a super junction structure, wherein the first direction is perpendicular to the thickness direction of the substrate; a second doped region located in the epitaxial layer, and in a second direction, the second doped region is located on the side of the super junction structure away from the substrate, the second direction being the thickness direction of the substrate; a third doped region located in the epitaxial layer, and in the second direction, the third doped region is located on the part of the surface of the second doped region away from the super junction structure, the doping type of the first doped region, the doping type of the second doped region and the doping type of the third doped region are the same; a first metal layer located on the side of the substrate away from the epitaxial layer; a second metal layer located on the side of the epitaxial layer away from the substrate.

[0007] Further, in a third direction, the first doped regions in two adjacent super junction structures are staggered.

[0008] Further, in the third direction, a minimum distance between two first doped regions of two adjacent super junction structures is a first width, a width of the first doped region is a second width, and the first width is greater than the second width.

[0009] Further, a width of the second doped region is greater than a width of the first doped region in the first direction.

[0010] Further, a thickness of the first doped region is greater than a thickness of the second doped region and a thickness of the third doped region, respectively.

[0011] Further, the third doped region includes at least two doped parts, and any two adjacent doped parts have a spacing therebetween.

[0012] Further, a normal projection of the third doped region on the second doped region is a first projection, a normal projection of the first doped region on the second doped region is a second projection, and the first projection and the second projection do not overlap.

[0013] Further, at least two of a doping concentration of the first doped region, a doping concentration of the second doped region, and a doping concentration of the third doped region are different.

[0014] Further, the second metal layer includes an ohmic metal layer and a Schottky metal layer, wherein the ohmic metal layer includes a plurality of ohmic metal parts having a spacing, the ohmic metal parts are respectively located on a side surface of the third doped region away from the second doped region, and the Schottky metal layer is located on the side surface of the third doped region away from the second doped region and a surface of the ohmic metal layer away from the epitaxial layer. In order to achieve the above-mentioned purpose, according to another aspect of the present application, a preparation method of a power semiconductor device is provided, including: providing a substrate; forming a first preliminary epitaxial layer on one side of the substrate, and processing part of the first preliminary epitaxial layer to obtain a first doped region, and the remaining first preliminary epitaxial layer forms an epitaxial region, and adjacent first doped regions and epitaxial regions form a super junction structure, wherein one end of the first doped region is in contact with the substrate, and a doping type of the first doped region and a doping type of the epitaxial region are different; forming a second doped region on a side of the first doped region away from the substrate; forming a third doped region on a side of the second doped region away from the first doped region to obtain an epitaxial layer, wherein a doping type of the first doped region, a doping type of the second doped region, and a doping type of the third doped region are the same; forming a first metal layer on a side of the substrate away from the epitaxial layer; and forming a second metal layer on a side of the epitaxial layer away from the substrate.

[0015] The technical scheme of the application provides a power semiconductor device, the epitaxial layer of the power semiconductor device comprises a first doped region, a second doped region and a third doped region which are sequentially stacked along a second direction, compared with the power semiconductor device comprising only the third doped region in the prior art, the size and area of the doped region are increased, in the case of inrush current, the power semiconductor device enters a bipolar conduction mode, the injection efficiency of the bipolar conduction is proportional to the area of the doped region, therefore, the injection efficiency of the power semiconductor device can be improved due to the increase of the area of the doped region, and the problem of the non-ideal injection efficiency of the power semiconductor device is solved. BRIEF DESCRIPTION OF DRAWINGS

[0016] The accompanying drawings, which form a part of the specification, are included to provide a further understanding of the application and are incorporated herein in conjunction with the description of the application. The embodiments of the present application, and its description, are used to explain the present application and are not intended to limit the present application. In the drawings:

[0017] Figure 1 A structure schematic diagram of a power semiconductor device provided by an embodiment of the application is shown;

[0018] Figure 2 A top view of Figure 1 is shown;

[0019] Figure 3 A sectional view obtained along the BB' direction of Figure 2 is shown;

[0020] Figure 4 A structure schematic diagram of another power semiconductor device provided by an embodiment of the application is shown;

[0021] Figure 5 A structure schematic diagram of still another power semiconductor device provided by an embodiment of the application is shown;

[0022] Figure 6 A structure schematic diagram of yet another power semiconductor device provided by an embodiment of the application is shown;

[0023] Figure 7 A structure schematic diagram of another power semiconductor device provided by an embodiment of the application is shown;

[0024] Figure 8 A top view of Figure 7 is shown;

[0025] Figure 9 A sectional view obtained along the BB' direction of Figure 8 is shown;

[0026] Figure 10A flow chart of a method for manufacturing a power semiconductor device is shown according to an embodiment of the present application;

[0027] Figure 11 A structure diagram corresponding to a specific flow of a method for manufacturing a power semiconductor device is shown according to an embodiment of the present application;

[0028] Figure 12 A structure diagram corresponding to a specific flow of another method for manufacturing a power semiconductor device is shown according to an embodiment of the present application.

[0029] Among the above figures, the following reference signs are included:

[0030] 10, substrate; 11, epitaxial layer; 12, super junction structure; 13, first doped region; 14, epitaxial region; 132, second doped region; 133, third doped region; 15, first metal layer; 16, second metal layer; 161, ohmic metal layer; 162, Schottky metal layer; 111, first preliminary epitaxial layer; 112, second preliminary epitaxial layer; 113, first recess; 114, first preliminary portion; 115, third preliminary epitaxial layer; 116, second recess; 117, fourth preliminary epitaxial layer; 118, third recess. DETAILED DESCRIPTION

[0031] It should be noted that the following detailed description is merely exemplary and is intended to provide further description of the present application. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

[0032] It is to be understood that the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. It should be noted that the terms "comprises", "comprising", "includes", "including", "contains", "containing" and the like are used in the sense of "including but not limited to".

[0033] It should be noted that the terms "first", "second", and the like in the description and in the claims of the present application and the above-described accompanying drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the application described herein can be implemented. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to only those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0034] It should be understood that when an element (such as a layer, film, region, or substrate) is described as "on" another element, it can be directly on the other element, or an intervening element can also be present. Also, in the specification and claims, when an element is described as "connected" to another element, it can be "directly connected" to the other element, or "connected" to the other element through a third element.

[0035] As introduced in the background, the injection efficiency of the power semiconductor device in the prior art is not ideal, to solve the above problems, the embodiment of the present application provides a power semiconductor device and a preparation method of the power semiconductor device.

[0036] The technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the accompanying drawings in the embodiments of the present application.

[0037] Figures 1 to 9 is a structural diagram of the power semiconductor device according to the embodiment of the present application. As shown in Figures 1 to 9 , it comprises:

[0038] a substrate 10;

[0039] Specifically, the material of the substrate can be silicon, silicon carbide, gallium nitride, diamond, gallium arsenide, sapphire, etc.

[0040] an epitaxial layer 11 located on one side of the substrate 10, the epitaxial layer 11 comprising first doped regions 13 and epitaxial regions 14 arranged alternately along a first direction D1, adjacent first doped regions 13 and epitaxial regions 14 forming super junction structures 12, wherein the first direction D1 is perpendicular to the thickness direction of the substrate 10;

[0041] In practical applications, the epitaxial layer can be a single-layer structure or a multi-layer structure. The super-junction technology is a special structure in the design of power semiconductor devices, mainly used to reduce the on-resistance of the device while maintaining or improving the breakdown voltage. The core of the super-junction technology is to form an alternating arrangement of N-type doped regions and P-type doped regions inside the power semiconductor device, which achieves charge balance, thereby significantly reducing the resistance of the drift region without reducing the breakdown voltage. The second doped region 132 is located in the epitaxial layer 11 and in the second direction D2, which is the thickness direction of the substrate 10, the second doped region 132 is located on the side of the super-junction structure 12 away from the substrate 10;

[0042] The third doped region 133 is located in the epitaxial layer 11 and in the second direction D2, which is the thickness direction of the substrate 10, the third doped region 133 is located on the part of the surface of the second doped region 132 away from the super-junction structure 12, and the doping type of the first doped region 13, the doping type of the second doped region 132 and the doping type of the third doped region 133 are the same;

[0043] The present application does not limit the width, depth and doping concentration of the first doped region, the second doped region and the third doped region, and those skilled in the art can set the width, depth and doping concentration of the first doped region, the second doped region and the third doped region according to actual needs. The doping type of the epitaxial layer and the doping type of the substrate are the same, and the doping type of the first doped region and the doping type of the epitaxial region are different. For example: the doping type of the substrate and the epitaxial layer is N-type, the doping type of the first doped region is P-type, and the doping type of the first doped region, the second doped region and the third doped region is also P-type.

[0044] The first metal layer 15 is located on the side of the substrate 10 away from the epitaxial layer 11;

[0045] Specifically, the material of the first metal layer can be at least one of Ni, Ti, Al, Cu and Ag.

[0046] The second metal layer 16 is located on the side of the epitaxial layer 11 away from the substrate 10.

[0047] In practical applications, the material of the second metal layer can be a single-layer structure or a multi-layer structure. In the case where the second metal layer is a single-layer structure, it can be a Schottky metal layer. In the case where the second metal layer is a multi-layer structure, it can be a double-layer structure of an ohmic contact metal layer and a Schottky metal layer. The material of the second metal layer can be at least one of Ti, Ni, Al and Cu. In addition, the power semiconductor device of the present application can be a diode, a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor field effect transistor (MOSFET), a thyristor and a gate-commutated thyristor (IGCT), etc., wherein the diode can be a fast recovery diode, a Schottky diode and a super junction diode, the MOSFET includes a low-voltage MOSFET and a high-voltage MOSFET; the thyristor includes a gate-controlled thyristor and a power diode.

[0048] Through this embodiment, a power semiconductor device is provided, wherein the epitaxial layer of the power semiconductor device includes a first doped region, a second doped region, and a third doped region stacked in sequence along a second direction. Compared with the power semiconductor device of the prior art that only includes the third doped region, the size and area of ​​the doped region are increased. Under the condition of surge current, the power semiconductor device enters a bipolar conduction mode. The injection efficiency of bipolar conduction is proportional to the area of ​​the doped region. Therefore, due to the increase in the area of ​​the doped region, the injection efficiency of the power semiconductor device can be improved due to the increase in the area of ​​the doped region, thus solving the problem of unsatisfactory injection efficiency of the power semiconductor device. In addition, under bipolar conduction, due to minority carrier injection, when the device exits the bipolar conduction mode, a large tail current will exist, and the turn-off time will be slow. The doped region extracts minority carriers from the epitaxial layer of the device. Due to the large area of ​​the doped region, the tail current of the power semiconductor device can be reduced, and the extraction efficiency can be higher, and the turn-off speed can be faster, thereby solving the technical problem of large tail current and slow turn-off after the power semiconductor device exits the bipolar conduction mode.

[0049] In the specific implementation process, Figure 2 As shown, in a third direction D3, the first doped regions 13 in the super junction structure 12 of two adjacent first doped regions are arranged in an alternating pattern, wherein the third direction D3 is perpendicular to the first direction and the second direction. Throughout the power semiconductor device, the alternating arrangement of the first doped regions 13 in the super junction structure 12 creates a checkerboard-like pattern, which makes the first doped regions 13 more evenly distributed, thereby improving the uniformity of charge distribution and further enhancing the stability of the power semiconductor device.

[0050] Figure 2 yes Figure 1 A top view ofFigure 1 is a sectional view taken along the AA' direction of Figure 2 Figure 3 is a sectional view taken along the BB' direction of Figure 2 Figure 2 As shown in the plan view, the second doped region 132 and the third doped region 133 overlap.

[0051] In practical applications, the shapes of the first doped region, the second doped region, and the third doped region can not be limited to the bar shape in the above embodiment, but can also be other shapes such as hexagon and circle. Figure 2

[0052] In order to further simplify the process flow of the power semiconductor device, in the third direction, the minimum distance between the first doped regions of two adjacent super junction structures is a first width, and the width of the first doped region is a second width, the first width being greater than the second width.

[0053] In the above implementation, the first width being greater than the second width means that the size ratio of the first doped region in the plan view is less than that of the remaining structure except the first doped region.

[0054] In some embodiments, the width of the second doped region in the first direction is greater than the width of the first doped region. This arrangement can further increase the area of the second doped region and increase the size of the surge current flow area, thereby further enhancing the ability of the power semiconductor device to withstand surge current.

[0055] Specifically, in the first direction, the width of the third doped region can be greater than or equal to the width of the second doped region, or less than the width of the second doped region. In the case where the width of the third doped region is greater than or equal to the width of the second doped region, the ability of the power semiconductor device to withstand surge current can be further enhanced.

[0056] In some embodiments, the thickness of the first doped region is greater than the thickness of the second doped region and the thickness of the third doped region, respectively. This arrangement can further increase the area of the first doped region and increase the size of the surge current flow area, thereby further enhancing the ability of the power semiconductor device to withstand surge current.

[0057] In the above implementation, the greater the thickness of the third doped region, the greater the distance of the second doped region from the second metal layer. That is, the thickness of the third doped region affects the JFET effect, thereby affecting the size of the on-resistance.

[0058] In another specific embodiment, as shown in Figure 4 and Figure 5 ​​​As shown, the super junction structure 12 does not penetrate the entire epitaxial layer 11, but is located on the side of the epitaxial layer 11 away from the substrate 10, or on the side of the epitaxial layer 11 close to the substrate 10, forming a semi-super junction structure. Figure 4 As shown, the super junction structure 12 is located on the side of the epitaxial layer 11 away from the substrate 10, the surface of the first doped region 13 close to the substrate 10 is spaced apart from the substrate 10, and the surface of the third doped region 133 away from the substrate 10 is flush with the surface of the epitaxial layer 11 away from the substrate 10. Figure 5 As shown, the super junction structure 12 is located on the side of the epitaxial layer 11 close to the substrate 10, the surface of the first doping region 13 close to the substrate 10 is flush with the surface of the epitaxial layer 11 close to the substrate 10, and the surface of the third doping region 133 away from the substrate 10 is spaced apart from the surface of the epitaxial layer 11 away from the substrate 10.

[0059] In some embodiments, as Figure 6 As shown, the third doping region 133 includes at least two doping portions, with a gap between any two adjacent doping portions. As the area of ​​the doping region increases, when the third doping region 133 is relatively large, the distance between two adjacent third doping regions 133 becomes narrower, potentially leading to an increase in forward voltage. Since the third doping region 133 includes two doping portions separated by a gap, the gap can serve as an overcurrent location, preventing an increase in forward voltage, thereby further improving the stability of the power semiconductor device.

[0060] Specifically, the number of the doped parts is not limited to Figure 6 There may be two or more of the above mentioned doping parts, as long as there is a gap between the two adjacent doping parts. The present application does not limit the width of the above mentioned gap, and those skilled in the art can set the width of the gap according to actual conditions.

[0061] like Figure 6 As shown, the orthographic projection of the third doped region on the second doped region is a first projection, and the orthographic projection of the first doped region on the second doped region is a second projection, and the first projection and the second projection do not overlap. In other words, a portion of the third doped region that overlaps with the second projection is separated, and this area can be used as an overcurrent location to prevent an increase in forward voltage, thereby further improving the stability of the power semiconductor device.

[0062] In some embodiments, at least two of the doping concentrations of the first doping region, the second doping region, and the third doping region are different. Setting different doping concentrations for the first doping region, the second doping region, and the third doping region can further balance the relationship between the breakdown voltage and on-resistance of the power semiconductor device.

[0063] Specifically, the first doping region, the second doping region, and the third doping region have different doping concentrations, which can shorten the PN junction length and improve the withstand voltage capability of the power semiconductor device.

[0064] like Figures 7 to 9 As shown, the second metal layer 16 includes an ohmic metal layer 161 and a Schottky metal layer 162. The ohmic metal layer 161 includes a plurality of spaced-apart ohmic metal portions. The ohmic metal portions are located on the surface of the third doping region 133 away from the second doping region 132. The Schottky metal layer 162 is located on the surface of the third doping region 133 away from the second doping region 132 and on the surface of the ohmic metal layer 161 away from the epitaxial layer 11. Selectively depositing an ohmic contact metal on the surface of the third doping region 133 away from the second doping region 132 can further enhance the surge resistance of the power device.

[0065] Figure 8 yes Figure 7 A top view of Figure 7 It is along Figure 8 The cross-sectional view obtained in the AA` direction, Figure 9 It is along Figure 8 A cross-sectional view taken along the BB' direction is shown. Specifically, the ohmic metal layer 161 can form an ohmic contact with the third doped region 133. An ohmic contact refers to a low-resistance, nearly linear current-voltage relationship formed when a metal contacts a semiconductor. The ohmic contact metal layer provides a low-resistance path, allowing current to flow smoothly through the semiconductor material without a significant voltage drop. This metal layer forms a good match with the semiconductor material, ensuring that there are no significant potential barriers at the contact point that hinder current flow. The ohmic metal layer 161 can be made of any of nickel (Ni), aluminum (Al), molybdenum (Mo), and titanium (Ti). In silicon carbide devices, Ni or Ti can be used as the ohmic contact material; in silicon devices, Al or Ti alloys can be used as the ohmic contact material. The Schottky metal layer 162 can form a Schottky contact with the third doped region 133. A Schottky contact is a non-rectifying or minimally rectifying contact formed when a metal contacts a semiconductor. The metal-semiconductor barrier formed at the contact is called a Schottky barrier. The purpose of Schottky metal layer 162 is to utilize this barrier property to form a fast-response, low-forward-voltage-drop diode or other related component. Materials for Schottky metal layer 162 may include platinum (Pt), tungsten (W), titanium (Ti), and palladium (Pd).

[0066] The present invention also provides a method for preparing a power semiconductor device. Figure 10is a flowchart of a method for manufacturing a power semiconductor device according to an embodiment of the present application. As shown in Figure 10 The method comprises the following steps.

[0067] In step S201, a substrate is provided.

[0068] Specifically, the material of the substrate can be silicon, silicon carbide, gallium nitride, diamond, gallium arsenide, sapphire, etc.

[0069] In step S202, a first preliminary epitaxial layer is formed on one side of the substrate, and a first doped region is obtained by processing part of the first preliminary epitaxial layer. The remaining first preliminary epitaxial layer forms an epitaxial region. The first doped region and the epitaxial region adjacent thereto form a super-junction structure. One end of the first doped region is in contact with the substrate, and the doping type of the first doped region is different from that of the epitaxial region.

[0070] In step S203, a second doped region is formed on the side of the first doped region away from the substrate.

[0071] In step S204, a third doped region is formed on the side of the second doped region away from the first doped region, thereby obtaining an epitaxial layer. The doping type of the first doped region, the doping type of the second doped region, and the doping type of the third doped region are the same.

[0072] In actual applications, the epitaxial layer can be a single-layer structure or a multi-layer structure. The super-junction technology is a special structure in the design of power semiconductor devices, mainly used to reduce the on-resistance of the device while maintaining or improving the breakdown voltage. The core of the super-junction technology is to form an alternating arrangement of N-type doped regions and P-type doped regions inside the power semiconductor device, thereby achieving charge balance, which can significantly reduce the resistance of the drift region without reducing the breakdown voltage.

[0073] In step S205, a first metal layer is formed on the side of the substrate away from the epitaxial layer.

[0074] Specifically, the material of the first metal layer can be at least one of Ni, Ti, Al, Cu, and Ag.

[0075] In step S206, a second metal layer is formed on the side of the epitaxial layer away from the substrate.

[0076] In practical applications, the material of the second metal layer can be a single-layer structure or a multi-layer structure. When the second metal layer is a single-layer structure, it can be a Schottky metal layer. When the second metal layer is a multi-layer structure, it can be a double-layer structure of an ohmic contact metal layer and a Schottky metal layer. The material of the second metal layer can be at least one of Ti, Ni, Al, and Cu.

[0077] By the embodiment, a preparation method of a power semiconductor device is provided. The epitaxial layer of the power semiconductor device includes a first doped region, a second doped region, and a third doped region arranged in sequence along a second direction. Compared with the power semiconductor device including only the third doped region in the prior art, the size and area of the doped region are increased. In the case of a surge current, the power semiconductor device enters a bipolar conduction mode. The injection efficiency of the bipolar conduction is proportional to the area of the doped region. Therefore, the injection efficiency of the power semiconductor device can be improved due to the increase of the area of the doped region, and the problem of the ideal injection efficiency of the power semiconductor device is solved. In addition, under the bipolar conduction, due to the injection of minority carriers, the device exits the bipolar conduction mode again, and there is a large tail current, and the turn-off time is slow. The first doped region extracts the minority carriers from the epitaxial layer of the device. Due to the large area of the first doped region, the tail current of the power semiconductor device can be reduced, the extraction efficiency can be higher, and the turn-off speed can be faster, thereby solving the technical problems of large tail current and slow turn-off after the power semiconductor device exits the bipolar conduction mode.

[0078] In practical applications, the first doped region, the second doped region, and the third doped region can be prepared by implantation or by trench etching and backfilling. The formation methods of the first doped region, the second doped region, and the third doped region can be the same or different.

[0079] For example, by trench etching and backfilling, the embodiment of the application further provides a preparation method of a power semiconductor device, which includes:

[0080] In step S301, a substrate 10 is provided, and a structure as shown in Figure 11 (a) is obtained.

[0081] In step S302, a first preliminary epitaxial layer 111 is formed on one side of the substrate 10, and a structure as shown in Figure 11 (b) is obtained. Part of the first preliminary epitaxial layer 111 is removed, and a second preliminary epitaxial layer 112 having a plurality of first grooves 113 arranged along a first direction D1 is obtained. Adjacent two first grooves 113 have a spacing, and the first direction D1 is perpendicular to the thickness direction of the substrate 10, and a structure as shown in Figure 11 (c) is obtained.

[0082] Step S303, forming a first preliminary portion 114 in each of the first grooves 113, obtaining a structure as shown in FIG. 11B, and removing part of the first preliminary portion 114 and part of the second preliminary epitaxial layer 112, obtaining a third preliminary epitaxial layer 115 having a plurality of second grooves 116 arranged along the first direction D1, adjacent two of the second grooves 116 having a spacing therebetween, and the remaining first preliminary portion 114 forming a first doped region 13, obtaining a structure as shown in FIG. 11C; Figure 11 (d) and removing part of the first preliminary portion 114 and part of the second preliminary epitaxial layer 112, obtaining a third preliminary epitaxial layer 115 having a plurality of second grooves 116 arranged along the first direction D1, adjacent two of the second grooves 116 having a spacing therebetween, and the remaining first preliminary portion 114 forming a first doped region 13, obtaining a structure as shown in FIG. 11C; Figure 11 (e) and removing part of the first preliminary portion 114 and part of the second preliminary epitaxial layer 112, obtaining a third preliminary epitaxial layer 115 having a plurality of second grooves 116 arranged along the first direction D1, adjacent two of the second grooves 116 having a spacing therebetween, and the remaining first preliminary portion 114 forming a first doped region 13, obtaining a structure as shown in FIG. 11C; (f) and removing part of the first preliminary portion 114 and part of the second preliminary epitaxial layer 112, obtaining a third preliminary epitaxial layer 115 having a plurality of second grooves 116 arranged along the first direction D1, adjacent two of the second grooves 116 having a spacing therebetween, and the remaining first preliminary portion 114 forming a first doped region 13, obtaining a structure as shown in FIG. 11C;

[0083] (f) and removing part of the first preliminary portion 114 and part of the second preliminary epitaxial layer 112, obtaining a third preliminary epitaxial layer 115 having a plurality of second grooves 116 arranged along the first direction D1, adjacent two of the second grooves 116 having a spacing therebetween, and the remaining first preliminary portion 114 forming a first doped region 13, obtaining a structure as shown in FIG. 11C; Figure 11 (f) and removing part of the first preliminary portion 114 and part of the second preliminary epitaxial layer 112, obtaining a third preliminary epitaxial layer 115 having a plurality of second grooves 116 arranged along the first direction D1, adjacent two of the second grooves 116 having a spacing therebetween, and the remaining first preliminary portion 114 forming a first doped region 13, obtaining a structure as shown in FIG. 11C; (f) and removing part of the first preliminary portion 114 and part of the second preliminary epitaxial layer 112, obtaining a third preliminary epitaxial layer 115 having a plurality of second grooves 116 arranged along the first direction D1, adjacent two of the second grooves 116 having a spacing therebetween, and the remaining first preliminary portion 114 forming a first doped region 13, obtaining a structure as shown in FIG. 11C;

[0084] (f) and removing part of the first preliminary portion 114 and part of the second preliminary epitaxial layer 112, obtaining a third preliminary epitaxial layer 115 having a plurality of second grooves 116 arranged along the first direction D1, adjacent two of the second grooves 116 having a spacing therebetween, and the remaining first preliminary portion 114 forming a first doped region 13, obtaining a structure as shown in FIG. 11C; Figure 11 (g) and removing part of the first preliminary portion 114 and part of the second preliminary epitaxial layer 112, obtaining a third preliminary epitaxial layer 115 having a plurality of second grooves 116 arranged along the first direction D1, adjacent two of the second grooves 116 having a spacing therebetween, and the remaining first preliminary portion 114 forming a first doped region 13, obtaining a structure as shown in FIG. 11C; (g) and removing part of the first preliminary portion 114 and part of the second preliminary epitaxial layer 112, obtaining a third preliminary epitaxial layer 115 having a plurality of second grooves 116 arranged along the first direction D1, adjacent two of the second grooves 116 having a spacing therebetween, and the remaining first preliminary portion 114 forming a first doped region 13, obtaining a structure as shown in FIG. 11C;

[0085] (g) and removing part of the first preliminary portion 114 and part of the second preliminary epitaxial layer 112, obtaining a third preliminary epitaxial layer 115 having a plurality of second grooves 116 arranged along the first direction D1, adjacent two of the second grooves 116 having a spacing therebetween, and the remaining first preliminary portion 114 forming a first doped region 13, obtaining a structure as shown in FIG. 11C; Figure 11 (g) and removing part of the first preliminary portion 114 and part of the second preliminary epitaxial layer 112, obtaining a third preliminary epitaxial layer 115 having a plurality of second grooves 116 arranged along the first direction D1, adjacent two of the second grooves 116 having a spacing therebetween, and the remaining first preliminary portion 114 forming a first doped region 13, obtaining a structure as shown in FIG. 11C; (g) and removing part of the first preliminary portion 114 and part of the second preliminary epitaxial layer 112, obtaining a third preliminary epitaxial layer 115 having a plurality of second grooves 116 arranged along the first direction D1, adjacent two of the second grooves 116 having a spacing therebetween, and the remaining first preliminary portion 114 forming a first doped region 13, obtaining a structure as shown in FIG. 11C;

[0086] (g) and removing part of the first preliminary portion 114 and part of the second preliminary epitaxial layer 112, obtaining a third preliminary epitaxial layer 115 having a plurality of second grooves 116 arranged along the first direction D1, adjacent two of the second grooves 116 having a spacing therebetween, and the remaining first preliminary portion 114 forming a first doped region 13, obtaining a structure as shown in FIG. 11C; Figure 11 (i) and forming a second metal layer 16 on a side of the epitaxial layer 11 away from the substrate 10, obtaining a structure as shown in FIG. 11H. (i) and forming a second metal layer 16 on a side of the epitaxial layer 11 away from the substrate 10, obtaining a structure as shown in FIG. 11H.

[0087] (i) and forming a second metal layer 16 on a side of the epitaxial layer 11 away from the substrate 10, obtaining a structure as shown in FIG. 11H. Figure 6 (i) and forming a second metal layer 16 on a side of the epitaxial layer 11 away from the substrate 10, obtaining a structure as shown in FIG. 11H. (i) and forming a second metal layer 16 on a side of the epitaxial layer 11 away from the substrate 10, obtaining a structure as shown in FIG. 11H.

[0088] In an injection manner, the application further provides a preparation method of a power semiconductor device, the method comprising:

[0089] Step S401, providing a substrate 10, obtaining a structure as shown in FIG. 11A; Figure 12 (a) and removing part of the first preliminary portion 114 and part of the second preliminary epitaxial layer 112, obtaining a third preliminary epitaxial layer 115 having a plurality of second grooves 116 arranged along the first direction D1, adjacent two of the second grooves 116 having a spacing therebetween, and the remaining first preliminary portion 114 forming a first doped region 13, obtaining a structure as shown in FIG. 11C; (a) and removing part of the first preliminary portion 114 and part of the second preliminary epitaxial layer 112, obtaining a third preliminary epitaxial layer 115 having a plurality of second grooves 116 arranged along the first direction D1, adjacent two of the second grooves 116 having a spacing therebetween, and the remaining first preliminary portion 114 forming a first doped region 13, obtaining a structure as shown in FIG. 11C;

[0090] Step S402, first epitaxial growth is performed on one side of the substrate 10 to form a first preliminary epitaxial layer 111, obtaining a structure as shown in Figure 12 (b); and ion implantation is performed on the first preliminary epitaxial layer 111 to obtain a first preliminary part 114, and the remaining first preliminary epitaxial layer 111 forms a second preliminary epitaxial layer 112, obtaining a structure as shown in Figure 12 (c);

[0091] Step S403, ion implantation is performed on the second preliminary epitaxial layer 112 and the first preliminary part 114 to form a second doped region 132, the remaining first preliminary part 114 forms a first doped region 13, and the remaining second preliminary epitaxial layer 112 forms a third preliminary epitaxial layer 115, obtaining a structure as shown in Figure 12 (d);

[0092] Step S404, second epitaxial growth is performed on the second doped region 132 away from the surface of the substrate 10 and the third preliminary epitaxial layer 115 away from the surface of the substrate 10 to form a fourth preliminary epitaxial layer 117, and a certain thickness is ensured by epitaxial growth, so that the second doped region 132 and the surface of the fourth preliminary epitaxial layer 117 away from the second doped region 132 are at a certain distance, obtaining a structure as shown in Figure 12 (e);

[0093] Step S405, surface particle region patterning and ion implantation are performed on the fourth preliminary epitaxial layer 117 to form a third doped region 133, obtaining an epitaxial layer 11, and the remaining third preliminary epitaxial layer 115 forms an epitaxial region 14, and the first doped region 13 and the epitaxial region 14 adjacent to each other form a super-junction structure 12, obtaining a structure as shown in Figure 12 (f);

[0094] Step S405, a first metal layer 15 is formed on the substrate 10 away from the epitaxial layer 11, obtaining a structure as shown in Figure 12 (g);

[0095] Step S408, a second metal layer 16 is formed on the epitaxial layer 11 away from the substrate 10, obtaining a structure as shown in Figure 6 .

[0096] From the above description, it can be seen that the above-mentioned embodiments of the present application achieve the following technical effects:

[0097] 1) The power semiconductor device of the present application has an epitaxial layer including a first doped region, a second doped region, and a third doped region stacked in sequence along a second direction. Compared with the power semiconductor device in the prior art that only includes a third doped region, the size and area of ​​the doped region are increased. In the case of a surge current, the power semiconductor device enters a bipolar conduction mode. The injection efficiency of the bipolar conduction is proportional to the area of ​​the doped region. Therefore, due to the increase in the area of ​​the doped region, this solution can improve the injection efficiency of the power semiconductor device, solving the problem of unsatisfactory injection efficiency of the power semiconductor device. In addition, under bipolar conduction, due to minority carrier injection, when the device exits the bipolar conduction mode, there will be a large tail current, and the turn-off time will be slow. The superjunction structure will extract the minority carriers from the epitaxial layer of the device. Due to the large area of ​​the superjunction structure, the tail current of the power semiconductor device can be reduced, and the extraction efficiency can be higher and the turn-off speed can be faster, thereby solving the technical problem of large tail current and slow turn-off after the power semiconductor device exits the bipolar conduction mode.

[0098] 2) In the preparation method of the power semiconductor device of the present application, the epitaxial layer of the power semiconductor device includes a first doping region, a second doping region, and a third doping region stacked in sequence along the second direction. Compared with the power semiconductor device in the prior art that only includes the third doping region, the size and area of ​​the doping region are increased. In the case of a surge current, the power semiconductor device enters a bipolar conduction mode. The injection efficiency of the bipolar conduction is proportional to the area of ​​the doping region. Therefore, due to the increase in the area of ​​the doping region, this solution can improve the injection efficiency of the power semiconductor device, solving the problem of unsatisfactory injection efficiency of the power semiconductor device. In addition, under bipolar conduction, due to minority carrier injection, when the device exits the bipolar conduction mode, there will be a large tail current, and the turn-off time will be slow. The superjunction structure will extract the minority carriers from the epitaxial layer of the device. Due to the large area of ​​the superjunction structure, the tail current of the power semiconductor device can be reduced, and the extraction efficiency can be higher and the turn-off speed can be faster, thereby solving the technical problem of large tail current and slow turn-off after the power semiconductor device exits the bipolar conduction mode.

[0099] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0100] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A power semiconductor device, characterized by, The power semiconductor device comprises: a substrate; an epitaxial layer located on one side of the substrate, the epitaxial layer comprising first doped regions and epitaxial regions arranged alternately along a first direction, adjacent first doped regions and epitaxial regions forming a super junction structure, wherein the first direction is perpendicular to the thickness direction of the substrate; a second doped region located on the epitaxial layer and located on the side of the super junction structure away from the substrate along a second direction, the second direction being the thickness direction of the substrate; a third doped region located on the epitaxial layer and located on the surface of the second doped region away from the super junction structure along the second direction, the doping type of the first doped region, the doping type of the second doped region and the doping type of the third doped region being the same; a first metal layer located on the side of the substrate away from the epitaxial layer; a second metal layer located on the side of the epitaxial layer away from the substrate.

2. The power semiconductor device according to claim 1, characterized in that, In a third direction, the first doped regions in adjacent two super junction structures are staggered, wherein the third direction is perpendicular to the first direction and the second direction respectively.

3. The power semiconductor device according to claim 2, characterized in that, In the third direction, the minimum distance between the first doped regions of adjacent two super junction structures is a first width, and the width of the first doped region is a second width, the first width being greater than the second width.

4. The power semiconductor device of claim 1, wherein, The width of the second doped region along the first direction is greater than the width of the first doped region.

5. The power semiconductor device of claim 1, wherein, The thickness of the first doped region is greater than the thickness of the second doped region and the thickness of the third doped region respectively.

6. The power semiconductor device of claim 1, wherein, The third doped region comprises at least two doped parts, and any two adjacent doped parts have a spacing therebetween.

7. The power semiconductor device of claim 1, wherein, The orthogonal projection of the third doped region on the second doped region is a first projection, and the orthogonal projection of the first doped region on the second doped region is a second projection, the first projection and the second projection not overlapping.

8. The power semiconductor device of claim 1, wherein, At least two of the doping concentration of the first doped region, the doping concentration of the second doped region and the doping concentration of the third doped region are different.

9. The power semiconductor device of claim 1, wherein, The second metal layer comprises an ohmic metal layer and a Schottky metal layer, wherein the ohmic metal layer comprises a plurality of ohmic metal parts with a spacing, the ohmic metal parts being located on the side surface of the third doped region away from the second doped region respectively, and the Schottky metal layer being located on the side surface of the third doped region away from the second doped region and the surface of the ohmic metal layer away from the epitaxial layer.

10. A method of manufacturing a power semiconductor device, characterized by, The method for manufacturing the power semiconductor device of any one of claims 1 to 9 comprises: providing a substrate; forming a first preliminary epitaxial layer on one side of the substrate, and processing part of the first preliminary epitaxial layer to obtain a first doped region, the remaining first preliminary epitaxial layer forming an epitaxial region, adjacent first doped regions and epitaxial regions forming a super junction structure, wherein one end of the first doped region is in contact with the substrate, and the doping type of the first doped region is different from the doping type of the epitaxial region; forming a second doped region on the side of the first doped region away from the substrate; A third doped region is formed on a side of the second doped region away from the first doped region, to obtain an epitaxial layer, wherein the doping type of the first doped region, the doping type of the second doped region, and the doping type of the third doped region are the same; A first metal layer is formed on a side of the substrate away from the epitaxial layer; A second metal layer is formed on a side of the epitaxial layer away from the substrate.

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