Gate trench power semiconductor devices with self-aligned trench shielding regions and related methods

Abstract

A method of forming a semiconductor device includes forming a first mask including a longitudinally extending first opening on a semiconductor layer structure, the first opening having a first width. Spacers are formed on sidewalls of the first mask exposed by the first opening to form a second mask, where the first mask and the second mask include a mask structure having a longitudinally extending second opening having a second width less than the first width. A dopant is implanted through the second opening to form an implanted region in the semiconductor layer structure. The spacers are at least partially removed from the sidewalls of the first mask to form a third opening in the mask structure. The semiconductor layer structure is then etched using the mask structure as an etch mask to form a gate trench in the semiconductor layer structure below the third opening.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to U.S. Patent Application Serial No. 18 / 093,343, filed January 5, 2023, the entirety of which is incorporated by reference herein as if set forth in its entirety. TECHNICAL FIELD

[0003] The present invention relates to power semiconductor devices, and more particularly to power semiconductor devices having gate trenches and methods of manufacturing the same. BACKGROUND

[0004] A metal-insulator-semiconductor field effect transistor (“MISFET”) is a well-known type of semiconductor transistor that can be used as a switching device. A MISFET is a three-terminal device having gate, drain, and source terminals and a semiconductor body. The semiconductor body is referred to herein as a “semiconductor layer structure.” Source and drain regions are formed in the semiconductor layer structure, separated by a channel region, and a gate electrode (which can act as or be electrically connected to the gate terminal) is disposed adjacent to the channel region and separated from the channel region by a thin insulating layer. A MISFET can be turned on or off by setting a bias voltage applied to the gate electrode above or below a threshold value. When the MISFET is turned on (i.e., is in an “on state”), current is conducted through the channel region of the MISFET between the source and drain regions. When the bias voltage falls below the threshold level, current ceases to be conducted through the channel region.

[0005] An n-type MISFET has source and drain regions of n-type (electron) conductivity and a channel of p-type (hole) conductivity. Thus, an n-type MISFET has an “n-p-n” design. An n-type MISFET turns on when a gate bias voltage is applied to the gate electrode sufficient to create a conductive n-type inversion layer in the p-type channel region that electrically connects the n-type source and drain regions, thereby allowing majority carrier conduction therebetween. A p-type MISFET has a “p-n-p” design and turns on when a gate bias voltage is applied to the gate electrode sufficient to create a conductive p-type inversion layer in the n-type channel region that electrically connects the p-type source and drain regions. In this document, the terms “first conductivity type” and “second conductivity type” are used to indicate n-type or p-type, where the first and second conductivity types are different. Thus, if a first region of a device has a first conductivity type and a second region of the device has a second conductivity type, then this means either the first region has n-type conductivity and the second region has p-type conductivity, or the first region has p-type conductivity and the second region has n-type conductivity.

[0006] As noted above, the gate electrode of a MISFET is separated from the channel region by a thin dielectric layer, which is referred to as the gate dielectric layer. Typically, power MISFETs implement the thin gate dielectric layer using an oxide layer, such as a silicon oxide layer. Power MISFETs that include an oxide gate dielectric layer are referred to as metal-oxide-semiconductor field-effect transistors ("MOSFETs"), and the gate dielectric layer is referred to as the gate oxide layer. Because oxide gate dielectric layers are almost always used due to their superior characteristics in most applications, implementations as gate oxide layers, the discussion herein will focus on MOSFETs rather than MISFETs. However, it will be recognized that the techniques described herein according to embodiments of the present application are equally applicable to devices having gate dielectric layers formed of materials other than oxides.

[0007] Because the gate electrode of a MOSFET is insulated from the channel region by the gate oxide layer, minimal gate current is required to maintain the MOSFET in the on state or to switch the MOSFET between the on state and the off state. Because the gate and channel regions form a capacitor, the gate current remains small during switching. Thus, only minimal charging and discharging currents are required during switching, allowing for simpler gate drive circuitry and faster switching speeds. MOSFETs can be standalone devices, or can be combined with other circuit devices. For example, an insulated gate bipolar transistor ("IGBT") is a semiconductor device that includes both a MOSFET and a bipolar junction transistor ("BJT"), combining the high impedance gate electrode of the MOSFET with the small on-state conduction losses that a BJT can provide. An IGBT can be implemented, for example, as a Darlington pair including a high voltage n-channel MOSFET at the input and a BJT at the output. The base current of the BJT is supplied through the channel of the MOSFET, allowing for simplified external drive circuitry (as the drive circuitry only charges and discharges the gate electrode of the MOSFET).

[0008] In some applications, a MOSFET can be required to carry large currents and / or be able to block high voltages. Such MOSFETs are often referred to as "power" MOSFETs. Power MOSFETs are often fabricated from wide bandgap semiconductor materials (in this document, the term "wide bandgap semiconductor" encompasses any semiconductor having a bandgap of at least 1.4 eV). Power semiconductor devices are often formed in silicon carbide ("SiC"), which has a number of advantageous characteristics, such as high electric field breakdown strength, high electron mobility, high thermal conductivity, high melting point, and high saturated electron drift velocity.

[0009] Power semiconductor devices, such as power MOSFETs, can have a lateral structure or a vertical structure. In devices having a lateral structure, the terminals of the device (e.g., the drain, gate, and source terminals of a power MOSFET) are located on the same major surface (i.e., the top or bottom) of the semiconductor layer structure. In contrast, in devices having a vertical structure, at least one terminal is provided on each major surface of the semiconductor layer structure (e.g., in a vertical MOSFET, the source and gate can be located on the top surface of the semiconductor layer structure, while the drain can be located on the bottom surface of the semiconductor layer structure). The semiconductor layer structure can or can not include an underlying substrate, such as a growth substrate. In this document, the term “semiconductor layer structure” refers to a structure that includes one or more semiconductor layers, such as a semiconductor substrate and / or a semiconductor epitaxial layer.

[0010] The semiconductor layer structure of a power semiconductor device typically includes an “active region” in which one or more functional semiconductor devices are formed. The active region acts as a main junction for blocking voltage during reverse bias (off state) operation and for providing current flow during forward bias (on state) operation. The power semiconductor device can also have edge termination in a termination region of the semiconductor layer structure that is adjacent to (and typically surrounds) the active region. Typically, multiple power semiconductor devices are formed in / on a common wafer, and each power semiconductor device will typically have its own edge termination. After the wafer is fully processed, the resulting structure can be diced to separate the individual edge-terminated power semiconductor devices. Each power semiconductor device can have a unit cell structure in which the active region of each power semiconductor device includes multiple individual “unit cell” devices that are electrically connected in parallel and that together function as a single power semiconductor device.

[0011] Vertical power semiconductor devices including MOSFETs can have a standard gate electrode design in which the gate electrode of the transistor is formed on the top of the semiconductor layer structure, or, alternatively, the gate electrode can be buried in a gate trench within the semiconductor layer structure. MOSFETs with a buried gate electrode are commonly referred to as gate trench MOSFETs. In the case of a standard gate electrode design, the channel region of each unit cell transistor is deployed horizontally underneath the gate electrode. In contrast, in a gate trench MOSFET design, the channel is typically deployed vertically. Gate trench MOSFETs can provide enhanced performance, but typically require a more complex manufacturing process.

[0012] One failure mechanism for power MOSFETs is so-called "breakdown" of the gate oxide layer. During normal device operation, the gate oxide layer is subjected to high electric fields. The stress caused by these electric fields on the gate oxide layer creates defects in the oxide material, which accumulate over time. When the concentration of defects reaches a critical value, a so-called "percolation path" through the gate oxide layer is created, which electrically connects the gate electrode to the source or drain region, creating a short that destroys the device. The "lifetime" of the gate oxide layer (i.e., how long the device can be operated before breakdown occurs) is a function of the magnitude of the electric field to which the gate oxide layer is subjected and the length of time for which the electric field is applied, among other things. Figure 1 is a schematic diagram illustrating the relationship between the time of operation until breakdown occurs ("gate oxide layer lifetime") and the level of the electric field applied to the gate oxide layer. This diagram assumes that the same electric field is applied at all times (which is not necessarily the case) and assumes that the gate oxide layer has a certain thickness. As shown in Figure 1 , when the gate oxide lifetime is plotted on a logarithmic scale, in some cases the relationship can be generally linear. An important point that can be drawn from Figure 1 is that the lifetime of the gate oxide layer decreases exponentially as the level of the electric field increases. The lifetime of the gate oxide layer can be increased by increasing the thickness of the gate oxide layer, but various performance parameters of the MOSFET can be a function of the thickness of the gate oxide layer, so increasing the thickness of the gate oxide layer is not generally an acceptable way to increase the lifetime of the gate oxide layer. SUMMARY

[0013] According to some embodiments of the present invention, there is provided a semiconductor device comprising a wide bandgap semiconductor layer structure. The wide bandgap semiconductor layer structure comprises: a drift region having a first conductivity type; a well region having a second conductivity type located on the drift region; a source region having the first conductivity type located on the well region; a gate electrode located within a gate trench; and a trench shield region having the second conductivity type located below the gate trench. A width of the trench shield region exceeds a width of the gate trench.

[0014] In some embodiments, the trench shield region is formed below the gate trench and extends onto lower portions of opposing sidewalls of the gate trench.

[0015] In some embodiments, the gate trench has a left sidewall and a right sidewall extending parallel to a longitudinal axis of the gate trench, the left sidewall and the right sidewall being spaced apart from each other in a lateral direction, and wherein a left lateral extension of the trench shield region exceeds a lower edge of the left sidewall of the gate trench by at least 0.1 microns, and a right lateral extension of the trench shield region exceeds a lower edge of the right sidewall of the gate trench by at least 0.1 microns.

[0016] In some embodiments, the gate trench has left and right sidewalls extending parallel to a longitudinal axis of the gate trench, the left and right sidewalls being spaced apart from each other in a lateral direction, and wherein the gate trench overlaps less than 95% of a lateral width of the trench shield region.

[0017] In some embodiments, a lower corner of the gate trench is a rounded corner.

[0018] In some embodiments, the drift region, the well region, the source region, and the shield region each comprise silicon carbide.

[0019] In some embodiments, the trench shield region extends continuously across an entire width of the gate trench.

[0020] In some embodiments, the trench shield region defines a bottom of the gate trench.

[0021] In some embodiments, the gate trench has left and right sidewalls extending parallel to a longitudinal axis of the gate trench, the left and right sidewalls being spaced apart from each other in a lateral direction, and wherein a left side of the trench shield region laterally extends at least 0.3 microns beyond a lower edge of the left sidewall of the gate trench, and a right side of the trench shield region laterally extends at least 0.3 microns beyond a lower edge of the right sidewall of the gate trench.

[0022] According to further embodiments of the present invention, there is provided a semiconductor device comprising a wide bandgap semiconductor layer structure, the wide bandgap semiconductor layer structure comprising: a drift region having a first conductivity type; a well region having a second conductivity type located on the drift region; a source region having the first conductivity type located on the well region; a gate electrode located within a gate trench; and a trench shield region having the second conductivity type located below the gate trench. A portion of the drift region having the first conductivity type is interposed between a bottom surface of the gate trench and the trench shield region.

[0023] In some embodiments, the gate trench has left and right sidewalls extending parallel to a longitudinal axis of the gate trench, the left and right sidewalls being spaced apart from each other in a lateral direction, and wherein a left side of the trench shield region laterally extends at least 0.1 microns beyond a lower edge of the left sidewall of the gate trench, and a right side of the trench shield region laterally extends at least 0.1 microns beyond a lower edge of the right sidewall of the gate trench.

[0024] In some embodiments, the gate trench has left and right sidewalls extending parallel to a longitudinal axis of the gate trench, the left and right sidewalls being spaced apart from each other in a lateral direction, and wherein the gate trench overlaps less than 95% of a lateral width of the trench shield region.

[0025] In some embodiments, a lower corner of the gate trench is a rounded corner.

[0026] In some embodiments, the trench shield region extends continuously across the entire width of the gate trench.

[0027] In some embodiments, the gate trench has a left sidewall and a right sidewall extending parallel to a longitudinal axis of the gate trench, the left sidewall and the right sidewall being spaced apart from each other in a laterally direction, and wherein a left side of the trench shielding region laterally extends beyond a lower edge of the left sidewall of the gate trench by at least 0.3 microns, and a right side of the trench shielding region laterally extends beyond a lower edge of the right sidewall of the gate trench by at least 0.3 microns.

[0028] According to further embodiments of the present invention, methods for forming a semiconductor device are provided. According to these methods, a first mask is formed on a semiconductor layer structure, the first mask including a first opening extending longitudinally and having a first width. Spacers are formed on the sidewalls of the first mask exposed by the first opening to form a second mask, the first mask and the second mask including a mask structure having a second opening extending longitudinally, the second opening having a second width less than the first width. Dopants are implanted into the semiconductor layer structure through the second opening to form an implantation region in the semiconductor layer structure. The spacers are at least partially removed from the sidewalls of the first mask to form a third opening in the mask structure. Finally, the semiconductor layer structure is etched using the mask structure as an etching mask to form a gate trench in the semiconductor layer structure below the third opening.

[0029] In some embodiments, the second mask comprises silicon. In some embodiments, the second mask further comprises oxygen. In some embodiments, the first mask comprises both silicon and nitrogen.

[0030] In some embodiments, forming spacers on sidewalls of the first mask exposed by the first opening to form the second mask includes oxidizing the sidewalls of the first mask exposed by the first opening.

[0031] In some embodiments, the implantation region is located below the gate trench and a width of the implantation region is greater than a width of the gate trench.

[0032] In some embodiments, the implant region extends onto lower portions of opposing sidewalls of the gate trench.

[0033] In some embodiments, lower corners of the gate trench are rounded corners.

[0034] In some embodiments, the drift region, the well region, the source region, and the shield region each include silicon carbide.

[0035] In some embodiments, the drift region has a first conductivity type, the well region has a second conductivity type, the source region has the first conductivity type, wherein at least a portion of the well region is positioned between the drift region and the source region, and the implant region has the second conductivity type.

[0036] In some embodiments, the implant region is self-aligned with the gate trench.

[0037] In some embodiments, the method further comprises removing some but not all of the portions of the second mask within the second openings prior to implanting the dopant into the semiconductor layer structure.

[0038] In some embodiments, the semiconductor layer structure is etched using the mask structure as an etch mask to form a gate trench in the semiconductor layer structure under the third openings exposing the implant region.

[0039] In some embodiments, the method further comprises, after etching the semiconductor layer structure using the mask structure as an etch mask to form a gate trench in the semiconductor layer structure under the third openings, performing an oxidation process on the semiconductor layer structure, and then removing the oxidized portions of the semiconductor layer structure.

[0040] In some embodiments, the method further comprises, after etching the semiconductor layer structure using the mask structure as an etch mask to form a gate trench in the semiconductor layer structure under the third openings, annealing the semiconductor layer structure in a hydrogen-containing environment.

[0041] In some embodiments, removing the spacers from the sidewalls of the first mask at least partially to form the third openings in the mask structure comprises removing the spacers from the sidewalls of the first mask completely such that the third openings have a first width.

[0042] According to yet further embodiments of the present invention, there is provided a method of forming a semiconductor device, wherein a first mask is formed on a semiconductor layer structure, the first mask comprising a first opening. Spacers are formed on sidewalls of the first mask exposed by the first opening to form a second mask, the first mask and the second mask comprising a mask structure having a second opening. A dopant is implanted into the semiconductor layer structure through the second opening to form an implant region in the semiconductor layer structure. The spacers are removed from the sidewalls of the first mask at least partially. The semiconductor layer structure is etched to form a gate trench self-aligned with the implant region.

[0043] In some embodiments, the semiconductor layer structure is a wide bandgap semiconductor layer structure comprising a drift region having a first conductivity type, a well layer having a second conductivity type, and a source region having the first conductivity type on the well layer, wherein the dopant implanted into the semiconductor layer structure through the second opening is a second conductivity type dopant.

[0044] In some embodiments, removing the spacers from the sidewalls of the first mask at least partially comprises removing the spacers from the sidewalls of the first mask completely such that the semiconductor layer structure is etched using only the first mask as an etch mask.

[0045] In some embodiments, the implant region is a trench shield region having the second conductivity type.

[0046] In some embodiments, the second opening exposes the semiconductor layer structure.

[0047] In some embodiments, the spacer covers the semiconductor layer structure exposed by the first opening, such that the second opening does not expose the semiconductor layer structure.

[0048] In some embodiments, the method further comprises, after etching the semiconductor layer structure to form the gate trench, removing the first mask, then oxidizing exposed portions of the semiconductor layer structure, then removing the oxidized portions of the semiconductor layer structure.

[0049] In some embodiments, the method further comprises, after etching the semiconductor layer structure to form the gate trench, the bottom corners of the gate trench can be rounded, and / or the implanted second conductivity dopant can be activated via a heating step.

[0050] In some embodiments, the second mask comprises silicon. In some embodiments, the second mask further comprises oxygen. In some embodiments, the first mask comprises both silicon and nitrogen.

[0051] In some embodiments, forming the spacer on the sidewalls of the first mask exposed by the first opening to form the second mask comprises oxidizing the sidewalls of the first mask.

[0052] In some embodiments, the implant region is located below the gate trench and has a width that is greater than a width of the gate trench.

[0053] In some embodiments, the implant region extends onto lower portions of opposing sidewalls of the gate trench.

[0054] According to additional embodiments of the present invention, methods of forming a semiconductor device are provided. According to these methods, a semiconductor layer structure is provided, the semiconductor layer structure comprising a drift region having a first conductivity type, a well region having a second conductivity type located on the drift region, and a source region having the first conductivity type located on the well region. A first mask is formed on the semiconductor layer structure, the first mask comprising a first opening. A second conductivity type dopant is implanted into the semiconductor layer structure through at least a portion of the semiconductor layer structure exposed by the first opening to form an implant region having the second conductivity type in the drift region. After implanting the second conductivity type dopant into the semiconductor layer structure, the portion of the source region exposed by the first opening still has the first conductivity type.

[0055] In some embodiments, after implanting the second conductivity type dopant into the semiconductor layer structure, the portion of the drift region between the well region and the implant region still has the first conductivity type.

[0056] In some embodiments, the first opening is a longitudinally extending first opening having a first width, the method further comprising forming a spacer on sidewalls of the first mask exposed by the first opening to form a second mask, the first and second masks comprising a mask structure having a longitudinally extending second opening having a second width less than the first width. In such embodiments, the second conductivity type dopant can be implanted into the semiconductor layer structure through the second opening.

[0057] In some embodiments, the method further comprises at least partially removing the spacer from the sidewalls of the first mask to form a third opening in the mask structure, and then etching the semiconductor layer structure using the mask structure as an etch mask to form a gate trench in the semiconductor layer structure beneath the third opening.

[0058] In some embodiments, the first mask comprises a material containing both silicon and nitrogen, and the second mask comprises silicon.

[0059] In some embodiments, the second mask further comprises oxygen.

[0060] In some embodiments, the implant region is located beneath the gate trench, and a width of the implant region is greater than a width of the gate trench.

[0061] In some embodiments, the implant region extends onto a lower portion of opposing sidewalls of the gate trench. BRIEF DESCRIPTION OF DRAWINGS

[0062] Figure 1 is a schematic diagram illustrating the relationship between the time to breakdown and the level of the electric field applied to the gate oxide layer of a power semiconductor device.

[0063] Figures 2A-2L is a schematic vertical cross-sectional view, while Figure 2M is a schematic horizontal cross-sectional view illustrating a method of fabricating a gate trench power MOSFET according to an embodiment of the invention.

[0064] Figure 2N and Figure 2O are schematic horizontal cross-sectional views illustrating different possible connection schemes between the p-well and the source contact that can be used instead of the connection scheme shown in Figure 2M .

[0065] Figure 3A and Figure 3B are corresponding schematic vertical cross-sectional views illustrating Figure 2H modified versions of the gate trench power MOSFET of Figures 2A-2M .

[0066] Figure 4 is a schematic vertical cross-sectional view corresponding to Figure 2DThe corresponding schematic vertical cross-sectional view illustrates the manufacturing process Figures 2L-2M Another approach to the gate of a trench power MOSFET.

[0067] Figures 5A-5E is a schematic vertical cross-sectional view, and Figure 5F is a schematic horizontal cross-sectional view illustrating a method of manufacturing a gate trench power MOSFET according to a further embodiment of the present invention.

[0068] Figure 6 is with Figure 5C The corresponding schematic vertical cross-sectional view shows Figures 5A-5F A modified version of the gate trench power MOSFET.

[0069] Figures 7-8 is a flow chart illustrating a method of manufacturing a gate trench semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0070] Vertical silicon carbide-based power semiconductor devices with gate trenches (such as vertical power MOSFETs and IGBTs) are attractive for many applications because of their inherently lower specific on-resistance, which results in more efficient operation of the power switching operation. Gate trench vertical power devices exhibit lower specific resistance during on-state operation because the channel is formed in the sidewalls of the gate trench. In addition, the carrier mobility in the sidewall channel can be 2-4 times higher than the corresponding carrier mobility in the horizontal channel of a standard (i.e., non-gate trench) vertical power device, which results in an increased current density during on-state operation, thereby allowing higher switching speeds. In addition, the gate trench design reduces the overall pitch of the device, thereby allowing for increased integration. Lower conduction losses (due to reduced on-state resistance) and improved switching speeds make gate trench power devices very suitable for high-frequency power applications with low to medium voltage blocking requirements (e.g., 600-1200 volts). These devices can have reduced requirements for associated passive components and require relatively simple cooling solutions. Since MOSFET is the most widely used silicon carbide-based trench power semiconductor gate device, the following discussion focuses on MOSFET embodiments. However, it will be appreciated that each of the embodiments described can alternatively be implemented using a non-oxide gate dielectric layer (e.g., nitride, high-k dielectric material, etc.), and the same techniques can be used to form other gate trench power semiconductor devices such as IGBTs, gate-controlled thyristors, etc.

[0071] As discussed above, gate trench power MOSFETs are susceptible to oxide reliability problems due to the high electric fields present in the gate oxide layer at the bottom and sidewalls of the gate trench. Over time, the high electric fields degrade the gate oxide layer and can eventually cause the device to fail. When a gate trench MOSFET is operated under reverse blocking operation (i.e., when the MOSFET is in its off state), the source terminal of the MOSFET is typically grounded, the gate terminal is typically grounded or at a negative bias voltage, and the drain terminal is typically at a high positive voltage. Under this reverse blocking operation, the high electric field extends upward from the drain terminal (which is on the bottom surface of the semiconductor layer structure) toward the top surface of the semiconductor layer structure. Thus, under reverse blocking operation, the bottom portion of the gate dielectric layer experiences the highest electric field levels. Due to the electric field crowding effect, the electric field level at the corner of the lower portion of the gate oxide layer at the bottom edge of the gate trench can be particularly high (i.e., the portion of the gate oxide layer covering the area where the sidewalls of the gate trench merge with the bottom of the gate trench). Moreover, due to the difference in dielectric constant between silicon carbide and silicon oxide, the electric field in the silicon oxide gate oxide layer can be approximately 2.6 times higher than the electric field in the adjacent silicon carbide. When the electric field reaches a critical level Ecr, the silicon oxide breaks down. To avoid this breakdown, the power MOSFET can be operated with the drain voltage at a lower level during reverse blocking operation to ensure that the electric field does not reach a level that would cause breakdown. In other words, the rated voltage of the power MOSFET can be set to ensure that premature gate oxide breakdown does not occur.

[0072] So-called "trench shield regions" are often provided under the gate trench of conventional gate trench power MOSFETs in order to reduce the electric field level in the gate oxide layer during reverse blocking operation. These trench shield regions include a highly doped semiconductor layer having the same conductivity type as the channel region of the device. The following discussion focuses on n-type devices having a channel region and trench shield regions of p-type. For example, the trench shield regions can extend downward from the bottom of the gate trench 0.5 to 1.0 microns or deeper into the semiconductor layer structure of the device. The protection of the gate oxide layer by these trench shield regions increases as the trench shield region depth increases. The trench shield regions are electrically connected to the source terminal of the MOSFET by p-type trench shield connection patterns. These trench shield connection patterns can be located within and / or outside the active area of the device.

[0073] The trench shield region is typically formed via one or more ion implantation processes in which p-type dopant ions are implanted into the bottom surfaces of the gate trenches. However, the sidewalls of the gate trenches are not typically perfectly vertical, but instead are sloped outward as the distance from the bottom of each gate trench increases. Thus, during the ion implantation process, some of the p-type dopant ions will be implanted directly into the sidewalls of each gate trench. In addition, some of the p-type dopant ions will bounce off of the exposed portions of the n-type drift region beneath each gate trench, with some of these "reflected" p-type dopant ions subsequently implanting into the sidewalls of the gate trenches. The implantation of p-type dopant ions into the sidewalls of the gate trenches via these two mechanisms during the ion implantation process performed to form the trench shield region can be problematic for two reasons.

[0074] First, the additional p-type dopant ions implanted into the sidewalls of the gate trenches increase the doping concentration of the p-type channel regions formed in these sidewalls. This degrades the performance of the MOSFET because the p-type channel regions are typically doped to a level that optimizes device performance. Second, the p-type ions implanted into the sidewalls can also convert the portions of the lightly doped n-type drift region that form the lower portions of each sidewall into p-type material. If this occurs, then the unit cell will no longer operate as a transistor. While an oxide spacer or other mask can be formed on the sidewalls of the gate trenches to prevent p-type dopant ions from being implanted into the sidewalls during the ion implantation process, the use of this mask complicates the manufacturing process and also limits the width of the trench shield region relative to the width of the gate trench.

[0075] Another potential problem with conventional techniques for forming trench shield regions is that the trench shield region can not be perfectly aligned with the gate trench at all times. For example, if the trench shield region is misaligned such that the center of the trench shield region is shifted to the left (e.g., by 0.1-0.6 microns) relative to the center of its associated gate trench, then the trench shield region will provide diminished protection to the portion of the gate oxide layer that lines the lower right side of the gate trench. Thus, a higher electric field will be formed in the gate oxide layer of the lower right side of the gate trench during device operation. When this misalignment exists, a reduced rated voltage of the device and / or a reduced device yield can become inevitable (to weed out devices with high levels of misalignment).

[0076] According to embodiments of the present invention, a gate trench power semiconductor device is provided that includes trench shield patterns that are self-aligned with their respective gate trenches. The gate trench power semiconductor device according to embodiments of the present invention can be manufactured by forming a mask structure on a suitable semiconductor layer structure, patterning the mask structure to expose the areas where the gate trenches are to be formed, and then performing a high-energy ion implantation process to form the trench shield regions in the semiconductor layer structure in the portions that are located below the subsequently formed gate trenches. A portion of the mask structure can be removed, and the remaining mask material can then be used as an etch mask during the gate trench formation process. By using at least a portion of the same mask structure in the trench shield ion implantation process and the gate trench etching process, the trench shield regions can be self-aligned with the respective gate trenches.

[0077] In some embodiments, a multi-level mask structure can be used during the ion implantation process that is performed to form the trench shield regions. The multi-level mask structure can include, for example, a first mask (e.g., a nitride, oxynitride, or polysilicon mask) that is patterned to form openings in the semiconductor layer structure over the areas where the gate trenches are to be formed. On the first mask (e.g., on the top surface of the first mask and on the sidewalls of the first mask that are exposed by the openings therein), a second mask in the form of, for example, an oxide spacer is formed. The second mask is used to reduce the width of each opening in the first mask. The trench shield ion implantation process is performed with the complete mask structure in place. Then, the second mask can be removed (or partially removed), which serves to widen the openings in the mask structure, and the etching process for forming the gate trenches can be performed. The thickness of the oxide spacer can be selected to optimize the width of each trench shield region compared to the width of the gate trench associated therewith. This approach allows the trench shield regions to be formed to extend well beyond the sidewalls of their associated gate trenches without the need to use angled ion implantation, while also enabling each trench shield region to be self-aligned with its associated gate trench.

[0078] In some embodiments, the ion implantation step for forming the trench shield regions can be a high-energy ion implantation step that primarily implants ions into portions of the semiconductor layer structure that are close to or below the bottom of the gate trenches formed in subsequent processing steps. This can allow the use of a single implantation step, and can also reduce the impact of the ion implantation step on portions of the semiconductor layer structure that will eventually be used as the channel regions of the device.

[0079] Since the ion implantation step for forming the trench shield region is performed prior to the formation of the gate trench, the problem of dopant ions implanting the non-vertical sidewalls of the gate trench is eliminated, as is the possibility of dopant ions reflecting from the bottom of the gate trench so that they implant the sidewalls of the gate trench. Thus, the problems discussed above of the doping concentration of the channel region or portions of the drift region below the channel region being adversely affected by unintentional implantation of the sidewalls of the gate trench can be avoided. Furthermore, in at least some embodiments, the relative widths of the gate trench and the trench shield region can be readily controlled by using a multi-layer mask structure. This allows the designer to optimize the trade-off between the specific on-resistance and the maximum electric field value in the gate oxide that exists when the device is operated at its rated voltage level. This is important because in some applications the limiting factor on device performance can be the maximum specific on-resistance value, while in other applications the limiting factor can be the maximum electric field value in the gate oxide, which acts to limit the rated voltage of the device. Thus, the techniques disclosed herein can allow the designer to fabricate devices that are optimized for different applications, meaning that the present invention allows devices to be fabricated that exhibit higher performance for a wider variety of different applications than can be provided using conventional fabrication techniques.

[0080] According to embodiments of the present invention, a semiconductor device is provided that includes a wide bandgap semiconductor layer structure. The wide bandgap semiconductor layer structure includes: a drift region having a first conductivity type; a well region having a second conductivity type located on the drift region; a source region having the first conductivity type located on the well region; a gate electrode located within a gate trench; and a trench shield region having the second conductivity type located below the gate trench. The trench shield region has a width that exceeds a width of the gate trench.

[0081] According to further embodiments of the present invention, a semiconductor device is provided that includes a wide bandgap semiconductor layer structure, wherein the wide bandgap semiconductor layer structure likewise includes: a drift region having a first conductivity type; a well region having a second conductivity type located on the drift region; a source region having the first conductivity type located on the well region; a gate electrode located within a gate trench; and a trench shield region having the second conductivity type located below the gate trench. A portion of the drift region having the first conductivity type is interposed between a bottom surface of the gate trench and the trench shield region.

[0082] According to additional embodiments of the present invention, methods of fabricating a power semiconductor device are provided. According to certain of these methods, a first mask is formed over a semiconductor layer structure, the first mask including a first opening having a first width that extends longitudinally. A spacer is formed on sidewalls of the first mask exposed by the first opening to form a second mask, wherein the first and second masks include a mask structure having a second opening that extends longitudinally, the second opening having a second width that is less than the first width. Dopants are implanted through the second opening to form an implanted region in the semiconductor layer structure. The spacer is at least partially removed from the sidewalls of the first mask to form a third opening in the mask structure. The semiconductor layer structure is then etched using the mask structure as an etch mask to form a gate trench in the semiconductor layer structure beneath the third opening.

[0083] According to further embodiments of the present invention, methods of fabricating a power semiconductor device are provided, wherein a first mask is formed over a semiconductor layer structure, the first mask including a first opening. A spacer is formed on sidewalls of the first mask exposed by the first opening to form a second mask, the first and second masks including a mask structure having a second opening. Dopants are implanted through the second opening into the semiconductor layer structure to form an implanted region in the semiconductor layer structure. The spacer is at least partially removed from the sidewalls of the first mask. The semiconductor layer structure is then etched to form a gate trench that is self-aligned to the implanted region.

[0084] According to still further embodiments of the present invention, methods of fabricating a power semiconductor device are provided. According to these methods, a semiconductor layer structure is provided, the semiconductor layer structure including a drift region having a first conductivity type, a well region having a second conductivity type located on the drift region, and a source region having the first conductivity type located on the well region. A first mask is formed over the semiconductor layer structure, wherein the first mask includes a first opening. A second conductivity type dopant is implanted into the semiconductor layer structure through at least a portion of the semiconductor layer structure exposed by the first opening to form an implanted region having the second conductivity type in the drift region. The portion of the source region exposed by the first opening still has the first conductivity type after the second conductivity type dopant is implanted into the semiconductor layer structure.

[0085] Reference will now be made to the drawings Figures 2A-8Embodiments of the invention are described in more detail. It will be appreciated that the features of the different embodiments disclosed herein can be combined in any manner to provide many additional embodiments. Accordingly, it will be appreciated that various features of the invention are described below with respect to specific examples, but that these features can be added to other embodiments and / or used in place of example features of other embodiments to provide many additional embodiments. Accordingly, the invention should be understood to encompass these different combinations. Furthermore, while the example embodiments focus on MOSFET implementations, it will be appreciated that the same technology can be used in other gate trench power semiconductor devices, such as insulated gate bipolar transistors (IGBTs), gate controlled thyristors, and the like.

[0086] Figures 2A-2M 1 is a schematic cross-sectional view illustrating a method of manufacturing a gate trench power MOSFET 100 according to an embodiment of the present invention. More specifically, Figures 2A-2L 1 is a schematic vertical cross-sectional view illustrating a method of manufacturing a semiconductor layer structure of a gate trench power MOSFET 100 . Figures 2M It is along Figure 2L Schematic horizontal cross-sectional view of MOSFET 100 taken along line 2M-2M. As used herein, a vertical cross-sectional view of a power semiconductor device refers to a view of a cross section taken through the device along a plane perpendicular to the major surface of the device's semiconductor layer structure. Similarly, a horizontal cross-sectional view of a power semiconductor device refers to a view of a cross section taken through the device along a plane parallel to the major surface of the device's semiconductor layer structure.

[0087] refer to Figure 2A , an n-type silicon carbide substrate 110 is provided. The substrate 110 may include, for example, a 4H-silicon carbide or a 6H-silicon carbide substrate. In other embodiments, the substrate 110 may be or include a different semiconductor material (e.g., a III-nitride-based material, silicon, gallium arsenide, zinc oxide, etc.). The substrate 110 may be heavily doped with n-type impurities (n + )(i.e., it can be n + The impurities may include, for example, nitrogen or phosphorus. The n-type doping concentration of the substrate 110 may be, for example, 1×10 18 atoms / cm 3 and 1x10 21 atoms / cm 3, but other doping concentrations may also be used. In some embodiments, substrate 110 may be relatively thick (e.g., 20-100 microns or thicker). It should be noted that although the substrate is shown as a relatively thin layer in the figures, this is to allow the thickness of other layers and regions in the figures to be magnified, and it will be appreciated that substrate 110 will typically be much thicker than shown in the figures. Similarly, the thickness of various other layers of the MOSFET according to embodiments of the present invention may not be shown to scale to allow other parts of the device to be magnified in the figures.

[0088] Lightly doped (n - ) A silicon carbide drift region 120 (also referred to herein as a drift layer 120) is provided on the upper surface of the substrate 110. The n-type drift region 120 may be formed, for example, by epitaxial growth on the substrate 110. The n-type drift region 120 may have a thickness of, for example, 5×10 15 Up to 5x10 17 Dopant / cm 3 The n-type drift region 120 may be a thick region having a vertical height of, for example, 3-50 microns above the substrate 110. In some embodiments, the upper portion of the n-type drift region 120 may include an n-type current spreading layer (not shown) that is more heavily doped than the lower portion of the n-type drift region 120. If provided, the n-type current spreading layer may have a thickness of, for example, 5x10 16 to 1x10 18 dopant concentration.

[0089] Still refer to Figure 2A Next, a medium-doped (p) p-type silicon carbide well layer 130 is formed on the upper surface of the n-type drift region 120. The medium-doped (p) p-type silicon carbide well layer 130 can be formed by epitaxial growth or as shown in FIG. Figure 2A As shown in FIG, the p-type well layer 130 is formed by implanting p-type dopant ions into the upper portion of the n-type drift region 120 to convert the upper portion of the n-type drift layer into a p-type well layer 130. In some embodiments, the moderately doped p-type well layer 130 may have a graded doping profile.

[0090] refer to Figure 2B , a heavily doped (n + ) silicon carbide source layer 140. As shown in the figure, the heavily doped n-type silicon carbide source layer 140 is usually formed by ion implantation. When formed by ion implantation, the upper portion of the p-type silicon carbide well layer 130 is converted into a heavily doped (n + ) silicon carbide source layer 140. The heavily doped n-type silicon carbide source layer 140 may have a thickness of, for example, 1×10 19 atoms / cm 3 Up to 5x1021 atoms / cm 3 Although the doping concentration is between Figure 2B Not visible in cross-section (but see Figure 2M ), but n-type dopants can be selectively implanted into the p-type silicon carbide well layer 130 so that in selected areas, the p-type well layer 130 will extend to the upper surface of the semiconductor layer structure 150. The substrate 110, drift region 120, well layer 130, and source layer 140, together with various regions / patterns formed therein (such as trench shield regions and trench shield connection patterns (discussed below)), constitute the semiconductor layer structure 150 of the power MOSFET 100.

[0091] refer to Figure 2C , a first mask 162 is formed on the upper surface of the source layer 140. The first mask 162 may include, for example, a nitride mask (e.g., silicon nitride) or an oxynitride mask (e.g., silicon oxynitride), or a multi-layer mask (such as a thin oxide (e.g., silicon oxide) layer with a nitride layer formed thereon). However, it will be appreciated that a variety of other materials may be used. For example, in other embodiments, the first mask 162 may include a polysilicon mask. Figure 2C , first mask 162 is then patterned (e.g., using standard photolithographic patterning techniques) to form openings 164 that expose selected portions of semiconductor layer structure 150. Openings 164 can be positioned over locations in semiconductor layer structure 150 where trench shielding regions will be formed in subsequent processing steps.

[0092] refer to Figure 2DA second mask 166 in the form of spacers is formed over the first mask 162 and the semiconductor layer structure 150. For example, the second mask 166 can be conformally formed over the first mask 162 and the semiconductor layer structure 150. Alternatively, the second mask 166 can be selectively deposited over the first mask 162 (and, as shown, optionally also over portions of the semiconductor layer structure 150 exposed by the openings 164 in the first mask 162). The first mask 162 and the second mask 166 together form a mask structure 160. The second mask 166 can comprise, for example, oxide spacers (e.g., silicon oxide spacers). Regardless of how the second mask 166 is formed, the second mask / spacers 166 can conformally cover the sidewalls of the first mask 162 exposed by the openings 164. Thus, the second mask / spacers 166 formed on the sidewalls of the first mask 162 reduce the size of the first openings 164, thereby forming second openings 168 in the mask structure 160. As shown, the second openings 168 do not extend completely through the mask structure 160, since the second mask can be formed over exposed portions of the semiconductor layer structure 150. To control the width of each second opening 168, the thickness of the second mask 166, and particularly the portion of the second mask 166 formed on the sidewalls of the first mask 162, can be carefully controlled.

[0093] Referring to Figure 2E , the second mask 166 can be patterned to remove portions thereof formed over the semiconductor layer structure 150 in the second openings 168 (if such portions of the second mask 166 were formed first) so as to expose selected portions of the semiconductor layer structure 150 in preparation for a subsequent ion implantation operation. However, it will be recognized that in some embodiments, the patterning step shown can be omitted, and portions of the second mask 166 formed over the semiconductor layer structure 150 in the second openings 168 can be left in place, and ion implantation can be performed through these portions of the second mask 166. Figure 2E

[0094] Referring to Figure 2F , an ion implantation process is performed to implant p-type dopant ions into portions of the semiconductor layer structure 150 underlying the second openings 168. The combined thickness of the first mask 162 and the second mask 166 (by "thickness" herein is meant the extent of something in the z-direction) can be sufficient to substantially block p-type dopant ions in the portion of the implant mask structure 160 in which the first mask 162 and the second mask 166 are vertically stacked from reaching the semiconductor layer structure 150. As shown in Figure 2F , the ion implantation step forms a plurality of preliminary trench shield regions 172 in the semiconductor layer structure 150. The preliminary trench shield regions 172 can be heavily doped (p + ) silicon carbide regions. ​

[0095] In example embodiments, the preliminary trench shield region 172 can have a dopant concentration between about 1 x 1010 17 and 1 x 1010 21 and can extend to a depth between 0.5 and 3.0 microns from an upper surface of the semiconductor layer structure 150. In other embodiments, the preliminary trench shield region 172 can have a dopant concentration between about 1 x 1010 18 and 1 x 1010 20 and 1 x 1010 19 and 1 x 1010 20 and 1 x 1010 17 and 1 x 1010 20 and 1 x 1010 18 and 1 x 1010 21 In other embodiments, the depth of the preliminary trench shield region 172 can be between 1.0 and 3.0 microns, 1.0 and 2.5 microns, 1.5 and 3.0 microns, 1.5 and 2.5 microns, or 0.5 and 2.5 microns. Any of the above dopant concentrations can be matched with the depths listed above for the preliminary trench shield region 172. As shown, the preliminary trench shield region 172 extends through the silicon carbide source layer 140 and through the silicon carbide well layer 130 into the silicon carbide drift region 120. The trench shield region 170 (as discussed below) formed from the preliminary trench shield region 172 in later processing steps can all serve to reduce the level of electric field formed in a gate oxide layer (as discussed below) formed in a gate trench (as discussed below) of the device during operation, as will be discussed in greater detail below.

[0096] As shown in Figure 2F , the p-type dopant ions scatter to some extent upon impinging protons and neutrons that form the material of the semiconductor layer structure 150. This causes the preliminary trench shield region 172 to "bloom" in the sense that the width of the preliminary trench shield region 172 increases as the depth from the upper surface of the semiconductor layer structure 150 increases.

[0097] Figure 2F The ion implantation step shown in +The source layer 140 and portions of the lightly doped n-type drift region 120 located beneath the second openings 168 are converted to p-type material to convert these n-type regions to p-type material. Thus, the preliminary trench shield regions 172 can convert the moderately doped p-type well layer 130 into a plurality of moderately doped p-wells 132 and can convert the heavily doped n-type silicon carbide source layer 140 into a plurality of heavily doped n-type source regions 142 that serve as source regions for the power MOSFET 100.

[0098] As will be described below with reference to Figures 5A-5F In some embodiments of the present application, a so-called "deep" ion implantation technique can be used in which ions are implanted at high energy such that almost all of the ions penetrate through the source layer 140 and the p-well 130. When such a deep ion implantation technique is used, the heavily doped n + The source layer 140 and portions of the p-well layer 130 beneath the second openings 168 in the drift region 120 (these portions of the drift region 120 are removed when the gate trenches are formed) can remain as n-type material. It will be appreciated that any type of ion implantation process can be used here. In other words, in other embodiments, a deep ion implantation technique discussed below with reference to Figures 5A-5F may be used instead of the "shallow and deep" ion implantation technique shown in Figure 2F

[0099] Referring to Figure 2G After the preliminary trench shield regions 172 are formed, the second mask 166 is at least partially removed to convert the second openings 168 into third openings 169 that are wider than the second openings 168. In the depicted embodiment, the second mask 166 is completely removed so that the only mask remaining on the device is the first mask 162. In this case, the third openings 169 are the same as the first openings 164 therein. The third openings 169 expose the preliminary trench shield regions 172 and portions of the source regions 142 in the semiconductor layer structure 150. In other embodiments (not shown), the second mask 166 can be thinned but not completely removed. In such embodiments, the third openings 169 are wider than the second openings 168 but narrower than the first openings 164.

[0100] Referring to Figure 2H A plurality of gate trenches 180 are formed via etching in the upper surface of the semiconductor layer structure 150 using the remaining mask structure 160 (here, the first mask 162) as an etch mask. Each of the gate trenches 180 extends into the upper surface of the n-type drift region 120. Although in the depicted embodiment the gate trenches 180 are formed in the n-type drift region 120, in other embodiments (not shown) the gate trenches 180 can be formed in the p-well 132. Figure 2H ​Only one complete gate trench 180 and a portion of a second gate trench 180 are shown, but it will be appreciated that a large number of gate trenches 180 are typically provided, with the longitudinal axis of each gate trench 180 extending in a first direction over the substrate 110 (here the gate trenches 180 extend in the x-direction), and the gate trenches 180 being spaced apart from one another in a second direction (here the y-direction), such that the gate trenches 180 extend longitudinally in parallel to one another. Each gate trench 180 has a length (corresponding to a distance in the x-direction), a width (corresponding to a distance in the y-direction), and a depth (corresponding to a distance in the z-direction). The length direction is the longest direction, so the longitudinal axis of each gate trench 180 refers to an axis extending down the middle of the gate trench 180 in the length direction. Each gate trench 180 has first and second opposing sidewalls, and a bottom surface, which each extend in the x-direction, so in parallel to the longitudinal axis. Reference herein to the "width" of a gate trench 180 refers to the shortest distance between opposing longitudinal sidewalls of the gate trench 180 (i.e. the shortest distance between opposing longitudinal sidewalls in the y-direction).

[0101] As noted above, if the preliminary trench shield region 172 extends to the upper surface of the semiconductor layer structure 150, then formation of the preliminary trench shield region 172 acts to convert the moderately doped p-type silicon carbide well layer 130 into a plurality of moderately doped p-wells 132, and to convert the heavily doped n-type silicon carbide source layer 140 into a plurality of heavily doped n-type source regions 142. In the case where the preliminary trench shield region 172 is formed as a deep implant only using a high energy ion implant process (see discussion below), then formation of the gate trench 180 acts to convert the moderately doped p-type silicon carbide well layer 130 into a plurality of moderately doped p-wells 132, and to convert the heavily doped n-type silicon carbide source layer 140 into a plurality of heavily doped n-type source regions 142. In either case, the portion of each p-type well 132 adjacent to the gate trench 180 acts as a transistor channel 134, as will be discussed below. Figures 5A-5F

[0102] Although Figure 2H ​MOSFET 100 is illustrated with a plurality of gate trenches 180 all extending parallel to one another in a first direction, but it will be recognized that embodiments of the present invention are not limited thereto. Power MOSFETs with a wide variety of gate trench designs are known in the art. For example, some power MOSFETs have both a first set of gate trenches extending in a first direction through the semiconductor layer structure and a second set of gate trenches extending in a second (typically perpendicular) direction through the semiconductor layer structure, such that the trenches in the two sets intersect one another. As another example, some MOSFETs have gate trenches formed in a rectangular, hexagonal, octagonal, or circular shape (when viewed from above), with the trenches surrounding a well region (with source regions therein). It will be recognized that the techniques disclosed herein can be used on MOSFETs with any gate trench design, including the example additional designs discussed above.

[0103] The etching step performed to form the gate trenches 180 removes the upper portion of each preliminary trench shield region 172, thereby forming a plurality of trench shield regions 170 beneath the respective gate trenches 180. In the depicted embodiment, each gate trench 180 is narrower (in the width direction) than the associated trench shield region 170 provided beneath the gate trench 180. Thus, each trench shield region 170 extends onto the lower sidewall of its associated gate trench 180. Since the width of the second mask 166 formed on the sidewall of the first mask 162 can be set to any desired value, the width W2 of each gate trench 180 relative to the width Wl of its associated trench shield region 170 can be set to any desired value. As noted above, Figure 2H An embodiment is illustrated in which the width Wl of the trench shield regions 170 (as measured at the depth of the bottom of the gate trenches 180) is slightly wider than the width W2 of their associated gate trenches 180.

[0104] Figure 3A is a cross-section of a MOSFET 100A according to a further embodiment of the present invention (corresponding to that of Figure 2H ), in which the width of the second mask 166 on the sidewall of the first mask 162 is reduced compared to that shown in Figures 2D-2F . As can be seen from Figure 3A , this results in the trench shield regions 170 having a width Wl (as measured at the depth of the bottom of their associated gate trenches 180) that is significantly wider than the width W2 of their associated gate trenches 180.

[0105] In contrast, Figure 3B is a cross-section of a MOSFET 100B according to a further embodiment of the present invention (corresponding to that of Figure 2Hcorresponding to the width of the second mask 166 on the sidewall of the first mask 162 Figures 2D-2F As can be seen from FIG. 1C, this results in the trench shield region 170 having a width Wl (measured at the depth of the bottom of its associated gate trench 180) that is narrower than the width W2 of its associated gate trench 180. Figure 3B As can be seen from FIG. 1C, this results in the trench shield region 170 having a width Wl (measured at the depth of the bottom of its associated gate trench 180) that is narrower than the width W2 of its associated gate trench 180.

[0106] In the embodiment of FIG. 1C, the trench shield region 170 has a left side that extends laterally beyond the lower edge of the left sidewall of the gate trench 180 by at least 0.1 microns, and a right side that extends laterally beyond the lower edge of the right sidewall of the gate trench 180 by at least 0.1 microns. Figure 2H and Figure 3A In the embodiment of FIG. 1C, the trench shield region 170 has a left side that extends laterally beyond the lower edge of the left sidewall of the gate trench 180 by at least 0.1 microns, and a right side that extends laterally beyond the lower edge of the right sidewall of the gate trench 180 by at least 0.1 microns.

[0107] In some embodiments, the left side of the trench shield region 170 can extend laterally beyond the lower edge of the left sidewall of the gate trench, and the right side of the trench shield region 170 can extend laterally beyond the lower edge of the right sidewall of the gate trench, each by between 0.1 microns and 0.8 microns. In other embodiments, the left side of the trench shield region 170 can extend laterally beyond the lower edge of the left sidewall of the gate trench, and the right side of the trench shield region 170 can extend laterally beyond the lower edge of the right sidewall of the gate trench, each by between 0.1 microns and 0.6 microns. In still other embodiments, the left side of the trench shield region 170 can extend laterally beyond the lower edge of the left sidewall of the gate trench, and the right side of the trench shield region 170 can extend laterally beyond the lower edge of the right sidewall of the gate trench, each by between 0.1 microns and 0.5 microns. In yet additional embodiments, the left side of the trench shield region 170 can extend laterally beyond the lower edge of the left sidewall of the gate trench, and the right side of the trench shield region 170 can extend laterally beyond the lower edge of the right sidewall of the gate trench, each by between 0.2 microns and 0.5 microns. It should be noted that in some embodiments, the left side of the trench shield region 170 can extend laterally beyond the lower edge of the left sidewall of the gate trench by a different amount than the right side of the trench shield region 170 can extend laterally beyond the lower edge of the right sidewall of the gate trench.

[0108] In some embodiments, the gate trench can overlap less than 98% of the lateral width of the trench shield region. In this context, "overlap" means that in a vertical cross-section such as Figure 2H the bottom of the gate trench 180 is located above the top of the trench shield region 170. Thus, for example, if in Figure 2H width W2 is 8 arbitrary units and width Wl is 10 arbitrary units, then the gate trench overlaps 80% of the lateral width of the trench shield region 170. In other embodiments, the gate trench can overlap less than 95%, less than 90%, or less than 85% of the lateral width of the trench shield region 170.

[0109] Referring to Figure 2I the remaining portion of the mask structure 160 can be removed. If the remaining portion of the mask structure 160 is the first mask 162 and was formed as a nitride mask, then the first mask 162 can be removed using a lift-off operation.

[0110] Referring to Figure 2JA sacrificial oxidation process can be performed to convert the exposed portions of the semiconductor layer structure 150 to silicon oxide. The "depth" to which the exposed silicon carbide is converted to silicon oxide can be controlled based on the length, temperature, pressure, and oxygen content in the environment of the oxidation process. An etching process is then performed to remove the oxidized silicon carbide. This sacrificial oxidation process can be used to remove surface portions of the silicon carbide that can have been damaged (e.g., roughened) during the ion implantation process. As shown, the sacrificial oxidation process can also widen the gate trench 180. In the depicted embodiment, the gate trench 180 is widened such that its associated trench shield region 170 extends onto the lower sidewalls of the gate trench 180 only to a small extent. It will be recognized that in other embodiments, the trench shield region 170 can be designed such that the trench shield region 170 is formed thicker and / or extends further upward on the lower sidewalls of its associated gate trench 180 (e.g., see Figure 3A ).

[0111] Referring to Figure 2K , a hydrogen etch can be performed. The hydrogen etch can further widen the gate trench 180 and etch the upper surface of the semiconductor layer structure 150. The hydrogen etch can also advantageously round the lower corners of each gate trench 180 (note that these "corners" extend the entire length of each gate trench 180 in the x-direction). The rounding of the lower corners of each gate trench 180 causes the gate oxide layer formed into each gate trench 180 during subsequent processing operations (see Figure 2L ) such that the gate oxide layer formed in the corners of each trench 180 also has a rounded cross-sectional profile. This rounding of the gate oxide layer serves to reduce the electric field level in the lower corners of the gate oxide layer during the reverse blocking operation as it reduces the electric field crowding effect that occurs in layers with sharp corners. This reduction in the electric field value can allow for a higher rated voltage of the power semiconductor device according to embodiments of the present invention. Although not shown in the figures, the hydrogen etch can also be used to round the upper corners of each gate trench 180. This rounding of the upper corners of the gate trench 180 can reduce the electric field value in the upper portion of the gate oxide layer during the on-state operation, which is also advantageous.

[0112] After the hydrogen etch is performed, an anneal process can be performed to activate the p-type dopants in the trench shield region 170.

[0113] Referring to Figure 2LA gate insulating layer 182 is formed on the bottom surface and sidewalls of each gate trench 180. Typically, the gate insulating layer 182 is an oxide layer, and thus will be referred to herein as a gate oxide layer 182. The gate oxide layer 182 can be formed by conformally forming an oxide layer on the bottom surface and sidewalls of each gate trench 180. The conformal gate oxide layer 182 can be formed by oxidizing the exposed silicon carbide via annealing in an oxygen-containing environment. Alternatively, the conformal gate oxide layer 182 can be formed by an oxide deposition step. Portions of the conformal gate oxide layer 182 can be removed to form openings at which source contacts 190 can be connected to the source regions 142 and p-well extensions (discussed below). Removing these portions of the conformal gate oxide layer 182 leaves the gate oxide layer 182 in each gate trench 180.

[0114] A gate electrode 184 is formed on each gate oxide layer 182 to fill the corresponding gate trench 180. Each gate electrode 184 can comprise a conductive material such as, for example, polysilicon, silicate, or metal. An intermetallic dielectric layer 186 is formed on exposed portions of the gate oxide layer 182 and gate electrode 184. A source contact 190 is formed on an upper portion of the device. The source contact 190 is physically and electrically connected to the n-type source regions 142. The source contact 190 can comprise, or can be electrically connected to, a source terminal of the MOSFET 100. Although not visible in the cross-section of FIG. 1, a p-well extension 136 is formed in the MOSFET 100 in selected regions of the device that physically and electrically connect the p-well 132 to the source contact 190. These p-well extensions 136 are discussed below in connection with FIG. 2. Figure 2L A gate contact (not shown) to the gate electrode 184, outside the cross-section of FIG. 1, is typically connected via one or more gate buses (not shown). Figure 2M A plan view of the MOSFET 100 is shown in FIG. 2, and the method of forming the p-well extensions is known in the art. In addition, a trench shield connection region (not shown) can be provided in the active and / or non-active regions of the MOSFET 100 that electrically connects the p-well 132 to the trench shield region 170. A drain contact 192 is formed on the lower surface of the substrate 110. A source contact 190 is also provided that is electrically connected to the source regions 142 and the p-well extensions 136. Figure 2L A gate contact (not shown) to the gate electrode 184, outside the cross-section of FIG. 1, is typically connected via one or more gate buses (not shown).

[0115] As discussed above, the portion of each p-well 132 adjacent to the gate trench 180 acts as a vertical transistor channel 134. Thus, when a sufficient gate bias voltage is applied, current will flow from the source contact 190 to the drain contact 192 along the current path shown by the arrows in FIG. 1. Figure 2L As discussed above, the portion of each p-well 132 adjacent to the gate trench 180 acts as a vertical transistor channel 134. Thus, when a sufficient gate bias voltage is applied, current will flow from the source contact 190 to the drain contact 192 along the current path shown by the arrows in FIG. 1.

[0116] Figure 2M A plan view of the MOSFET 100 is shown in FIG. 2, and the method of forming the p-well extensions is known in the art. In addition, a trench shield connection region (not shown) can be provided in the active and / or non-active regions of the MOSFET 100 that electrically connects the p-well 132 to the trench shield region 170. A drain contact 192 is formed on the lower surface of the substrate 110. A source contact 190 is also provided that is electrically connected to the source regions 142 and the p-well extensions 136. Figure 2Lhorizontal cross-sections taken through the device shown in FIG. 1A (i.e., the cross-sections are taken along the top surface of the semiconductor layer structure 150). Figure 2M It is shown how the p-well extensions 136 can comprise a series of island-like structures that extend upward through the source regions 142 to the upper surface of the semiconductor layer structure 150. The p-well extensions 136 can be highly doped (p + ) type regions. The p-well extensions 136 electrically connect the p-well 132 to the source contact 190. It will be appreciated that, Figure 2M A possible design is illustrated in which the p-well extensions 136 are formed as islands in the source regions 142 when viewed from above. Other designs are possible. For example, Figure 2N A modified version of the MOSFET 100 is illustrated in which the p-well extensions 136 are formed as horizontal strips. Figure 2O Another modified version of the MOSFET 100 is illustrated in which the p-well extensions 136 are formed as vertical strips within the source regions 142.

[0117] The trench shield regions 170 help to protect the corners of the gate oxide layer 182 from high electric fields during reverse blocking operation. However, there is a trade-off between the on-resistance of the MOSFET 100 and the maximum electric field value that can occur in the gate oxide layer 182. In particular, the trench shield regions 170 create a so-called JFET region 176 in the drift layer. Current flows out of the source contact 190, through the channel 134 on its way to the drain contact 192, and then into this JFET region 176. If the trench shield regions 170 are wider than the gate trenches 180, then the trench shield region 170 associated with an adjacent gate trench 180 acts to narrow the width of the JFET region 176, which acts to increase the on-resistance of the MOSFET 100 (because the current is now forced to flow through a narrower region). This can be seen, for example, with reference to Figure 3A (as described above) in which the trench shield regions 180 are significantly wider than the gate trenches 180. In some applications, low on-resistance can be more important than high voltage rating. In such embodiments, it can be beneficial to keep the width Wl of the trench shield regions 170 less than or equal to the width W2 of their associated gate trenches 180.

[0118] Because the thickness of the second mask 166 formed on the sidewalls of the first mask 162 can be carefully controlled, the method of forming a power semiconductor device disclosed herein allows careful control of the relative widths of the trench shield regions 170 and the gate trenches 180, such that each trench shield region 170 can extend any desired width beyond the sidewalls of its associated gate trench 180. The method described herein also allows the designer to easily account for the widening of the gate trenches 180 that can occur during the sacrificial oxidation and / or hydrogen etch processing steps discussed above. In some applications, on-state resistance can be the limiting factor, while in other applications, the rated voltage can be more important. The techniques disclosed herein allow the designer to easily optimize the relative widths of the trench shield regions 170 and the gate trenches 180 in order to optimize performance for any particular application.

[0119] Another potential problem in the manufacture of gate trench power semiconductor devices is that the trench shield regions and the gate trenches of the device can not be aligned. In some conventional manufacturing techniques, different masks are used for the ion implantation step used to form the trench shield regions and the etching step used to form the gate trenches. If the second of these masks is not perfectly aligned with the position of the first mask, then the trench shield regions 170 will be misaligned laterally (i.e., in the y-direction) with respect to the corresponding gate trenches 180. If this occurs, then on one side of each gate trench 180, the trench shield region 170 will extend laterally beyond the gate trench 180, such that the JFET region 176 is narrowed, resulting in an increase in on-state resistance. This problem of lateral misalignment in conventional power semiconductor devices can be reduced or eliminated by reducing the width of the trench shield regions 170. However, as discussed above, reducing the width of the trench shield regions 170 reduces their effectiveness, and thus the rated voltage of the MOSFET 100, in order to keep the electric field generated in the gate oxide layer at a level that will not degrade the gate oxide. As described above, the techniques according to embodiments of the present application automatically self-align each trench shield region 170 with its associated gate trench 180, thereby avoiding the performance degradation associated with misalignment of the trench shield regions 170.

[0120] It will be recognized that in further embodiments, the processing steps discussed above with reference to Figures 2A-2M may be performed in different orders. As an example, the hydrogen etch step discussed with reference to Figure 2J may be performed prior to the sacrificial oxidation step discussed with reference to Figure 2K It will also be recognized that in other embodiments, some of the processing steps (e.g., the hydrogen etch step, the sacrificial oxidation, etc.) can be omitted.

[0121] Figures 2A-2MA method for forming the MOSFET 100 is illustrated in which spacers (e.g., oxide spacers) are deposited on the patterned first mask 162 as a second mask 166. According to further embodiments of the application, the second mask 166A can instead be formed by oxidizing the first mask 162A. This is schematically shown in Figure 4 Figure 4 Figure 2D corresponding.

[0122] As shown in Figure 4 , in embodiments of the application in which the second mask 166A is formed by oxidation, the first mask 162A can be formed using an easily oxidizable material, such as polysilicon. Once the first mask 162A has been patterned, as discussed above with reference to Figure 2D , the second mask 166A can be formed by performing an oxidation process on the device (e.g., heating the device in an oxygen-containing environment). Since polysilicon is more easily oxidized than silicon carbide, the thickness of the second mask 166A formed on the upper surface and sidewalls of the polysilicon first mask 162A is thicker than the thickness on the exposed portions of the upper surface of the semiconductor layer structure 150. As discussed above with reference to Figure 2E , the oxidized material formed on the exposed portions of the upper surface of the semiconductor layer structure 150 can then be removed, or can be left in place, such that the ion implantation steps discussed above with reference to Figure 2F are performed by the oxidized silicon carbide material. The device shown in Figures 2D-2M can then be fabricated using the same processing steps as discussed above with reference to Figure 4 , and therefore further description thereof will be omitted here.

[0123] Figures 5A-5F is a schematic cross-sectional view of a gate trench power MOSFET 200 according to further embodiments of the application. More specifically, Figures 5A-5E is a schematic vertical cross-sectional view illustrating a method of fabricating a semiconductor layer structure of the MOSFET 200. Figure 5F is a schematic horizontal cross-sectional view of the MOSFET 200 taken along the line 5F-5F of Figure 5E .

[0124] Referring to Figure 5A , an optional spacer (e.g., nitride spacer) 265 can be formed on the upper surface of the semiconductor layer structure 150. The semiconductor layer structure 150 can be fabricated using the same processing steps as discussed above with reference to Figures 2A-2B ​​The discussed approach forms. A mask 262 is then formed over spacers 266 (or, if spacers 266 are not provided, over the upper surface of semiconductor layer structure 150). Mask 262 can comprise, for example, an oxide mask (e.g., silicon oxide). Mask 262 is patterned (e.g., using standard photolithographic patterning techniques) to form openings 264 and 266 that expose selected portions of semiconductor layer structure 150. Openings 264 can be positioned over locations in semiconductor layer structure 150 where trench shield regions will be formed in subsequent process steps. Openings 266 can be positioned over locations in semiconductor layer structure 150 where trench support shields will be formed in subsequent process steps. It will be recognized that, in some embodiments, trench support shields can be omitted. In such embodiments, openings 266 are not formed in mask 262.

[0125] Referring to Figure 5B , a high-energy "deep" ion implant process is performed to implant p-type dopant ions through openings 264, 266. Due to the high energy level of the implant, most of the p-type ions are implanted through source layer 140, p-well layer 130, and into drift region 120. Thus, after the ion implant step is performed, source layer 140 can remain n-type, and in some cases, portions of drift layer 120 directly below p-well layer 130 can also remain n-type after the ion implant process is completed. As shown in Figure 5B , the ion implant process forms a plurality of buried preliminary trench shield regions 272 in semiconductor layer structure 150. Preliminary trench shield regions 272 can be heavily doped (p + ) silicon carbide regions having any of the doping concentrations listed above for preliminary trench shield regions 172. Preliminary trench shield regions 272 can likewise extend to any of the depths listed above for preliminary trench shield regions 172. As further shown in Figure 5B , the ion implant process also forms a plurality of buried trench support shields 274 in semiconductor layer structure 150. Trench support shields 274, if included in the device, can be heavily doped (p + ) silicon carbide regions. Trench support shields 274 can serve to reduce the level of electric field formed in the gate oxide layer (discussed below) during device operation. Trench support shields 274 can also provide a low-resistance current path between the source and drain terminals of MOSFET 200 if avalanche breakdown occurs. This lower-resistance current path helps to reduce the amount of heat generated by the device during an avalanche breakdown event, increasing the likelihood that MOSFET 200 can survive such an event without being damaged.

[0126] As shown in Figure 5BIt can also be seen that the p-type dopant ions scatter to some extent upon impinging upon the protons and neutrons that constitute the semiconductor layer structure 150. This results in the preliminary trench shield regions 272 and the trench support shield 274 to "bloom" in the sense that the width of the preliminary trench shield regions 272 increases with depth from the upper surface of the semiconductor layer structure 150. Note that in Figure 5B In the example shown in FIG. 2, the mask 262 is used as an etch mask for forming both the preliminary trench shield regions 172 and the trench support shield 274. It will be appreciated that in other embodiments, separate masks and ion implantation steps can be used to form the preliminary trench shield regions 172 and the trench support shield 274. In such embodiments, the preliminary trench shield regions 172 can be formed, for example, using a high-energy "deep" ion implantation process (and thus will have the shape shown in FIG. 2), while the trench support shield 274 can be formed using a shallow and deep ion implantation process. This can allow the trench support shield 274 to extend farther toward the upper surface of the semiconductor layer structure 150, such that the trench support shield 274 is physically and electrically connected to the P-well layer 130. Figure 5B

[0127] Referring to Figure 5C An additional mask material can be formed to fill the openings 266 while leaving the openings 264 intact. For example, a selective oxide deposition can be performed to fill the openings 266. Next, a plurality of gate trenches 180 are formed in the upper surface of the semiconductor layer structure 150 via etching. The gate trenches 180 are formed using the mask 262 as an etch mask. Each gate trench 180 extends into the upper surface of the n-type drift region 120. Although Figure 5C Only one complete gate trench 180 and a portion of a second gate trench 180 are shown, but it will be appreciated that a large number of gate trenches 180 are typically provided, as discussed above with reference to the MOSFET 100. The gate trenches 180 convert the moderately doped p-type silicon carbide well layer 130 into a plurality of moderately doped p-wells 132, and convert the heavily doped n-type silicon carbide source layer 140 into a plurality of heavily doped n-type source regions 142. The portion of each p-well 132 that is adjacent to a gate trench 180 acts as a transistor channel 134. Although Figure 5C Devices having a plurality of gate trenches 18 all extending parallel to one another in a first direction are illustrated, as discussed above with reference to the MOSFET 100, but embodiments of the present invention are not limited thereto.

[0128] The etching step performed to form the gate trenches 180 can remove an upper portion of each preliminary trench shield region 272, thereby forming a plurality of trench shield regions 270 beneath the respective gate trenches 180.

[0129] Referring to Figure 5D ​, the mask 262 and the optimized spacer 265 can be removed. Afterwards, a sacrificial oxidation process and / or hydrogen etching can be performed. Since these processes can be similar to those described above with reference to Figures 2J-2K The discussed process is the same, so further description thereof will be omitted here.Afterwards, an annealing process to activate the p-type dopant in the trench shield region 270 may be performed.

[0130] like Figure 5E As shown in the above reference Figure 2L The gate oxide layer 182, gate electrode 184, intermetallic dielectric layer 186, source contact 190, and drain contact 192 are formed in the manner discussed above to form MOSFET 200. MOSFET 200 may also include p-well extensions 136 that physically and electrically connect p-well 132 to source contact 190. These p-well extensions 136 are formed in the manner discussed above to form MOSFET 200. Figure 5F Furthermore, a trench shield connection region (not shown) that electrically connects the p-well 132 to the trench shield region 170 may be provided in the active region and / or the inactive region of the MOSFET 200 .

[0131] Figure 5F It passes along line 5F-5F Figure 5E The device shown in FIG. 1 is taken in a horizontal cross-section (ie, the cross-section is taken along the top surface of the semiconductor layer structure 150 ). Figure 5F It shows how the p-well extension 136 can include a series of islands extending upward through the source region 142 to the upper surface of the semiconductor layer structure 150. The p-well extension 136 can be a highly doped (p + ). The p-well extension 136 electrically connects the p-well 132 to the source contact 190.

[0132] The upper surface of the preliminary trench shielding region 272 of the MOSFET 200 is formed at a depth from the top surface of the semiconductor layer structure 150 that is less than the depth of the gate trench 180. Therefore, the gate trench 180 (see FIG. 1 ) is created. Figure 5C ) removes an upper portion of each preliminary trench shield region 272 to form trench shield region 270. However, it will be appreciated that in further embodiments of the present invention, a MOSFET may be provided in which the preliminary trench shield region 272 is formed so that its upper surface is at a depth in the semiconductor layer structure 150 that is lower than the depth of the bottom of the gate trench 180. In such a MOSFET, the formation of the gate trench does not alter the preliminary trench shield region 272, and thus the trench shield region 270 may be the same as the preliminary trench shield region 272. Figure 6 is a schematic cross-sectional view of MOSFET 300 having such a configuration.

[0133] As can be seen from the figure, Figure 6MOSFET 300 is very similar to the MOSFET 200 of Figure 5E The MOSFET 200 of FIG. 2B is very similar to the MOSFET 200 of FIG. 2A, except that the trench shield regions 270 and the trench support shields 274 are formed deeper in the semiconductor layer structure 150. As a result of this change, a portion of the lightly doped n-type drift region 120 is interposed between each trench shield region 270 and its associated gate trench 180. As the trench shield regions extend deeper into the semiconductor layer structure 150, this design can further protect the gate oxide layer 182 that lines the bottom of the respective gate trench 180.

[0134] Figure 7 is a flowchart illustrating a method for fabricating a gate trench semiconductor device, such as, for example, a power wide bandgap gate trench semiconductor device, in accordance with an embodiment of the present application.

[0135] As shown in FIG. 2A, a first mask is formed over a semiconductor layer structure ("SLS") (operation 200). The first mask includes a first opening having a first width. A spacer is formed on sidewalls of the first mask exposed by the first opening to form a second mask (operation 210). The first and second masks constitute a mask structure having a second opening that has a second width that is less than the first width. Doping is implanted through the second opening into the semiconductor layer structure to form an implanted region in the semiconductor layer structure (operation 220). The spacer is then at least partially removed from the sidewalls of the first mask to form a third opening in the mask structure (operation 230). The semiconductor layer structure is then etched using the mask structure as an etch mask to form a gate trench in the semiconductor layer structure under the third opening (operation 240). Figure 7

[0136] is a flowchart illustrating a method for fabricating a gate trench semiconductor device, such as a power wide bandgap gate trench semiconductor device, in accordance with a further embodiment of the present application. Figure 8 As shown in FIG. 2A, a first mask is formed over a semiconductor layer structure ("SLS") (operation 200). The first mask includes a first opening having a first width. A spacer is formed on sidewalls of the first mask exposed by the first opening to form a second mask (operation 210). The first and second masks constitute a mask structure having a second opening that has a second width that is less than the first width. Doping is implanted through the second opening into the semiconductor layer structure to form an implanted region in the semiconductor layer structure (operation 220). The spacer is then at least partially removed from the sidewalls of the first mask to form a third opening in the mask structure (operation 230). The semiconductor layer structure is then etched using the mask structure as an etch mask to form a gate trench in the semiconductor layer structure under the third opening (operation 240).

[0137] Figure 8 As shown in FIG. 2A, a first mask is formed over a semiconductor layer structure ("SLS") (operation 200). The first mask includes a first opening having a first width. A spacer is formed on sidewalls of the first mask exposed by the first opening to form a second mask (operation 210). The first and second masks constitute a mask structure having a second opening that has a second width that is less than the first width. Doping is implanted through the second opening into the semiconductor layer structure to form an implanted region in the semiconductor layer structure (operation 220). The spacer is then at least partially removed from the sidewalls of the first mask to form a third opening in the mask structure (operation 230). The semiconductor layer structure is then etched using the mask structure as an etch mask to form a gate trench in the semiconductor layer structure under the third opening (operation 240).

[0138] ​In the above description, each example embodiment has a specific conductivity type. It will be recognized that by simply reversing the conductivity of the n-type and p-type layers in each of the above embodiments, devices of the opposite conductivity type can be formed. Thus, it will be recognized that the present application covers both n-channel and p-channel devices for each of the different device structures (e.g., MOSFET, IGBT, etc.).

[0139] The present application has been discussed above primarily with respect to silicon carbide-based power semiconductor devices. However, it will be recognized that silicon carbide is used herein as an example, and that the devices discussed herein can be formed in any appropriate wide bandgap semiconductor material system. As an example, in any of the above embodiments, gallium nitride-based semiconductor materials (e.g., gallium nitride, aluminum gallium nitride, etc.) can be used in place of silicon carbide.

[0140] Embodiments of the present application have been described above with reference to the accompanying drawings, in which embodiments of the application are shown. However, it will be recognized that the application can be embodied in many different forms and should not be interpreted as limited to the embodiments set forth above. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art. Throughout the disclosure, like reference numerals refer to like elements.

[0141] In this document, the term "a plurality" means two or more. In this document, "substantially" means within + / - 10%.

[0142] It will be understood that, although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present application. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0143] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this document, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0144] It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements can also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0145] Relative terms such as "below" or "above" or "upper" or "lower" or "top" or "bottom" can be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0146] Embodiments of the present application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Additionally, as used herein the expression "from about a to about b" or "between about a and b" indicates the range between about a and about b inclusive. Embodiments of the present application are also described with reference to block diagrams and flowchart illustrations of methods, apparatuses and computer program products. It will be understood that each block of the block diagrams and flowchart illustrations, and combinations of blocks in the block diagrams and flowchart illustrations, can be implemented by computer program instructions. Such computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, implement the functions specified in the block diagrams and flowchart illustrations.

[0147] Some embodiments of the present application are described with reference to semiconductor layers and / or regions that are characterized as having a conductivity type, such as n-type or p-type, which refers to the majority carrier concentration in the layer and / or region. Thus, an n-type material has a majority equilibrium concentration of negatively charged electrons, while a p-type material has a majority equilibrium concentration of positively charged holes. A certain material can be designated with a "+" or "-" (e.g., n+, n-, p+, p-, n++, n--, p++, p--, etc.) to indicate a relatively large ("+") or small ("-") majority carrier concentration as compared to another layer or region. However, such notation does not imply the presence of a particular concentration of majority or minority carriers in the layer or region.

[0148] In the drawings and specification, there have been disclosed typical embodiments of the application and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the application being set forth in the following claims.

Claims

1. A semiconductor device comprising a wide bandgap semiconductor layer structure, the wide bandgap semiconductor layer structure comprising: a drift region having a first conductivity type; a well region having a second conductivity type located on the drift region; a source region having the first conductivity type located on the well region; a gate electrode located within a gate trench; and a trench shield region having the second conductivity type located below the gate trench, wherein a width of the trench shield region exceeds a width of the gate trench.

2. The semiconductor device of claim 1, wherein the trench shield region is formed below the gate trench and extends onto lower portions of opposing sidewalls of the gate trench.

3. The semiconductor device of claim 1, wherein the gate trench has left and right sidewalls extending parallel to a longitudinal axis of the gate trench, the left and right sidewalls being spaced apart from each other in a lateral direction, and wherein a left lateral extent of the trench shield region exceeds a lower edge of the left sidewall of the gate trench by at least 0.1 microns, and a right lateral extent of the trench shield region exceeds a lower edge of the right sidewall of the gate trench by at least 0.1 microns.

4. The semiconductor device of any one of claims 1-3, wherein the gate trench has left and right sidewalls extending parallel to a longitudinal axis of the gate trench, the left and right sidewalls being spaced apart from each other in a lateral direction, and wherein the gate trench overlaps less than 95% of a lateral width of the trench shield region.

5. The semiconductor device of any one of claims 1-4, wherein lower corners of the gate trench are rounded corners.

6. The semiconductor device of any one of claims 1-5, wherein the drift region, the well region, the source region, and the shield region each comprise silicon carbide.

7. The semiconductor device of any one of claims 1-6, wherein the trench shield region extends continuously across an entire width of the gate trench.

8. A semiconductor device comprising a wide bandgap semiconductor layer structure, the wide bandgap semiconductor layer structure comprising: a drift region having a first conductivity type; a well region having a second conductivity type located on the drift region; a source region having the first conductivity type located on the well region; a gate electrode located within a gate trench; and a trench shield region having the second conductivity type located below the gate trench, wherein a portion of the drift region having the first conductivity type is interposed between a bottom surface of the gate trench and the trench shield region.

9. The semiconductor device of claim 8, wherein the gate trench has left and right sidewalls extending parallel to a longitudinal axis of the gate trench, the left and right sidewalls being spaced apart from each other in a lateral direction, and wherein a left lateral extent of the trench shield region exceeds a lower edge of the left sidewall of the gate trench by at least 0.1 microns, and a right lateral extent of the trench shield region exceeds a lower edge of the right sidewall of the gate trench by at least 0.1 microns.

10. The semiconductor device of claim 8, wherein the gate trench has left and right sidewalls extending parallel to a longitudinal axis of the gate trench, the left and right sidewalls being spaced apart from each other in a lateral direction, and wherein the gate trench overlaps less than 95% of a lateral width of the trench shield region. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 11. The semiconductor device of any of claims 8-10, wherein lower corners of the gate trench are rounded corners.

12. The semiconductor device of any of claims 8-10, wherein the trench shield region extends continuously across an entire width of the gate trench.

13. A method of forming a semiconductor device, the method comprising: forming a first mask on a semiconductor layer structure, the first mask including a first opening having a first width that extends longitudinally; forming a spacer on sidewalls of the first mask exposed by the first opening to form a second mask, the first mask and the second mask including a mask structure having a second opening that extends longitudinally, the second opening having a second width that is less than the first width; implanting a dopant into the semiconductor layer structure through the second opening to form an implant region in the semiconductor layer structure; removing the spacer at least partially from the sidewalls of the first mask to form a third opening in the mask structure; and etching the semiconductor layer structure using the mask structure as an etch mask to form a gate trench in the semiconductor layer structure beneath the third opening.

14. The method of claim 13, wherein the second mask includes silicon.

15. The method of claim 14, wherein the second mask further includes oxygen.

16. The method of claim 13, wherein the first mask includes both silicon and nitrogen.

17. The method of any of claims 13-16, wherein forming the spacer on the sidewalls of the first mask exposed by the first opening to form the second mask includes oxidizing the sidewalls of the first mask exposed by the first opening.

18. The method of claim 13, wherein the implant region is located beneath the gate trench and a width of the implant region is greater than a width of the gate trench.

19. The method of claim 18, wherein the implant region extends onto lower portions of opposing sidewalls of the gate trench.

20. The method of any of claims 13-16, wherein lower corners of the gate trench are rounded corners.

21. The method of claims 13-16, wherein the drift region, the well region, the source region, and the shield region each include silicon carbide.

22. The method of claims 13-16, wherein the semiconductor layer structure includes a drift region having a first conductivity type, a well region having a second conductivity type, and a source region having the first conductivity type, wherein at least a portion of the well region is positioned between the drift region and the source region, and the implant region has the second conductivity type.

23. The method of claims 13-16, wherein the implant region is self-aligned with the gate trench.

24. The method of claims 13-16, further comprising removing some but not all of a portion of the second mask within the second opening prior to implanting the dopant into the semiconductor layer structure.

25. The method of claims 13-16, wherein etching the semiconductor layer structure using the mask structure as an etch mask to form the gate trench in the semiconductor layer structure beneath the third opening exposes the implant region. ​ 26. The method of claims 13-16, further comprising: After etching the semiconductor layer structure using the mask structure as an etch mask to form a gate trench in the semiconductor layer structure under the third opening, an oxidation process is performed on the semiconductor layer structure, and then the oxidized portions of the semiconductor layer structure are removed.

27. The method of claims 13-16, further comprising: After etching the semiconductor layer structure using the mask structure as an etch mask to form a gate trench in the semiconductor layer structure under the third opening, the semiconductor layer structure is annealed in a hydrogen-containing environment.

28. The method of claims 13-16, wherein removing the spacers from the sidewalls of the first mask at least partially to form the third opening in the mask structure comprises removing the spacers from the sidewalls of the first mask completely, such that the third opening has a first width.

29. A method of forming a semiconductor device, the method comprising: forming a first mask on a semiconductor layer structure, the first mask comprising a first opening; forming spacers on sidewalls of the first mask exposed by the first opening to form a second mask, the first mask and the second mask comprising a mask structure having a second opening; implanting a dopant into the semiconductor layer structure through the second opening to form an implanted region in the semiconductor layer structure; removing the spacers from the sidewalls of the first mask at least partially; and etching the semiconductor layer structure to form a gate trench self-aligned to the implanted region.

30. The method of claim 29, wherein the semiconductor layer structure is a wide bandgap semiconductor layer structure comprising a drift region having a first conductivity type, a well layer having a second conductivity type, and a source region having the first conductivity type on the well layer, and wherein the dopant implanted into the semiconductor layer structure through the second opening is a second conductivity type dopant.

31. The method of claim 30, wherein at least partially removing the spacer from the sidewalls of the first mask comprises: removing the spacers from the sidewalls of the first mask completely, such that the semiconductor layer structure is etched using only the first mask as an etch mask.

32. The method of claim 30, wherein the implanted region is a trench shield region having the second conductivity type.

33. The method of claim 29, wherein the second opening exposes the semiconductor layer structure.

34. The method of claim 29, wherein the spacers cover the semiconductor layer structure exposed by the first opening, such that the second opening does not expose the semiconductor layer structure.

35. The method of claim 29, further comprising, after etching the semiconductor layer structure to form the gate trench: removing the first mask; oxidizing exposed portions of the semiconductor layer structure; and removing the oxidized portions of the semiconductor layer structure.

36. The method of claim 29, further comprising, after etching the semiconductor layer structure to form the gate trench: rounding a bottom corner of the gate trench; and activating the implanted second conductivity dopant.

37. The method of claim 29, wherein the second mask comprises silicon.

38. The method of claim 37, wherein the second mask further comprises oxygen.

39. The method of claim 38, wherein the first mask comprises both silicon and nitrogen.

40. The method of any of claims 29-39, wherein forming spacers on sidewalls of the first mask exposed by the first openings to form a second mask comprises: oxidizing the sidewalls of the first mask.

41. The method of any of claims 29-39, wherein the implanted region is located under the gate trench, and a width of the implanted region is greater than a width of the gate trench.

42. The method of claim 41, wherein the implant region extends onto lower portions of opposite sidewalls of the gate trench.

43. A method of forming a semiconductor device, the method comprising: providing a semiconductor layer structure, the semiconductor layer structure comprising a drift region having a first conductivity type, a well region having a second conductivity type on the drift region, and a source region having the first conductivity type on the well region; forming a first mask on the semiconductor layer structure, the first mask comprising a first opening; implanting a second conductivity type dopant into the semiconductor layer structure through at least a portion of the semiconductor layer structure exposed by the first opening to form an implant region having the second conductivity type in the drift region, wherein after implanting the second conductivity type dopant into the semiconductor layer structure, a portion of the source region exposed by the first opening still has the first conductivity type.

44. The method of claim 43, wherein after implanting the second conductivity type dopant into the semiconductor layer structure, a portion of the drift region between the well region and the implant region still has the first conductivity type.

45. The method of claim 44, wherein the first opening is a first opening that is longitudinally extending and has a first width, the method further comprising forming a spacer on sidewalls of the first mask exposed by the first opening to form a second mask, the first mask and the second mask comprising a mask structure having a second opening that is longitudinally extending and has a second width that is less than the first width, wherein implanting second conductivity type dopants into the semiconductor layer structure through the portion of the semiconductor layer structure exposed by the first opening to form an implanted region having the second conductivity type in the drift region comprises: implanting the second conductivity type dopant into the semiconductor layer structure through the second opening.

46. The method of claim 45, further comprising: at least partially removing the spacer from the sidewalls of the first mask to form a third opening in the mask structure; and etching the semiconductor layer structure using the mask structure as an etch mask to form a gate trench in the semiconductor layer structure under the third opening.

47. The method of claim 45, wherein the first mask comprises a material that contains both silicon and nitrogen, and the second mask comprises silicon.

48. The method of claim 47, wherein the second mask further comprises oxygen.

49. The method of claim 46, wherein the implant region is under the gate trench and has a width that is greater than a width of the gate trench.

50. The method of claim 49, wherein the implant region extends onto lower portions of opposite sidewalls of the gate trench.

51. The semiconductor device of claim 1, wherein the trench shield region defines a bottom of the gate trench.

52. The semiconductor device of claim 1, wherein the gate trench has a left sidewall and a right sidewall that extend parallel to a longitudinal axis of the gate trench, the left sidewall and the right sidewall being spaced apart from each other in a lateral direction, and wherein a left side of the trench shield region laterally extends at least 0.3 microns beyond a lower edge of the left sidewall of the gate trench, and a right side of the trench shield region laterally extends at least 0.3 microns beyond a lower edge of the right sidewall of the gate trench.

53. The semiconductor device of Claim 8, wherein the gate trench has a left sidewall and a right sidewall that extend parallel to a longitudinal axis of the gate trench, the left sidewall and the right sidewall being spaced apart from one another in a lateral direction, and wherein the left side of the trench shield region laterally extends at least 0.3 microns beyond a lower edge of the left sidewall of the gate trench, and the right side of the trench shield region laterally extends at least 0.3 microns beyond a lower edge of the right sidewall of the gate trench.

Images