Tri-binary converter realized by using on-chip optical mode

Abstract

The invention discloses a tri-binary converter realized by using an on-chip optical mode, and belongs to the technical field of integrated photoelectronics. The converter mainly comprises an input waveguide, an optical switch and an output area. An input optical signal is routed to three different paths through the optical switch under the control of an electric signal; the output area directly converts the optical signals representing each bit of the ternary system into different optical mode combinations representing specific binary weights through a mode conversion and mapping structure; finally, light intensity of each mode is detected in parallel through a photoelectric detector and converted into an electric signal, and a binary result is output after summation of an electrical full adder. By utilizing the parallelism of the optical mode, the speed bottleneck and the decimal transfer link of the traditional electronic conversion are avoided, the high-speed data conversion device has the advantages of high speed, low power consumption and high parallelism, and an efficient data conversion interface is provided for ternary and binary computing systems.

Description

Technical Field

[0001] This invention belongs to the field of optoelectronics and relates to an on-chip binary converter, specifically a three-to-binary converter implemented on-chip using optical modes and electro-optic and opto-electric converters. Background Technology

[0002] In modern digital systems, binary (base-2) has become the absolute mainstream in computers and digital information processing due to its simple physical implementation, clear logical operation rules, and high compatibility with Boolean algebra. However, in recent years, non-binary computing models have regained attention, especially ternary (base-3) systems. Ternary systems use three symbols (e.g., 0, 1, 2, or -1, 0, +1 in balanced ternary), and the information capacity of a single ternary digit (Trit) is approximately log₂₃ ≈ 1.584 bits, higher than a binary bit. This characteristic allows the same number of bits to represent a wider range of values ​​or more complex states in ternary systems, or fewer bits to represent the same value, thus offering potential efficiency advantages in specific applications.

[0003] Historically, although ternary computers have not become mainstream, there have been landmark applications. For example, the Soviet Union's Setun computer, developed in the 1950s, successfully employed a balanced ternary system, demonstrating the advantages of ternary in operational symmetry, hardware simplification (such as multiplier design), and high reliability and energy efficiency. Despite limitations imposed by engineering and industrial ecosystems, ternary systems remain of significant research value in quantum computing (three-state qubits), fault-tolerant computing, high-density numerical representation, and certain specialized data processing fields.

[0004] With the resurgence of ternary computing models, the need for efficient and accurate conversion between ternary and binary systems has become increasingly prominent. As a key interface connecting these two computing architectures, the performance of ternary-to-binary converters directly impacts the overall system throughput, latency, and energy efficiency. Traditional electronic conversion schemes are often limited by the serial processing characteristics and latency accumulation of electronic devices, making it difficult to meet the demands of high-speed, high-parallelism applications.

[0005] Optical computing technology, with its advantages of high bandwidth, low latency, high parallelism, and resistance to electromagnetic interference, provides a new technological path for binary number conversion. In particular, the development of integrated photonics has made it possible to realize complex optical networks on chips, laying the foundation for building optical domain 3-to-2-binary converters. By using optical modes to represent different weights and combining electro-optic modulation and photoelectric detection, high-speed, parallel binary number conversion processes can be achieved, significantly improving conversion efficiency and system compatibility.

[0006] Therefore, it is necessary to propose a novel three-to-binary converter based on on-chip optical mode, which can fully utilize the parallel processing capability of photons, overcome the speed bottleneck in traditional electronic conversion, and provide a transparent and efficient data conversion interface for future heterogeneous computing systems. Summary of the Invention

[0007] The present invention aims to solve the following problems existing in the prior art: Traditional electronic ternary-to-binary converters are limited by the serial processing characteristics of electronic devices, and the conversion speed is a bottleneck, making it difficult to meet the needs of high-speed and high-parallel data processing; while the scheme of directly using optical computing to realize the conversion often faces technical challenges such as complex system structure, difficulty in controlling mode crosstalk, large optical power loss, and poor compatibility with traditional electronic systems.

[0008] To address the aforementioned technical problems, this invention provides a three-to-two converter implemented using on-chip optical modes. Its core lies in adopting an optoelectronic collaborative architecture, controlling the optical path state through electrical signals, directly completing the number system mapping by utilizing the parallelism of optical modes, and finally achieving complete conversion through electrical summation.

[0009] The converter includes: The input section is used to receive the input waveguide carrying the optical signal; The electro-optical conversion and routing section includes at least one optical switch, which is used to receive an electrical signal representing a ternary digit and to route the input optical signal to one of three output waveguides according to the logic level of the electrical signal. The mode mapping and conversion section is optically connected to the output waveguide of the electro-optic conversion and routing section. It is used to map the input optical signal into a specific optical mode combination representing binary weights according to the weights of the ternary digits and output the signal, where different optical modes represent different bit weights of the binary number. The detection section includes multiple photodetectors for detecting the optical power of a specific optical mode output by the mode mapping and conversion section, and converting it into a corresponding electrical signal; The adder is used to sum multiple sets of binary electrical signals output by the probe section, each representing a different ternary digit weight, and output the final binary number.

[0010] Furthermore, the mode mapping and conversion section includes a mode converter, a beam splitter, and a waveguide structure, used to realize mode conversion, splitting and combining, or dissipation of optical signals.

[0011] Furthermore, the optical switch is preferably a microring resonator type optical switch or a Mach-Zehnder interferometer type optical switch.

[0012] Furthermore, the optical mode is the transverse electric mode TE in a silicon-based optical waveguide.m In this context, TE0 mode represents the least significant bit, TE1 mode represents the second bit, and higher-order TE... m The pattern represents the higher bits of the binary representation.

[0013] Furthermore, the specific architecture of the pattern mapping and conversion part is customized according to the weights of the ternary digits being processed.

[0014] Furthermore, the detection section performs detection of multiple optical modes in parallel.

[0015] Furthermore, the adder is an electrical binary full adder.

[0016] Compared with the prior art, the three-to-binary converter implemented using on-chip optical modes provided by the present invention has the following significant advantages: 1. High speed and low latency: By utilizing the inherent characteristics of optical signals and the parallel transmission capability of optical modes, the mapping process from ternary bits to binary is completed in parallel in the optical domain, which greatly improves the conversion speed and avoids the cascading delay problem in pure electronic conversion. 2. High parallelism and high efficiency: By carrying information with different binary bit weights in parallel through different optical modes, true parallel processing is achieved. Multiple bit mappings can be completed in a single operation, resulting in high processing throughput. 3. Compact structure and low power consumption: The solution is based on mature on-chip photonic integration technology, and all optical functional units can be integrated on the same chip. The system structure is compact and small in size, and optical computing itself has the advantage of low power consumption. 4. Excellent compatibility: It innovatively adopts a hybrid architecture of "electro-optical computing - photoelectric conversion - electrical summation". The front end uses the advantages of electrical signals for easy control and storage to set the state, the middle end uses light for high-speed parallel computing, and finally outputs a standard electrical signal, which is perfectly compatible with existing binary computing systems and realizes seamless bridging between heterogeneous computing systems; 5. Flexibility and scalability: By customizing its pattern mapping architecture for ternary digits with different weights, this scheme can be scaled up to ternary-to-binary conversion with more bits in principle, providing a feasible path for future large-scale optical computing systems. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the optical chip architecture of the present invention.

[0018] Figure 2 This is a schematic diagram of the output area architecture for the least significant bit of a ternary signal, as described in this invention.

[0019] Figure 3 This is a schematic diagram of the output area architecture for the second bit of a ternary signal in this invention.

[0020] Figure 4 This is a schematic diagram of the output area architecture for the third bit of a ternary signal in this invention.

[0021] Figure 5 This is a schematic diagram of the overall process for implementing the least significant bit conversion of a ternary signal according to the present invention.

[0022] Figure 6 This is a schematic diagram of the overall process for implementing the second bit conversion of a ternary signal according to the present invention.

[0023] Figure 7 This is a schematic diagram of the overall process for implementing the conversion of the third bit of a ternary signal in this invention.

[0024] Figure 8 This is a schematic diagram of the photoelectric conversion and electrical summation part of the present invention. Detailed Implementation

[0025] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings. This embodiment uses the conversion of a three-bit ternary number (C1B1A1) into a five-bit binary number (E2D2C2B2A2) as an example for illustration, but the present invention is not limited thereto, and those skilled in the art can extend it to more bits based on the same principle.

[0026] 1. Overall Architecture The present invention utilizes optical modes to implement a three-to-two converter architecture, as follows: Figure 1 As shown, it is mainly divided into three parts: The first part is the first waveguide, which is used to input optical signals.

[0027] The second part is an optical switch, which realizes the conversion between electrical signals and optical signals. When a ternary electrical signal is input, it can be distributed to different optical paths through different levels.

[0028] The third part is the output area, which will be adjusted according to different bit lengths. It uses optical mode to realize the conversion of ternary signals to binary.

[0029] 2. Specific implementation of the optical switch section The optical switch can be either a microring resonator type or a Mach-Zehnder interferometer type. The choice depends on the application scenario, including using the microring resonator type in high-integration scenarios and choosing the Mach-Zehnder type when a larger bandwidth is required.

[0030] After the lowest level electrical signal (e.g., 0 in 0, 1, 2 and -1 in -1, 0, 1) is applied to the optical switch, the optical signal is output from the second waveguide.

[0031] After a signal with an intermediate level (e.g., 1 in 0, 1, 2 and 0 in -1, 0, 1) is applied to the optical switch, the optical signal is output in the third waveguide.

[0032] After the highest level signal (e.g., 2 in 0, 1, 2 and 1 in -1, 0, 1) is loaded onto the optical switch, the optical signal is output in the fourth waveguide.

[0033] 3. Specific implementation of the pattern mapping and conversion section This invention utilizes different modes to load binary signals. The least significant bit in the binary signal is represented by TE0, the second bit by TE1, the third bit by TE2, the fourth bit by TE3, and the fifth bit by TE4. That is, E2, D2, C2, B2, and A2 in the five-bit binary signal E2D2C2B2A2 can be loaded into TE4, TE3, TE2, TE1, and TE0 modes, respectively.

[0034] 3.1 Processing of bit A1 (least significant bit) (corresponding to...) Figure 2 and Figure 5 ) After inputting the optical mode of TE0 at the optical input port, the second part of the optical switch is entered, and the electrical signal of A1 is loaded onto the optical switch.

[0035] When A1 is 0: the light is switched to the waveguide with electrical input 0 (second waveguide) and outputs in TE0 mode. In the third part, the TE0 in the waveguide with electrical input 0 is dissipated by a dissipation scheme, so no signal detection is required, and the corresponding binary signal is 00000.

[0036] When A1 is 1: the light is switched to the waveguide with electrical input 1 (the third waveguide) and output in TE0 mode. In the third part, TE0 in the waveguide with electrical input 1 does not need to be changed. It is directly output as TE0 and the optical power of TE0 is detected. The corresponding binary signal is 00001.

[0037] When A1 is 2: the light is switched to the waveguide (fourth waveguide) with electrical input 2 and output in TE0 mode. In the third part, the TE0 in the waveguide with electrical input 2 is converted to TE1 mode by the mode converter, output in TE1 and the optical power of TE1 is detected, the corresponding binary signal is 00010.

[0038] 3.2 Processing of B1 bit (second bit) (corresponding to) Figure 3 and Figure 6 ) After inputting the optical mode of TE0 at the optical input port, the second part of the optical switch is entered, and the electrical signal of B1 is loaded onto the optical switch.

[0039] When B1 is 0: the light is switched to the waveguide with electrical input 0 and output in TE0 mode. The optical signal is dissipated and does not require detection, corresponding to 00000.

[0040] When B1 is 1: the light is switched to the waveguide with electrical input 1 and output in TE0 mode. In the third part, a portion of TE0 is converted to TE1 mode by a mode converter, while the other portion continues to be output in TE0 in the original waveguide. The optical power of TE0 and TE1 is detected, and the corresponding binary signal is 00011.

[0041] When B1 is 2: the light is switched to the waveguide of electrical input 2 and output in TE0 mode. In the third part, a portion of the power of TE0 is converted to TE2 mode by a mode converter, and the other portion is converted to TE1 mode by a mode converter. The optical power of TE2 and TE1 is detected, and the corresponding binary signal is 00110.

[0042] 3.3 Processing of C1 bit (third bit) (corresponding to) Figure 4 and Figure 7 ) After inputting the optical mode of TE0 at the optical input port, the second part of the optical switch is entered, and the electrical signal of C1 is loaded onto the optical switch.

[0043] When C1 is 0: the light is switched to the waveguide with electrical input 0 and output in TE0 mode. The optical signal is dissipated and does not require detection, corresponding to 00000.

[0044] When C1 is 1: the light is switched to the waveguide with electrical input 1 and output in TE0 mode. In the third part, a portion of TE0 is converted to TE3 mode by a mode converter, while the other portion continues to be output in TE0 in the original waveguide. The optical power of TE0 and TE3 is detected, and the corresponding binary signal is 01001.

[0045] When C1 is 2: the light is switched to the waveguide of electrical input 2 and output in TE0 mode. In the third part, a portion of the power of TE0 is converted to TE4 mode by a mode converter, and the other portion is converted to TE1 mode by a mode converter. The optical power of TE4 and TE1 is detected, and the corresponding binary signal is 10010.

[0046] 4. Photoelectric detection and final calculation Different modes output from different ports, and each output channel requires a single detector to detect light intensity. On-chip detectors and off-chip detector solutions are relatively mature.

[0047] The optical signals collected from three different architectures (corresponding to A1, B1, and C1) are converted into electrical signals (e.g., ...) by a photoelectric converter. Figure 8(As shown in the figure), then input it into a regular electrical binary full adder for calculation to obtain the final ternary-to-binary calculation result. The calculation process and correspondence are detailed in the ternary-to-binary truth table shown in Table 1.

[0048] Table 1 Truth Table for Ternary to Binary Conversion 5. Extended Explanation To further expand the bit depth, the same logic can be followed to achieve conversion between more ternary and binary signals. Current research reports a 15th-order mode converter (On-chip metamaterial-enabled high-order mode-division multiplexing), providing a feasible basis for higher-order expansion of this scheme. To ensure the purity of high-order mode transmission, asymmetric waveguide design or mode isolators can be used to suppress mode crosstalk. For potential transmission losses, power compensation can be achieved by integrating a miniature semiconductor optical amplifier (SOA) at critical nodes (such as after the high-order mode converter).

Claims

1. A three-to-two converter implemented using on-chip optical modes, characterized in that, include: The input section is used to receive the input waveguide carrying the optical signal; The electro-optical conversion and routing section includes at least one optical switch configured to receive an electrical signal representing a ternary digit and to route the input optical signal to one of three output waveguides according to the logic level of the electrical signal. The mode mapping and conversion section is optically connected to the output waveguide of the electro-optic conversion and routing section. It is configured to map the input optical signal into a specific optical mode combination representing binary weights according to the weights of the ternary digits and output the signal, where different optical modes represent different bit weights of the binary number. The detection section includes multiple photodetectors, which are configured to detect the optical power of a specific optical mode output by the mode mapping and conversion section and convert it into a corresponding electrical signal. The adder is used to sum multiple sets of binary electrical signals output by the probe section, each representing a different ternary digit weight, and finally obtain a binary number output that is equal to the input ternary number.

2. The three-to-two converter using on-chip optical modes according to claim 1, characterized in that, The mode mapping and conversion section includes a mode converter, a beam splitter, and a waveguide structure, used to perform at least one of the following operations: converting a fundamental mode optical signal into a higher-order mode, splitting a beam of optical signal into multiple paths and guiding them to different ports, or dissipating the optical signal.

3. The three-to-two converter using on-chip optical modes according to claim 1, characterized in that, The optical switch is a micro-ring resonator type optical switch or a Mach-Zehnder interferometer type optical switch.

4. The three-to-two converter implemented using on-chip optical modes according to claim 1, characterized in that, The optical mode is the transverse electric mode TE in a silicon-based optical waveguide. m In this context, TE0 mode represents the least significant bit, TE1 mode represents the second bit, and higher-order TE... m The pattern represents the higher bits of the binary representation.

5. The three-to-two converter implemented using on-chip optical modes according to claim 1, characterized in that, The specific structure of the mode mapping and conversion section varies depending on the weight of the ternary digits being processed. For ternary digits with higher weights, the structure is configured to use a higher-order optical mode for mapping.

6. The three-to-two converter using on-chip optical modes according to claim 1, characterized in that, The detection section performs detection of multiple optical modes in parallel.

7. The three-to-two converter using on-chip optical modes according to claim 1, characterized in that, The adder is an electrical binary full adder.

8. A three-to-binary conversion method based on the converter described in any one of claims 1 to 7, characterized in that, Includes the following steps: 1) Input the digital electrical signals representing each digit of the ternary system in parallel to the corresponding electro-optical conversion and routing section; 2) The input optical signal is routed to the output waveguide corresponding to the electrical signal level via an optical switch; 3) In the mode mapping and conversion section, the optical signal is converted into one or more optical modes representing specific binary weights based on the weights of the ternary digits; 4) The light intensity of the optical mode is detected in parallel using a photodetector and converted into multiple sets of binary electrical signals; 5) Input the multiple sets of binary electrical signals into the adder for summation, and output the final binary result.

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