Data transmission method, shifter and FPGA chip
By setting shift pointers and valid data start pointers in digital circuits, the shift operation information is determined and the left shift operation is performed, which solves the problem of bit width mismatch between upstream and downstream modules, and achieves the saving of logic resources and simplification of shift architecture.
Patent Information
- Application Number
- CN202510682848.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-26
- Publication Date
- 2025-10-28
AI Technical Summary
In digital circuits, when the bit widths of upstream and downstream modules do not match, an additional bit width adaptation module is required, which increases the consumption of logic resources.
By setting the shift pointer and the start pointer of valid data, the shift operation information is determined, and the left shift operation is performed to update the valid data length of the downstream module. When appropriate, the downstream module is notified to take the data, thus avoiding the use of a right shifter and an additional bit width adaptation module.
It reduces the consumption of logical resources, simplifies the shift architecture, and reduces the use of logical resources.
Smart Images
Figure CN120848953A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of digital circuit technology, and in particular to a data transmission method, a shifter, and an FPGA chip. Background Art
[0002] When data is transmitted between modules in a digital circuit, the bit width of the upstream module and the bit width of the downstream module may not match. For example, the bit width of the upstream module is 8 bytes and the bit width of the downstream module is 4 bytes. In this case, an additional bit width adaptation module needs to be set up to achieve bit width adaptation, which will increase the consumption of logic resources.
[0003] Reference Figure 1 The diagram illustrates the data transmission provided by the relevant technology. The upstream module has a bit width of 8 bytes, and the downstream module has a bit width of 4 bytes. First, invalid placeholder data between valid data in the upstream module is removed through a shift operation. Then, an additional bit width adaptation module converts the 8 bytes to 4 bytes. Summary of the Invention
[0004] This application provides a data transmission method, a shifter, and an FPGA chip.
[0005] In a first aspect, embodiments of this application provide a data transmission method, comprising: setting a shift pointer; obtaining a valid data start pointer; determining shift operation information based on the shift pointer and the valid data start pointer, the shift operation information indicating the number of left shifts; performing a shift operation according to the shift operation information; updating the valid data length of the downstream module; generating a target signal when the valid data length of the downstream module is greater than or equal to the bit width of the downstream module, the target signal indicating that the downstream module takes away data; updating the shift pointer after the downstream module takes away data; and updating the valid data start pointer.
[0006] Secondly, embodiments of this application provide a shifter, which includes a shift controller and a plurality of data selectors; the shift controller is configured to: set a shift pointer; acquire a valid data start pointer; determine shift operation information based on the shift pointer and the valid data start pointer, the shift operation information being used to indicate the number of left shifts; the plurality of data selectors are configured to: perform a shift operation according to the shift operation information; the shift controller is further configured to: update the valid data length of the downstream module; generate a target signal when the valid data length of the downstream module is greater than or equal to the bit width of the downstream module, the target signal being used to instruct the downstream module to take data; and update the shift pointer and the valid data start pointer after the downstream module takes data.
[0007] Thirdly, embodiments of this application provide an FPGA chip, including the shifter as described in the first aspect.
[0008] Compared to related technologies, the technical solution provided in this application updates the effective data length of the downstream module after each shift operation during data transmission. If the effective data length of the downstream module is greater than or equal to its bit width, the downstream module is notified to retrieve the data promptly, thus completing bit width adaptation. This eliminates the need for an additional bit width adaptation module, reducing logic resource consumption. Furthermore, by unifying all shift operations into left shift operations and avoiding the use of right shifters, the shift architecture can be simplified, further reducing logic resource consumption. Attached Figure Description
[0009] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0010] Figure 1 This is a schematic diagram of data transmission provided by related technologies.
[0011] Figure 2 This is a structural diagram of a shifter provided in one embodiment of this application.
[0012] Figure 3 This is a flowchart of a data transmission method provided in one embodiment of this application.
[0013] Figure 4 This is a flowchart of a data transmission method provided in another embodiment of this application.
[0014] Figure 5 This is a flowchart of a data transmission method provided in another embodiment of this application.
[0015] Figure 6 This is a structural block diagram of a shifter provided in one embodiment of this application.
[0016] Figure 7 This is a structural block diagram of an FPGA chip provided in one embodiment of this application. Detailed Implementation
[0017] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.
[0018] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0019] Please refer to Figure 2 The diagram illustrates the structure of a shifter 20 provided in one embodiment of this application. The shifter 20 may be a barrel shifter. A barrel shifter is a digital circuit that can shift a data word by a specific number of bits within one clock cycle.
[0020] The shifter 20 establishes communication connections, such as bus connections, with both upstream and downstream modules. The shifter 20 transmits data with the upstream and downstream modules based on a specified communication protocol. Optionally, the specified communication protocol is the Advanced eXtensible Interface 4 (AXI4) protocol.
[0021] The shifter 20 includes a shift controller 210 and multiple register slices 220, each of which includes multiple 2-to-1 data selectors. The shift controller 210 is connected to the multiple register slices 220. The shift controller 210 is used to determine shift operation information and control the multiple register slices 220 to perform shift operations according to the shift operation information. In addition, the shift controller 210 is also used to interact with upstream and downstream modules to exchange control signals, such as receiving a valid data signal (valid), a valid data start pointer (sptr), and a valid data length (length) sent by the upstream module, sending a ready signal (ready) to the upstream module, sending a valid data signal to the downstream module, and receiving a ready signal (ready) sent by the downstream module. Furthermore, the shift controller 20 can also obtain the set shift pointer (eptr) and the last data (flush_last_data) written from memory to disk or persistent storage medium.
[0022] Multiple data selectors are used to implement the shift operation. In some embodiments, the number of data selectors is positively correlated with the bit width of the upstream module; that is, the larger the bit width of the upstream module, the larger the number of data selectors, and the smaller the bit width of the upstream module, the fewer the number of data selectors. Optionally, the number of digital selectors k and the bit width n of the upstream module satisfy the following formula: k = n * log₂n. For example, when the bit width of the upstream module is 4 bytes, the shifter 20 includes two register slices 220, each of which includes four 2-to-1 data selectors; when the bit width of the upstream module is 8 bytes, the shifter 20 includes three register slices 220, each of which includes eight 2-to-1 data selectors. In this way, the number of register slices included in the shifter 20 (i.e., the number of data selectors) can be flexibly adjusted according to resource and performance requirements, thereby adjusting the architecture of the shifter 20 to improve timing and achieve a balance between performance and resources.
[0023] exist Figure 2 In this embodiment, the shifter 20 includes three register slices 220. The first register slice 220 includes eight data selectors, namely m0_0, m0_1, m0_2, m0_3, m0_4, m0_5, m0_6, and m0_7; the second register slice 220 includes eight data selectors, namely m1_0, m1_1, m1_2, m1_3, m1_4, m1_5, m1_6, and m1_7; and the third register slice 220 includes eight data selectors, namely m2_0, m2_1, m2_2, m2_3, m2_4, m2_5, m2_6, and m2_7.
[0024] In some embodiments, the shifter 20 further includes a data buffer 230 for buffering data. The length of data that the data buffer 230 can buffer can be determined based on the bit width of the downstream module. Optionally, the length of data that the data buffer 230 can buffer is slightly smaller than the bit width of the downstream module. For example, if the bit width of the downstream module is 4 bytes, then the length of data that the data buffer 230 can buffer is 3 bytes. As another example, if the bit width of the downstream module is 8 bytes, then the length of data that the data buffer 230 can buffer is 7 bytes.
[0025] Please refer to Figure 3 The diagram illustrates a flowchart of a data transmission method provided in one embodiment of this application. The method includes the following steps.
[0026] S301, set the shift pointer.
[0027] A shift pointer is used to indicate the starting position of data alignment. The position of the shift pointer can be determined based on the bit width of the downstream module. For example, if the bit width of the downstream module is 4 bytes, the shift pointer position can be set to 0 / 1 / 2 / 3; and if the bit width of the downstream module is 8 bytes, the shift pointer position can be set to 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7. The shift pointer can be represented by `eptr`.
[0028] S302, Get the start pointer for valid data.
[0029] The valid data start pointer indicates the starting position of valid data. The valid data start pointer can be represented by `sptr`. Optionally, the shifter receives a first specified signal sent by the upstream module and determines the valid data start pointer based on the first specified signal. The first specified signal can be determined according to the communication protocol between the shifter and the upstream module. Optionally, when data transmission between the upstream module and the shifter is based on the AXI4 protocol, the first specified signal is the AWADDR signal, which indicates the target address of the data to be written.
[0030] In some embodiments, the shifter acquires the valid data start pointer and the valid data length simultaneously. Optionally, the shifter receives a second specified signal sent by the upstream module and determines the valid data length based on the second specified signal. Optionally, when data transmission between the upstream module and the shifter is based on the AXI4 protocol, the second specified signal includes an AWSIZE signal and an AWLEN signal. The AWSIZE signal indicates the bit width of the transmission, i.e., how many bytes are transmitted at once, and the AWLEN signal indicates the total number of transmissions.
[0031] In some embodiments, the shifter first detects whether valid data exists. If valid data is detected, step S302 is executed. If valid data does not exist, the shifter continues to wait until valid data is detected. Optionally, the shifter detects whether a valid data signal sent by an upstream module exists. If a valid data signal sent by an upstream module is detected, it is determined that valid data exists.
[0032] S303: Determine the shift operation information based on the shift pointer and the valid data start pointer.
[0033] The shift operation information is used to indicate the number of bits to shift left. The process of determining the shift operation information will be described in the embodiments below. In the embodiments of this application, the shifter unifies all shift operations into left shift operations, avoiding the use of right shift shifters, which can simplify the shift architecture and reduce the consumption of logic resources.
[0034] S304, Perform the shift operation according to the shift operation information.
[0035] The shift controller controls multiple data selectors to perform shift operations according to the shift operation information.
[0036] S305, Update the effective data length of the downstream module.
[0037] The effective data length of the downstream module refers to the length of effective data that the downstream module is allowed to retrieve. The process of updating the effective data length of the downstream module will be described in the following examples.
[0038] S306 generates the target signal when the effective data length of the downstream module is greater than or equal to the bit width of the downstream module.
[0039] The target signal is used to instruct the downstream module to retrieve the data. Optionally, the target signal is a valid signal. In this embodiment, if the valid data length of the downstream module is greater than or equal to the bit width of the downstream module, the downstream module will be notified to retrieve the data in a timely manner, thereby completing the bit width adaptation and avoiding the need to set up an additional bit width adaptation module, thus reducing the consumption of logic resources.
[0040] In some embodiments, when the effective data length of the downstream module is less than the bit width of the downstream module, the shifter caches the effective data through a data buffer.
[0041] In some embodiments, when the shifter detects a forced output data control signal, it generates a target signal to notify the downstream module to take the currently valid data.
[0042] S307: After the downstream module retrieves the data, update the shift pointer and update the valid data start pointer.
[0043] The process of updating the shift pointer and the valid data start pointer will be described in the following examples.
[0044] The shifter repeats steps S303-S307 until the effective data length of the upstream module is 0, that is, all the effective data of the upstream module has been taken away.
[0045] In summary, the technical solution provided in this application updates the effective data length of the downstream module after each shift operation during data transmission. If the effective data length of the downstream module is greater than or equal to its bit width, the downstream module is notified to retrieve the data promptly. This allows bit width adaptation to be completed simultaneously during the shift and splicing stage, eliminating the need for an additional bit width adaptation module and reducing logic resource consumption. Furthermore, by unifying all shift operations into left shift operations and avoiding the use of right shifters, the shift architecture can be simplified, further reducing logic resource consumption.
[0046] Please refer to Figure 4This illustrates a flowchart of a data transmission method provided in one embodiment of this application. Based on... Figure 3 In an optional embodiment provided by the example, S305 is replaced by S405-S407. The method includes the following procedures.
[0047] S401, set the shift pointer.
[0048] S402, Get the start pointer for valid data.
[0049] S403, determine the shift operation information based on the shift pointer and the valid data start pointer.
[0050] The shift operation information is used to indicate the number of bits to shift left.
[0051] S404, Perform the shift operation according to the shift operation information.
[0052] S405, obtain the valid data length of the upstream module.
[0053] exist Figure 3 As mentioned in the embodiment, the effective data length of the upstream module is sent to the shifter by the upstream module.
[0054] S406, obtain the difference between the bit width of the downstream module and the first value.
[0055] The first value refers to the remainder when the shift pointer is divided by the bit width of the downstream module. For example, if the bit width of the downstream module is 4 bytes and the shift pointer is 3, then the first value is (3%4) = 3.
[0056] S407, the minimum value between the difference and the effective data length of the upstream module is determined as the effective data length of the downstream module.
[0057] Optionally, the update process of the effective data length s_length of the downstream module is represented by the following calculation formula: s_length = min(m - (eptr % m), m_length), where m is the bit width of the downstream module, eptr is a shift pointer, % indicates the remainder, eptr % m is the remainder of eptr divided by the bit width of the downstream module, and m_length is the effective data length of the upstream module.
[0058] S408 generates the target signal when the effective data length of the downstream module is greater than or equal to the bit width of the downstream module.
[0059] The target signal is used to instruct the downstream module to take the data.
[0060] S409: After the downstream module retrieves the data, update the shift pointer, update the valid data start pointer, and update the valid data length of the upstream module.
[0061] Optionally, updating the shift pointer is implemented by updating the remainder of the second value divided by the bit width of the downstream module to the new shift pointer.
[0062] The second value refers to the sum of the shift pointer and the effective data length of the downstream module. That is, the update process of the shift pointer is represented by the following calculation: eptr = (eptr + s_length) % m, where s_length is the effective data length of the downstream module.
[0063] For example, the effective data length of the downstream module is 4, eptr is 1, and the bit width of the downstream module is 4 bytes. At this time, the new shift pointer = (1+4)%4 = 1.
[0064] Optionally, updating the valid data start pointer is implemented by updating the remainder of the third value divided by the bit width of the upstream module to the new valid data start pointer.
[0065] The third value refers to the sum of the effective data start pointer and the effective data length of the downstream module. That is, the update process of the effective data start pointer is represented by the following calculation formula: sptr = (sptr + s_length) % n, where n is the bit width of the upstream module.
[0066] For example, the effective data length of the downstream module is 4, sptr is 6, and the bit width of the upstream module is 8 bytes. At this time, the new effective data start pointer = (6+4)%8 = 2.
[0067] Optionally, updating the effective data length of the upstream module is achieved by subtracting the effective data length of the downstream module from the effective data length of the upstream module, and then updating the effective data length of the upstream module to the new effective data length. That is, the update process of the effective data length of the upstream module is expressed by the following formula: m_length = m_length – s_length.
[0068] For example, the effective data length of the downstream module is 4, and the effective data length of the upstream module is 16. At this time, the effective data length of the new upstream module is 16-14=12.
[0069] In summary, the technical solution provided in this application updates the effective data length of the downstream module after each shift operation during data transmission. If the effective data length of the downstream module is greater than or equal to its bit width, the downstream module is notified to retrieve the data promptly. This allows bit width adaptation to be completed simultaneously during the shift and splicing stage, eliminating the need for an additional bit width adaptation module and reducing logic resource consumption. Furthermore, by unifying all shift operations into left shift operations and avoiding the use of right shifters, the shift architecture can be simplified, further reducing logic resource consumption.
[0070] Please refer to Figure 5 This illustrates a flowchart of a data transmission method provided in one embodiment of this application. Based on... Figure 3 In an optional embodiment provided by the example, S303 is replaced by S503-S504. The method includes the following procedures.
[0071] S501, set the shift pointer.
[0072] S502, Get the start pointer for valid data.
[0073] S503, the remainder of the fourth value divided by the bit width of the upstream module is determined as the shift control value.
[0074] The fourth value is the difference between the shift pointer and the valid data start pointer. Optionally, the process of determining the shift control quantity is expressed by the following formula: si = (eptr - sptr) % n.
[0075] For example, if the bit width of the upstream module is 8 bytes, the bit width of the downstream module is 4 bytes, the shift pointer eptr is 3, and the valid data start pointer sptr is 1, then the shift control quantity si = (3-1)%8 = 2.
[0076] S504 determines shift operation information based on shift control quantities.
[0077] In some embodiments, when the shift control amount is greater than zero, the left shift number is determined as the shift control amount. When the shift control amount is less than zero, the left shift number is determined as a fifth value, which is the difference between the bit width of the upstream module and the absolute value of the shift control amount.
[0078] For example, with a shift control value of 2, the left shift number is 2 units. As another example, if the upstream module has a bit width of 8 bytes and a shift control value of -2, then the left shift number is (8-2) = 6 units.
[0079] S505, perform the shift operation according to the shift operation information.
[0080] S506, Update the valid data length of the downstream module.
[0081] S507 generates the target signal when the effective data length of the downstream module is greater than or equal to the bit width of the downstream module.
[0082] The target signal is used to instruct the downstream module to take the data.
[0083] S508 updates the shift pointer and the valid data start pointer after the downstream module retrieves the data.
[0084] In summary, the technical solution provided in this application determines the shift operation information during data transmission using a shift pointer and a valid data start pointer. This unifies all shift operations into left shift operations, avoiding the use of right shift shifters, simplifying the shift architecture, and reducing the consumption of logic resources. Furthermore, after each shift operation, the valid data length of the downstream module is updated. If the valid data length of the downstream module is greater than or equal to its bit width, the downstream module is notified to retrieve the data promptly. This allows bit width adaptation to be completed simultaneously during the shift and splicing stage, eliminating the need for an additional bit width adaptation module and further reducing logic resource consumption.
[0085] Please refer to Figure 6 The diagram illustrates the structure of a shifter 20 according to an embodiment of this application. The shifter 20 includes a shift controller 210 and a plurality of data selectors 221.
[0086] The shift controller 210 is configured to: set a shift pointer; acquire a valid data start pointer; and determine shift operation information based on the shift pointer and the valid data start pointer, the shift operation information being used to indicate the number of left shifts.
[0087] Multiple data selectors 221 are configured to perform shift operations according to shift operation information;
[0088] The shift controller 210 is also configured to: update the effective data length of the downstream module; generate a target signal when the effective data length of the downstream module is greater than or equal to the bit width of the downstream module, the target signal being used to instruct the downstream module to take data; and update the shift pointer and the effective data start pointer after the downstream module takes data.
[0089] In some embodiments, the number of data selectors is positively correlated with the bit width of the upstream module.
[0090] In some embodiments, the shift controller 210 is configured to: obtain the effective data length of the upstream module; obtain the difference between the bit width of the downstream module and a first value, wherein the first value is the remainder when the shift pointer is divided by the bit width of the downstream module; and determine the minimum value between the difference and the effective data length of the upstream module as the effective data length of the downstream module.
[0091] In some embodiments, the shift controller 210 is configured to update the effective data length of the upstream module by subtracting the effective data length of the downstream module from the effective data length of the upstream module after the downstream module has taken the data.
[0092] In some embodiments, the shift controller 210 is configured to: update the remainder of a second value divided by the bit width of the downstream module as a new shift pointer, the second value being the sum of the shift pointer and the effective data length of the downstream module; and update the remainder of a third value divided by the bit width of the upstream module as a new effective data start pointer, the third value being the sum of the effective data start pointer and the effective data length of the downstream module.
[0093] In some embodiments, the shift controller 210 is configured to: determine the remainder of a fourth value divided by the bit width of the upstream module as a shift control quantity, wherein the fourth value is the difference between the shift pointer and the valid data start pointer; and determine shift operation information based on the shift control quantity.
[0094] In some embodiments, the shift controller 210 is configured to: determine the left shift number as the shift control amount when the shift control amount is greater than zero; and determine the left shift number as a fifth value when the shift control amount is less than zero, wherein the fifth value is the difference between the bit width of the upstream module and the absolute value of the shift controller.
[0095] In some embodiments, the shifter 20 further includes a data buffer 230; the data buffer 230 is configured to buffer the valid data of the downstream module when the valid data length of the downstream module is less than the bit width of the downstream module.
[0096] In summary, the technical solution provided in this application updates the effective data length of the downstream module after each shift operation during data transmission. If the effective data length of the downstream module is greater than or equal to its bit width, the downstream module is notified to retrieve the data promptly. This allows bit width adaptation to be completed simultaneously during the shift and splicing stage, eliminating the need for an additional bit width adaptation module and reducing logic resource consumption. Furthermore, by unifying all shift operations into left shift operations and avoiding the use of right shifters, the shift architecture can be simplified, further reducing logic resource consumption.
[0097] Please refer to Figure 7 This diagram illustrates the structure of an FPGA chip 70 according to an embodiment of this application. The FPGA chip 70 includes a shifter 20, which is used to implement, for example... Figure 3-5 Each step in any embodiment.
[0098] In summary, the technical solution provided in this application updates the effective data length of the downstream module after each shift operation during data transmission. If the effective data length of the downstream module is greater than or equal to its bit width, the downstream module is notified to retrieve the data promptly. This allows bit width adaptation to be completed simultaneously during the shift and splicing stage, eliminating the need for an additional bit width adaptation module and reducing logic resource consumption. Furthermore, by unifying all shift operations into left shift operations and avoiding the use of right shifters, the shift architecture can be simplified, further reducing logic resource consumption.
[0099] In specific implementation, the modules / units included in the various devices and products described in the above embodiments can be software modules / units, hardware modules / units, or a combination of both.
[0100] For example, for various devices and products applied to or integrated into a chip, each module / unit can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into a chip module, each module / unit can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The components can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, each of its components / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or in different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.
[0101] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.
Claims
1. A data transmission method, characterized in that, The method includes: Set the shift pointer; Get the start pointer of valid data; Based on the shift pointer and the valid data start pointer, shift operation information is determined, wherein the shift operation information is used to indicate the number of left shifts; Perform the shift operation according to the shift operation information; Update the effective data length of the downstream module; When the effective data length of the downstream module is greater than or equal to the bit width of the downstream module, a target signal is generated, which is used to instruct the downstream module to take the data. After the downstream module retrieves the data, the shift pointer is updated, and the valid data start pointer is updated.
2. The method according to claim 1, characterized in that, The effective data length of the updated downstream module includes: Obtain the valid data length of the upstream module; Obtain the difference between the bit width of the downstream module and a first value, where the first value is the remainder when the shift pointer is divided by the bit width of the downstream module. The minimum value between the difference and the effective data length of the upstream module is determined as the effective data length of the downstream module.
3. The method according to claim 2, characterized in that, The method further includes: After the downstream module retrieves the data, the difference between the effective data length of the upstream module and the effective data length of the downstream module is used to update the effective data length of the upstream module.
4. The method according to claim 1, characterized in that, The update of the shift pointer includes: The remainder of the second value divided by the bit width of the downstream module is updated as a new shift pointer, where the second value is the sum of the shift pointer and the effective data length of the downstream module; Updating the start pointer of the valid data includes: The remainder of the third value divided by the bit width of the upstream module is updated as the new valid data start pointer. The third value refers to the sum of the valid data start pointer and the valid data length of the downstream module.
5. The method according to any one of claims 1 to 4, characterized in that, The step of determining the shift operation information based on the shift pointer and the valid data start pointer includes: The remainder of the fourth value divided by the bit width of the upstream module is determined as the shift control value, where the fourth value is the difference between the shift pointer and the valid data start pointer. The shift control quantity is determined as the shift operation information.
6. The method according to claim 5, characterized in that, The determination of the shift operation information based on the shift control amount includes: If the shift control value is greater than zero, the left shift number is determined as the shift control value; When the shift control amount is less than zero, the left shift number is determined to be the fifth value, which is the difference between the bit width of the upstream module and the absolute value of the shift control amount.
7. The method according to any one of claims 1 to 4, characterized in that, The method further includes: If the effective data length of the downstream module is less than the bit width of the downstream module, the effective data is cached.
8. A shifter, characterized in that, The shifter includes a shift controller and multiple data selectors; The shift controller is configured to: set a shift pointer; acquire a valid data start pointer; and determine shift operation information based on the shift pointer and the valid data start pointer, wherein the shift operation information is used to indicate the number of left shifts; The plurality of data selectors are configured to perform a shift operation according to the shift operation information; The shift controller is further configured to: update the effective data length of the downstream module; generate a target signal when the effective data length of the downstream module is greater than or equal to the bit width of the downstream module, the target signal being used to instruct the downstream module to take data; and update the shift pointer and the effective data start pointer after the downstream module takes data.
9. The shifter according to claim 8, characterized in that, The number of data selectors is positively correlated with the bit width of the upstream module.
10. The shifter according to claim 8, characterized in that, The shifter also includes a data buffer; The data buffer is configured to cache the valid data of the downstream module when the valid data length of the downstream module is less than the bit width of the downstream module.
11. An FPGA chip, characterized in that, Including a shifter as described in any one of claims 8-10.