Memory optimization method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a memory optimization method and device, electronic equipment and a storage medium. After a target program runs, memory running information is obtained; according to the memory operation information, a memory load level is obtained, and the memory load level represents the memory load level of the memory demand of the target program; according to the memory load level, a target optimization strategy is executed, the target optimization strategy comprises at least two conditional execution sub-optimization strategies, the sub-optimization strategies are used for releasing cache data of the corresponding type in the memory, and execution conditions of the sub-optimization strategies correspond to the memory load level. By judging the memory load level for the memory demand of the target program and executing the target optimization strategy based on the memory load level, dynamic type memory recovery based on the memory load level is realized, the problems of slow program loading speed, program lagging and the like caused by excessive memory recovery and untimely memory recovery are avoided, and the memory recovery efficiency is improved. And the use experience of the application program is improved.

Description

Technical Field

[0001] This disclosure relates to the field of mobile application technology, and in particular to a memory optimization method, apparatus, electronic device, and storage medium. Background Technology

[0002] Currently, when applications perform memory-intensive functions such as video editing, the loading and display of data such as materials and draft templates require a large amount of device memory, resulting in a high memory load on the terminal device. This is especially true for mobile terminal devices with limited memory resources, which often leads to problems such as stuttering and frame drops.

[0003] In existing technologies, for mobile terminal devices, when memory resources are detected to be low, the operating system will automatically reclaim memory resources to free up available memory for executing corresponding program functions.

[0004] However, existing operating system-based system resource reclamation functions suffer from problems such as untimely memory resource reclamation and excessive memory resource reclamation, which affect the stability of program operation. Summary of the Invention

[0005] This disclosure provides a memory optimization method, apparatus, electronic device, and storage medium to overcome the problems of untimely memory resource reclamation and excessive memory resource reclamation.

[0006] In a first aspect, embodiments of this disclosure provide a memory optimization method, including:

[0007] After the target program runs, memory operation information is obtained; based on the memory operation information, a memory load level is obtained, wherein the memory load level represents the memory load level for the memory requirements of the target program; based on the memory load level, a target optimization strategy is executed, wherein the target optimization strategy includes at least two conditionally executed sub-optimization strategies, the sub-optimization strategies are used to release cached data of the corresponding type in memory, and the execution conditions of the sub-optimization strategies correspond to the memory load level.

[0008] In a second aspect, embodiments of this disclosure provide a memory optimization apparatus, comprising:

[0009] The acquisition module is used to obtain memory runtime information after the target program has run.

[0010] The load module is used to obtain the memory load level based on the memory operation information, wherein the memory load level represents the memory load level for the memory requirements of the target program;

[0011] The strategy module is used to execute a target optimization strategy based on the memory load level, wherein the target optimization strategy includes at least two conditionally executed sub-optimization strategies, the sub-optimization strategies being used to release cached data of the corresponding type in memory, and the execution conditions of the sub-optimization strategies corresponding to the memory load level.

[0012] Thirdly, embodiments of this disclosure provide an electronic device, including: a processor and a memory;

[0013] The memory stores computer-executed instructions;

[0014] The processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the memory optimization method described in the first aspect and various possible designs of the first aspect.

[0015] Fourthly, embodiments of this disclosure provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the memory optimization method described in the first aspect and various possible designs of the first aspect.

[0016] Fifthly, embodiments of this disclosure provide a computer program product, including a computer program that, when executed by a processor, implements the memory optimization method described in the first aspect and various possible designs of the first aspect.

[0017] The memory optimization method, apparatus, electronic device, and storage medium provided in this embodiment acquire memory operation information after the target program runs; obtain a memory load level based on the memory operation information, wherein the memory load level represents the memory load level for the memory requirements of the target program; and execute a target optimization strategy based on the memory load level, wherein the target optimization strategy includes at least two conditionally executed sub-optimization strategies, the sub-optimization strategies being used to release corresponding types of cached data in memory, and the execution conditions of the sub-optimization strategies corresponding to the memory load level. By determining the memory load level for the memory requirements of the target program based on real-time memory operation information after the program runs, and generating a memory load level, and then executing the target optimization strategy based on the memory load level to execute the sub-optimization strategies corresponding to the memory load level and release corresponding types of cached data, dynamic memory reclamation based on memory load level is achieved. This makes the memory reclamation action for the target program more accurate and effective, avoiding problems such as slow program loading speed and program lag caused by excessive memory reclamation and untimely memory reclamation, thereby improving the user experience of the application. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is an application scenario diagram of the memory optimization method provided in the embodiments of this disclosure;

[0020] Figure 2 Flowchart of the memory optimization method provided in the embodiments of this disclosure Figure 1 ;

[0021] Figure 3 for Figure 2 A flowchart illustrating the specific implementation of step S102 in the illustrated embodiment;

[0022] Figure 4 This is a schematic diagram illustrating the numerical matching relationship between memory state values ​​and threshold pairs provided in an embodiment of this disclosure.

[0023] Figure 5 This is a schematic diagram illustrating the correspondence between different memory types and memory load levels, provided in an embodiment of the present disclosure.

[0024] Figure 6 Flowchart of the memory optimization method provided in the embodiments of this disclosure Figure 2 ;

[0025] Figure 7 for Figure 6 A flowchart illustrating the specific implementation of step S203 in the illustrated embodiment;

[0026] Figure 8 for Figure 6 A flowchart illustrating the specific implementation of step S204 in the illustrated embodiment;

[0027] Figure 9 This is a schematic diagram illustrating the process of implementing an objective optimization strategy according to an embodiment of the present disclosure;

[0028] Figure 10 This is a structural block diagram of the memory optimization apparatus provided in the embodiments of this disclosure;

[0029] Figure 11 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure;

[0030] Figure 12 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0032] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this disclosure are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of the relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation portals are provided for users to choose to authorize or refuse.

[0033] The application scenarios of the embodiments of this disclosure are explained below:

[0034] The memory optimization method provided in this disclosure can be applied to scenarios where applications (APPs) are running, and is particularly suitable for application scenarios with high memory resource consumption, such as running video editing applications on mobile terminal devices or performing video editing based on such video editing applications. More specifically, the execution subject of this embodiment can be the terminal device running the above-mentioned application, a server deploying the server corresponding to the above-mentioned application, or other electronic devices that perform similar functions.

[0035] In some embodiments, the terminal device or server can implement the memory optimization method provided in this application by running various computer-executable instructions or computer programs. For example, computer-executable instructions can be program-level commands, machine instructions, or software instructions. Computer programs can be native programs or software modules in an operating system; they can be local applications, i.e., programs that need to be installed in the operating system to run, or small programs embedded in any APP, i.e., programs that run based on a browser environment. In summary, the aforementioned computer-executable instructions can be any form of instruction, and the aforementioned computer programs can be any form of application, module, or plugin; the specific implementation can be configured as needed. Further, in some embodiments, the server can be an independent physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud storage, cloud communication, cloud databases, cloud computing, cloud functions, network services, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms. The cloud services can be interactive processing services that can be invoked by the terminal device.

[0036] Figure 1 This is an application scenario diagram of the memory optimization method provided in the embodiments of this disclosure, with reference to... Figure 1 As shown in the diagram, taking a terminal device as an example, when the terminal device runs a target program with video editing capabilities (shown as an APP in the diagram), in a video editing scenario, the terminal device needs to load a large amount of templates, drafts, materials, effects, and other data within the video editing window. This data may be further loaded into multiple tracks as needed. Simultaneously, the terminal device also needs to display the edited video clips in the preview window, causing the target program to consume a significant amount of memory resources during operation. In this situation, for example... Figure 1 As shown, when a program consumes too much memory, the operating system's memory reclamation mechanism will be triggered to release the data in memory, thereby ensuring the normal operation of the program.

[0037] However, in existing solutions, on the one hand, the memory reclamation action automatically triggered by the operating system at any time can preempt the central processing unit (CPU) resources, causing the program to run slower, or even freeze or crash; on the other hand, during the process of the operating system reclaiming memory, there may be a phenomenon of excessive memory reclamation, that is, releasing the target program's business cache data from memory, causing the program to need to re-acquire the cache data, which in turn slows down the program's running speed and affects the user experience.

[0038] This disclosure provides a memory optimization method that solves the above-mentioned problems by more accurately controlling the timing and target of memory reclamation.

[0039] refer to Figure 2 , Figure 2 Flowchart of the memory optimization method provided in the embodiments of this disclosure Figure 1 .

[0040] For example, the method of this embodiment can be applied in a terminal device, and the memory optimization method includes:

[0041] Step S101: After the target program runs, obtain memory operation information.

[0042] Step S102: Obtain the memory load level based on the memory operation information, where the memory load level represents the memory load level for the memory requirements of the target program.

[0043] refer to Figure 1 The illustrated application scenario diagram illustrates that, exemplarily, after the terminal device runs the target program, it can read the device's memory operation information through a memory monitoring component set within the program. This memory operation information includes various implementation methods, such as device physical memory, process physical memory, and process virtual memory. The specific implementation method of the memory operation information can be set as needed, and this embodiment does not impose any restrictions. Furthermore, exemplarily, the memory monitoring component can run as a service within the terminal device. The memory monitoring component can obtain the aforementioned memory operation information by periodically calling interfaces provided by the operating system; the specific implementation method will not be elaborated further.

[0044] Furthermore, after obtaining memory operation information, the terminal device generates a memory load level corresponding to the target program based on this information. The memory load level characterizes the memory load level relative to the target program's memory requirements. Specifically, the memory load level can be a specific level identifier, such as Level 1, Level I, Level A, etc. A higher memory load level indicates a higher memory load, meaning a greater load. For example, a memory load level of Level I indicates that the device's current available memory is much greater than the target program's memory requirements, meaning the target program can run normally; a memory load level of Level II indicates that the device's current available memory is roughly equivalent to the target program's memory requirements, and the target program can run normally, but there is a possibility of insufficient memory; a memory load level of Level III indicates that the device's current available memory is less than the target program's memory requirements, and there is insufficient available memory.

[0045] Furthermore, it should be noted that the memory load level represented by this memory load level is the load level relative to the memory requirements of the target program. That is, it is related not only to the available memory of the current device, but also to the memory requirements of the target program. For example, in one possible case, the available memory of the current device is 10 (dimensionless unit), while the memory requirement of the target program is 12 (dimensionless unit, the same as available memory), then the memory load level is level III, indicating a very high memory load level, meaning insufficient available memory; while in another possible case, the available memory of the current device is 10, while the memory requirement of the target program is 6, then the memory load level is level I, indicating a low memory load level, meaning sufficient available memory.

[0046] In one possible implementation, such as Figure 3 As shown, the specific implementation of step S102 includes:

[0047] Step S1021: Based on the memory operation information, obtain the first memory status value and the second memory status value, wherein the first memory status value represents the memory utilization rate and the second memory status value represents the remaining memory amount.

[0048] Step S1022: Based on the memory category corresponding to the memory operation information, obtain the corresponding memory threshold group. The memory threshold group includes at least two threshold pairs, and the at least two threshold pairs correspond one-to-one with at least two preset memory load levels.

[0049] Step S1023: Obtain the memory load level based on the numerical matching relationship between the first memory state value, the second memory state value and the threshold pairs in the memory threshold group.

[0050] For example, firstly, based on the memory category of the memory operation information, a first memory status value and a second memory status value are obtained. For instance, if the memory operation information corresponds to the device's physical memory, then the memory utilization rate and remaining memory balance of the device's physical memory are obtained; if the memory operation information corresponds to the process's physical memory, then the memory utilization rate and remaining memory balance of the process's physical memory are obtained. More specifically, the memory utilization rate can be expressed as a percentage, such as 90%; the remaining memory balance can be expressed as a specific value, such as 800M. Next, based on the memory category corresponding to the memory operation information, a corresponding memory threshold group is obtained. The memory category is, as in the example above, device physical memory, process virtual memory, device physical memory, etc. Each memory category has a corresponding memory threshold group, and each memory threshold group includes at least two threshold pairs. Each threshold pair corresponds one-to-one with at least two preset memory load levels. Further, each threshold pair includes a first memory threshold and a second memory threshold, where the first memory threshold corresponds to the first memory status value, and the second memory threshold corresponds to the second memory status value. The first and second memory thresholds are determined based on the memory requirements of the target program; that is, the first and second memory thresholds may change when different target programs are running. The memory threshold groups corresponding to the different target programs can be pre-stored on the terminal device or a server in the form of a configuration table.

[0051] Furthermore, the threshold pair includes a first memory threshold and a second memory threshold. In one possible implementation, step S1023 specifically includes: when the first memory state value is greater than or equal to the first memory threshold in the target threshold pair, and the second memory state value is less than the second memory threshold in the target threshold pair, the preset memory load level corresponding to the target threshold pair is determined as the memory load level.

[0052] Figure 4 This is a schematic diagram illustrating the numerical matching relationship between memory state values ​​and threshold pairs provided in an embodiment of this disclosure, such as... Figure 4As shown, exemplarily, taking the case where the memory type corresponding to the memory operation information is "process physical memory" as an example, firstly, based on the device's process physical memory, the first memory status value P1 = 88 and the second memory status value P2 = 90 are obtained; indicating that the current memory utilization rate of the process physical memory is 88%, and the remaining memory is 90M. Then, based on the memory category corresponding to the memory operation information, i.e., "process physical memory," and the preset threshold data table, the memory threshold group Group_1 corresponding to the process physical memory is obtained. The memory threshold group Group_1 includes threshold pairs T1 = [85, 100] and T2 = [90, 50], where "88" in T1 and "90" in T2 are the first memory thresholds in each threshold pair; "100" in T2 and "50" in T2 are the second memory thresholds in each threshold pair. Further, threshold pair T1 corresponds to memory load level I, and threshold pair T2 corresponds to memory load level II. Based on the numerical matching relationship between the first memory state value P1 and the second memory state value P2 and the threshold pairs in memory threshold groups T1 and T2, it can be determined that the first memory state value P1 satisfies the condition of being greater than 85% and the second memory state value P2 satisfies the condition of being less than 100%. Therefore, the first memory state value P1 and the second memory state value P2 both fall within the range of threshold pair T1 = [85, 100], that is, they hit memory threshold group T1 and miss memory threshold group T2. Thus, the memory load level corresponding to the first memory state value P1 and the second memory state value P2 (corresponding to the physical memory of the process) is determined to be memory load level I.

[0053] Furthermore, in the above embodiments, the implementation method of obtaining the memory load level based on the memory operation information is described using the case where the memory type corresponding to the memory operation information is "process physical memory" as an example. In other possible implementations, the memory type corresponding to the memory operation information can also be process virtual memory, device physical memory, etc., and the corresponding memory thresholds are also different when the memory type corresponding to the memory operation information is different. Specifically, the first memory threshold corresponding to process physical memory is less than the first memory threshold corresponding to process virtual memory and greater than the first memory threshold corresponding to device physical memory; the second memory threshold corresponding to process virtual memory is less than the second memory threshold corresponding to process physical memory and greater than the second memory threshold corresponding to device physical memory.

[0054] Furthermore, in another possible implementation, the memory load level can be determined by using memory threshold groups corresponding to two or more memory types in the memory operation information. The memory threshold groups corresponding to different memory types are pre-stored in the terminal device or server in the form of a configuration table. Figure 5 This is a schematic diagram illustrating the correspondence between different memory types and memory load levels, provided in an embodiment of this disclosure. Figure 5As shown, the memory threshold groups corresponding to the physical memory of a process include threshold pairs T1 and T2, where threshold pair T1 corresponds to memory load level I and threshold pair T2 corresponds to memory load level II. Similarly, the memory threshold groups corresponding to the virtual memory of a process include threshold pairs M1 and M2, where threshold pair M1 corresponds to memory load level I and threshold pair M2 corresponds to memory load level II; the memory threshold groups corresponding to the physical memory of a device include threshold pairs N1 and N2, where threshold pair N1 corresponds to memory load level I and threshold pair N2 corresponds to memory load level II. Further, for threshold pair T1, the first memory threshold T1_1 = 85 and the second memory threshold T1_2 = 100, representing memory load level I when memory utilization is greater than or equal to 85% and remaining memory is less than 100 (M); for threshold pair T2, the first memory threshold T2_1 = 90 and the second memory threshold T2_2 = 50, representing memory load level II when memory utilization is greater than or equal to 90% and remaining memory is less than 50 (M). Similarly, for threshold M1, the first memory threshold M1_1 = 90, and the second memory threshold M1_2 = 400; for threshold M2, the first memory threshold M2_1 = 95, and the second memory threshold M2_2 = 200. For threshold N1, the first memory threshold N1_1 = 70, and the second memory threshold N1_2 = 800; for threshold N2, the first memory threshold N2_1 = 80, and the second memory threshold N2_2 = 500.

[0055] In addition to the physical memory consumed by its own logic during program execution, the system also consumes physical memory when the program interacts with system processes. Therefore, by adding a judgment on the remaining memory (second memory threshold) on top of setting the memory utilization rate (first memory threshold), the accuracy of judging the current real memory operating status of the device can be improved. In this embodiment, based on the characteristics of memory operating information of different memory types, memory threshold groups corresponding to different memory types under different memory load levels are set in the above manner to achieve a more accurate judgment of the device operating status and program operating status, thereby improving the memory optimization effect.

[0056] Step S103: Execute the target optimization strategy according to the memory load level. The target optimization strategy includes at least two conditionally executed sub-optimization strategies. The sub-optimization strategies are used to release cached data of the corresponding type in memory. The execution conditions of the sub-optimization strategies correspond to the memory load level.

[0057] For example, after obtaining the memory load level, the system further invokes a target optimization strategy to perform memory optimization based on that memory load level. The target optimization strategy includes at least two conditionally executed sub-optimization strategies; that is, depending on the memory load level, a sub-strategy matching a threshold is selected for execution, thereby dynamically adjusting the memory optimization method. Specifically, the sub-optimization strategies are used to release cached data of the corresponding type in memory, and the execution conditions of the sub-optimization strategies correspond to the memory load level. For example, when the memory load level is Level I, the first sub-strategy (e.g., the first sub-optimization strategy in a later embodiment) is executed to release cached data of category A in memory; while when the memory load level is Level II, the second sub-strategy (e.g., the second sub-optimization strategy in a later embodiment) is executed to release cached data of category B in memory. Optimizing different categories of cached data has different degrees of impact on the target program. Generally, cached data with large memory usage is a critical category that has a greater impact on the business function experience of the target program, while cached data with small memory usage is a non-critical category that has a smaller impact on the business function experience of the target program. Therefore, in this embodiment, by dynamically releasing cached data of the corresponding type according to the memory load level, the necessary cached data in the target program is guaranteed to the greatest extent while releasing memory, thereby improving the functional experience of the program.

[0058] In this embodiment, memory operation information is obtained after the target program runs; based on the memory operation information, a memory load level is obtained, where the memory load level represents the memory load level for the memory requirements of the target program; based on the memory load level, a target optimization strategy is executed, where the target optimization strategy includes at least two conditionally executed sub-optimization strategies. The sub-optimization strategies are used to release cached data of the corresponding type in memory, and the execution conditions of the sub-optimization strategies correspond to the memory load level. By determining the memory load level for the memory requirements of the target program based on real-time memory operation information after the program runs, and generating a memory load level, the target optimization strategy is then executed based on the memory load level to execute the sub-optimization strategies corresponding to the memory load level and release cached data of the corresponding type. This achieves dynamic memory reclamation based on the memory load level, making the memory reclamation action for the target program more accurate and effective, avoiding problems such as slow program loading speed and program lag caused by excessive memory reclamation and untimely memory reclamation, and improving the user experience of the application.

[0059] refer to Figure 6 , Figure 6 Flowchart of the memory optimization method provided in the embodiments of this disclosure Figure 2 This embodiment is in Figure 2 Based on the illustrated embodiment, step S103 is further refined, and the memory optimization method includes:

[0060] Step S201: After the target program runs, obtain memory operation information.

[0061] Step S202: Based on the memory operation information, obtain the memory load level, where the memory load level represents the memory load level for the memory requirements of the target program.

[0062] For example, the target optimization strategy includes a first sub-optimization strategy and a second sub-optimization strategy, and after step S202, it further includes:

[0063] Step S203: When the memory load level is the first load level, execute the first sub-optimization strategy, which is used to release the first type of cached data in memory.

[0064] For example, the memory load level corresponding to the first load level is lower than the memory load level corresponding to the second load level. Specifically, the first load level specifically represents "slight memory shortage" or "low memory redundancy," while the second load level specifically represents "severe memory shortage." Of course, more load levels representing different load levels can be defined as needed, but these will not be elaborated on here. Taking the case of only dividing the first and second load levels as an example, when the memory load level is the first load level, the first sub-optimization strategy is executed. The first sub-optimization strategy is used to release the first type of cached data in memory. Specifically, the first type of cached data refers to device-specific cached data, such as performance monitoring data, frame rate data, slow function data, image loading monitoring data, page loading time data, etc. The above data are all device-specific cached data, that is, not only cached data used for the current target application. When the memory load level is the first load level (i.e., the lighter case), the general cached data is requested first. On the one hand, this can release some memory resources, and on the other hand, it can hardly affect the business functions of the target program.

[0065] One possible implementation is, such as Figure 7 As shown, the specific implementation of step S203 includes:

[0066] Step S2031: When the memory load level is the first load level, obtain at least one non-memory operation information, which includes the following: processor utilization, interface frame rate, and number of garbage collections.

[0067] Step S2032: If the non-memory running information meets the target conditions, then execute the first sub-optimization strategy, wherein the first type of cached data is general-purpose cached data for the device.

[0068] For example, when the memory load level is at the first load level, it can be assumed that the target program is not currently experiencing lag or slowdown. However, it is necessary to take preventative measures against insufficient memory to avoid program lag and ensure continuous smooth operation. At the same time, since general-purpose cached data may affect other programs and multitasking processes on the terminal device, in this embodiment, when the memory load level is determined to be at the first load level, the terminal device first obtains non-memory operating information, such as processor utilization, interface frame rate, and garbage collection count. Then, based on this non-memory operating information, the device's operating status is further assessed. If the processor utilization, interface frame rate, or garbage collection count is abnormal—for example, the processor utilization is greater than a utilization threshold, the interface frame rate is less than a frame rate threshold, or the number of garbage collections (per unit time) is greater than a count threshold—then a first sub-optimization strategy is executed to achieve preventative memory optimization. If no problems are found in the non-memory operating information, the first sub-optimization strategy can be temporarily suspended to avoid excessive cache data cleanup. Through these steps, the smoothness and stability of the program's operation can be further improved.

[0069] Step S204: When the memory load level is the second load level, execute the second sub-optimization strategy. The second sub-optimization strategy includes at least two chain-triggered optimization steps. The at least two chain-triggered optimization steps are used to release different types of cached data in memory, and at least one optimization step has a pre-triggered condition.

[0070] For example, the second sub-optimization strategy includes a chained, conditionally triggered first optimization step and a second optimization step. Specifically, the first optimization step and the second optimization step are progressively triggered optimization steps. If the desired effect is not achieved after the first optimization step is executed, the second optimization step is executed. That is, the second optimization step has a pre-triggered condition. For example, after the first optimization step is executed, the updated memory load level is obtained. If the updated memory load level is still the second load level, the second optimization step is executed. Otherwise, if the updated memory load level is reduced to the first load level or a lower load level, the second optimization step is not executed.

[0071] Meanwhile, the memory data released in the two optimization steps are of different types. For example, the first optimization step releases general cache data for the device in memory, which is the same optimization process performed by the first sub-optimization strategy. The second optimization step releases business cache data for the target program in memory. This business cache data includes data required to run the target program or functions within the target program. Taking a video editing application as an example, business cache data may include template cache data, image library memory cache data, video player cache data, video frame cache data, etc.

[0072] One possible implementation is, such as Figure 8 As shown, the specific implementation of step S204 includes:

[0073] Step S2041: When the memory load level is the second load level, execute the first optimization step.

[0074] Step S2042: After the first optimization step is completed, obtain the updated memory load level.

[0075] Step S2043: If the memory load level is the second load level, then execute the second optimization step.

[0076] Step S2044: After the second optimization step is completed, obtain the updated memory load level.

[0077] Optionally, after step S2044, the method further includes:

[0078] Step S2045: If the memory load level is the second load level, then execute the third optimization step, which is used to reduce the business performance of the target program.

[0079] For example, in the steps provided in this disclosure embodiment, if the optimization effect still does not meet the requirements after the second optimization step is performed, a third optimization step can be further performed to further release memory resources. Specifically, after performing the second optimization step (releasing business cache data), the memory load level is updated. At this time, if the memory load level is still the second load level, that is, the memory is severely insufficient, the business performance of the target program is reduced, thereby reducing the memory required to run the target program, that is, reducing the memory requirement of the target program referred to in step S202, thereby achieving the purpose of reducing the memory load level. The specific implementation of reducing the business performance of the target program can be achieved by executing a script to adjust the running parameters of the target program. For example, the third optimization step includes at least one of the following: reducing the color format level of the bitmap used in the target program; reducing the resolution of the materials used in the target program; reducing the number of special effects used in the target program; converting the dynamic images used in the target program into static images; and unloading the foreground invisible functional modules used in the target program.

[0080] Meanwhile, in this embodiment, after steps S203 and S204 are completed, the process returns to step S202 to obtain updated memory operation information and the corresponding updated memory load level. The above steps are then repeated to achieve continuous memory optimization for the target program, ensuring the program always runs smoothly. It should also be noted that in the above embodiment, if the conditions in the triggering steps are not met, the process can return to the step of obtaining memory operation information (e.g., step S201) to collect updated memory operation information until the conditions in the above steps are met.

[0081] Figure 9 This is a schematic diagram illustrating the process of implementing an objective optimization strategy according to an embodiment of the present disclosure. The following is in conjunction with... Figure 9 To further explain the above process, such as... Figure 9As illustrated, exemplarily, firstly, after obtaining the memory load level based on memory operation information, if the memory load level is the first load level, a first sub-optimization strategy is invoked. This strategy uses additional non-memory operation information as a trigger condition. After the first sub-optimization strategy is triggered, the first optimization step is executed to release general cached data for the device in memory, completing the memory optimization process. Afterward, the step of obtaining the memory load level based on the memory operation information is periodically re-executed. On the other hand, if the memory load level is the second load level, a second sub-optimization strategy is invoked, conditionally chaining the first, second, and third optimization steps. After the first and second optimization steps are completed, an updated memory load level is obtained as a prerequisite for triggering the next optimization step. The memory optimization process ends when the third optimization step is completed or the execution condition for the next optimization step is no longer met.

[0082] In this embodiment, the first and second sub-optimization strategies are executed according to different memory load levels. When the memory load is low, the first sub-optimization strategy is used to preventively release general cache data, thereby ensuring that the target program has a large memory redundancy during operation and ensuring the stability and smoothness of program operation. When the memory load is high, the second sub-optimization strategy is used to conditionally trigger the corresponding optimization steps in multiple stages, thereby ensuring the memory required for the target program to run while minimizing the release of cache data in memory and minimizing the reduction of program business performance, thus improving the stability, smoothness and business performance of program operation.

[0083] In this embodiment, the implementation of steps S201-S202 is the same as that in this disclosure. Figure 2 The implementation methods of steps S101-S102 in the illustrated embodiment are the same, and will not be described in detail here.

[0084] Corresponding to the memory optimization method in the above embodiments, Figure 10 This is a structural block diagram of a memory optimization device provided in an embodiment of this disclosure. The method described in the above embodiments can be executed by this memory optimization device, which can be implemented by software and / or hardware, and can be integrated into an electronic device with certain data processing capabilities. The electronic device may include, but is not limited to, mobile terminals with big data processing capabilities, as well as fixed terminals with big data processing capabilities such as desktop computers and supercomputers.

[0085] For ease of explanation, only the parts relevant to embodiments of this disclosure are shown. (Refer to...) Figure 10 The memory optimization device 3 includes:

[0086] The acquisition module 31 is used to acquire memory operation information after the target program runs.

[0087] The load module 32 is used to obtain the memory load level based on the memory operation information, wherein the memory load level represents the memory load level for the memory requirements of the target program.

[0088] The strategy module 33 is used to execute a target optimization strategy based on the memory load level. The target optimization strategy includes at least two conditionally executed sub-optimization strategies. The sub-optimization strategies are used to release cached data of the corresponding type in memory. The execution conditions of the sub-optimization strategies correspond to the memory load level.

[0089] According to one or more embodiments of this disclosure, the load module 32 is specifically configured to: obtain a first memory status value and a second memory status value based on memory operation information, wherein the first memory status value represents memory utilization and the second memory status value represents the remaining memory amount; obtain a corresponding memory threshold group based on the memory category corresponding to the memory operation information, wherein the memory threshold group includes at least two threshold pairs, and the at least two threshold pairs correspond one-to-one with at least two preset memory load levels; and obtain the memory load level based on the numerical matching relationship between the first memory status value, the second memory status value and the threshold pairs in the memory threshold group.

[0090] According to one or more embodiments of this disclosure, the threshold pair includes a first memory threshold and a second memory threshold. When the load module 32 obtains the memory load level based on the numerical matching relationship between the first memory state value and the second memory state value and the threshold pair in the memory threshold group, it is specifically used to: when the first memory state value is greater than or equal to the first memory threshold in the target threshold pair and the second memory state value is less than the second memory threshold in the target threshold pair, determine the preset memory load level corresponding to the target threshold pair as the memory load level.

[0091] According to one or more embodiments of this disclosure, the memory category corresponding to the memory operation information includes one of the following: process physical memory, process virtual memory, and device physical memory; wherein, the first memory threshold corresponding to process physical memory is less than the first memory threshold corresponding to process virtual memory and greater than the first memory threshold corresponding to device physical memory; the second memory threshold corresponding to process virtual memory is less than the second memory threshold corresponding to process physical memory and greater than the second memory threshold corresponding to device physical memory.

[0092] According to one or more embodiments of this disclosure, the target optimization strategy includes a first sub-optimization strategy and a second sub-optimization strategy. The strategy module 33 is specifically used to include: when the memory load level is a first load level, executing the first sub-optimization strategy, which is used to release cached data of a first type in memory; when the memory load level is a second load level, executing the second sub-optimization strategy, which includes at least two chain-triggered optimization steps, each of which is used to release cached data of a different type in memory, and at least one optimization step has a pre-triggered condition; wherein the memory load level corresponding to the first load level is lower than the memory load level corresponding to the second load level.

[0093] According to one or more embodiments of this disclosure, the second sub-optimization strategy includes a chain-triggered first optimization step and a second optimization step, wherein the first optimization step is used to release general cache data for the device in memory; the second optimization step is used to release business cache data for the target program in memory; the pre-triggered condition for the second optimization step includes: after the first optimization step is completed, the memory load level is the second load level.

[0094] According to one or more embodiments of this disclosure, the second sub-optimization strategy further includes a third optimization step triggered after the second optimization step, the third optimization step being used to reduce the business performance of the target program.

[0095] According to one or more embodiments of this disclosure, the target program is a video editing program, and the third optimization step includes at least one of the following: reducing the color format level of the bitmap used in the target program; reducing the resolution of the material used in the target program; reducing the number of special effects used in the target program; converting the dynamic images used in the target program into static images; and unloading the foreground-invisible functional modules used in the target program.

[0096] According to one or more embodiments of this disclosure, when the strategy module 33 executes the first sub-optimization strategy when the memory load level is the first load level, it is specifically used to: when the memory load level is the first load level, obtain at least one non-memory operation information, the non-memory operation information including the following: processor utilization, interface frame rate, garbage collection count; if the non-memory operation information meets the target conditions, then execute the first sub-optimization strategy, wherein the first type of cache data is general-purpose cache data for the device.

[0097] The acquisition module 31, load module 32, and strategy module 33 are connected sequentially. The memory optimization device 3 provided in this embodiment can execute the technical solutions of the above method embodiments, and its implementation principle and technical effects are similar; therefore, they will not be described again here.

[0098] Figure 11 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure, such as... Figure 11 As shown, the electronic device 4 includes:

[0099] Processor 41, and memory 42 communicatively connected to processor 41;

[0100] Memory 42 stores instructions executed by the computer;

[0101] The processor 41 executes computer execution instructions stored in the memory 42 to achieve, for example, Figures 2-9 The memory optimization method in the illustrated embodiment.

[0102] Optionally, the processor 41 and the memory 42 are connected via a bus 43.

[0103] For relevant instructions, please refer to the corresponding text. Figures 2-9 The relevant descriptions and effects of the steps in the corresponding embodiments are understood, and will not be elaborated on here.

[0104] This disclosure provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement this disclosure. Figures 2-9 The memory optimization method provided in any of the corresponding embodiments.

[0105] This disclosure provides a computer program product, including a computer program, which, when executed by a processor, implements this disclosure. Figures 2-9 The memory optimization provided in any of the corresponding embodiments.

[0106] To implement the above embodiments, this disclosure also provides an electronic device.

[0107] refer to Figure 12 The diagram illustrates a structural schematic of an electronic device 900 suitable for implementing embodiments of the present disclosure. The electronic device 900 can be a terminal device or a server. The terminal device can include, but is not limited to, mobile terminals such as mobile phones, laptops, digital radio receivers, personal digital assistants (PDAs), portable Android devices (PADs), portable media players (PMPs), and in-vehicle terminals (e.g., in-vehicle navigation terminals), as well as fixed terminals such as digital TVs and desktop computers. Figure 12 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0108] like Figure 12 As shown, the electronic device 900 may include a processing unit (e.g., a central processing unit, a graphics processing unit, etc.) 901, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 902 or a program loaded from a storage device 908 into a random access memory (RAM) 903. The RAM 903 also stores various programs and data required for the operation of the electronic device 900. The processing unit 901, ROM 902, and RAM 903 are interconnected via a bus 904. An input / output (I / O) interface 905 is also connected to the bus 904.

[0109] Typically, the following devices can be connected to I / O interface 905: input devices 906 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 907 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 908 including, for example, magnetic tapes, hard disks, etc.; and communication devices 909. Communication device 909 allows electronic device 900 to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 12 An electronic device 900 with various devices is shown; however, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively.

[0110] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 909, or installed from a storage device 908, or installed from a ROM 902. When the computer program is executed by a processing device 901, it performs the functions defined in the methods of embodiments of this disclosure.

[0111] It should be noted that the computer-readable medium described in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0112] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device.

[0113] The aforementioned computer-readable medium carries one or more programs, which, when executed by the electronic device, cause the electronic device to perform the methods shown in the above embodiments.

[0114] Computer program code for performing the operations of this disclosure can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0115] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0116] The units or modules described in the embodiments of this disclosure can be implemented in software or hardware. The names of the units or modules do not necessarily limit the specific unit itself.

[0117] The functions described above in this document can be performed, at least in part, by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: Field Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), Application Standard Products (ASSPs), System-on-Chip (SoCs), Complex Programmable Logic Devices (CPLDs), and so on.

[0118] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0119] In a first aspect, according to one or more embodiments of this disclosure, a memory optimization method is provided, comprising:

[0120] After the target program runs, memory operation information is obtained; based on the memory operation information, a memory load level is obtained, wherein the memory load level represents the memory load level for the memory requirements of the target program; based on the memory load level, a target optimization strategy is executed, wherein the target optimization strategy includes at least two conditionally executed sub-optimization strategies, the sub-optimization strategies are used to release cached data of the corresponding type in memory, and the execution conditions of the sub-optimization strategies correspond to the memory load level.

[0121] According to one or more embodiments of this disclosure, obtaining the memory load level based on the memory operation information includes: obtaining a first memory status value and a second memory status value based on the memory operation information, wherein the first memory status value represents memory utilization and the second memory status value represents the remaining memory amount; obtaining a corresponding memory threshold group based on the memory category corresponding to the memory operation information, wherein the memory threshold group includes at least two threshold pairs, and the at least two threshold pairs correspond one-to-one with at least two preset memory load levels; and obtaining the memory load level based on the numerical matching relationship between the first memory status value and the second memory status value and the threshold pairs in the memory threshold group.

[0122] According to one or more embodiments of this disclosure, the threshold pair includes a first memory threshold and a second memory threshold. The step of obtaining the memory load level based on the numerical matching relationship between the first memory state value and the second memory state value and the threshold pair in the memory threshold group includes: when the first memory state value is greater than or equal to the first memory threshold in the target threshold pair, and the second memory state value is less than the second memory threshold in the target threshold pair, the preset memory load level corresponding to the target threshold pair is determined as the memory load level.

[0123] According to one or more embodiments of this disclosure, the memory category corresponding to the memory operation information includes one of the following: process physical memory, process virtual memory, and device physical memory; wherein, the first memory threshold corresponding to the process physical memory is less than the first memory threshold corresponding to the process virtual memory and greater than the first memory threshold corresponding to the device physical memory; the second memory threshold corresponding to the process virtual memory is less than the second memory threshold corresponding to the process physical memory and greater than the second memory threshold corresponding to the device physical memory.

[0124] According to one or more embodiments of this disclosure, the target optimization strategy includes a first sub-optimization strategy and a second sub-optimization strategy. Executing the target optimization strategy according to the memory load level includes: when the memory load level is a first load level, executing the first sub-optimization strategy, which is used to release cached data of a first type in memory; when the memory load level is a second load level, executing the second sub-optimization strategy, which includes at least two chained optimization steps, each chained optimization step being used to release cached data of a different type in memory, and at least one of the optimization steps having a pre-triggered condition; wherein the memory load level corresponding to the first load level is lower than the memory load level corresponding to the second load level.

[0125] According to one or more embodiments of this disclosure, the second sub-optimization strategy includes a chain-triggered first optimization step and a second optimization step, wherein the first optimization step is used to release general cache data for the device in memory; the second optimization step is used to release business cache data for the target program in memory; and the pre-triggered condition for the second optimization step includes: after the first optimization step is completed, the memory load level is the second load level.

[0126] According to one or more embodiments of this disclosure, the second sub-optimization strategy further includes a third optimization step triggered after the second optimization step, the third optimization step being used to reduce the business performance of the target program.

[0127] According to one or more embodiments of this disclosure, the target program is a video editing program, and the third optimization step includes at least one of the following: reducing the color format level of the bitmaps used in the target program; reducing the resolution of the materials used in the target program; reducing the number of special effects used in the target program; converting the dynamic images used in the target program into static images; and uninstalling the foreground-invisible functional modules used in the target program.

[0128] According to one or more embodiments of this disclosure, the step of executing a first sub-optimization strategy when the memory load level is a first load level includes: when the memory load level is a first load level, acquiring at least one piece of non-memory operating information, the non-memory operating information including one of the following: processor utilization, interface frame rate, and garbage collection count; if the non-memory operating information meets the target conditions, then executing the first sub-optimization strategy, wherein the first type of cache data is general-purpose cache data for the device.

[0129] Secondly, according to one or more embodiments of this disclosure, a memory optimization apparatus is provided, comprising:

[0130] The acquisition module is used to obtain memory operation information after the target program runs.

[0131] The load module is used to obtain the memory load level based on the memory operation information, wherein the memory load level represents the memory load level for the memory requirements of the target program.

[0132] The strategy module is used to execute a target optimization strategy based on the memory load level, wherein the target optimization strategy includes at least two conditionally executed sub-optimization strategies, the sub-optimization strategies being used to release cached data of the corresponding type in memory, and the execution conditions of the sub-optimization strategies corresponding to the memory load level.

[0133] According to one or more embodiments of this disclosure, the load module is specifically configured to: obtain a first memory status value and a second memory status value based on the memory operation information, wherein the first memory status value represents memory utilization and the second memory status value represents the remaining memory amount; obtain a corresponding memory threshold group based on the memory category corresponding to the memory operation information, wherein the memory threshold group includes at least two threshold pairs, and the at least two threshold pairs correspond one-to-one with at least two preset memory load levels; and obtain the memory load level based on the numerical matching relationship between the first memory status value and the second memory status value and the threshold pairs in the memory threshold group.

[0134] According to one or more embodiments of this disclosure, the threshold pair includes a first memory threshold and a second memory threshold. When the load module obtains the memory load level based on the numerical matching relationship between the first memory state value and the second memory state value and the threshold pair in the memory threshold group, it is specifically used to: when the first memory state value is greater than or equal to the first memory threshold in the target threshold pair, and the second memory state value is less than the second memory threshold in the target threshold pair, determine the preset memory load level corresponding to the target threshold pair as the memory load level.

[0135] According to one or more embodiments of this disclosure, the memory category corresponding to the memory operation information includes one of the following: process physical memory, process virtual memory, and device physical memory; wherein, the first memory threshold corresponding to the process physical memory is less than the first memory threshold corresponding to the process virtual memory and greater than the first memory threshold corresponding to the device physical memory; the second memory threshold corresponding to the process virtual memory is less than the second memory threshold corresponding to the process physical memory and greater than the second memory threshold corresponding to the device physical memory.

[0136] According to one or more embodiments of this disclosure, the target optimization strategy includes a first sub-optimization strategy and a second sub-optimization strategy. The strategy module is specifically configured to: execute the first sub-optimization strategy when the memory load level is a first load level, wherein the first sub-optimization strategy is used to release cached data of a first type in memory; execute the second sub-optimization strategy when the memory load level is a second load level, wherein the second sub-optimization strategy includes at least two chain-triggered optimization steps, wherein the at least two chain-triggered optimization steps are respectively used to release cached data of different types in memory, and at least one of the optimization steps has a pre-triggered condition; wherein the memory load level corresponding to the first load level is lower than the memory load level corresponding to the second load level.

[0137] According to one or more embodiments of this disclosure, the second sub-optimization strategy includes a chain-triggered first optimization step and a second optimization step, wherein the first optimization step is used to release general cache data for the device in memory; the second optimization step is used to release business cache data for the target program in memory; and the pre-triggered condition for the second optimization step includes: after the first optimization step is completed, the memory load level is the second load level.

[0138] According to one or more embodiments of this disclosure, the second sub-optimization strategy further includes a third optimization step triggered after the second optimization step, the third optimization step being used to reduce the business performance of the target program.

[0139] According to one or more embodiments of this disclosure, the target program is a video editing program, and the third optimization step includes at least one of the following: reducing the color format level of the bitmaps used in the target program; reducing the resolution of the materials used in the target program; reducing the number of special effects used in the target program; converting the dynamic images used in the target program into static images; and uninstalling the foreground-invisible functional modules used in the target program.

[0140] According to one or more embodiments of this disclosure, when the strategy module executes the first sub-optimization strategy when the memory load level is a first load level, it is specifically configured to: when the memory load level is a first load level, obtain at least one piece of non-memory operating information, the non-memory operating information including the following: processor utilization, interface frame rate, and garbage collection count; if the non-memory operating information meets the target conditions, then execute the first sub-optimization strategy, wherein the first type of cache data is general-purpose cache data for the device.

[0141] Thirdly, according to one or more embodiments of the present disclosure, an electronic device is provided, comprising: at least one processor and a memory;

[0142] The memory stores computer-executed instructions;

[0143] The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the memory optimization method described in the first aspect and various possible designs of the first aspect.

[0144] Fourthly, according to one or more embodiments of the present disclosure, a computer-readable storage medium is provided, wherein computer-executable instructions are stored therein, and when a processor executes the computer-executable instructions, the memory optimization method described in the first aspect and various possible designs of the first aspect is implemented.

[0145] Fifthly, according to one or more embodiments of the present disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements the memory optimization method described in the first aspect and various possible designs of the first aspect.

[0146] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

[0147] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0148] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

Claims

1. A memory optimization method, characterized in that, include: After the target program runs, obtain memory operation information; Based on the memory operation information, the memory load level is obtained, wherein the memory load level represents the memory load level for the memory requirements of the target program; Based on the memory load level, a target optimization strategy is executed, wherein the target optimization strategy includes at least two conditionally executed sub-optimization strategies, the sub-optimization strategies being used to release cached data of the corresponding type in memory, and the execution conditions of the sub-optimization strategies corresponding to the memory load level.

2. The method according to claim 1, characterized in that, The step of obtaining the memory load level based on the memory operation information includes: Based on the memory operation information, a first memory status value and a second memory status value are obtained, wherein the first memory status value represents the memory utilization rate and the second memory status value represents the remaining memory amount; Based on the memory category corresponding to the memory operation information, a corresponding memory threshold group is obtained. The memory threshold group includes at least two threshold pairs, and the at least two threshold pairs correspond one-to-one with at least two preset memory load levels. The memory load level is obtained based on the numerical matching relationship between the first memory state value, the second memory state value and the threshold pairs in the memory threshold group.

3. The method according to claim 2, characterized in that, The threshold pair includes a first memory threshold and a second memory threshold. The step of obtaining the memory load level based on the numerical matching relationship between the first memory state value and the second memory state value and the threshold pairs in the memory threshold group includes: When the first memory status value is greater than or equal to the first memory threshold in the target threshold pair, and the second memory status value is less than the second memory threshold in the target threshold pair, the preset memory load level corresponding to the target threshold pair is determined as the memory load level.

4. The method according to claim 2, characterized in that, The memory category corresponding to the memory operation information includes one of the following: Process physical memory, process virtual memory, device physical memory; Wherein, the first memory threshold corresponding to the process physical memory is less than the first memory threshold corresponding to the process virtual memory, and greater than the first memory threshold corresponding to the device physical memory; The second memory threshold corresponding to the process virtual memory is less than the second memory threshold corresponding to the process physical memory, but greater than the second memory threshold corresponding to the device physical memory.

5. The method according to claim 1, characterized in that, The target optimization strategy includes a first sub-optimization strategy and a second sub-optimization strategy. Executing the target optimization strategy according to the memory load level includes: When the memory load level is the first load level, the first sub-optimization strategy is executed, which is used to release cached data of the first type in memory; When the memory load level is the second load level, a second sub-optimization strategy is executed. The second sub-optimization strategy includes at least two chain-triggered optimization steps, which are respectively used to release different types of cached data in memory, and at least one of the optimization steps has a pre-triggered condition. The memory load level corresponding to the first load level is lower than the memory load level corresponding to the second load level.

6. The method according to claim 5, characterized in that, The second sub-optimization strategy includes a chain-triggered first optimization step and a second optimization step, wherein the first optimization step is used to release general cache data for the device in memory; and the second optimization step is used to release business cache data for the target program in memory. The prerequisite for the second optimization step includes: after the first optimization step is completed, the memory load level is the second load level.

7. The method according to claim 6, characterized in that, The second sub-optimization strategy also includes a third optimization step triggered after the second optimization step, the third optimization step being used to reduce the business performance of the target program.

8. The method according to claim 7, characterized in that, The target program is a video editing program, and the third optimization step includes at least one of the following: Reduce the color format level of the bitmaps used in the target program; Reduce the resolution of the materials used in the target program; Reduce the number of special effects used in the target program; Convert the animated images used in the target program into static images; Uninstall the foreground-invisible functional modules used in the target program.

9. The method according to claim 5, characterized in that, When the memory load level is the first load level, the first sub-optimization strategy is executed, including: When the memory load level is the first load level, at least one non-memory operation information is obtained, including the following: processor utilization, interface frame rate, and number of garbage collections. If the non-memory runtime information meets the target conditions, the first sub-optimization strategy is executed, wherein the first type of cached data is general-purpose cached data for the device.

10. A memory optimization device, characterized in that, include: The acquisition module is used to obtain memory runtime information after the target program has run. The load module is used to obtain the memory load level based on the memory operation information, wherein the memory load level represents the memory load level for the memory requirements of the target program; The strategy module is used to execute a target optimization strategy based on the memory load level, wherein the target optimization strategy includes at least two conditionally executed sub-optimization strategies, the sub-optimization strategies being used to release cached data of the corresponding type in memory, and the execution conditions of the sub-optimization strategies corresponding to the memory load level.

11. An electronic device, characterized in that, include: Processor and memory; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory, causing the processor to perform the memory optimization method as described in any one of claims 1 to 9.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, implement the memory optimization method as described in any one of claims 1 to 9.

13. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the memory optimization method as described in any one of claims 1 to 9.

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