Cache architecture, method, electronic device and storage medium of AXI interconnection module

Abstract

The application provides a cache architecture of an AXI interconnection module, a method, an electronic device and a storage medium, and relates to the technical field of storage. The cache architecture comprises an index cache area, a shared cache area and a shared cache access controller. The index cache area comprises an index entry list, and the shared cache area comprises an instruction cache area and a data cache area. Each index cache area corresponds to a master device, and the shared cache area corresponds to all master devices. The index entry list is used to record index information of an access transaction of a corresponding master device. Each index entry in the index entry list corresponds to an access transaction. The shared cache access controller is used to store instruction information corresponding to the access transaction in the instruction cache area and store data information corresponding to the access transaction in the data cache area based on the index information. The scheme of the application can improve the on-chip resource utilization efficiency on the basis of ensuring the transaction processing performance.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a caching architecture, method, electronic device, and storage medium for an AXI interconnect module. Background Technology

[0002] The Advanced eXtensible Interface 4 (AXI4) is a core component of the Advanced Microcontroller Bus Architecture 4 (AMBA4) and is primarily used to enable high-speed data communication between functional modules within a System on Chip (SoC). The AXI4 protocol employs a point-to-point transmission mechanism, meaning it only supports direct information exchange between two modules at a time. However, in actual SoC designs, there are often multiple master and slave devices. In such cases, AXI4 interconnect modules are needed to route transmission transactions between multiple devices to meet the communication requirements of multiple masters and slaves. AXI4 interconnect modules can be categorized into three topologies based on the number of master and slave devices: single-master multi-slave, multi-master single-slave, and multi-master multi-slave. The multi-master multi-slave topology, in particular, presents a design challenge due to the complex inter-device interactions.

[0003] In multi-master, multi-slave scenarios, achieving transparent AXI transmission (i.e., master and slave devices do not need to be aware of the interconnect module's existence, and the communication logic is consistent with point-to-point transmission) requires compatibility with several key features of the AXI4 protocol, including Outstanding Transactions, Out-of-Order Responses, and ReadInterleave. These features necessitate complex caching structures in the AXI4 interconnect module to temporarily store incomplete requests and data, while also requiring arbitration logic to coordinate access conflicts between multiple master devices and slave devices. However, SoC on-chip resources have physical limitations; therefore, reducing resource consumption while ensuring AXI4 interconnect module functionality compliance becomes a pressing technical challenge. Summary of the Invention

[0004] This application provides a caching architecture, method, electronic device, and storage medium for an AXI interconnect module, in order to at least solve the above-mentioned technical problems existing in the prior art.

[0005] According to a first aspect of this application, a caching architecture for an AXI interconnect module is provided. The caching architecture includes an index cache, a shared cache, and a shared cache access controller. The index cache includes a list of index entries, and the shared cache includes an instruction cache and a data cache. Each index cache corresponds to one master device, and the shared cache corresponds to all master devices, wherein:

[0006] The index entry list is used to record the index information of the access transactions of the corresponding master device; each index entry in the index entry list corresponds to one access transaction.

[0007] The shared cache access controller is used to store the instruction information corresponding to the access transaction in the instruction cache area and the data information corresponding to the access transaction in the data cache area based on the index information.

[0008] In one possible implementation, the index cache further includes an instruction temporary storage area and a data temporary storage area, wherein,

[0009] The instruction buffer is used to temporarily store instruction information for the current access transaction;

[0010] The data temporary storage area is used to temporarily store the data information of the current access transaction.

[0011] In one possible implementation, the index information includes an instruction cache index, urgency, slave device number, access type, and status value, wherein,

[0012] The instruction cache index is the storage location index of the instruction information corresponding to the access transaction in the instruction cache area;

[0013] The urgency level is the processing priority of the access transaction;

[0014] The slave device number is the slave device number corresponding to the access transaction;

[0015] The access type is the operation type of the access transaction;

[0016] The status value indicates the current execution phase of the access transaction.

[0017] In one possible implementation, the index cache is used to update the status values ​​in the index information in real time according to the current execution stage of the access transaction; the execution stage includes waiting to send, sending, response in progress, waiting to receive, and invalid.

[0018] In one possible implementation, the index cache is further configured to, in response to the presence of an invalid index entry in the index entry list, rearrange the entry positions of the index entries other than the invalid index entries based on the status value and index value of each index entry.

[0019] In one possible implementation, the index cache is further used to filter index entries whose slave device numbers point to the same slave device, and determine the index entry with the lowest urgency as the sending front entry;

[0020] If there are multiple index entries with the same urgency, the index entry with the smallest index value is determined as the sending front entry; the sending front entry is the index entry that initiates the access request to the corresponding slave device first.

[0021] In one possible implementation, the instruction cache includes an instruction memory and an instruction status table;

[0022] The instruction memory includes a preset number of instruction entries, and each instruction entry corresponds to an access transaction;

[0023] The instruction status in the instruction status table corresponds one-to-one with the instruction entries in the instruction memory, and is used to mark whether the corresponding instruction entry is occupied.

[0024] In one possible implementation, each instruction entry stores instruction information for the access transaction, including AXI instruction information, a data cache address header, a data cache address tail, and a data cache operation address, wherein...

[0025] The AXI instruction information includes the address channel information and response transaction information of the access transaction;

[0026] The data cache address header is the index header of the data cache area that the access transaction needs to allocate;

[0027] The data cache address tail is the index tail of the data cache area that the access transaction needs to allocate;

[0028] The data cache operation address is the index identifier of the next data operation position.

[0029] In one possible implementation, the data cache includes a data storage device and a data status table;

[0030] The data storage includes a preset number of data entries, and one or more consecutive data entries correspond to one access transaction;

[0031] The data status in the data status table corresponds one-to-one with the data entries in the data storage, and is used to mark whether the corresponding data entry is occupied.

[0032] In one possible implementation, the shared cache access controller is further configured to:

[0033] In response to the instruction buffer of any index cache being in a non-empty state, instruction information to be stored is selected from the non-empty instruction buffer based on the urgency of the index entry list.

[0034] In response to the presence of an invalid instruction entry in the instruction cache and a consecutive unoccupied data entry in the data cache that meets the conditions, the instruction information to be stored is stored in the instruction cache.

[0035] In one possible implementation, the shared cache access controller is further configured to:

[0036] In response to the fact that the data buffer of any index cache is not empty, or that there is data in any slave device read data channel, the data information to be stored is determined based on the instruction entry corresponding to the data information.

[0037] The data to be stored is stored in the data cache area.

[0038] In one possible implementation, the shared cache access controller is further configured to:

[0039] In response to the existence of instruction information to be retrieved, the instruction information to be retrieved is retrieved from the instruction buffer according to the index entry, so as to send the instruction information to be retrieved to the address channel of the target slave device through the sending module;

[0040] Obtain the transaction response instruction information sent by the target slave device based on the instruction information to be retrieved, and replace the AXI instruction information in the instruction entry with the transaction response instruction information.

[0041] In one possible implementation, the shared cache access controller is further configured to:

[0042] In response to the existence of data information to be retrieved, the target instruction entry corresponding to the data information to be retrieved is determined according to the index entry;

[0043] According to the target instruction entry, retrieve the data information to be retrieved from the data buffer.

[0044] According to a second aspect of this application, a caching method for an AXI interconnect module is provided. The method is applied to the caching architecture of the AXI interconnect module, which includes an index cache, a shared cache, and a shared cache access controller. The index cache includes a list of index entries, and the shared cache includes an instruction cache and a data cache. Each index cache corresponds to one master device, and the shared cache corresponds to all master devices. The method includes:

[0045] The index entry list records the index information of the access transactions of the corresponding master device; each index entry in the index entry list corresponds to one access transaction.

[0046] The shared cache access controller stores the instruction information corresponding to the access transaction in the instruction cache area based on the index information, and stores the data information corresponding to the access transaction in the data cache area.

[0047] In one possible implementation, the index cache further includes an instruction temporary storage area and a data temporary storage area;

[0048] Accordingly, the method further includes:

[0049] The instruction information for the current access transaction is temporarily stored in the instruction buffer area;

[0050] The data information of the current access transaction is temporarily stored in the data temporary storage area.

[0051] In one possible implementation, the index information includes an instruction cache index, urgency, slave device number, access type, and status value, wherein,

[0052] The instruction cache index is an index that records the storage location of the instruction information corresponding to the access transaction in the instruction cache area;

[0053] The urgency level is the processing priority of the access transaction;

[0054] The slave device number is the slave device number corresponding to the access transaction;

[0055] The access type is the operation type of the access transaction;

[0056] The status value indicates the execution phase of the access transaction.

[0057] In one possible implementation, the method further includes:

[0058] The index cache updates the status values ​​in the index information in real time according to the current execution stage of the access transaction; the execution stages include waiting to send, sending, response in progress, waiting to receive, and invalid.

[0059] In one possible implementation, the method further includes:

[0060] In response to the presence of an invalid index entry in the index entry list via the index cache, the positions of the index entries other than the invalid index entry are rearranged based on the status value and index value of each index entry.

[0061] According to a third aspect of this application, an electronic device is provided, comprising:

[0062] At least one processor; and,

[0063] A memory communicatively connected to the at least one processor; wherein,

[0064] The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method described in this application.

[0065] According to a fourth aspect of this application, a non-transitory computer-readable storage medium is provided storing computer instructions for causing the computer to perform the methods described in this application.

[0066] The caching architecture, method, electronic device, and storage medium of the AXI interconnect module in this application adopt a two-level caching structure. The first level is an index cache dedicated to each master device, and the second level is a shared cache area shared by all master devices. Utilizing this caching structure, unnecessary blocking during the operation of the AXI4 interconnect module can be reduced through the division of labor and cooperation between the two levels of caching, effectively improving overall operating efficiency. Simultaneously, on the one hand, by configuring a separate index cache for each master device, the cache capacity requirements during concentrated bursts of access transactions initiated independently by each master device can be met; on the other hand, because the shared cache area is shared by multiple master devices, the overall on-chip resource consumption can be significantly reduced.

[0067] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0068] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of this application are illustrated in the drawings by way of example and not limitation, wherein:

[0069] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

[0070] Figure 1 This paper illustrates the composition structure of the cache structure of the AXI interconnect module according to an embodiment of this application. Figure 1 ;

[0071] Figure 2 This paper illustrates the composition structure of the cache structure of the AXI interconnect module according to an embodiment of this application. Figure 2 ;

[0072] Figure 3 A schematic diagram illustrating the composition structure of an index entry according to an embodiment of this application is shown;

[0073] Figure 4 This illustration shows a schematic diagram of a state value switching process according to an embodiment of this application;

[0074] Figure 5 This illustration shows a schematic diagram of an index entry rearrangement according to an embodiment of this application;

[0075] Figure 6 A schematic diagram illustrating the composition structure of an instruction entry according to an embodiment of this application is shown;

[0076] Figure 7 This illustration shows a schematic diagram of an instruction information storage process in a cache according to an embodiment of this application;

[0077] Figure 8 This illustration shows a schematic diagram of an instruction information retrieval cache process according to an embodiment of this application;

[0078] Figure 9 This illustration shows a data information storage cache process according to an embodiment of this application;

[0079] Figure 10 This illustration shows a data information retrieval cache process according to an embodiment of this application;

[0080] Figure 11 A schematic diagram illustrating the implementation flow of the caching method of the AXI interconnect module according to an embodiment of this application is shown;

[0081] Figure 12 A schematic diagram of the composition structure of an electronic device according to an embodiment of this application is shown. Detailed Implementation

[0082] To make the objectives, features, and advantages of this application more apparent and understandable, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0083] In a multi-master, multi-slave AXI4 interconnect topology, each master and slave device operates independently. The AXI interconnect module determines the slave device based on pre-defined rules, such as sideband information or address ranges, routes access transactions from the master device to the corresponding slave device, and returns the response transaction from the slave device to the source master device that initiated the access.

[0084] When a master device continuously sends access transactions to multiple slave devices, the sending process will be blocked if the slave device corresponding to the current access transaction is not ready. Furthermore, if the slave device corresponding to the next access transaction is idle, this blocking will prevent the next executable transaction from being sent in a timely manner, thus affecting the overall system access efficiency. In this situation, it is necessary to utilize the cache and cache control module in the AXI interconnect module to design a caching mechanism to store the current access transaction, thereby allowing the master device to send the next access transaction and improving access efficiency.

[0085] On the other hand, when a slave device responds to access transactions from multiple master devices, the response process will be blocked if the master device corresponding to the current response transaction is not ready. Furthermore, if the master device corresponding to the next response transaction is idle, this blocking will prevent the next executable response from being sent in a timely manner, thus affecting the overall system access efficiency. In this case, it is necessary to design a caching mechanism through the AXI interconnect module's buffer and response control module to store the current response transaction, thereby allowing the slave device to send the next response transaction and improving access efficiency.

[0086] The caching mechanisms in related technologies have the following problems. First, on-chip resources are limited. While configuring a buffer for each master or slave device can meet caching needs, the transaction sending frequency of each master or slave device differs, and some devices may not even need a buffer to meet system requirements, leading to resource waste. Using a shared buffer can achieve resource sharing between devices and between read / write access buffers, optimizing resource allocation to some extent. However, due to the hardware design of a single write interface, when multiple master devices simultaneously initiate cached access transactions, these concurrent transactions can only be written sequentially to the shared buffer, severely impacting transaction processing efficiency. Furthermore, when multiple master devices send access transactions to the same slave device with the same ID, or when the same master device sends access transactions to multiple slave devices with the same ID, according to the AXI protocol rules, for the same master device, access transactions with the same ID must return responses sequentially in the order they were sent. However, existing caching mechanisms struggle to properly handle the return order of slave device responses to their corresponding master devices, easily leading to out-of-order responses. In addition, there is a lack of priority handling capabilities.

[0087] To address the aforementioned technical problems, a first aspect of this application proposes a caching architecture for an AXI interconnect module, such as... Figure 1As shown, the caching architecture includes an index cache, a shared cache, and a shared cache access controller. The index cache includes an index entry list, and the shared cache includes an instruction cache and a data cache. Each index cache corresponds to one master device, and the shared cache corresponds to all master devices. The index entry list records the index information of access transactions for the corresponding master device. Each index entry in the index entry list corresponds to one access transaction. The shared cache access controller stores the instruction information corresponding to the access transaction in the instruction cache and the data information corresponding to the access transaction in the data cache based on the index information.

[0088] In the cache structure of this embodiment, each master device corresponds to an independent index cache area. For example... Figure 1 As shown, master device 0 ( ), Main equipment N-1 ( Each of these components has its own dedicated index cache. The master device, such as the CPU (Central Processing Unit) or GPU (Graphics Processing Unit), initiates read and write data requests to slave devices. The master device obtains these access transactions through its AXI output channel. After obtaining the access transaction, its corresponding index information is stored in the master device's corresponding index cache. The index cache includes a list of index entries, recording the index information for all access transactions from the corresponding master device. This index information points to the storage information of the corresponding access transaction in the shared cache. Because the information contained is relatively concise, the index cache consumes relatively few on-chip resources.

[0089] The index cache design provides each master device with a dedicated space for managing access transaction indexes, ensuring that each master device can independently manage its own transactions and avoid mutual interference. At the same time, it reduces overall on-chip resource consumption through streamlined index information, balancing management independence with rational resource allocation.

[0090] The shared cache access controller, located between the index cache and the shared cache, stores the instruction information corresponding to the access transaction in the instruction cache of the shared cache based on the index information in the index entry list. It also stores the data information of the access transaction in the data cache of the shared cache. The instruction and data information corresponding to the access transaction include both information related to the access request sent by the master device and information returned by the slave device after responding to the access transaction request.

[0091] The shared cache is a storage area used by all master devices, comprising an instruction cache and a data cache. The instruction cache centrally stores instruction information for each master device's access transactions, while the data cache centrally stores data information for each access transaction. For example, when an access transaction is a read data transaction, the instruction cache stores the relevant instructions for the master device to initiate the read operation, while the data cache temporarily stores the data returned by the slave device in response to the read request. When an access transaction is a write data transaction, the instruction cache stores the relevant instructions for the master device to initiate the write operation, while the data cache temporarily stores the data that the master device needs to write to the slave device.

[0092] This embodiment employs a two-level caching structure. The first level is a dedicated index cache for each master device, and the second level is a shared cache shared by all master devices. This caching structure reduces unnecessary blocking during the operation of the AXI4 interconnect module through the division of labor and cooperation between the two levels of cache, effectively improving overall operating efficiency. Simultaneously, by configuring a separate index cache for each master device, the cache capacity requirements during concentrated bursts of access transactions initiated independently by each master device can be met; furthermore, because the shared cache is used by multiple master devices, the overall on-chip resource consumption can be significantly reduced.

[0093] In another possible embodiment of this application, such as Figure 2 As shown, the index cache area also includes an instruction temporary storage area and a data temporary storage area. The instruction temporary storage area is used to temporarily store the instruction information of the current access transaction, and the data temporary storage area is used to temporarily store the data information of the current access transaction.

[0094] The instruction buffer is used to temporarily store instruction information for the current access transaction, and only one instruction can be stored at a time. This instruction will then be stored in the instruction cache by the shared cache access controller. The data buffer is used to temporarily store data information for the current access transaction, specifically the data loaded by the current access transaction within one clock cycle. This data will then be stored in the data cache by the shared cache access controller.

[0095] This embodiment effectively reduces the waiting time of master devices when multiple master devices send access transactions in parallel by setting up instruction and data buffers in the index cache. Considering that there are multiple clock intervals between each access transaction of a single master device, when multiple master devices send access transactions simultaneously, the instruction and data information of the access transactions can be stored in their respective instruction and data buffers, without waiting for other master devices to complete the storage of their access transactions in the shared cache before storing their own transaction information. Subsequently, the shared cache access controller can utilize the clock intervals between access transactions to serially store the instruction and data information from the buffers into the shared cache. During this time interval, each master device does not need to wait and can perform other tasks normally, thereby improving the working efficiency of the master devices and the overall operating efficiency of the AXI interconnect module.

[0096] In another possible embodiment of this application, such as Figure 3 As shown, the index information includes an instruction cache index, urgency, slave device number, access type, and status value. Specifically, the instruction cache index is the storage location index of the instruction information corresponding to the access transaction in the instruction cache area; the urgency is the processing priority of the access transaction; the slave device number is the number of the slave device corresponding to the access transaction; the access type is the operation type of the access transaction; and the status value is the execution stage of the access transaction.

[0097] In the index cache area of ​​this cache structure, the index entry list records at least five types of index information: instruction cache index, urgency rank, slave ID, access type, and state.

[0098] Among them, the instruction cache index is the storage location index of the corresponding access transaction in the instruction cache area of ​​the shared cache area. The specific location of the access transaction in the instruction cache area can be quickly located through this index.

[0099] Urgency is the processing priority of access transactions. Its value is non-negative. The smaller the value, the higher the processing priority of the access transaction. It is used to support the priority scheduling strategy of transactions.

[0100] The slave device number is the slave device number corresponding to the access transaction, that is, the transmission object of the access transaction;

[0101] The access type refers to the operation type of the access transaction, including read data transactions and write data transactions;

[0102] The status value represents the execution stage of the access transaction, including five stages: waiting to send, sending, response in progress, waiting to receive, and invalid, reflecting the current execution status of the transaction.

[0103] Meanwhile, the length and composition of each index entry in the index entry list are kept consistent, which ensures that the management of access transaction index information for each master device is standardized and consistent.

[0104] This embodiment achieves effective management of access transactions by storing corresponding index information for each access transaction, including its index position in the shared cache, its urgency for priority scheduling, and a status value marking the current execution stage. Furthermore, since the index information mainly records the relevant location and status of the access transaction in the shared cache, for different types of access transactions, only the access type differs; other index information remains consistent. Therefore, index resources can be shared, eliminating the need to configure separate cache resources for different types of access transactions, thereby further reducing overall resource requirements.

[0105] In another embodiment of this application, the index cache is used to update the status value in the index information in real time according to the current execution stage of the access transaction; the execution stage includes waiting to send, sending, response in progress, waiting to receive, and invalid.

[0106] Specifically, such as Figure 4As shown, after the process starts, it will continuously monitor if no new access transactions occur. When a new access transaction occurs, if the access transaction's instruction information has been stored in the instruction cache but the process of sending it to the slave device has not yet started, the status value is marked as "Waiting to send". If the access transaction's instruction information has been loaded into the corresponding instruction channel and data information is continuously being loaded into the data channel, the status value is marked as "Sending". In addition, if the arbitration logic allows the access transaction to directly send address information when it is stored in the instruction cache, the "Waiting to send" status will be skipped and it will be directly marked as "Sending". If the data information is sent, it will be marked as "Response in progress". Furthermore, if the arbitration logic allows the access transaction to send data information, and the data information can be sent simultaneously with the instruction information, the "Sending" status will also be skipped and it will be directly marked as "Response in progress". The "Response in progress" status means waiting for the slave device to return response data, or continuously receiving subsequent response data after the slave device starts returning response data. After receiving response data, if the data buffer corresponding to the access transaction contains data that has not yet been sent to the master device, it is marked as "Waiting to Receive". If the master device has received all response data, it is marked as "Invalid". Furthermore, if the master device allows receiving response data while in the "Response in Progress" state, and the master device receives the response data at the same time as the slave device sends it, then it does not enter the "Waiting to Receive" state but is directly marked as "Invalid". The "Invalid" state means that this buffer entry has no access transaction to process and can be stored as the buffer information for a new access transaction.

[0107] It should be noted that, Figure 4 A and B in the diagram serve only to connect different parts of the process, making it easier to clearly present the logical flow of the entire transaction processing process.

[0108] The solution in this embodiment updates the status value in real time according to the stage of the access transaction execution through the index cache, which can accurately and dynamically reflect the progress of the transaction execution. Switching between different states can avoid unnecessary state waiting and improve the efficiency of the transaction processing flow. At the same time, it can efficiently reuse cache resources, allowing the index cache to take over new access transactions in a timely manner, ensuring the smoothness of access transaction processing and the utilization rate of cache resources.

[0109] In another embodiment of this application, the index cache is further configured to, in response to the presence of an invalid index entry in the index entry list, rearrange the entry positions of index entries other than the invalid index entries based on the status value and index value of each index entry.

[0110] The index cache in this application is configured with an entry status management thread to manage related transactions. Specifically, the entry status management thread's process is as follows: When a new access transaction is received and allocated to the corresponding master device's index cache, it starts storing the cache entry with the lowest index value. Subsequent access transactions are stored in the cache entry with the lowest index value that is in an "invalid" state. If no cache entry in an "invalid" state exists, it enters a waiting state until an "invalid" cache entry appears in the index cache. During operation, the status value of each cache entry will be updated according to... Figure 4 The process shown has been updated.

[0111] In this embodiment, when a cached entry becomes "invalid" again after completing an access transaction, the cached entries are rearranged. During the rearrangement, entries with index values ​​larger than those that have become "invalid" are moved sequentially in the direction of decreasing index values ​​until all positions of entries in the "invalid" state are filled.

[0112] refer to Figure 5 As shown: i) There are 9 cache entries in the index cache. White cache entries indicate that they are in an "invalid" state, and gray cache entries indicate that they are in other states; ii) Cache entries 3 and 5 (d and f) are switched to the "invalid" state; After rearranging the cache entries other than d and f according to the above rearrangement rules, the result is shown in iii).

[0113] This embodiment's solution, through dynamic management of index cache entries, ensures that the storage order of access transactions with the same ID in the index cache is completely consistent with the order in which they enter the AXI interconnect module. Furthermore, when sending access transactions to slave devices, if access transactions with the same ID have the same urgency, the entry with the smallest position value will be sent first. When receiving response transactions from slave devices, the system can also accurately locate the cache entry with the same ID and the smallest position value, thereby ensuring the correct execution of access transactions with the same ID and further guaranteeing the timing accuracy and logical reliability of transaction processing in the AXI interconnect module.

[0114] In another embodiment of this application, the index cache is further used to filter index entries whose slave device numbers point to the same slave device, and determine the index entry with the lowest urgency as the sending front entry; if there are multiple index entries with the same urgency, the index entry with the smallest index value is determined as the sending front entry; the sending front entry is the index entry that initiates an access request to the corresponding slave device first.

[0115] The index cache in this application has an urgency management thread to manage the urgency of index entries. The specific process is as follows: When a new access transaction arrives, the system assigns an urgency value to the transaction according to the priority control strategy, which is then used as the urgency value of the corresponding index entry. When an access transaction is sent to the target slave device (i.e., the slave device pointed to by the slave device number), the urgency value of the index entry corresponding to the sent transaction is set to an invalid value. Simultaneously, for other index entries, if their slave device number is the same as the slave device number of the sent transaction, and their own urgency value is not zero, the urgency value of these index entries is automatically decremented by 1.

[0116] To reduce delays caused by urgency comparisons, this embodiment uses an urgency management thread to pre-determine the leading-edge transmission entries for each slave device. Specifically, for each slave device, all index entries with slave device numbers pointing to that slave device are first filtered out, and then a judgment is made based on the urgency values ​​of these entries. The index entry with the smallest urgency value is determined as the leading-edge transmission entry for the corresponding master device for that slave device; if multiple index entries have the same minimum urgency value, the entry with the smallest index value is selected as the leading-edge transmission entry.

[0117] In this embodiment, when a slave device is ready to receive an access transaction, there is no need to perform an urgent value comparison within the master device to select a sending front entry. Instead, it can directly select one from the sending front entries of each master device for that slave device and send it, which effectively improves the overall operating efficiency.

[0118] In another embodiment of this application, the index cache area also includes an instruction cache index configuration thread. For a new access transaction, the initial value of the instruction cache index (Cmd cache index) in its corresponding index cache entry is invalid. After the system allocates a storage location for the access transaction in the instruction cache area, it transmits the allocated location value to the instruction cache index configuration thread. This thread then updates the instruction cache index value in the index cache entry according to the received location value, ensuring that it accurately points to the transaction's storage location in the instruction cache area.

[0119] In another possible embodiment of this application, such as Figure 2 As shown, the instruction cache includes an instruction memory and an instruction status table; the instruction memory includes a preset number of instruction entries, each instruction entry corresponding to an access transaction; the instruction status in the instruction status table corresponds one-to-one with the instruction entries in the instruction memory, and is used to mark whether the corresponding instruction entry is occupied.

[0120] In this embodiment, the instruction cache consists of two parts: an instruction memory and an instruction status table. Each instruction status in the instruction status table corresponds one-to-one with an instruction entry in the instruction memory. The instruction memory contains a preset number of instruction entries (e.g., ...). Figure 2 The 0 to the marked -1) Each instruction entry is dedicated to storing the instruction information for one access transaction, ensuring that each access transaction instruction has its own independent storage unit. The specific number of preset entries can be determined based on factors such as transaction processing requirements and on-chip resource scale in the actual application scenario. The instruction status table is used to mark the occupancy status of the corresponding instruction entry in the instruction memory, that is, to mark whether the instruction entry currently stores the instruction information for an access transaction. Through this status marking, the usage of each instruction entry in the instruction memory can be monitored in real time, providing an intuitive and reliable basis for allocating storage locations for subsequent new access transaction instruction information, thereby effectively avoiding storage resource allocation conflicts and ensuring the orderly operation of the instruction cache.

[0121] In another possible embodiment of this application, such as Figure 6 As shown, each instruction entry stores instruction information for the access transaction, including AXI instruction information, a data cache address header, a data cache address tail, and a data cache operation address. The AXI instruction information comprises the address channel information and response transaction information of the access transaction; the data cache address header is the index header of the data cache area to be allocated by the access transaction; the data cache address tail is the index tail of the data cache area to be allocated by the access transaction; and the data cache operation address is the index identifier of the next data operation position.

[0122] In this embodiment, the access transaction instruction information stored in each instruction entry specifically includes four parts: AXI instruction information (AXIcmd info), data cache address header (Data addr head), data cache address tail (Data addr tail), and data cache operation address (Data op addr).

[0123] The AXI instruction information includes the address channel information and response transaction information for the access transaction. Address channel information includes address, burst length, burst type, data size, Quality of Service (QoS), and region. Response transaction information includes write response information (such as write data channel sideband signals and write response signals (brsp signals)) and read response information (excluding read data, but including read response signals "rrsp signals" and read data channel sideband signals).

[0124] The data cache address header is the index header of the data cache area that needs to be allocated for accessing the transaction, and the data cache address tail is the corresponding data cache area index tail; the data cache operation address is used to identify the index of the next data operation position, which can be used as the index position for storing the next data item into the data cache, or as the index position for retrieving the next data item from the write data cache.

[0125] During the execution of an access transaction, the data cache address header and data cache operation address are updated according to specific rules: Initially, the values ​​of the data cache operation address and the data cache address header are consistent. Regardless of whether the access transaction is a write or read transaction, data in the data channel is typically stored over multiple clock cycles. The starting position for each storage is the current data cache operation address, and the data cache operation address is simultaneously offset by the length of the written data as the next storage location. Regardless of the transaction type, stored data can be retrieved simultaneously during or after data storage, but retrieval is only allowed if the value of the data cache address header is greater than the value of the data cache operation address. After retrieval, the data cache address header is offset by the length of the retrieved data as the next retrieval location. When the value of the data cache address header is greater than the value of the data cache address tail, it indicates that the data transmission of the access transaction has been completed. At this time, the values ​​of both the data cache address header and the data cache address tail are set to invalid values ​​to release the occupied data cache resources.

[0126] This embodiment achieves complete and standardized storage of access transaction instruction information by setting AXI instruction information, a data cache address header, a data cache address tail, and a data cache operation address in each instruction entry. The AXI instruction information can store address channel information and response information (excluding read data) according to the execution stage of the access transaction, reducing resource consumption through this dynamic reuse. Simultaneously, the content of the stored items in the instruction cache entries for read and write access transactions remains consistent, enabling universal storage and eliminating the need to design separate storage structures for different types of access transactions.

[0127] In another possible embodiment of this application, such as Figure 2 As shown, the data cache includes a data storage device and a data status table; the data storage device includes a preset number of data entries, and one or more consecutive data entries correspond to an access transaction; the data status in the data status table corresponds one-to-one with the data entries in the data storage device, and is used to mark whether the corresponding data entry is occupied.

[0128] In this embodiment, the data buffer consists of a data storage unit and a data status table. Each data status in the data status table corresponds to a data entry in the data storage unit. The data storage unit contains a preset number of data entries, each used to store data information for an access transaction, and each data entry contains a fixed number of bytes. One access transaction corresponds to one or more consecutive data entries (i.e., the data buffer for that access transaction). The start position of this data buffer corresponds to the data cache address header in the access transaction instruction entry, and the end position corresponds to the data cache address tail in the instruction entry. The data status table, corresponding one-to-one with the data storage unit, is used to mark the occupancy status of its corresponding data entry, that is, to determine whether the data entry currently stores data information for an access transaction. Through this status marking, the usage status of each data entry in the data storage unit can be clearly understood, providing a basis for the storage allocation of subsequent access transaction data information.

[0129] Furthermore, the functional logic of the data storage and data status table in the data buffer is basically the same as that of the instruction storage and instruction status table in the instruction buffer described above, so the basic functional details will not be elaborated here.

[0130] In another embodiment of this application, the shared cache access controller is further configured to: in response to the instruction temporary storage area of ​​any index cache being in a non-empty state, filter instruction information to be stored from the non-empty instruction temporary storage area based on the urgency of the index entry list; and in response to the existence of an invalid instruction entry in the instruction cache area and the existence of consecutive unoccupied data entries that meet the conditions in the data cache area, store the instruction information to be stored into the instruction cache area.

[0131] In this embodiment, the shared cache access controller is equipped with an instruction cache storage thread, which stores the instruction information corresponding to access transactions initiated by multiple master devices into the instruction cache area of ​​the shared cache. Its specific workflow can be found in the appendix. Figure 7 The detailed steps are as follows:

[0132] First, the instruction cache storage thread monitors the status of the index cache corresponding to each master device in real time. When it detects that the instruction temporary storage area of ​​any index cache is not empty, it is determined that a master device has initiated a new access transaction, and the instruction filtering process is triggered. The filtering process follows these rules: based on the urgency recorded in the index entry list, the instruction temporary storage area with the lowest urgency among all non-empty instruction temporary storage areas is selected. If multiple instruction temporary storage areas correspond to transactions with the same urgency, an ascending round-robin mechanism is further used for selection. For example, if the instruction temporary storage area of ​​master device 1's index cache was selected for storage operation last time, the instruction temporary storage area of ​​master device 2's index cache will be selected sequentially this time, and subsequently, the instruction information to be stored will be determined by ascending order of master device number.

[0133] After determining the instruction information to be stored, the system checks whether there are any invalid instruction entries (i.e., unoccupied entries) in the instruction cache and whether there are any consecutive unoccupied data entries in the data cache that meet certain conditions. When both conditions are met, the previously determined instruction information to be stored is moved from the instruction temporary storage area of ​​the corresponding index cache and written to that location, completing the cached storage of the instruction. Specifically, meeting the conditions means that the number of consecutive unoccupied data entries in the data cache is not less than the expected data storage requirement of the access transaction associated with the instruction information to be stored, and the address range corresponding to this consecutive unoccupied entry does not conflict with the target data address recorded in the instruction entry to be stored in the instruction cache. Furthermore, it conforms to the data storage address continuity verification rules preset by the shared cache access controller, ensuring that subsequent data read and write operations can be executed sequentially and without conflict.

[0134] In addition, the storage location needs to be fed back to the index cache of the corresponding master device, which will then store this location value into the instruction cache index of the corresponding entry. Simultaneously, the smallest data cache start and end entry positions are selected, and these two location values ​​are stored in the data cache address header, data cache operation address, and data cache address tail of the corresponding instruction cache entry.

[0135] In this embodiment, when storing instruction information, priority is given to storing the contents of the instruction temporary storage area with low urgency, ensuring that high-priority transactions are processed first and meeting real-time requirements. During storage, if there are invalid entries in the pending instruction cache and sufficient contiguous space in the data cache, conflicts are avoided. The smallest cache location is selected according to rules to improve utilization and overall enhance the processing efficiency and stability of the AXI interconnect module.

[0136] In another embodiment of this application, the shared cache access controller is further configured to: in response to the existence of instruction information to be retrieved, retrieve the instruction information to be retrieved from the instruction cache according to the index entry, and send the instruction information to be retrieved to the address channel of the target slave device through the sending module; obtain the transaction response instruction information sent by the target slave device based on the instruction information to be retrieved, and replace the AXI instruction information in the instruction entry with the transaction response instruction information.

[0137] The shared cache access controller is also configured with an instruction cache entry retrieval thread. Its workflow is shown in Figure 8: The thread first enters a waiting state, and the arbitration logic, combined with the preset priority strategy (such as transaction urgency, master device priority, etc.) and the current busy / idle status of the slave device (whether it is in a ready state to receive instructions), filters and determines the instruction entries that can be sent from the index cache area of ​​each master device.

[0138] When a sendable entry is determined to exist (i.e., there is instruction information to be retrieved), the thread locates and filters the corresponding instruction entry from the instruction cache area based on the instruction cache index recorded in the index entry. Then, it extracts the address channel information from this entry and sends it to the sending module responsible for instruction forwarding in the system. Afterward, the sending module pushes this instruction information to the address channel of the target slave device. Here, the target slave device refers to the final processing object of this access transaction (such as a specific storage device or peripheral), and its address channel is mainly used to receive and parse externally sent access instructions.

[0139] After the instruction information is sent, the thread continuously listens for the response from the target slave device. Once it obtains the transaction response instruction information generated by the slave device in response to the instruction, it replaces the AXI instruction information (AXI cmd info) carried in the original instruction information with the transaction response instruction information, thus completing the update of the instruction response.

[0140] Finally, the thread waits for the corresponding master device to finish reading the access transaction response information stored in the instruction entry. Once the master device has completed its read operation, it immediately marks the current instruction entry as invalid to release the cache resources occupied by the entry, making them available for subsequent storage of new instruction information and achieving the recycling of cache space.

[0141] In another embodiment of this application, the shared cache access controller is further configured to: in response to the data temporary storage area of ​​any index cache being in a non-empty state, or data existing in any slave device read data channel, determine the data information to be stored based on the instruction information corresponding to the data information; and store the data information to be stored into the data cache.

[0142] In this embodiment, the shared cache access controller is also configured with a data cache storage thread, which is used to store data information in the access transaction into the data cache area. For detailed workflow, please refer to [link / reference]. Figure 9 As shown, when it is detected that the data storage area of ​​any index cache is not empty (i.e., the area has cached data related to the access transaction initiated by the master device), or when there is data to be transmitted in the read data channel of any slave device (i.e., the slave device has completed data reading and is ready to return data), the data storage process is triggered.

[0143] The system first locates the instruction entry corresponding to the data, and then, based on the information contained in the instruction entry, determines the specific data content that needs to be stored in the data buffer, i.e., the data information to be stored.

[0144] Then, the shared cache access controller extracts the data cache operation address from the corresponding instruction entry and uses this as the starting position to write the data information to be stored into the data cache area. After the data is stored, the data cache operation address (Data op addr) value in the instruction information is automatically added to the length of the data stored this time and updated to a new address value, reserving a starting position for possible subsequent continuous data storage.

[0145] In another embodiment of this application, the shared cache access controller is further configured to: in response to the existence of data information to be retrieved, determine the target instruction entry corresponding to the data information to be retrieved based on the index entry; and retrieve the data information to be retrieved from the data buffer based on the target instruction entry.

[0146] The shared cache access controller also includes a data cache entry retrieval thread. This thread starts working when the system has data to retrieve. The data to be retrieved includes access transaction entries in the index cache that can be sent, as well as response data received by the system that needs to be processed. For example, in a write access transaction, write data needs to be sent to the write data channel of the corresponding slave device. In a read access transaction, read data needs to be pushed to the read data channel of the corresponding master device.

[0147] The specific workflow of the data cache entry retrieval thread is shown in Figure 10: First, the corresponding instruction entry in the instruction cache, i.e., the target instruction entry, is determined based on the index entry. Then, based on the data cache address header recorded in the target instruction entry and the size value contained in the AXI instruction information, the corresponding data is accurately retrieved from the data cache.

[0148] After the data is retrieved, the data cache address header value of the target instruction entry is added to the length of the retrieved data, and the new address header value is updated. If the calculated new address header value is greater than the data cache address tail value, it indicates that all the data corresponding to the instruction entry has been retrieved. At this time, both the data cache address header and the data cache address tail are updated to invalid values ​​to release the relevant cache resources.

[0149] This application's solution achieves efficient coordination of data access by uniformly storing write and read data channels, and precisely locating the write and read positions using the corresponding instruction cache entries' Data op addr and Data addr head. Simultaneously, write and read operations can be performed in parallel. Combined with the real-time dynamic update mechanism of the Data op addr and Data addr head, cache space for completed operations can be released instantly during data processing, significantly reducing resource idle time and substantially improving data cache turnover efficiency and overall utilization. This provides more efficient storage support for concurrent access transactions from multiple master devices, reduces system latency, and enhances processing throughput.

[0150] A second aspect of this application provides a caching method for an AXI interconnect module, which is applied to the caching architecture of the aforementioned AXI interconnect module, such as... Figure 11 As shown, the method includes:

[0151] The index entry list records the index information of the access transactions of the corresponding master device; each index entry in the index entry list corresponds to one access transaction.

[0152] The shared cache access controller stores the instruction information corresponding to the access transaction in the instruction cache area based on the index information, and stores the data information corresponding to the access transaction in the data cache area.

[0153] In another embodiment of this application, the index cache further includes an instruction buffer and a data buffer; correspondingly, the method further includes: temporarily storing instruction information of the current access transaction through the instruction buffer; and temporarily storing data information of the current access transaction through the data buffer.

[0154] In another embodiment of this application, the index information includes an instruction cache index, urgency, slave device number, access type, and status value. The instruction cache index is an index recording the storage location of the instruction information corresponding to the access transaction in the instruction cache area; the urgency is the processing priority of the access transaction; the slave device number is the number of the slave device corresponding to the access transaction; the access type is the operation type of the access transaction; and the status value is the execution stage of the access transaction.

[0155] In another embodiment of this application, the method further includes: updating the status value in the index information in real time according to the current execution stage of the access transaction through the index cache; the execution stage includes waiting to send, sending, response in progress, waiting to receive, and invalid.

[0156] In another embodiment of this application, the method further includes: responding to the presence of an invalid index entry in the index entry list through the index cache, and rearranging the entry positions of the index entries other than the invalid index entries based on the status value and index value of each index entry.

[0157] According to embodiments of this application, this application also provides an electronic device and a readable storage medium.

[0158] Figure 12 A schematic block diagram of an example electronic device 800 that can be used to implement embodiments of this application is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the application described and / or claimed herein.

[0159] like Figure 12 As shown, the electronic device 800 includes a computing unit 801, which can perform various appropriate actions and processes based on a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 into a random access memory (RAM) 803. The RAM 803 may also store various programs and data required for the operation of the electronic device 800. The computing unit 801, ROM 802, and RAM 803 are interconnected via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0160] Multiple components in electronic device 800 are connected to I / O interface 805, including: input unit 806, such as keyboard, mouse, etc.; output unit 807, such as various types of displays, speakers, etc.; storage unit 808, such as disk, optical disk, etc.; and communication unit 809, such as network card, modem, wireless transceiver, etc. Communication unit 809 allows electronic device 800 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0161] The computing unit 801 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the various methods and processes described above, such as the caching method of the AXI interconnect module. For example, in some embodiments, the caching method of the AXI interconnect module can be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 808. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 800 via ROM 802 and / or communication unit 809. When the computer program is loaded into RAM 803 and executed by the computing unit 801, one or more steps of the caching method of the AXI interconnect module described above can be performed. Alternatively, in other embodiments, computing unit 801 may be configured to perform the caching method of the AXI interconnect module by any other suitable means (e.g., by means of firmware).

[0162] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transferring data and instructions to the storage system, the at least one input device, and the at least one output device.

[0163] The program code used to implement the methods of this application may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing device, such that when executed by the processor or controller, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0164] In the context of this application, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0165] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0166] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0167] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0168] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.

[0169] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0170] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A caching architecture for an AXI interconnect module, characterized in that, The caching architecture includes an index cache, a shared cache, and a shared cache access controller. The index cache includes a list of index entries, and the shared cache includes an instruction cache and a data cache. Each index cache corresponds to one master device, and the shared cache corresponds to all master devices. The index entry list is used to record the index information of the access transactions of the corresponding master device; each index entry in the index entry list corresponds to one access transaction. The shared cache access controller is used to store the instruction information corresponding to the access transaction in the instruction cache area and the data information corresponding to the access transaction in the data cache area based on the index information.

2. The caching architecture according to claim 1, characterized in that, The index cache area also includes an instruction temporary storage area and a data temporary storage area, wherein, The instruction buffer is used to temporarily store instruction information for the current access transaction; The data temporary storage area is used to temporarily store the data information of the current access transaction.

3. The caching architecture according to claim 2, characterized in that, The index information includes instruction cache index, urgency, slave device number, access type, and status value, wherein, The instruction cache index is the storage location index of the instruction information corresponding to the access transaction in the instruction cache area; The urgency level is the processing priority of the access transaction; The slave device number is the slave device number corresponding to the access transaction; The access type is the operation type of the access transaction; The status value indicates the current execution phase of the access transaction.

4. The caching architecture according to claim 3, characterized in that, The index cache is used to update the status values ​​in the index information in real time according to the current execution stage of the access transaction; the execution stage includes waiting to send, sending, response in progress, waiting to receive, and invalid.

5. The caching architecture according to claim 4, characterized in that, The index cache is also used to respond to the presence of an invalid index entry in the index entry list by rearranging the entry positions of the index entries other than the invalid index entries based on the status value and index value of each index entry.

6. The caching architecture according to claim 3, characterized in that, The index cache is also used to filter index entries that point to the same slave device from the slave device number, and to determine the index entry with the lowest urgency as the sending front entry; If there are multiple index entries with the same urgency, the index entry with the smallest index value is determined as the sending front entry; the sending front entry is the index entry that initiates the access request to the corresponding slave device first.

7. The caching architecture according to claim 1, characterized in that, The instruction cache includes an instruction memory and an instruction status table; The instruction memory includes a preset number of instruction entries, and each instruction entry corresponds to an access transaction; The instruction status in the instruction status table corresponds one-to-one with the instruction entries in the instruction memory, and is used to mark whether the corresponding instruction entry is occupied.

8. The caching architecture according to claim 7, characterized in that, Each instruction entry stores instruction information for the access transaction, including AXI instruction information, a data cache address header, a data cache address tail, and a data cache operation address. The AXI instruction information includes the address channel information and response transaction information of the access transaction; The data cache address header is the index header of the data cache area that the access transaction needs to allocate; The data cache address tail is the index tail of the data cache area that the access transaction needs to allocate; The data cache operation address is the index identifier of the next data operation position.

9. The caching architecture according to claim 1, characterized in that, The data cache includes a data storage device and a data status table; The data storage includes a preset number of data entries, and one or more consecutive data entries correspond to one access transaction; The data status in the data status table corresponds one-to-one with the data entries in the data storage, and is used to mark whether the corresponding data entry is occupied.

10. The caching architecture according to claim 3, characterized in that, The shared cache access controller is also used for: In response to the instruction buffer of any index cache being in a non-empty state, instruction information to be stored is selected from the non-empty instruction buffer based on the urgency of the index entry list. In response to the presence of an invalid instruction entry in the instruction cache and a consecutive unoccupied data entry in the data cache that meets the conditions, the instruction information to be stored is stored in the instruction cache.

11. The caching architecture according to claim 3, characterized in that, The shared cache access controller is also used for: In response to the fact that the data buffer of any index cache is not empty, or that there is data in any slave device read data channel, the data information to be stored is determined based on the instruction entry corresponding to the data information. The data to be stored is stored in the data cache area.

12. The caching architecture according to claim 3, characterized in that, The shared cache access controller is also used for: In response to the existence of instruction information to be retrieved, the instruction information to be retrieved is retrieved from the instruction buffer according to the index entry, so as to send the instruction information to be retrieved to the address channel of the target slave device through the sending module; Obtain the transaction response instruction information sent by the target slave device based on the instruction information to be retrieved, and replace the AXI instruction information in the instruction entry with the transaction response instruction information.

13. The caching architecture according to claim 3, characterized in that, The shared cache access controller is also used for: In response to the existence of data information to be retrieved, the target instruction entry corresponding to the data information to be retrieved is determined according to the index entry; According to the target instruction entry, retrieve the data information to be retrieved from the data buffer.

14. A caching method for an AXI interconnect module, characterized in that, The method is applied to the caching architecture of the AXI interconnect module. The caching architecture includes an index cache, a shared cache, and a shared cache access controller. The index cache includes a list of index entries, and the shared cache includes an instruction cache and a data cache. Each index cache corresponds to one master device, and the shared cache corresponds to all master devices. The method includes: The index entry list records the index information of the access transactions of the corresponding master device; each index entry in the index entry list corresponds to one access transaction. The shared cache access controller stores the instruction information corresponding to the access transaction in the instruction cache area based on the index information, and stores the data information corresponding to the access transaction in the data cache area.

15. The method according to claim 14, characterized in that, The index cache area also includes an instruction temporary storage area and a data temporary storage area; Accordingly, the method further includes: The instruction information for the current access transaction is temporarily stored in the instruction buffer area; The data information of the current access transaction is temporarily stored in the data temporary storage area.

16. The method according to claim 15, characterized in that, The index information includes instruction cache index, urgency, slave device number, access type, and status value, wherein, The instruction cache index is an index that records the storage location of the instruction information corresponding to the access transaction in the instruction cache area; The urgency level is the processing priority of the access transaction; The slave device number is the slave device number corresponding to the access transaction; The access type is the operation type of the access transaction; The status value indicates the execution phase of the access transaction.

17. The method according to claim 16, characterized in that, The method further includes: The index cache updates the status values ​​in the index information in real time according to the current execution stage of the access transaction; the execution stages include waiting to send, sending, response in progress, waiting to receive, and invalid.

18. The method according to claim 17, characterized in that, The method further includes: In response to the presence of an invalid index entry in the index entry list via the index cache, the positions of the index entries other than the invalid index entry are rearranged based on the status value and index value of each index entry.

19. An electronic device, characterized in that, include: At least one processor; as well as, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 14-18.

20. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 14-18.

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