Low power multi-interface data conversion system and method

Abstract

The application belongs to the technical field of data conversion systems, and particularly relates to a low-power-consumption multi-interface data conversion system and method. The system comprises a control module, a power management module, a CAN interface module, a Flash storage unit, an eMMC storage unit, a DDR cache unit, a serial port module, a PC, a connector and a debugging backplane, and the control module, the power management module, the CAN interface module, the Flash storage unit, the eMMC storage unit, the DDR cache unit and the serial port module are arranged on the same circuit board. The application can realize multi-channel CAN bus communication, support multi-channel network data conversion into one-channel network data function, and support multi-channel CAN data conversion into one-channel CAN data function. Through AXI4 high-speed bus connection, low-delay data exchange is realized, and the bottleneck of communication between chips in the traditional discrete scheme is avoided.

Description

Technical Field

[0001] This invention belongs to the field of data conversion system technology, and in particular to a low-power multi-interface data conversion system and method. Background Technology

[0002] With the increasing sophistication of equipment information technology, the types of data acquisition systems are becoming more and more diverse. Traditional low-speed data acquisition systems use standard low-speed transmission protocols, such as RS232 and RS485 serial ports, and the equipment platform is implemented using microprocessors such as microcontrollers and ARM processors. Higher-speed acquisition systems, on the other hand, often use FPGA platforms, such as systems using Ethernet protocols. The former uses dedicated interfaces, which are simple to implement, but have a limited number of interfaces. The latter uses general-purpose I / O, resulting in a larger number of interfaces, but is more difficult to implement. Multi-chip systems that combine both often have limited inter-chip communication and a higher overall power consumption budget.

[0003] The PSOC (Power over Components) fully programmable system-on-a-chip (SoC) incorporates a high-performance ARM processor, supports the Linux operating system, and offers hardware customization capabilities for its programmable logic section. This chip tightly integrates the processor system with programmable logic and hard IP peripherals, providing a perfect combination of flexibility, configurability, and performance.

[0004] The PSOC (System-on-a-Chip) fully programmable chip utilizes a large number of interface IP cores to build arbitrary custom functions required by the target application. Inter-device access between master and slave devices is routed via AXI interconnects based on the address range assigned to each slave device. Multiple master devices can access multiple slave devices simultaneously, and each AXI interconnect uses an arbitration mechanism of magnitude to resolve contention issues.

[0005] The PSOC (Power over Components) fully programmable system-on-a-chip (SoC) allows for flexible task partitioning. Control tasks are handled by the ARM architecture, while computationally intensive tasks are accelerated via FPGA hardware, resulting in a 10-20x performance improvement. It leverages IP from Xilinx's Vivado tools, and Fudan Microelectronics has provided software support for commonly used IP drivers such as Ethernet, CAN, and serial ports, as well as the Linux kernel, enabling one-stop booting of Linux systems and easy integration into the ARM software ecosystem.

[0006] Therefore, a low-power, multi-interface data conversion system can be designed using a PSOC (Power over Programmable System-on-Chip). Summary of the Invention

[0007] The purpose of this invention is to overcome the shortcomings of the prior art and provide a low-power multi-interface data conversion system and method.

[0008] The technical solution adopted by this invention to solve its technical problem is: A low-power multi-interface data conversion system includes a control module, a power management module, a CAN interface module, a Flash memory unit, an eMMC memory unit, a DDR cache unit, a serial port module, a PC, connectors, and a debugging baseboard. The control module, power management module, CAN interface module, Flash memory unit, eMMC memory unit, DDR cache unit, and serial port module are all mounted on the same circuit board. The control module includes a PS terminal and a PL terminal. The PS terminal is connected to the PL terminal via an AXI bus, the PL port is connected to a connector, the PS terminal is connected to a serial port module, and the PL terminal is connected to a CAN interface module. The PC is connected to the debugging baseboard, the serial port module, and the CAN interface module via communication cables. The DDR cache module is connected to the PS terminal, the Flash storage unit and the eMMC storage unit are connected to the PL terminal, the PS terminal and the PL terminal are connected to the connector via the Ethernet interface module, the power management module is connected to the connector, the PC and the connector are both connected to the debugging base plate, the debugging base plate is connected to the external power supply, and the PC communicates with the Ethernet interface module via communication cable, the debugging base plate and the connector. The PL terminal can support partial reconfiguration during runtime. The PL terminal can build a multi-interface reconfigurable control module through the IP core, and work with the PS terminal to continuously monitor the status of each interface and make protocol conversion judgments based on the status monitoring results.

[0009] Furthermore, the control module is a PSOC chip, the connector is a CPEX onboard connector, the circuit board has a 6UCPEX structure, the power supply for the circuit board is input through the CPEX connector, the DDR cache unit consists of a DDR3 chip and peripheral circuits, the Flash storage unit consists of a Flash chip and peripheral circuits, the serial port unit consists of a serial port chip and circuits, the Ethernet interface unit uses a highly integrated four-channel Ethernet physical layer transceiver and its peripheral circuits, the CAN interface unit consists of a CAN transceiver and its peripheral circuits, and the power management unit consists of a power chip, a timing controller, and its peripheral circuits.

[0010] Furthermore, the circuit board has a 6U CPEX structure. The external power supply provides +12V to the CPEX connector through the debugging baseboard. The power management unit uses the LM4644 power management module, which can convert +12V to +5.0V, +3.3V, +1.8V, +1.5V, +1.2V, and +1.0V required by the PSOC chip and interface circuit. The 0.75V chip required by the DDR chip is implemented using the XC51200 power chip. The power-on timing control of the PSOC chip is performed using an RSS85004 timing controller. The PSOC chip is a JFMQL15T485-N type PSOC chip; the DDR cache unit uses an LS6D3423 chip with a capacity of 4Gb, using two DDR chips in a balanced T-branch topology, with the DDR bit width extended to 32 bits; the Flash memory unit uses a JEFM25F128A-E16 chip, which can support a maximum of 128Mbit of information storage, and can complete the PL-side hardware program logic initialization configuration and operating system booting of the PSOC chip via the SPI serial interface; the serial port unit uses an XYI3232 RS-232 signal transceiver; the Ethernet interface unit uses a single-channel PHY chip XYI8211 on the PS side and a dedicated SerDes pin on the PL side, using an XYI8214 four-channel Ethernet physical layer transceiver; the eMMC memory unit uses an SMFC32GBMP type chip; and the CAN interface unit uses a CP3053T-B type CAN transceiver.

[0011] The steps for using the system as described above are as follows: (1) During operation, the external power supply inputs +12V voltage through the debugging baseboard. After power-on, the power management module controls the power-on sequence and provides various levels to the PSOC chip accordingly. Then the PSOC chip starts up, first automatically loading the boot file in the Flash storage unit, the PS terminal in the PSOC enters u-boot, and at the same time loads the executable file in the PL terminal to realize programmable logic. Then loads the image file stored in the eMMC storage unit, enters the system, and completes system initialization. The system runs in the DDR cache module. (2) After system initialization, first configure the Ethernet interface module, set the network delay and IP address. After configuration, the Ethernet interface module can provide a total of five gigabit Ethernet interfaces. Then configure the baud rate of each CAN interface of the CAN interface module. After configuration, the CAN interface module can provide four isolated CAN interfaces. Using the UART hardware resources of the PS end in combination with the serial port module, one RS232 serial port can be provided. (3) The PC sends data to the four PL network simultaneously through the Ethernet interface module and receives all network data through the PS network; the PC sends and receives data to the three CAN interfaces through the CAN interface module and can receive all data from the fourth CAN interface; the PC is connected through the serial port module to realize serial communication, print system operation information, and input operation commands.

[0012] Furthermore, the CAN communication process of the CAN interface module is as follows: (1) After the module is powered on, the PC sends CAN protocol data to the first three CAN interface modules through the communication cable. The CAN interface modules transmit the data to the PL terminal of the PSOC chip through the designated pin. (2) After the data enters the PL terminal, the program first transmits the data to the three corresponding AXI_CAN IP cores according to the specified pin. The AXI_CAN IP core sends the CAN protocol data to the AXI Interconnect IP core through the AXI bus. At this time, the AXI Interconnect IP core acts as the AXI bus slave device and the AXI_CAN IP core acts as the master device. The AXI Interconnect IP core then forwards the data to the ZYNQ processing system IP core, which is also the PS terminal. After receiving the CAN data, the PS terminal determines which CAN interface the data comes from according to the address of the AXI_CAN IP core and adds the interface flag. The data enters the CAN application. The CAN application first stores the CAN data in the protocol stack and then extracts the data according to the first-in-first-out rule. When extracting, the extraction signal variable is set to ensure that the data does not enter during extraction and cause errors. (3) The extracted data is sent by the ZYNQ processing system IP core to another AXIInterconnect IP core. The AXIInterconnect IP core forwards the data to the fourth AXI_CAN IP core. The fourth AXI_CAN IP core sends the data to the fourth CAN interface module through the specified pin. The CAN interface module then sends the data to the PC through the communication cable. The PC receives the data.

[0013] Furthermore, the network communication process of the Ethernet interface module is as follows: (1) After the module is powered on, the PC sends four network protocol data to the debugging baseboard through the communication cable. The debugging baseboard transmits the data to the Ethernet interface module through the connector. The Ethernet interface module transmits the data to the PL terminal of the PSOC chip through the designated pin. (2) The PL end sends the data to the AXI 1G / 2.5G Ethernet Subsystem IP core according to the specified pin. The AXI 1G / 2.5G Ethernet Subsystem IP core is divided into master mode and slave mode. The slave mode IP core shares the clock and other resources of the master mode IP core. The AXI 1G / 2.5G Ethernet Subsystem IP core sends the data to the AXI Interconnect IP core. The AXI Interconnect IP core forwards the data to the ZYNQ processing system IP core. After receiving the data, the PS end can distinguish the network interface data according to the network IP address. The data enters the network application. The network application stores the data into the protocol stack. Then, according to the first-in-first-out rule, the data is extracted from the protocol stack. After the data is extracted, it is sent to the fourth Ethernet interface module through the hardware resources of the PS end. Then, the data is sent to the PC through the connector, debugging baseboard and communication cable. This completes the function of sending four Ethernet data through one Ethernet. (3) The PC can also send data to the fifth Ethernet interface module via communication cable, debugging baseboard and connector, and the Ethernet interface module will transmit the data to the PS end; (4) After receiving the data, the PS application sends it to another AXI Interconnect IP core. The AXI Interconnect IP core stores the data in the AXI Direct Memory Access IP core, and then the AXI Direct Memory Access IP core sends the data to the 1G / 2.5G Ethernet Subsystem IP core. The 1G / 2.5G Ethernet Subsystem IP core then sends the data to the four-way Ethernet interface module through the fixed pin of the PL end. The Ethernet interface module sends the data to the PC through the connector, debugging baseboard and communication cable. This completes the function of sending one Ethernet data through four Ethernet data.

[0014] The advantages and positive effects of this invention are as follows: 1. This invention enables dynamic hardware reconfiguration. The PL (Programmer) side supports partial reconfiguration during runtime, allowing hardware function updates without a restart, similar to software hot-swapping. The PL side can build multi-interface reconfigurable control modules via IP cores, while the PS (Power Supply) side continuously monitors the status of each interface and determines protocol conversion based on the monitoring results, enabling arbitrary switching between multiple protocols. EMIO (Electronic Interface Optimization) is used to expand the eMMC interface using SDIO resources, while a gigabit Ethernet port is directly extended from the PS side using Ethernet resources.

[0015] 2. Compared to traditional solutions that require independent processors, FPGAs, and peripheral chips, this solution significantly improves integration, reduces PCB area considerably, lowers power consumption by 50% in typical applications, and reduces the number of components, thus achieving optimal cost optimization. It supports dynamic voltage / frequency adjustment and independent PS / PL power domain control.

[0016] 3. This invention enables multi-channel network communication with low power consumption; it supports multi-channel CAN bus communication; it supports the conversion of multiple network data streams into a single network data stream; and it supports the conversion of multiple CAN data streams into a single CAN data stream. Through the AXI4 high-speed bus connection, low-latency data exchange is achieved, avoiding the bottleneck of inter-chip communication in traditional discrete solutions. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a structural connection according to the present invention; Figure 2 This is a logic block diagram of the PL in this invention; Figure 3 This is a timing control diagram of the PSOC chip in this invention. Detailed Implementation

[0018] The present invention will be further described below with reference to the embodiments. The following embodiments are descriptive and not limiting, and should not be used to limit the scope of protection of the present invention.

[0019] The various experimental operations involved in the specific embodiments are all conventional techniques in the field. For parts not specifically annotated in this document, those skilled in the art can refer to various commonly used reference books, scientific and technological documents or related instructions and manuals prior to the filing date of this invention to carry out the operations.

[0020] A low-power, multi-interface data conversion system, such as Figure 1 As shown, the system includes a control module, a power management module, a CAN interface module, a Flash memory unit, an eMMC memory unit, a DDR cache unit, a serial port module, a PC, connectors, and a debugging baseboard. The control module, power management module, CAN interface module, Flash memory unit, eMMC memory unit, DDR cache unit, and serial port module are all mounted on the same circuit board. The control module includes a PS terminal and a PL terminal. The PS terminal is connected to the PL terminal via an AXI bus, the PL port is connected to a connector, the PS terminal is connected to a serial port module, and the PL terminal is connected to a CAN interface module. The PC is connected to the debugging baseboard, the serial port module, and the CAN interface module via communication cables. The DDR cache module is connected to the PS terminal, the Flash storage unit and the eMMC storage unit are connected to the PL terminal, the PS terminal and the PL terminal are connected to the connector via the Ethernet interface module, the power management module is connected to the connector, the PC and the connector are both connected to the debugging base plate, the debugging base plate is connected to the external power supply, and the PC communicates with the Ethernet interface module via communication cable, the debugging base plate and the connector. The PL terminal supports partial reconfiguration during runtime, allowing hardware functions to be updated without a restart, similar to software hot-swapping. The PL terminal can build multi-interface reconfigurable control modules using IP cores, and work with the PS terminal to continuously monitor the status of each interface. Based on the status monitoring results, it makes protocol conversion decisions and can switch between multiple protocols arbitrarily.

[0021] More specifically: The control module is a PSOC chip, the connector is a CPEX onboard connector, the circuit board is a 6U CPEX structure, the power supply to the circuit board is input through the CPEX connector, the DDR cache unit consists of a DDR3 chip and peripheral circuits, the Flash storage unit consists of a Flash chip and peripheral circuits, the serial port unit consists of a serial port chip and circuits, the Ethernet interface unit uses a highly integrated four-channel Ethernet physical layer transceiver and its peripheral circuits, the CAN interface unit consists of a CAN transceiver and its peripheral circuits, and the power management unit consists of a power chip, a timing controller, and its peripheral circuits. Using the CPEX connector as the onboard connector, and defining signals and power according to the CPEX standard, a Fudan Microelectronics PSOC chip is used as the control core, along with a Fudan Microelectronics configuration chip, signal conversion circuits, DC / DC power conversion circuits, and IP cores to complete network and CAN communication. The system implements the DDR cache unit, Flash storage unit, serial port unit, Ethernet interface unit, eMMC storage unit, CAN interface unit, and power management unit.

[0022] This system uses a PSOC as its core, along with signal level conversion circuits and DC / DC power conversion circuits. Combined with a debugging baseboard, it provides power to the chip platform and exposes standard communication interfaces. It uses a PC for printing system information, Ethernet and CAN bus communication, and integrates DDR cache, Flash memory, serial port, Ethernet interface, eMMC memory, CAN interface, and power management units. The control logic for the PL port is as follows: Figure 2 As shown.

[0023] The circuit board has a 6U CPEX structure, and the platform power supply provides +12V through the CPEX connector on the baseboard. The power management unit uses an LM4644 power management module to convert the +12V to +5.0V, +3.3V, +1.8V, +1.5V, +1.2V, and +1.0V required by the PSOC chip and interface circuits. The 0.75V required by the DDR chip is implemented using an XC51200 power supply chip. An RSS85004 timing controller is used for the power-on timing control of the PSOC chip. The timing control diagram is shown below. Figure 3 As shown; The PSOC chip is a JFMQL15T485-N type; the DDR cache unit uses an LS6D3423 chip with a capacity of 4Gb. Two DDR chips are selected, employing a balanced T-branch topology to extend the DDR bit width to 32 bits, ensuring signal integrity and strict timing requirements; the Flash memory unit uses a JEFM25F128A-E16 chip, which supports a maximum information storage of 128Mbit. The PL-side hardware program logic initialization configuration and operating system boot are completed via the SPI serial interface. The serial port unit uses an XYI3232 RS-232 transceiver. The Ethernet interface unit uses a single-channel PHY chip XYI8211 on the PS side, and a four-channel Ethernet physical layer transceiver XYI8214 using a dedicated SerDes pin on the PL side. The eMMC storage unit uses an SMFC32GBMP chip. The CAN interface unit uses a CP3053T-B CAN transceiver.

[0024] The steps for using the system described above are as follows: (1) During operation, a +12V voltage is input through the debugging baseboard. The PC is connected to the debugging baseboard, serial port module, and CAN interface module via communication cables. After power-on, the power management module controls the power-on sequence, thereby providing various voltage levels to the PSOC chip. When the PSOC chip starts up, it first automatically loads the boot file in the Flash memory unit. The PS terminal in the PSOC enters u-boot, and at the same time, the executable file on the PL terminal is loaded to implement programmable logic. Then, the image file stored in the eMMC memory unit is loaded, the system enters, and the system initialization is completed. The system runs in the DDR cache module.

[0025] (2) After system initialization, first configure the Ethernet interface module, set the network latency and IP address. After configuration, the Ethernet interface module can provide a total of five gigabit Ethernet interfaces. Then configure the baud rate of each CAN interface of the CAN interface module. After configuration, the CAN interface module can provide four isolated CAN interfaces. Using the UART hardware resources of the PS end in combination with the serial port module, one RS232 serial port can be provided.

[0026] (3) The PC is connected to the Ethernet interface module via communication cable, debugging base plate and connector, and sends data to the four PL terminal network at the same time, and receives all network data through the PS terminal network; the PC is connected to the CAN interface module via communication cable, and sends and receives data to three CAN interfaces, and can receive all data from the fourth CAN interface; the PC is connected to the serial port module via communication cable to realize serial communication, and can print system operation information and input operation commands.

[0027] This method enables the implementation of four-channel network interface functions and four-channel CAN interface functions, and supports the conversion of multiple network data channels into one network data channel and multiple CAN data channels into one CAN data channel.

[0028] The CAN communication and network communication processes in this method are as follows: The CAN communication process is as follows: After the module is powered on, the PC sends CAN protocol data to the first three CAN interface modules through the communication cable. The CAN interface modules then transmit the data to the PL terminal of the PSOC chip through the designated pins.

[0029] like Figure 2 As shown, after the data enters the PL terminal, the program first transmits the data to the corresponding three AXI_CAN IP cores according to the specified pins. The AXI_CAN IP cores send the CAN protocol data to the AXI Interconnect IP core through the AXI bus. At this time, the AXI Interconnect IP core acts as an AXI bus slave device, and the AXI_CAN IP core acts as a master device. The AXI Interconnect IP core then forwards the data to the ZYNQ processing system IP core, which is also the PS terminal. After receiving the CAN data, the PS terminal determines which CAN interface the data comes from based on the address of the AXI_CAN IP core and adds an interface flag. The data enters the CAN application program. The CAN application program first stores the CAN data in the protocol stack, and then extracts the data according to the first-in-first-out rule. During extraction, an extraction signal variable is set to ensure that data does not enter during extraction, causing errors.

[0030] The extracted data is sent by the ZYNQ processing system IP core to another AXI Interconnect IP core. The AXI Interconnect IP core forwards the data to the fourth AXI_CAN IP core. The fourth AXI_CAN IP core sends the data to the fourth CAN interface module through a designated pin. The CAN interface module then sends the data to the PC through the communication cable, and the PC receives the data.

[0031] The network communication process is as follows: After the module is powered on, the PC sends four network protocol data to the debugging baseboard through the communication cable. The debugging baseboard transmits the data to the Ethernet interface module through the connector. The Ethernet interface module transmits the data to the PL terminal of the PSOC chip through the designated pin.

[0032] like Figure 2As shown, the PL terminal sends data to the AXI 1G / 2.5G Ethernet Subsystem IP core according to the specified pin. The AXI 1G / 2.5G Ethernet Subsystem IP core has master mode and slave mode. The slave mode IP core shares the clock and other resources of the master mode IP core. The AXI 1G / 2.5G Ethernet Subsystem IP core sends data to the AXIInterconnect IP core. The AXI Interconnect IP core forwards the data to the ZYNQ processing system IP core. After receiving the data, the PS terminal can distinguish the network interface data according to the network IP address. The data enters the network application, which stores the data in the protocol stack. Then, according to the first-in-first-out rule, the data is extracted from the protocol stack. After extraction, the data is sent to the fourth Ethernet interface module through the PS terminal hardware resources. Then, through the connector, debugging baseboard and communication cable, the data is sent to the PC. This completes the function of sending four Ethernet data through one Ethernet. The PC can also send data to the fifth Ethernet interface module via communication cables, a test baseboard, and connectors. The Ethernet interface module transmits the data to the PS end. After receiving the data, the PS application sends it to another AXI Interconnect IP core. The AXI Interconnect IP core stores the data in the AXI Direct Memory Access IP core, which then sends the data to the 1G / 2.5G Ethernet Subsystem IP core. The 1G / 2.5G Ethernet Subsystem IP core then sends the data to the four Ethernet interface modules via the fixed pins on the PL end. The Ethernet interface modules then send the data to the PC via connectors, a test baseboard, and communication cables. This completes the function of transmitting one Ethernet data stream through four Ethernet streams.

[0033] In the above process, CAN communication and network communication can be carried out simultaneously without affecting each other.

[0034] The power consumption of the present invention at different temperatures is shown in Table 1 below, which compares the present invention with that of conventional devices.

[0035] Therefore, as shown in Table 1 above, the present invention has the effect of low power consumption compared with traditional devices.

[0036] Although embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will understand that various substitutions, variations, and modifications are possible without departing from the spirit and scope of the invention and the appended claims. Therefore, the scope of the invention is not limited to the contents disclosed in the embodiments.

Claims

1. A low-power, multi-interface data conversion system, characterized in that: The system includes a control module, a power management module, a CAN interface module, a Flash memory unit, an eMMC memory unit, a DDR cache unit, a serial port module, a PC, connectors, and a debugging baseboard. The control module, power management module, CAN interface module, Flash memory unit, eMMC memory unit, DDR cache unit, and serial port module are all mounted on the same circuit board. The control module includes a PS terminal and a PL terminal. The PS terminal is connected to the PL terminal via an AXI bus, the PL port is connected to a connector, the PS terminal is connected to a serial port module, and the PL terminal is connected to a CAN interface module. The PC is connected to the debugging baseboard, the serial port module, and the CAN interface module via communication cables. The DDR cache module is connected to the PS terminal, the Flash storage unit and the eMMC storage unit are connected to the PL terminal, the PS terminal and the PL terminal are connected to the connector via the Ethernet interface module, the power management module is connected to the connector, the PC and the connector are both connected to the debugging base plate, the debugging base plate is connected to the external power supply, and the PC communicates with the Ethernet interface module via communication cable, the debugging base plate and the connector. The PL terminal can support partial reconfiguration during runtime. The PL terminal can build a multi-interface reconfigurable control module through the IP core, and work with the PS terminal to continuously monitor the status of each interface and make protocol conversion judgments based on the status monitoring results.

2. The system according to claim 1, characterized in that: The control module is a PSOC chip, the connector is a CPEX onboard connector, the circuit board is a 6U CPEX structure, the power supply of the circuit board is input through the CPEX connector, the DDR cache unit consists of a DDR3 chip and peripheral circuits, the Flash storage unit consists of a Flash chip and peripheral circuits, the serial port unit consists of a serial port chip and circuits, the Ethernet interface unit uses a highly integrated four-channel Ethernet physical layer transceiver and its peripheral circuits, the CAN interface unit consists of a CAN transceiver and its peripheral circuits, and the power management unit consists of a power chip, a timing controller and its peripheral circuits.

3. The system according to claim 2, characterized in that: The circuit board has a 6U CPEX structure. The external power supply provides +12V to the CPEX connector through the debugging baseboard. The power management unit uses the LM4644 power management module, which can convert +12V to +5.0V, +3.3V, +1.8V, +1.5V, +1.2V, and +1.0V required by the PSOC chip and interface circuit. The 0.75V chip required by the DDR chip is implemented using the XC51200 power chip. The power-on timing control of the PSOC chip is performed using an RSS85004 timing controller. The PSOC chip is a JFMQL15T485-N type PSOC chip; the DDR cache unit uses an LS6D3423 chip with a capacity of 4Gb, using two DDR chips in a balanced T-branch topology, with the DDR bit width extended to 32 bits; the Flash memory unit uses a JEFM25F128A-E16 chip, which can support a maximum of 128Mbit of information storage, and can complete the PL-side hardware program logic initialization configuration and operating system booting of the PSOC chip via the SPI serial interface; the serial port unit uses an XYI3232 RS-232 signal transceiver; the Ethernet interface unit uses a single-channel PHY chip XYI8211 on the PS side and a dedicated SerDes pin on the PL side, using an XYI8214 four-channel Ethernet physical layer transceiver; the eMMC memory unit uses an SMFC32GBMP type chip; and the CAN interface unit uses a CP3053T-B type CAN transceiver.

4. The method of using the system as described in any one of claims 2 to 3, characterized in that: The steps are as follows: (1) During operation, the external power supply inputs +12V voltage through the debugging baseboard. After power-on, the power management module controls the power-on sequence and provides various levels to the PSOC chip accordingly. Then the PSOC chip starts up, first automatically loading the boot file in the Flash storage unit, the PS terminal in the PSOC enters u-boot, and at the same time loads the executable file in the PL terminal to realize programmable logic. Then loads the image file stored in the eMMC storage unit, enters the system, and completes system initialization. The system runs in the DDR cache module. (2) After system initialization, first configure the Ethernet interface module, set the network delay and IP address. After configuration, the Ethernet interface module can provide a total of five gigabit Ethernet interfaces. Then configure the baud rate of each CAN interface of the CAN interface module. After configuration, the CAN interface module can provide four isolated CAN interfaces. Using the UART hardware resources of the PS end in combination with the serial port module, one RS232 serial port can be provided. (3) The PC sends data to the four PL network simultaneously through the Ethernet interface module and receives all network data through the PS network; the PC sends and receives data to the three CAN interfaces through the CAN interface module and can receive all data from the fourth CAN interface; the PC is connected through the serial port module to realize serial communication, print system operation information, and input operation commands.

5. The method according to claim 4, characterized in that: The CAN communication process of the CAN interface module is as follows: (1) After the module is powered on, the PC sends CAN protocol data to the first three CAN interface modules through the communication cable. The CAN interface modules transmit the data to the PL terminal of the PSOC chip through the designated pin. (2) After the data enters the PL terminal, the program first transmits the data to the three corresponding AXI_CAN IP cores according to the specified pin. The AXI_CAN IP core sends the CAN protocol data to the AXI Interconnect IP core through the AXI bus. At this time, the AXI Interconnect IP core acts as the AXI bus slave device and the AXI_CAN IP core acts as the master device. The AXI Interconnect IP core then forwards the data to the ZYNQ processing system IP core, which is also the PS terminal. After receiving the CAN data, the PS terminal determines which CAN interface the data comes from according to the address of the AXI_CAN IP core and adds the interface flag. The data enters the CAN application. The CAN application first stores the CAN data in the protocol stack and then extracts the data according to the first-in-first-out rule. When extracting, the extraction signal variable is set to ensure that the data does not enter during extraction and cause errors. (3) The extracted data is sent by the ZYNQ processing system IP core to another AXI Interconnect IP core. The AXI Interconnect IP core forwards the data to the fourth AXI_CAN IP core. The fourth AXI_CAN IP core sends the data to the fourth CAN interface module through the specified pin. The CAN interface module then sends the data to the PC through the communication cable. The PC receives the data.

6. The method according to claim 4, characterized in that: The network communication process of the Ethernet interface module is as follows: (1) After the module is powered on, the PC sends four network protocol data to the debugging baseboard through the communication cable. The debugging baseboard transmits the data to the Ethernet interface module through the connector. The Ethernet interface module transmits the data to the PL terminal of the PSOC chip through the designated pin. (2) The PL end sends the data to the AXI 1G / 2.5G Ethernet Subsystem IP core according to the specified pin. The AXI 1G / 2.5G Ethernet Subsystem IP core is divided into master mode and slave mode. The slave mode IP core shares the clock and other resources of the master mode IP core. The AXI 1G / 2.5G Ethernet Subsystem IP core sends the data to the AXI Interconnect IP core. The AXI Interconnect IP core forwards the data to the ZYNQ processing system IP core. After receiving the data, the PS end can distinguish the network interface data according to the network IP address. The data enters the network application. The network application stores the data into the protocol stack. Then, according to the first-in-first-out rule, the data is extracted from the protocol stack. After the data is extracted, it is sent to the fourth Ethernet interface module through the hardware resources of the PS end. Then, the data is sent to the PC through the connector, debugging baseboard and communication cable. This completes the function of sending four Ethernet data through one Ethernet. (3) The PC sends data to the fifth Ethernet interface module via communication cable, debugging baseboard and connector, and the Ethernet interface module transmits the data to the PS end; (4) After receiving the data, the PS application sends it to another AXI Interconnect IP core. The AXI Interconnect IP core stores the data in the AXI Direct Memory Access IP core, and then the AXI Direct Memory Access IP core sends the data to the 1G / 2.5G Ethernet Subsystem IP core. The 1G / 2.5G Ethernet Subsystem IP core then sends the data to the four-way Ethernet interface module through the fixed pin of the PL end. The Ethernet interface module sends the data to the PC through the connector, debugging baseboard and communication cable. This completes the function of sending one Ethernet data through four Ethernet data.

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