Power supply control circuit and power supply control method

Abstract

The invention relates to a power supply control circuit and a power supply control method, the power supply control circuit comprises a control circuit and a plurality of time sequence signal generation circuits, and the time sequence signal generation circuits generate time sequence signals of second driving signals according to input voltage, output voltage of corresponding output branches and time sequence signals of first driving signals. And the control circuit drives the upper tube to be switched off when the conduction time of the upper tube reaches the target conduction time. The time sequence signal of the second driving signal comprises the maximum conduction time of the upper tube, the target conduction time is smaller than or equal to the maximum conduction time, and the ratio of the maximum conduction time to the switching period of the converter is smaller than or equal to the duty ratio of the converter. Therefore, the power supply control circuit limits the maximum conduction time of the upper tube of the converter, and controls the conduction time of the upper tube not to exceed the maximum conduction time, so as to reduce the crosstalk among the branches when the output branches are switched.

Description

Technical Field

[0001] This application relates to the field of converters, and in particular to a power control circuit and a power control method. Background Art

[0002] Single-inductor multi-output converters achieve multiple outputs of different voltages through a single inductor, resulting in high operating efficiency and low standby power consumption, making them widely used in portable electronic devices.

[0003] In the case of single-inductor multi-output converters in related technologies, when sudden changes occur such as load jumps or power-on, the inductor current does not return to zero when different output branches switch. As a result, when the next output branch is turned on, there will be residual current interference between different output branches, which will lead to output voltage jitter and instability. Summary of the Invention

[0004] The embodiments of this application aim to provide a power control circuit and a power control method that can reduce crosstalk between output branches and improve the stability of the power supply output by the converter.

[0005] To address the aforementioned technical problems, this application provides the following technical solutions: In a first aspect, embodiments of this application provide a power control circuit applied to a single-inductor multi-output converter, wherein the converter includes a plurality of output branches, each output branch alternately outputting an output voltage, and when one output branch outputs an output voltage, the other output branches are turned off. The power control circuit includes: a control circuit and a plurality of timing signal generation circuits, wherein the timing signal generation circuits correspond one-to-one with the output branches. The timing signal generation circuit is respectively connected to the input voltage of the converter, the output voltage of the corresponding output branch, and the timing signal of the first drive signal of the corresponding output branch. The timing signal generation circuit is also connected to the control circuit. The timing signal generation circuit is used to generate a timing signal of a second drive signal based on the input voltage, the output voltage of the corresponding output branch, and the timing signal of the first drive signal of the corresponding output branch. The first drive signal is used to drive the corresponding output branch to turn on or off, and the second drive signal is used to drive the upper transistor of the converter to turn on or off. The timing signal of the second drive signal includes the maximum on-time of the upper transistor of the converter during the on-time of each output branch, and the maximum on-time satisfies the following constraint: the ratio of the maximum on-time to the switching period of the converter is less than or equal to the duty cycle of the converter. The control circuit is used to receive the timing signal of the second drive signal during the conduction period of each output branch, and to drive the upper transistor to turn off when the conduction time of the upper transistor reaches the target conduction time, wherein the target conduction time is less than or equal to the maximum conduction time of the upper transistor.

[0006] In some embodiments, the timing signal generation circuit includes a first delay unit, a first inverter, and a first AND gate; The input terminal of the first delay unit is used to receive the timing signal of the first driving signal, the input voltage, and the output voltage. The output terminal of the first delay unit is connected to the input terminal of the first inverter. The first delay unit is used to output a delay signal according to the timing signal of the first driving signal, the input voltage, and the output voltage. The output terminal of the first inverter is connected to the first input terminal of the first AND gate. The second input terminal of the first AND gate is used to receive the timing signal of the first driving signal. The first inverter is used to respond to the input of the delay signal and output the inverted signal of the delay signal. The first AND gate responds to the timing signal of the first driving signal and the inverted signal of the delay signal and outputs the timing signal of the second driving signal.

[0007] In some embodiments, the first delay unit includes a conversion unit, a mirror unit, a switching unit, an energy storage unit, and a generation unit; The first input terminal of the conversion unit is used to receive the first sampling voltage, and the output terminal of the conversion unit is connected to the first terminal of the mirror unit. The conversion unit is used to convert the first sampling voltage into a sampling current, wherein the first sampling voltage is the sampling voltage of the input voltage. The second end of the mirror unit is connected to the first end of the switching unit, and the mirror unit is used to mirror the sampling current to generate a mirror current. The second terminal of the switching unit is connected to the first input terminal of the energy storage unit and the first input terminal of the generation unit, respectively. The third terminal of the switching unit is grounded. The control terminal of the switching unit is used to receive the timing signal of the first driving signal. The switching unit is used to respond to the input of the timing signal of the first driving signal and control the mirror current to charge the energy storage unit, so as to raise the voltage of the first input terminal of the generation unit, or to connect the first input terminal of the generation unit to ground, so as to lower the voltage of the first input terminal of the generation unit. The second input terminal of the generation unit is used to receive the second sampling voltage, and the third input terminal of the generation unit is used to receive the timing signal of the first driving signal. The generation unit is used to compare the second sampling voltage with the voltage of the first input terminal of the generation unit to generate a comparison signal, and generate the delay signal according to the comparison signal and the timing signal of the first driving signal, wherein the second sampling voltage is the sampling voltage of the output voltage.

[0008] In some embodiments, the conversion unit includes a first operational amplifier, a first resistor, and a first MOSFET; The non-inverting input of the first operational amplifier is used to connect to the first sampling voltage. The inverting input of the first operational amplifier is connected to one end of the first resistor and the source of the first MOS transistor. The other end of the first resistor is grounded. The output of the first operational amplifier is connected to the gate of the first MOS transistor. The drain of the first MOS transistor is connected to the first end of the mirror unit.

[0009] In some embodiments, the mirror unit includes a second MOS transistor and a third MOS transistor; The drain of the second MOS transistor is connected to the drain of the first MOS transistor. The drain of the second MOS transistor is also connected to the gate of the second MOS transistor and the gate of the third MOS transistor. The source of the second MOS transistor and the source of the third MOS transistor are connected to the first power supply. The drain of the third MOS transistor is connected to the first terminal of the switching unit.

[0010] In some embodiments, the switching unit includes a fourth MOSFET, a fifth MOSFET, and a second inverter; The gate of the fourth MOS transistor and the input terminal of the second inverter are both used to receive the timing signal of the first drive signal. The drain of the fourth MOS transistor is connected to the drain of the third MOS transistor. The source of the fourth MOS transistor is connected to the drain of the fifth MOS transistor, the energy storage unit, and the first input terminal of the generation unit, respectively. The source of the fifth MOS transistor is grounded, and the gate of the fifth MOS transistor is connected to the output terminal of the second inverter.

[0011] In some embodiments, the energy storage unit includes a first capacitor, one end of which is connected to the source of the fourth MOS transistor, the drain of the fifth MOS transistor, and the first end of the generation unit, and the other end of the first capacitor is grounded.

[0012] In some embodiments, the generation unit includes a first comparator and a second AND gate; The non-inverting input of the first comparator is connected to the first capacitor, the source of the fourth MOSFET, and the drain of the fifth MOSFET, respectively. The inverting input of the first comparator is used to input the second sampling voltage. The output of the first comparator is connected to the first input of the second AND gate. The second input of the second AND gate is used to input the timing signal of the first driving signal. The output of the second AND gate is connected to the control circuit. The output of the second AND gate is used to output the timing signal of the second driving signal.

[0013] In a second aspect, embodiments of this application provide a power control method applied to the power control circuit described above, the method comprising: The timing signal of the second drive signal is generated by the timing signal generation circuit. The timing signal of the second drive signal includes the maximum on-time of the upper transistor of the converter during the conduction of each output branch. The maximum on-time satisfies the following constraint: the ratio of the maximum on-time to the switching period of the converter is less than or equal to the duty cycle of the converter. During the conduction period of each output branch, the timing signal of the second drive signal is received by the control circuit, and when the conduction time of the upper transistor reaches the target conduction time, the upper transistor is driven to turn off, wherein the target conduction time is less than or equal to the maximum conduction time of the upper transistor.

[0014] In some embodiments, the power control circuit further includes a current detection circuit, which is connected to the inductor in the converter and the control circuit respectively. The method further includes: During the conduction of each output branch, the current flowing through the inductor is detected by the current detection circuit to obtain the sampled current, and in response to the result that the sampled current is greater than or equal to the maximum current threshold, a first-level trigger signal is output. The control circuit receives the trigger signal and drives the upper transistor to turn off when the trigger signal is at the first level.

[0015] In various embodiments of this application, the power control circuit includes a control circuit and a plurality of timing signal generation circuits. Each timing signal generation circuit corresponds to an output branch. The timing signal generation circuit is connected to the input voltage of the converter, the output voltage of the corresponding output branch, and the timing signal of the first drive signal of the corresponding output branch. The timing signal generation circuit is also connected to the control circuit. The timing signal generation circuit generates a timing signal of a second drive signal based on the input voltage, the output voltage of the corresponding output branch, and the timing signal of the first drive signal of the corresponding output branch. During the conduction period of each output branch, the control circuit receives the timing signal of the second drive signal and drives the upper transistor to turn off when the conduction time of the upper transistor reaches the target conduction time. The first driving signal is used to drive the output branch to turn on or off, and the second driving signal is used to drive the upper transistor of the converter to turn on or off. The timing signal of the second driving signal includes the maximum on-time of the upper transistor of the converter during the on-time of each output branch. The target on-time is less than or equal to the maximum on-time of the upper transistor, and the maximum on-time satisfies the following constraint: the ratio of the maximum on-time to the switching cycle of the converter is less than or equal to the duty cycle of the converter.

[0016] Therefore, during the conduction period of each output branch, the power control circuit controls the maximum conduction time of the converter's master transistor to satisfy the constraint that the ratio of the maximum conduction time to the converter's switching cycle is less than or equal to the converter's duty cycle. When the conduction time of the converter's master transistor reaches the target conduction time, the master transistor is driven to turn off, and the target conduction time is less than or equal to the maximum conduction time. This ensures that before the next output branch is turned on, the current flowing through the converter's inductor drops to zero, thereby reducing crosstalk between output branches during output branch switching or load transitions, reducing power supply jitter, and improving the stability of the converter's output power. Attached Figure Description

[0017] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0018] Figure 1 This is a schematic diagram of the structure of one of the single-inductor multi-output converters provided in the embodiments of this application; Figure 2 This is a schematic diagram of the structure of one of the power control circuits provided in the embodiments of this application; Figure 3 This is a timing diagram of the timing signal of the first driving signal, the timing signal of the second driving signal, and the clock signal of the converter, provided in one embodiment of this application. Figure 4This is a schematic diagram of the structure of one of the power control circuits provided in the embodiments of this application; Figure 5 This is a schematic diagram of the structure of one of the timing signal generation circuits provided in the embodiments of this application; Figure 6 This is a schematic diagram of the structure of one of the first delay units provided in the embodiments of this application; Figure 7 This is a schematic diagram of the circuit structure of one of the first delay units provided in the embodiments of this application; Figure 8 This is a schematic diagram of the circuit structure of one of the power control circuits provided in the embodiments of this application; Figure 9 This is a schematic flowchart of one of the power control methods provided in the embodiments of this application; Figure 10 This is a flowchart illustrating one of the power control methods provided in the embodiments of this application. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0020] Please see Figure 1 , Figure 1 This is a schematic diagram of a single-inductor multi-output converter provided in an embodiment of this application. Figure 1 The example shown uses two output branches. This single-inductor multi-output converter belongs to the synchronous buck converter type of DC-DC converters. It includes an inductor L, a power transistor MP, and a synchronous transistor MN. MP is a power transistor, and MN is a synchronous transistor. The converter also includes a control circuit 10. The two output terminals of the control circuit 10 are connected to the control terminals of MP and MN, respectively. The control circuit 10 outputs drive signals, such as a second drive signal to control the conduction or cutoff of MP, and a third drive signal to control the conduction or cutoff of MN.

[0021] The input terminal of the upper transistor MP is connected to the input voltage vin. The corresponding load circuit includes two output branches. The first output branch includes switch S1 and capacitor Co1. When switch S1 is on, inductor L and capacitor Co1 are connected, and their common connection point is used to output the output voltage vo1. The second output branch includes switch S2 and capacitor Co2. When switch S2 is on, inductor L and capacitor Co2 are connected, and their common connection point is used to output the output voltage vo2.

[0022] The switching frequency of the upper transistor MP is fixed. Switches S1 and S2 are turned on alternately. When S1 is on, the inductor current powers the capacitor Co1, and the output voltage vo1 is output. When S2 is on, S1 is off, and the inductor current powers the capacitor Co2, and the output voltage vo2 is output.

[0023] Therefore, this single-inductor multi-output converter achieves two different voltage outputs through a single inductor. This single-inductor multi-output converter has two operating modes: Connected-on mode (CCM) and Discontinuous-on mode (DCM). The operating mode depends on the output load. When the output load is small, the converter operates in DCM mode. In this mode, the control circuit 10 first drives the upper transistor MP to conduct during the switching cycle. After conducting for a period of time, it drives MP to turn off and drives the lower transistor MN to conduct. When the inductor current returns to zero, it drives MN to turn off. The upper transistor MP and the lower transistor MN remain off for a period of time. Therefore, when the converter operates in DCM mode, the inductor current returns to zero before the end of the current switching cycle. When the output load is large, the converter operates in CCM mode. At the end of the current switching cycle, the inductor current is not zero. Therefore, when the next output branch conducts, there will be residual current interference between different output branches, leading to output voltage jitter and instability.

[0024] Based on the above problems, this application provides a power control circuit 100, which can solve the cross-interference problem caused by the sharing of inductors among the output branches. It ensures that the inductor current is reduced to zero before the next output branch is turned on, thereby reducing interference between the output branches, reducing output voltage jitter, and improving power supply stability.

[0025] Specifically, if Figure 2 As shown, the power control circuit 100 includes several timing signal generation circuits 20 and a control circuit 10, with each timing signal generation circuit 20 corresponding to an output branch. The timing signal generation circuit 20 is connected to the input voltage of the converter, the output voltage of the corresponding output branch, and the timing signal of the first drive signal of the corresponding output branch. The timing signal generation circuit 20 is also connected to the control circuit 10. Figure 2 The example shown uses two output branches.

[0026] The timing signal generation circuit 20 generates a timing signal for the second driving signal during the conduction period of the corresponding output branch based on the input voltage, the output voltage of the corresponding output branch, and the timing signal of the first driving signal of the corresponding output branch. The first driving signal is used to drive the output branch to turn on or off, and the second driving signal is used to drive the upper transistor MP of the converter to turn on or off. The timing signal of the second driving signal includes the maximum conduction time of the upper transistor MP of the converter, and the maximum conduction time satisfies the following constraint: the ratio of the maximum conduction time to the switching period of the converter is less than or equal to the duty cycle of the converter.

[0027] by Figure 1 Taking the two output branches as an example, the timing signal of the first drive signal is as follows: Figure 3 As shown, ck represents the reference clock generated by the oscillator. Timing signal S11 is the timing signal for the first drive signal of the first output branch. When timing signal S11 is high, switch S1 is on; when timing signal S11 is low, switch S1 is off. Timing signal S22 is the timing signal for the first drive signal of the second output branch. When timing signal S22 is high, switch S2 is on; when timing signal S22 is low, switch S2 is off. When timing signal S11 is high, timing signal S22 is low, causing switches S1 and S2 to alternately conduct.

[0028] The first timing signal generation circuit 20 is connected to the input voltage vin of the converter, the output voltage vo1 of the first output branch, and the timing signal S11, respectively, and is also connected to the control circuit 10. The second timing signal generation circuit 20 is connected to the input voltage vin of the converter, the output voltage vo2 of the second output branch, and the timing signal S22, respectively, and is also connected to the control circuit 10.

[0029] The ratio of the maximum on-time to the converter's switching cycle is less than or equal to the converter's duty cycle, meaning the maximum on-time satisfies the following constraint: (1) Where ton_max is the maximum on-time, vo is the output voltage, vin is the input voltage, and T is the switching period of the converter.

[0030] vo is the output voltage, such as output voltage vo1 or output voltage vo2. During the conduction period of switch S1, the maximum conduction time of the upper transistor MP satisfies the following constraint: (2) Wherein, ton_max1 is the maximum on-time of the upper transistor MP during the on-time of switch S1, and vo1 is the output voltage of the converter during the on-time of switch S1.

[0031] Similarly, during the conduction of switch S2, the maximum conduction time of the upper transistor MP satisfies the following constraint: (3) Wherein, ton_max2 is the maximum on-time of the upper transistor MP during the on-time of switch S2, and vo2 is the output voltage of the converter during the on-time of switch S2.

[0032] In formula (1), the ratio of output voltage v0 to input voltage vin is the duty cycle of the converter. Therefore, the ratio of maximum on-time ton_max to switching period T is less than or equal to the duty cycle.

[0033] Please continue reading. Figure 3 The timing signals of the second drive signals of the two output branches are as follows: Figure 3 As shown, the timing signal of the second drive signal of the first output branch is timing signal tonmax1, which remains high for the maximum conduction time ton_max1. When timing signal tonmax1 is high, control circuit 10 drives the upper transistor MP to conduct. When the conduction time of upper transistor MP reaches the target conduction time, control circuit 10 drives upper transistor MP to turn off. The target conduction time is less than or equal to the maximum conduction time, so that the inductor current returns to zero at the end of the switching cycle, without affecting the output of the next output branch. If, due to an abnormal situation, upper transistor MP is not turned off when the target conduction time is reached, then when timing signal tonmax1 becomes low (indicating that the conduction time of upper transistor MP has reached the maximum conduction time ton_max1), control circuit 10 forcibly turns off upper transistor MP to ensure that the conduction time of upper transistor MP is less than or equal to the maximum conduction time ton_max1, so that the inductor current returns to zero at the end of the switching cycle, without affecting the output of the next output branch.

[0034] Similarly, the timing signal for the second drive signal of the second output branch is timing signal tonmax2, which remains high for the maximum on-time ton_max2. When timing signal tonmax2 is high, control circuit 10 drives the upper transistor MP to turn on. When the on-time of upper transistor MP reaches the target on-time, control circuit 10 drives upper transistor MP to turn off, so that the inductor current returns to zero at the end of the switching cycle, without affecting the output of the next output branch. If, due to an abnormal situation, upper transistor MP is not turned off when the target on-time is reached, control circuit 10 forcibly turns off upper transistor MP when timing signal tonmax2 goes low, to ensure that the on-time of upper transistor MP is less than or equal to the maximum on-time ton_max2, so that the inductor current returns to zero at the end of the switching cycle, the converter operates in DCM mode, without affecting the output of the next output branch.

[0035] The target conduction time is the set conduction time or preset conduction time of the upper-level transistor MP. The target conduction times of the two output branches can be the same or different, but the target conduction time of the first output branch shall not exceed the maximum conduction time ton_max1, and the target conduction time of the second output branch shall not exceed the maximum conduction time ton_max2, so as to ensure that the conduction time of the upper-level transistor MP does not exceed the corresponding maximum conduction time during the conduction period of each output branch.

[0036] In summary, during the conduction period of each output branch, the power control circuit controls the maximum conduction time of the converter's master transistor to ensure that the ratio of the maximum conduction time to the converter's switching cycle is less than or equal to the converter's duty cycle. When the conduction time of the converter's master transistor reaches the target conduction time, the master transistor is driven to turn off, and the target conduction time is less than or equal to the maximum conduction time. This causes the current flowing through the converter's inductor to drop to zero before the next output branch is turned on. Consequently, when the output branch switches or the load changes, the crosstalk between the output branches is reduced, power supply jitter is reduced, and the stability of the converter's output power supply is improved.

[0037] In some embodiments, when the input voltage or output voltage changes abruptly, or when a sudden load is applied, the converter may still briefly enter the CCM state by simply limiting the maximum on-time of the upper transistor MP, which will affect the output of the next output branch and cause crosstalk between the output branches.

[0038] To address the aforementioned issues, this application provides a power control circuit 100 that can further reduce crosstalk between output branches.

[0039] Specifically, if Figure 4As shown, the power control circuit 100 also includes a current detection circuit 30. The current detection circuit 30 is connected to the inductor L in the converter and the control circuit 10, respectively. The current detection circuit 30 detects the current flowing through the inductor L to obtain the sampled current. When the sampled current is greater than or equal to the maximum current threshold, the current detection circuit 30 outputs a first-level trigger signal. When the sampled current is less than the maximum current threshold, the current detection circuit 30 outputs a second-level trigger signal.

[0040] During the conduction of each output branch, the control circuit 10 receives a trigger signal ocp. If a trigger signal of the first level is received, it indicates that the inductor current is greater than or equal to the maximum current threshold. Then, the upper transistor MP is driven to turn off to ensure that the inductor current can be reduced to zero before the next output branch is turned on, thereby reducing interference to the next output branch.

[0041] If a trigger signal of the second level is received, it indicates that the inductor current is less than the maximum current threshold, and the upper transistor MP will continue to be turned on. The first level and the second level can be set as needed. In this embodiment, the first level is a high level and the second level is a low level.

[0042] It should be noted that when the control circuit 10 receives the second-level trigger signal, if the target conduction time of the upper transistor MP has not yet been reached, the upper transistor MP will continue to be conducted. When the target conduction time of the upper transistor MP is reached, the upper transistor MP will be driven to be turned off. However, if due to an abnormal situation, the upper transistor MP is not turned off when the target conduction time of the upper transistor MP is reached, the upper transistor MP will be forcibly turned off when the conduction time of the upper transistor MP reaches the maximum conduction time, so as to ensure that the conduction time of the upper transistor MP does not exceed the maximum conduction time.

[0043] If the control circuit 10 receives a first-level trigger signal before the target on-time of the upper-level transistor MP is reached, it indicates that the inductor current has reached the maximum current threshold, and the upper-level transistor MP is driven to turn off. If it receives a second-level trigger signal, it indicates that the inductor current has not reached the maximum inductor current threshold, and the upper-level transistor MP continues to be on.

[0044] Therefore, when the conduction time of the upper transistor MP reaches the target conduction time, where the target conduction time is less than or equal to the maximum conduction time, and the maximum conduction time satisfies the constraint that the ratio of the maximum conduction time to the switching cycle of the converter is less than or equal to the duty cycle of the converter, or when the trigger signal is at the first level, the control circuit 10 will drive the upper transistor MP to turn off, so as to ensure that the converter operates in DCM mode in steady state, and the inductor current returns to zero before the next output branch is turned on, thereby reducing crosstalk between the output branches.

[0045] In some embodiments, the maximum current threshold is determined based on the output voltage, input voltage, switching cycle, and the inductance of inductor L.

[0046] Specifically, when the converter operates in critical conduction mode (BCM mode), the inductor current is calculated using the following formula: (4) Where i is the inductor current, T is the switching period of the converter, L1 is the inductance of the converter's inductor L, vo is the output voltage, and vin is the maximum value of the input voltage.

[0047] In formula (4), the output voltage vo, the switching period T and the inductance L1 are fixed values. When the input voltage vin is at its maximum, the inductor current i is at its maximum. Therefore, the maximum inductor current is determined as the maximum current threshold.

[0048] Specifically, the maximum current threshold is: (5) Among them, i max vin is the maximum current threshold. max This represents the maximum value of the input voltage.

[0049] Therefore, for the first output branch, the inductor current should be limited to... Therefore, when the inductor current is greater than or equal to imax1, the upper transistor MP is driven to turn off. For the second output branch, the inductor current should be limited to... The following applies: when the inductor current is greater than or equal to imax2, the upper transistor MP is driven to turn off.

[0050] Please see Figure 5 , Figure 5 This is a schematic diagram of a timing signal generation circuit provided in an embodiment of this application, as shown below. Figure 5 As shown, the timing signal generation circuit 20 includes a first delay unit 21, a first inverter INV1, and a first AND gate A1. The first delay unit 21, the first inverter INV1, and the first AND gate A1 are in one-to-one correspondence, and the number of the first delay unit 21, the number of the first inverter INV1, and the number of the first AND gate A1 are all the same as the number of output branches.

[0051] For example, if there are N output branches, then the number of first delay units 21, the number of first inverters INV1, and the number of first AND gates A1 are all N. If the converter has... Figure 3 The two output branches shown have two first delay units 21, two first inverters INV1, and two first AND gates A1, and the first delay units 21, the first inverters INV1, and the first AND gates A1 are in one-to-one correspondence. Figure 5 It is shown by taking two output branches as an example.

[0052] The input end of the first delay unit 21 is used to access the timing signal of the first driving signal, the input voltage, and the output voltage. The output end of the first delay unit 21 is connected to the input end of the first inverter INV1. The output end of the first inverter INV1 is connected to the first input end of the first AND gate A1. The second input end of the first AND gate A1 is used to access the timing signal of the first driving signal.

[0053] The first delay unit 21 outputs a delay signal according to the timing signal of the first driving signal, the input voltage, and the output voltage. The first inverter INV1 then inverts the delay signal to output the inverted signal of the delay signal. The first AND gate A1 performs an AND operation on the inverted signal of the delay signal and the timing signal of the first driving signal to output the timing signal of the second driving signal.

[0054] Among them, when the first delay unit 21 performs a delay operation according to the timing signal of the first driving signal, the input voltage, and the output voltage and outputs a delay signal, the delay time of the delay signal is the maximum conduction time, and the maximum conduction time is designed according to ton_max < vo / vin*T.

[0055] In some embodiments, the timing signal of the first driving signal and the working clock of the converter can be obtained through a non-overlapping circuit and a second delay unit. Specifically, as Figure 5 shown, the timing signal generation circuit 20 further includes a non-overlapping circuit 22, several second delay units 23, several third inverters INV2, several second AND gates A3, and a first OR gate G1. The number of the second delay units 23, the third inverters INV2, and the second AND gates A3 is the same as the number of output branches, and the second delay units 23, the third inverters INV2, and the second AND gates A3 correspond to each other one by one. Among them, Figure 5 taking two output branches as an example for illustration, the timing signal generation circuit 20 further includes a non-overlapping circuit 22, two second delay units 23, two third inverters INV2, two second AND gates A3, and a first OR gate G1.

[0056] The non-overlapping circuit 22 includes inverters INV3 to INV7, AND gate G2, and AND gate G3. The input of inverter INV4 and the first input of OR gate G2 are used to connect to the reference clock generated by the oscillator. The second input of OR gate G2 is connected to the output of inverter INV6. The output of inverter INV4 is connected to the first input of OR gate G3. The second input of OR gate G3 is connected to the output of inverter INV3. The output of OR gate G3 is connected to the input of inverter INV5. The output of inverter INV5 is connected to the input of inverter INV6. The output of OR gate G2 is connected to the input of inverter INV7. The output of inverter INV7 is connected to the input of inverter INV3.

[0057] After the reference clock passes through the non-overlapping circuit 22, it generates timing signals for the first drive signals of each output branch, such as the timing signal S11 for the first drive signal of the first output branch and the timing signal S22 for the first drive signal of the second output branch. The timing signal S11 is output through the output terminal of the inverter INV3 and the timing signal S22 is output through the output terminal of the inverter INV6.

[0058] Timing signals S11 and S22 are input to the first delay unit 21 on one side to generate the timing signal of the second drive signal, and input to the input terminals of the two second inverters INV2 on the other side to obtain the working clock of the converter.

[0059] Specifically, the input terminal of the first second inverter INV2 is used to receive the timing signal S11, the output terminal of the first second inverter INV2 is connected to the input terminal of the first second delay unit 23, the output terminal of the first second delay unit 23 is connected to the first input terminal of the first second AND gate A3, the second input terminal of the first second AND gate A3 is used to receive the timing signal S11, and the output terminal of the first second AND gate A3 is connected to the first input terminal of the first OR gate G1.

[0060] Similarly, the input of the second inverter INV2 is used to receive the timing signal S22, the output of the second inverter INV2 is connected to the input of the second delay unit 23, the output of the second delay unit 23 is connected to the first input of the second AND gate A3, the second input of the second AND gate A3 is used to receive the timing signal S22, and the output of the second AND gate A3 is connected to the second input of the first OR gate G1.

[0061] The first group of second inverters INV2, second delay unit 23, and second AND gate A3 invert, delay, and AND the timing signal S11 to output a first signal. The second group of second inverters INV2, second delay unit 23, and second AND gate A3 invert, delay, and AND the timing signal S22 to output a second signal. The first OR gate G1 performs an OR operation on the first signal and the second signal to output the converter's operating clock.

[0062] The converter's operating clock is as follows Figure 3 As shown in the clock signal ck1, the rising edge triggers the converter to enter the next working cycle. If the period of the reference clock ck generated by the oscillator is 2T, then the interval between two rising edges is equal to one switching cycle T.

[0063] Please see Figure 6 , Figure 6 This is a schematic diagram of the structure of a first delay unit provided in an embodiment of this application, as shown below. Figure 6 As shown, the first delay unit 21 includes a conversion unit 211, a mirror unit 212, a switching unit 213, an energy storage unit 214, and a generation unit 215. The first input terminal of the conversion unit 211 is used to receive a first sampling voltage. The output terminal of the conversion unit 211 is connected to the first terminal of the mirror unit 212. The second terminal of the mirror unit 212 is connected to the first terminal of the switching unit 213. The second terminal of the switching unit 213 is connected to the first input terminals of both the energy storage unit 214 and the generation unit 215. The third terminal of the switching unit 213 is grounded.

[0064] The first sampling voltage is the sampling voltage of the input voltage. The conversion unit 211 converts the first sampling voltage into a sampling current, realizing the conversion between voltage and current. The sampling current flows into the mirror unit 212, which mirrors the sampling current to generate a mirror current. The ratio of the mirror current to the sampling current can be 1:1.

[0065] The control terminal of the switching unit 213 is used to receive the timing signal of the first driving signal (such as timing signal S11 or timing signal S22). The timing signal of the first driving signal controls the working state of the switching unit 213 to control the voltage level of the first input terminal of the generation unit 215.

[0066] When the timing signal of the first drive signal is at a high level, the control switch unit 213 is in the first state, so that the mirror current flows to the energy storage unit 214 to charge the energy storage unit 214 and gradually raise the voltage of the first input terminal of the generation unit 215.

[0067] When the timing signal of the first drive signal is at a low level, the control switch unit 213 is in the second state, so that the mirror current can no longer flow to the energy storage unit 214, and connects the connection between the first input terminal of the generation unit 215 and the ground, pulling down the voltage of the first input terminal of the generation unit 215 and pulling the voltage of the first input terminal of the generation unit 215 to the ground.

[0068] The second input terminal of the generation unit 215 is used to receive the second sampling voltage, and the third input terminal of the generation unit 215 is used to receive the timing signal of the first driving signal. The generation unit 215 generates a delay signal based on the second sampling voltage, the voltage at the first input terminal of the generation unit 215, and the timing signal of the first driving signal.

[0069] The second sampling voltage is the sampling voltage of the output voltage. The generation unit 215 compares the second sampling voltage with the voltage of its first input terminal to generate a comparison signal. When the voltage of its first input terminal is raised, the comparison signal is at the first level. When its first input terminal is grounded, the comparison signal is at the second level, thereby generating a high-low level comparison signal.

[0070] The generation unit 215 then generates a delay signal based on the timing signal of the comparison signal between the high and low levels and the first drive signal.

[0071] Please see Figure 7 , Figure 7 This is a schematic diagram of the circuit structure of a first delay unit provided in an embodiment of this application, as shown below. Figure 7 As shown, the conversion unit 211 includes a first operational amplifier U1, a first resistor R, and a first MOS transistor M1. The non-inverting input of the first operational amplifier U1 is used to connect to the first sampling voltage. The inverting input of the first operational amplifier U1 is connected to one end of the first resistor R and the source of the first MOS transistor M1, respectively. The other end of the first resistor R is grounded. The output of the first operational amplifier U1 is connected to the gate of the first MOS transistor M1. The drain of the first MOS transistor M1 is connected to the first end of the mirror unit 212.

[0072] The mirror unit 212 includes a second MOSFET M2 and a third MOSFET M3. The drain of the second MOSFET M2 is connected to the drain of the first MOSFET M1. The drain of the second MOSFET M2 is also connected to the gate of the second MOSFET M2 and the gate of the third MOSFET M3. The source of the second MOSFET M2 and the source of the third MOSFET M3 are connected to a DC power supply. The drain of the third MOSFET M3 is connected to the first terminal of the switching unit 213.

[0073] The switching unit 213 includes a fourth MOSFET M4, a fifth MOSFET M5, and a second inverter INV8. The gate of the fourth MOSFET M4 and the input of the second inverter INV8 are both used to receive the timing signal of the first drive signal. The drain of the fourth MOSFET M4 is connected to the drain of the third MOSFET M3. The source of the fourth MOSFET M4 is connected to the drain of the fifth MOSFET M5, the first input of the energy storage unit 214, and the generation unit 215, respectively. The source of the fifth MOSFET M5 is grounded, and the gate of the fifth MOSFET M5 is connected to the output of the second inverter INV8.

[0074] The energy storage unit 214 includes a first capacitor C. One end of the first capacitor C is connected to the source of the fourth MOSFET M4, the drain of the fifth MOSFET M5, and the first end of the generation unit 215, respectively. The other end of the first capacitor C is grounded.

[0075] The generation unit 215 includes a first comparator U2 and a second AND gate A4. The non-inverting input of the first comparator U2 is connected to the first capacitor C, the source of the fourth MOSFET M4, and the drain of the fifth MOSFET M5, respectively. The inverting input of the first comparator U2 is used to input the second sampling voltage. The output of the first comparator U2 is connected to the first input of the second AND gate A4. The second input of the second AND gate A4 is used to input the timing signal of the first driving signal. The output of the second AND gate A4 is connected to the control circuit 10. The output of the second AND gate A4 is used to output the timing signal of the second driving signal.

[0076] If the first sampling voltage is η*vin and the second sampling voltage is λ*vo, where η is the proportionality coefficient between the first sampling voltage and the input voltage, and λ is the proportionality coefficient between the second sampling voltage and the output voltage, and the connection node between the first resistor R and the first MOSFET M1 is node VX, and the first operational amplifier U1 clamps the voltage at node VX to the first sampling voltage, then the current flowing through the first MOSFET M1 and the first resistor R is the sampling current, calculated using the following formula: (6) Where I1 is the sampling current, R1 is the resistance of the first resistor R, η is the ratio coefficient of the first sampling voltage to the input voltage, and vin is the input voltage.

[0077] The first operational amplifier U1, the first MOSFET M1, and the first resistor R convert the first sampling voltage into a sampling current I1. The current flowing through the second MOSFET M2 is also the sampling current I1. The third MOSFET M3 mirrors the sampling current I1, generating a mirror current I2 with a mirror ratio of 1:1. Therefore, the mirror current I2 = I1.

[0078] When the timing signal of the first drive signal is high, the fourth MOSFET M4 is turned on, the second inverter INV8 converts the high-level signal to a low-level signal, then the fifth MOSFET M5 is turned off, the mirror current I2 flows into the first capacitor C, charging the first capacitor C and raising the voltage at the non-inverting input of the first comparator U2.

[0079] When the timing signal of the first drive signal is low, the fourth MOSFET M4 is turned off, the second inverter INV8 converts the low-level signal to a high-level signal, then the fifth MOSFET M5 is turned on, the mirror current I2 cannot flow into the first capacitor C, and the non-inverting input terminal of the first comparator U2 is connected to ground, so the voltage at the non-inverting input terminal of the first comparator U2 drops to zero.

[0080] The first comparator U2 compares the second sampled voltage with the voltage at its non-inverting input. When the voltage at the non-inverting input of the first comparator U2 is high, the first comparator U2 outputs a high-level comparison signal. When the voltage at the non-inverting input of the first comparator U2 is low, the first comparator U2 outputs a low-level comparison signal.

[0081] The second AND gate A4 performs an AND operation on the timing signals of the comparison signal and the first drive signal. When the timing signal of the first drive signal is high and the comparison signal is high, the timing signal of the second drive signal output by the second AND gate A4 is high. When the timing signal of the first drive signal is low or the comparison signal is low, the timing signal of the second drive signal output by the second AND gate A4 is low.

[0082] The first delay unit 21 delays the rising edge of the timing signal of the first drive signal, and the delay time is the maximum conduction time, which is calculated by the following formula: (7) Where ton_max is the maximum on-time, C1 is the capacitance of the first capacitor C, R1 is the resistance of the first resistor R, λ is the ratio coefficient of the second sampling voltage to the output voltage, η is the ratio coefficient of the first sampling voltage to the input voltage, vin is the input voltage, and vo is the output voltage.

[0083] Since the maximum conduction time ton_max must satisfy formula (1), substituting formula (7) into formula (1) will yield the following formula: (8) Therefore, by reasonably designing the switching cycle T, the capacitance C1 of the first capacitor C, the resistance R1 of the first resistor R, the proportional coefficient λ and the proportional coefficient η, so that they satisfy the constraint relationship of formula (8), the maximum conduction time can satisfy formula (1), and in steady state, each output branch can be forced to work in DCM mode, so that there is no mutual interference between each output branch, thus ensuring the stability of the power supply.

[0084] To better describe how to limit the maximum on-time of the master transistor MP in a single-inductor L multi-output DC-DC converter in order to reduce crosstalk between output branches, this application uses two output branches as an example to describe the working process of the converter.

[0085] Please see Figure 8 , Figure 8 This is a schematic diagram of the circuit structure of a converter provided in an embodiment of this application, such as... Figure 8 As shown, the converter is a single-inductor dual-output converter. In addition to the upper transistor MP, the lower transistor MN, the inductor L, the first output branch and the second output branch, the converter also includes a feedback circuit 200 and a power control circuit 100.

[0086] The feedback circuit 200 is connected to the first output branch, the second output branch, and the control circuit 10 in the power control circuit 100. The feedback circuit 200 is used to sample the first output voltage vo1 during the conduction period of the first output branch, and output the corresponding PWM signal to the control circuit 10 according to the output voltage vo1, so that the control circuit 10 outputs the corresponding first drive signal according to the corresponding PWM signal to drive the upper transistor MP, and outputs the corresponding third drive signal to drive the lower transistor MN.

[0087] The feedback circuit 200 is also used to sample the second output voltage vo2 during the conduction period of the second output branch, and output the corresponding PWM signal to the control circuit 10 according to the output voltage vo1, so that the control circuit 10 outputs the corresponding first drive signal according to the corresponding PWM signal to drive the upper transistor MP, and outputs the corresponding third drive signal to drive the lower transistor MN.

[0088] When the first drive signal is low, the upper transistor MP is turned on; when the first drive signal is high, the upper transistor MP is turned off. When the third drive signal is low, the lower transistor MN is turned off; when the third drive signal is high, the lower transistor MN is turned on.

[0089] The timing signal generation circuit 20 is used to generate the timing signal of the first drive signal. The timing signals of the first drive signal corresponding to the two output branches are as follows: Figure 3As shown, the clock signal ck is the clock generated by the oscillator, the clock signal ck1 is the working clock of the converter, the rising edge triggers the converter to enter the next working cycle, the timing signal S11 is the working timing of the first driving signal of the driving switch S1, the timing signal S22 is the working timing of the first driving signal of the driving switch S2, the timing signal tonmax1 is the timing signal of the first driving signal during the first output branch conduction period, the duration of the high level in the timing signal tonmax1 is the maximum conduction time ton_max1 of the upper transistor MP during the first output branch conduction period, the timing signal tonmax2 is the maximum conduction time ton_max2 of the upper transistor MP during the second output branch conduction period, and the maximum conduction time ton_max1 and the maximum conduction time ton_max2 both satisfy formula (1).

[0090] During the first output branch conduction period, the control circuit 10 receives the timing signal tonmax1. When the conduction time of the upper transistor MP reaches the target conduction time, the control circuit 10 drives the upper transistor MP to turn off. If, due to abnormal circumstances, the upper transistor MP does not turn off when the conduction time reaches the target conduction time, the control circuit 10 drives the upper transistor MP to be forcibly turned off when the timing signal tonmax1 reaches the falling edge or when the timing signal tonmax1 turns to a low level, so as to ensure that the conduction time of the upper transistor MP does not exceed the maximum conduction time ton_max1. The maximum conduction time is limited by formula (1) so that when switching to the next output branch, the inductor current returns to zero, preventing current crosstalk between output branches.

[0091] During the conduction of the second output branch, the control circuit 10 receives the timing signal tonmax2. When the conduction time of the upper transistor MP reaches the target conduction time, the control circuit 10 drives the upper transistor MP to turn off. If, due to an abnormal situation, the upper transistor MP does not turn off when the conduction time reaches the target conduction time, the control circuit 10 drives the upper transistor MP to be forcibly turned off when the timing signal tonmax2 reaches the falling edge or when the timing signal tonmax2 turns to a low level, so as to ensure that the conduction time of the upper transistor MP does not exceed the maximum conduction time ton_max2. The maximum conduction time is limited by formula (1) so that when switching to the next output branch, the inductor current returns to zero, preventing current crosstalk between output branches.

[0092] In the above manner, during the conduction period of each output branch, when the conduction time of the upper transistor MP reaches the target conduction time, the upper transistor MP is turned off, and the target conduction time is less than or equal to the maximum conduction time. At the same time, the maximum conduction time of the upper transistor MP is limited by formula (1) so that when switching to the next output branch, the inductor current returns to zero, thereby reducing the interference between output branches.

[0093] In some embodiments, the power control circuit 100 further includes a current detection circuit 30, which is used to detect the inductor current. When the inductor current is greater than or equal to the maximum current threshold, the current detection circuit 30 outputs a high-level trigger signal OCP1, and when the inductor current is less than the maximum current threshold, the current detection circuit 30 outputs a low-level trigger signal OCP2. The maximum current threshold i of the first output branch is determined according to formula (5). max1 And the maximum current threshold i of the second output branch max2 .

[0094] If the control circuit 10 receives a high-level trigger signal OCP1, the control circuit 10 outputs a high-level second drive signal to drive the upper transistor MP to turn off.

[0095] Therefore, when the input voltage or output voltage changes abruptly or when a sudden load is applied, the maximum current of the inductor is limited to ensure that the converter can operate safely in DCM mode and that the inductor current returns to zero when the next output branch is switched.

[0096] In summary, during the conduction period of each output branch, the power control circuit controls the maximum conduction time of the converter's master transistor to ensure that the ratio of the maximum conduction time to the converter's switching cycle is less than or equal to the converter's duty cycle. When the conduction time of the converter's master transistor reaches the target conduction time, the master transistor is driven to turn off, and the target conduction time is less than or equal to the maximum conduction time. This ensures that the current flowing through the converter's inductor drops to zero before the next output branch is turned on. Consequently, when the output branch switches or the load changes, crosstalk between the output branches is reduced, power jitter is decreased, and the stability of the converter's output power is improved.

[0097] As another aspect of the embodiments of this application, the following embodiments of this application provide a charge-discharge conversion method applied to the power control circuit 100 described in the above embodiments. Figure 9 As shown, the power control method S100 includes: S10: The timing signal of the second drive signal is generated by the timing signal generation circuit. The timing signal of the second drive signal includes the maximum on-time of the upper transistor of the converter during the conduction of each output branch. The maximum on-time satisfies the following constraint: the ratio of the maximum on-time to the switching period of the converter is less than or equal to the duty cycle of the converter. S20: During the conduction period of each output branch, the timing signal of the second drive signal is received through the control circuit, and when the conduction time of the upper transistor reaches the target conduction time, the upper transistor is driven to turn off, wherein the target conduction time is less than or equal to the maximum conduction time of the upper transistor.

[0098] In this embodiment, during the conduction period of each output branch, the power control method controls the maximum conduction time of the converter's master transistor to satisfy the constraint that the ratio of the maximum conduction time to the converter's switching cycle is less than or equal to the converter's duty cycle. When the conduction time of the converter's master transistor reaches the target conduction time, the master transistor is driven to turn off, and the target conduction time is less than or equal to the maximum conduction time. This ensures that before the next output branch is turned on, the current flowing through the converter's inductor drops to zero, thereby reducing crosstalk between output branches, reducing power jitter, and improving the stability of the converter's output power supply when the output branch switches or the load changes.

[0099] In some embodiments, the power control circuit further includes a current detection circuit, which is connected to both the inductor in the converter and the control circuit. Figure 10 As shown, the power control method S100 further includes: S30: During the conduction period of each output branch, the current flowing through the inductor is detected by the current detection circuit to obtain the sampled current, and in response to the result that the sampled current is greater than or equal to the maximum current threshold, a first-level trigger signal is output. S40: Receive the trigger signal through the control circuit, and drive the upper transistor to turn off when the trigger signal is at the first level.

[0100] In some embodiments, the maximum current threshold is , where i max Where is the maximum current of the inductor, T is the switching period of the converter, L1 is the inductance of the converter's inductor, vo is the output voltage, and vin max This is the maximum value of the input voltage.

[0101] Therefore, during the conduction period of each output branch, the control circuit receives the trigger signal OCP. If the first level trigger signal is received, it indicates that the inductor current is greater than or equal to the maximum current threshold. Then, the upper transistor is driven to turn off to ensure that the inductor current can be reduced to zero before the next output branch is turned on, thereby reducing interference to the next output branch.

[0102] It should be noted that in the above embodiments, there is no necessarily a certain order between the steps. Those skilled in the art can understand from the description of the embodiments of this application that the above steps may have different execution orders in different embodiments, that is, they may be executed in parallel or in turn, etc.

[0103] Since the power control method described above is based on the same inventive concept as the power control circuit 100 in the above embodiments, the corresponding content in the circuit embodiments above is also applicable to the method embodiments, and will not be described in detail here.

[0104] In summary, during the conduction period of each output branch, this power control method controls the maximum conduction time of the converter's master transistor to ensure that the ratio of the maximum conduction time to the converter's switching cycle is less than or equal to the converter's duty cycle. When the conduction time of the converter's master transistor reaches the target conduction time, the master transistor is driven to turn off, and the target conduction time is less than or equal to the maximum conduction time. This ensures that before the next output branch is turned on, the current flowing through the converter's inductor L drops to zero. Consequently, when the output branch switches or the load changes, crosstalk between the output branches is reduced, power jitter is decreased, and the stability of the converter's output power is improved.

[0105] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above, which are not provided in detail for the sake of brevity; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A power supply control circuit applied to a single-inductor multi-output converter, wherein, The converter includes several output branches, each of which alternately outputs an output voltage. When one output branch outputs an output voltage, the other output branches are turned off. The power control circuit includes a control circuit and several timing signal generation circuits, wherein the timing signal generation circuits correspond one-to-one with the output branches. The timing signal generation circuit is respectively connected to the input voltage of the converter, the output voltage of the corresponding output branch, and the timing signal of the first drive signal of the corresponding output branch. The timing signal generation circuit is also connected to the control circuit. The timing signal generation circuit is used to generate a timing signal of a second drive signal based on the input voltage, the output voltage of the corresponding output branch, and the timing signal of the first drive signal of the corresponding output branch. The first drive signal is used to drive the corresponding output branch to turn on or off, and the second drive signal is used to drive the upper transistor of the converter to turn on or off. The timing signal of the second drive signal includes the maximum on-time of the upper transistor of the converter during the on-time of each output branch, and the maximum on-time satisfies the following constraint: the ratio of the maximum on-time to the switching period of the converter is less than or equal to the duty cycle of the converter. The control circuit is used to receive the timing signal of the second drive signal during the conduction period of each output branch, and to drive the upper transistor to turn off when the conduction time of the upper transistor reaches the target conduction time, wherein the target conduction time is less than or equal to the maximum conduction time of the upper transistor.

2. The power control circuit according to claim 1, characterized in that, The timing signal generation circuit includes a first delay unit, a first inverter, and a first AND gate; The input terminal of the first delay unit is used to receive the timing signal of the first driving signal, the input voltage, and the output voltage. The output terminal of the first delay unit is connected to the input terminal of the first inverter. The first delay unit is used to output a delay signal according to the timing signal of the first driving signal, the input voltage, and the output voltage. The output terminal of the first inverter is connected to the first input terminal of the first AND gate. The second input terminal of the first AND gate is used to receive the timing signal of the first driving signal. The first inverter is used to respond to the input of the delay signal and output the inverted signal of the delay signal. The first AND gate responds to the timing signal of the first driving signal and the inverted signal of the delay signal and outputs the timing signal of the second driving signal.

3. The power control circuit according to claim 2, characterized in that, The first delay unit includes a conversion unit, a mirror unit, a switching unit, an energy storage unit, and a generation unit; The first input terminal of the conversion unit is used to receive the first sampling voltage, and the output terminal of the conversion unit is connected to the first terminal of the mirror unit. The conversion unit is used to convert the first sampling voltage into a sampling current, wherein the first sampling voltage is the sampling voltage of the input voltage. The second end of the mirror unit is connected to the first end of the switching unit, and the mirror unit is used to mirror the sampling current to generate a mirror current. The second terminal of the switching unit is connected to the first input terminal of the energy storage unit and the first input terminal of the generation unit, respectively. The third terminal of the switching unit is grounded. The control terminal of the switching unit is used to receive the timing signal of the first driving signal. The switching unit is used to respond to the input of the timing signal of the first driving signal and control the mirror current to charge the energy storage unit, so as to raise the voltage of the first input terminal of the generation unit, or to connect the first input terminal of the generation unit to ground, so as to lower the voltage of the first input terminal of the generation unit. The second input terminal of the generation unit is used to receive the second sampling voltage, and the third input terminal of the generation unit is used to receive the timing signal of the first driving signal. The generation unit is used to compare the second sampling voltage with the voltage of the first input terminal of the generation unit to generate a comparison signal, and generate the delay signal according to the comparison signal and the timing signal of the first driving signal, wherein the second sampling voltage is the sampling voltage of the output voltage.

4. The power control circuit according to claim 3, characterized in that, The conversion unit includes a first operational amplifier, a first resistor, and a first MOSFET; The non-inverting input of the first operational amplifier is used to connect to the first sampling voltage. The inverting input of the first operational amplifier is connected to one end of the first resistor and the source of the first MOS transistor. The other end of the first resistor is grounded. The output of the first operational amplifier is connected to the gate of the first MOS transistor. The drain of the first MOS transistor is connected to the first end of the mirror unit.

5. The power control circuit according to claim 4, characterized in that, The mirror unit includes a second MOS transistor and a third MOS transistor; The drain of the second MOS transistor is connected to the drain of the first MOS transistor. The drain of the second MOS transistor is also connected to the gate of the second MOS transistor and the gate of the third MOS transistor. The source of the second MOS transistor and the source of the third MOS transistor are connected to the first power supply. The drain of the third MOS transistor is connected to the first terminal of the switching unit.

6. The power control circuit according to claim 5, characterized in that, The switching unit includes a fourth MOSFET, a fifth MOSFET, and a second inverter; The gate of the fourth MOS transistor and the input terminal of the second inverter are both used to receive the timing signal of the first drive signal. The drain of the fourth MOS transistor is connected to the drain of the third MOS transistor. The source of the fourth MOS transistor is connected to the drain of the fifth MOS transistor, the energy storage unit, and the first input terminal of the generation unit, respectively. The source of the fifth MOS transistor is grounded, and the gate of the fifth MOS transistor is connected to the output terminal of the second inverter.

7. The power control circuit according to claim 6, characterized in that, The energy storage unit includes a first capacitor, one end of which is connected to the source of the fourth MOS transistor, the drain of the fifth MOS transistor, and the first end of the generation unit, respectively, and the other end of the first capacitor is grounded.

8. The power control circuit according to claim 7, characterized in that, The generation unit includes a first comparator and a second AND gate; The non-inverting input of the first comparator is connected to the first capacitor, the source of the fourth MOSFET, and the drain of the fifth MOSFET, respectively. The inverting input of the first comparator is used to receive the second sampling voltage. The output of the first comparator is connected to the first input of the second AND gate. The second input of the second AND gate is used to receive the timing signal of the first driving signal. The output of the second AND gate is connected to the control circuit. The output of the second AND gate is used to output the timing signal of the second driving signal.

9. A power supply control method, characterized in that, The method, applied to the power control circuit as described in any one of claims 1-8, comprises: The timing signal of the second drive signal is generated by the timing signal generation circuit. The timing signal of the second drive signal includes the maximum on-time of the upper transistor of the converter during the conduction of each output branch. The maximum on-time satisfies the following constraint: the ratio of the maximum on-time to the switching period of the converter is less than or equal to the duty cycle of the converter. During the conduction period of each output branch, the timing signal of the second drive signal is received by the control circuit, and when the conduction time of the upper transistor reaches the target conduction time, the upper transistor is driven to turn off, wherein the target conduction time is less than or equal to the maximum conduction time of the upper transistor.

10. The method according to claim 9, characterized in that, The power control circuit further includes a current detection circuit, which is connected to the inductor in the converter and the control circuit respectively. The method further includes: During the conduction of each output branch, the current flowing through the inductor is detected by the current detection circuit to obtain the sampled current, and in response to the result that the sampled current is greater than or equal to the maximum current threshold, a first-level trigger signal is output. The control circuit receives the trigger signal and drives the upper transistor to turn off when the trigger signal is at the first level.

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